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-rw-r--r--arch/arm/mach-omap2/am35xx-emac.c37
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c38
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c37
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c25
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c30
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c30
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c32
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c37
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c37
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c29
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c46
-rw-r--r--arch/arm/mach-omap2/board-overo.c25
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c4
-rw-r--r--arch/arm/mach-omap2/board-rx51.c38
-rw-r--r--arch/arm/mach-omap2/board-zoom-display.c1
-rw-r--r--arch/arm/mach-omap2/common.h2
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c298
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c126
-rw-r--r--arch/arm/mach-omap2/devices.c7
-rw-r--r--arch/arm/mach-omap2/gpio.c2
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c3
-rw-r--r--arch/arm/mach-omap2/gpmc.c3
-rw-r--r--arch/arm/mach-omap2/hwspinlock.c2
-rw-r--r--arch/arm/mach-omap2/io.c1
-rw-r--r--arch/arm/mach-omap2/irq.c3
-rw-r--r--arch/arm/mach-omap2/mux.c2
-rw-r--r--arch/arm/mach-omap2/omap-secure.c1
-rw-r--r--arch/arm/mach-omap2/omap-wakeupgen.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c1143
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c1526
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c1921
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c266
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c562
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c3001
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c4931
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h71
-rw-r--r--arch/arm/mach-omap2/pm.h21
-rw-r--r--arch/arm/mach-omap2/pm24xx.c3
-rw-r--r--arch/arm/mach-omap2/pm34xx.c10
-rw-r--r--arch/arm/mach-omap2/prm_common.c4
-rw-r--r--arch/arm/mach-omap2/serial.c2
-rw-r--r--arch/arm/mach-omap2/timer.c15
-rw-r--r--arch/arm/mach-omap2/usb-tusb6010.c2
43 files changed, 5921 insertions, 8455 deletions
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 1f97e747520..447682c4e11 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -39,26 +39,23 @@ static struct platform_device am35xx_emac_mdio_device = {
39 39
40static void am35xx_enable_emac_int(void) 40static void am35xx_enable_emac_int(void)
41{ 41{
42 u32 regval; 42 u32 v;
43 43
44 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); 44 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
45 regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | 45 v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
46 AM35XX_CPGMAC_C0_TX_PULSE_CLR | 46 AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
47 AM35XX_CPGMAC_C0_MISC_PULSE_CLR | 47 omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
48 AM35XX_CPGMAC_C0_RX_THRESH_CLR); 48 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
49 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
50 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
51} 49}
52 50
53static void am35xx_disable_emac_int(void) 51static void am35xx_disable_emac_int(void)
54{ 52{
55 u32 regval; 53 u32 v;
56 54
57 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); 55 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
58 regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | 56 v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
59 AM35XX_CPGMAC_C0_TX_PULSE_CLR); 57 omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
60 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); 58 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
61 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
62} 59}
63 60
64static struct emac_platform_data am35xx_emac_pdata = { 61static struct emac_platform_data am35xx_emac_pdata = {
@@ -92,7 +89,7 @@ static struct platform_device am35xx_emac_device = {
92 89
93void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) 90void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
94{ 91{
95 unsigned int regval; 92 u32 v;
96 int err; 93 int err;
97 94
98 am35xx_emac_pdata.rmii_en = rmii_en; 95 am35xx_emac_pdata.rmii_en = rmii_en;
@@ -110,8 +107,8 @@ void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
110 return; 107 return;
111 } 108 }
112 109
113 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); 110 v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
114 regval = regval & (~(AM35XX_CPGMACSS_SW_RST)); 111 v &= ~AM35XX_CPGMACSS_SW_RST;
115 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); 112 omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
116 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); 113 omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
117} 114}
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index da75f239873..37abb0d49b5 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -37,7 +37,7 @@
37#include <plat/dma.h> 37#include <plat/dma.h>
38#include <plat/gpmc.h> 38#include <plat/gpmc.h>
39#include <video/omapdss.h> 39#include <video/omapdss.h>
40#include <video/omap-panel-dvi.h> 40#include <video/omap-panel-tfp410.h>
41 41
42#include <plat/gpmc-smc91x.h> 42#include <plat/gpmc-smc91x.h>
43 43
@@ -113,9 +113,6 @@ static struct gpio sdp3430_dss_gpios[] __initdata = {
113 {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"}, 113 {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
114}; 114};
115 115
116static int lcd_enabled;
117static int dvi_enabled;
118
119static void __init sdp3430_display_init(void) 116static void __init sdp3430_display_init(void)
120{ 117{
121 int r; 118 int r;
@@ -129,44 +126,18 @@ static void __init sdp3430_display_init(void)
129 126
130static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev) 127static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
131{ 128{
132 if (dvi_enabled) {
133 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
134 return -EINVAL;
135 }
136
137 gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1); 129 gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
138 gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1); 130 gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
139 131
140 lcd_enabled = 1;
141
142 return 0; 132 return 0;
143} 133}
144 134
145static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev) 135static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
146{ 136{
147 lcd_enabled = 0;
148
149 gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0); 137 gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
150 gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0); 138 gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
151} 139}
152 140
153static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
154{
155 if (lcd_enabled) {
156 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
157 return -EINVAL;
158 }
159
160 dvi_enabled = 1;
161
162 return 0;
163}
164
165static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev)
166{
167 dvi_enabled = 0;
168}
169
170static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev) 141static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
171{ 142{
172 return 0; 143 return 0;
@@ -186,15 +157,14 @@ static struct omap_dss_device sdp3430_lcd_device = {
186 .platform_disable = sdp3430_panel_disable_lcd, 157 .platform_disable = sdp3430_panel_disable_lcd,
187}; 158};
188 159
189static struct panel_dvi_platform_data dvi_panel = { 160static struct tfp410_platform_data dvi_panel = {
190 .platform_enable = sdp3430_panel_enable_dvi, 161 .power_down_gpio = -1,
191 .platform_disable = sdp3430_panel_disable_dvi,
192}; 162};
193 163
194static struct omap_dss_device sdp3430_dvi_device = { 164static struct omap_dss_device sdp3430_dvi_device = {
195 .name = "dvi", 165 .name = "dvi",
196 .type = OMAP_DISPLAY_TYPE_DPI, 166 .type = OMAP_DISPLAY_TYPE_DPI,
197 .driver_name = "dvi", 167 .driver_name = "tfp410",
198 .data = &dvi_panel, 168 .data = &dvi_panel,
199 .phy.dpi.data_lines = 24, 169 .phy.dpi.data_lines = 24,
200}; 170};
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 130ab00c09a..b4ad706c145 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -666,6 +666,10 @@ static struct nokia_dsi_panel_data dsi1_panel = {
666 .use_ext_te = false, 666 .use_ext_te = false,
667 .ext_te_gpio = 101, 667 .ext_te_gpio = 101,
668 .esd_interval = 0, 668 .esd_interval = 0,
669 .pin_config = {
670 .num_pins = 6,
671 .pins = { 0, 1, 2, 3, 4, 5 },
672 },
669}; 673};
670 674
671static struct omap_dss_device sdp4430_lcd_device = { 675static struct omap_dss_device sdp4430_lcd_device = {
@@ -674,13 +678,6 @@ static struct omap_dss_device sdp4430_lcd_device = {
674 .type = OMAP_DISPLAY_TYPE_DSI, 678 .type = OMAP_DISPLAY_TYPE_DSI,
675 .data = &dsi1_panel, 679 .data = &dsi1_panel,
676 .phy.dsi = { 680 .phy.dsi = {
677 .clk_lane = 1,
678 .clk_pol = 0,
679 .data1_lane = 2,
680 .data1_pol = 0,
681 .data2_lane = 3,
682 .data2_pol = 0,
683
684 .module = 0, 681 .module = 0,
685 }, 682 },
686 683
@@ -715,6 +712,10 @@ static struct nokia_dsi_panel_data dsi2_panel = {
715 .use_ext_te = false, 712 .use_ext_te = false,
716 .ext_te_gpio = 103, 713 .ext_te_gpio = 103,
717 .esd_interval = 0, 714 .esd_interval = 0,
715 .pin_config = {
716 .num_pins = 6,
717 .pins = { 0, 1, 2, 3, 4, 5 },
718 },
718}; 719};
719 720
720static struct omap_dss_device sdp4430_lcd2_device = { 721static struct omap_dss_device sdp4430_lcd2_device = {
@@ -723,12 +724,6 @@ static struct omap_dss_device sdp4430_lcd2_device = {
723 .type = OMAP_DISPLAY_TYPE_DSI, 724 .type = OMAP_DISPLAY_TYPE_DSI,
724 .data = &dsi2_panel, 725 .data = &dsi2_panel,
725 .phy.dsi = { 726 .phy.dsi = {
726 .clk_lane = 1,
727 .clk_pol = 0,
728 .data1_lane = 2,
729 .data1_pol = 0,
730 .data2_lane = 3,
731 .data2_pol = 0,
732 727
733 .module = 1, 728 .module = 1,
734 }, 729 },
@@ -758,21 +753,6 @@ static struct omap_dss_device sdp4430_lcd2_device = {
758 .channel = OMAP_DSS_CHANNEL_LCD2, 753 .channel = OMAP_DSS_CHANNEL_LCD2,
759}; 754};
760 755
761static void sdp4430_lcd_init(void)
762{
763 int r;
764
765 r = gpio_request_one(dsi1_panel.reset_gpio, GPIOF_DIR_OUT,
766 "lcd1_reset_gpio");
767 if (r)
768 pr_err("%s: Could not get lcd1_reset_gpio\n", __func__);
769
770 r = gpio_request_one(dsi2_panel.reset_gpio, GPIOF_DIR_OUT,
771 "lcd2_reset_gpio");
772 if (r)
773 pr_err("%s: Could not get lcd2_reset_gpio\n", __func__);
774}
775
776static struct omap_dss_hdmi_data sdp4430_hdmi_data = { 756static struct omap_dss_hdmi_data sdp4430_hdmi_data = {
777 .hpd_gpio = HDMI_GPIO_HPD, 757 .hpd_gpio = HDMI_GPIO_HPD,
778}; 758};
@@ -858,7 +838,6 @@ static void __init omap_4430sdp_display_init(void)
858 if (r) 838 if (r)
859 pr_err("%s: Could not get display_sel GPIO\n", __func__); 839 pr_err("%s: Could not get display_sel GPIO\n", __func__);
860 840
861 sdp4430_lcd_init();
862 sdp4430_picodlp_init(); 841 sdp4430_picodlp_init();
863 omap_display_init(&sdp4430_dss_data); 842 omap_display_init(&sdp4430_dss_data);
864 /* 843 /*
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 3645285a3e2..99790eb646e 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -37,7 +37,7 @@
37#include <plat/usb.h> 37#include <plat/usb.h>
38#include <video/omapdss.h> 38#include <video/omapdss.h>
39#include <video/omap-panel-generic-dpi.h> 39#include <video/omap-panel-generic-dpi.h>
40#include <video/omap-panel-dvi.h> 40#include <video/omap-panel-tfp410.h>
41 41
42#include "am35xx-emac.h" 42#include "am35xx-emac.h"
43#include "mux.h" 43#include "mux.h"
@@ -207,31 +207,14 @@ static struct omap_dss_device am3517_evm_tv_device = {
207 .platform_disable = am3517_evm_panel_disable_tv, 207 .platform_disable = am3517_evm_panel_disable_tv,
208}; 208};
209 209
210static int am3517_evm_panel_enable_dvi(struct omap_dss_device *dssdev) 210static struct tfp410_platform_data dvi_panel = {
211{ 211 .power_down_gpio = -1,
212 if (lcd_enabled) {
213 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
214 return -EINVAL;
215 }
216 dvi_enabled = 1;
217
218 return 0;
219}
220
221static void am3517_evm_panel_disable_dvi(struct omap_dss_device *dssdev)
222{
223 dvi_enabled = 0;
224}
225
226static struct panel_dvi_platform_data dvi_panel = {
227 .platform_enable = am3517_evm_panel_enable_dvi,
228 .platform_disable = am3517_evm_panel_disable_dvi,
229}; 212};
230 213
231static struct omap_dss_device am3517_evm_dvi_device = { 214static struct omap_dss_device am3517_evm_dvi_device = {
232 .type = OMAP_DISPLAY_TYPE_DPI, 215 .type = OMAP_DISPLAY_TYPE_DPI,
233 .name = "dvi", 216 .name = "dvi",
234 .driver_name = "dvi", 217 .driver_name = "tfp410",
235 .data = &dvi_panel, 218 .data = &dvi_panel,
236 .phy.dpi.data_lines = 24, 219 .phy.dpi.data_lines = 24,
237}; 220};
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 909a8b91b56..45746cb56c6 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -44,7 +44,7 @@
44#include <plat/usb.h> 44#include <plat/usb.h>
45#include <video/omapdss.h> 45#include <video/omapdss.h>
46#include <video/omap-panel-generic-dpi.h> 46#include <video/omap-panel-generic-dpi.h>
47#include <video/omap-panel-dvi.h> 47#include <video/omap-panel-tfp410.h>
48#include <plat/mcspi.h> 48#include <plat/mcspi.h>
49 49
50#include <mach/hardware.h> 50#include <mach/hardware.h>
@@ -218,25 +218,6 @@ static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev)
218 gpio_set_value(CM_T35_LCD_EN_GPIO, 0); 218 gpio_set_value(CM_T35_LCD_EN_GPIO, 0);
219} 219}
220 220
221static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev)
222{
223 if (lcd_enabled) {
224 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
225 return -EINVAL;
226 }
227
228 gpio_set_value(CM_T35_DVI_EN_GPIO, 0);
229 dvi_enabled = 1;
230
231 return 0;
232}
233
234static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev)
235{
236 gpio_set_value(CM_T35_DVI_EN_GPIO, 1);
237 dvi_enabled = 0;
238}
239
240static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev) 221static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev)
241{ 222{
242 return 0; 223 return 0;
@@ -260,15 +241,14 @@ static struct omap_dss_device cm_t35_lcd_device = {
260 .phy.dpi.data_lines = 18, 241 .phy.dpi.data_lines = 18,
261}; 242};
262 243
263static struct panel_dvi_platform_data dvi_panel = { 244static struct tfp410_platform_data dvi_panel = {
264 .platform_enable = cm_t35_panel_enable_dvi, 245 .power_down_gpio = CM_T35_DVI_EN_GPIO,
265 .platform_disable = cm_t35_panel_disable_dvi,
266}; 246};
267 247
268static struct omap_dss_device cm_t35_dvi_device = { 248static struct omap_dss_device cm_t35_dvi_device = {
269 .name = "dvi", 249 .name = "dvi",
270 .type = OMAP_DISPLAY_TYPE_DPI, 250 .type = OMAP_DISPLAY_TYPE_DPI,
271 .driver_name = "dvi", 251 .driver_name = "tfp410",
272 .data = &dvi_panel, 252 .data = &dvi_panel,
273 .phy.dpi.data_lines = 24, 253 .phy.dpi.data_lines = 24,
274}; 254};
@@ -316,7 +296,6 @@ static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
316static struct gpio cm_t35_dss_gpios[] __initdata = { 296static struct gpio cm_t35_dss_gpios[] __initdata = {
317 { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, "lcd enable" }, 297 { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, "lcd enable" },
318 { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW, "lcd bl enable" }, 298 { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW, "lcd bl enable" },
319 { CM_T35_DVI_EN_GPIO, GPIOF_OUT_INIT_HIGH, "dvi enable" },
320}; 299};
321 300
322static void __init cm_t35_init_display(void) 301static void __init cm_t35_init_display(void)
@@ -335,7 +314,6 @@ static void __init cm_t35_init_display(void)
335 314
336 gpio_export(CM_T35_LCD_EN_GPIO, 0); 315 gpio_export(CM_T35_LCD_EN_GPIO, 0);
337 gpio_export(CM_T35_LCD_BL_GPIO, 0); 316 gpio_export(CM_T35_LCD_BL_GPIO, 0);
338 gpio_export(CM_T35_DVI_EN_GPIO, 0);
339 317
340 msleep(50); 318 msleep(50);
341 gpio_set_value(CM_T35_LCD_EN_GPIO, 1); 319 gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index a2010f07de3..b063f0d2faa 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -47,7 +47,7 @@
47#include <plat/usb.h> 47#include <plat/usb.h>
48#include <video/omapdss.h> 48#include <video/omapdss.h>
49#include <video/omap-panel-generic-dpi.h> 49#include <video/omap-panel-generic-dpi.h>
50#include <video/omap-panel-dvi.h> 50#include <video/omap-panel-tfp410.h>
51 51
52#include <plat/mcspi.h> 52#include <plat/mcspi.h>
53#include <linux/input/matrix_keypad.h> 53#include <linux/input/matrix_keypad.h>
@@ -118,19 +118,6 @@ static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
118 gpio_set_value_cansleep(dssdev->reset_gpio, 0); 118 gpio_set_value_cansleep(dssdev->reset_gpio, 0);
119} 119}
120 120
121static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
122{
123 if (gpio_is_valid(dssdev->reset_gpio))
124 gpio_set_value_cansleep(dssdev->reset_gpio, 1);
125 return 0;
126}
127
128static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
129{
130 if (gpio_is_valid(dssdev->reset_gpio))
131 gpio_set_value_cansleep(dssdev->reset_gpio, 0);
132}
133
134static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = { 121static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
135 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), 122 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
136}; 123};
@@ -154,15 +141,14 @@ static struct omap_dss_device devkit8000_lcd_device = {
154 .phy.dpi.data_lines = 24, 141 .phy.dpi.data_lines = 24,
155}; 142};
156 143
157static struct panel_dvi_platform_data dvi_panel = { 144static struct tfp410_platform_data dvi_panel = {
158 .platform_enable = devkit8000_panel_enable_dvi, 145 .power_down_gpio = -1,
159 .platform_disable = devkit8000_panel_disable_dvi,
160}; 146};
161 147
162static struct omap_dss_device devkit8000_dvi_device = { 148static struct omap_dss_device devkit8000_dvi_device = {
163 .name = "dvi", 149 .name = "dvi",
164 .type = OMAP_DISPLAY_TYPE_DPI, 150 .type = OMAP_DISPLAY_TYPE_DPI,
165 .driver_name = "dvi", 151 .driver_name = "tfp410",
166 .data = &dvi_panel, 152 .data = &dvi_panel,
167 .phy.dpi.data_lines = 24, 153 .phy.dpi.data_lines = 24,
168}; 154};
@@ -244,13 +230,7 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
244 } 230 }
245 231
246 /* gpio + 7 is "DVI_PD" (out, active low) */ 232 /* gpio + 7 is "DVI_PD" (out, active low) */
247 devkit8000_dvi_device.reset_gpio = gpio + 7; 233 dvi_panel.power_down_gpio = gpio + 7;
248 ret = gpio_request_one(devkit8000_dvi_device.reset_gpio,
249 GPIOF_OUT_INIT_LOW, "DVI PowerDown");
250 if (ret < 0) {
251 devkit8000_dvi_device.reset_gpio = -EINVAL;
252 printk(KERN_ERR "Failed to request GPIO for DVI PowerDown\n");
253 }
254 234
255 return 0; 235 return 0;
256} 236}
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 740cee9369b..accbbb17319 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -32,7 +32,7 @@
32#include <plat/gpmc.h> 32#include <plat/gpmc.h>
33#include <plat/usb.h> 33#include <plat/usb.h>
34#include <video/omapdss.h> 34#include <video/omapdss.h>
35#include <video/omap-panel-dvi.h> 35#include <video/omap-panel-tfp410.h>
36#include <plat/onenand.h> 36#include <plat/onenand.h>
37 37
38#include "mux.h" 38#include "mux.h"
@@ -444,28 +444,15 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
444 .setup = igep_twl_gpio_setup, 444 .setup = igep_twl_gpio_setup,
445}; 445};
446 446
447static int igep2_enable_dvi(struct omap_dss_device *dssdev) 447static struct tfp410_platform_data dvi_panel = {
448{ 448 .i2c_bus_num = 3,
449 gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1); 449 .power_down_gpio = IGEP2_GPIO_DVI_PUP,
450
451 return 0;
452}
453
454static void igep2_disable_dvi(struct omap_dss_device *dssdev)
455{
456 gpio_direction_output(IGEP2_GPIO_DVI_PUP, 0);
457}
458
459static struct panel_dvi_platform_data dvi_panel = {
460 .platform_enable = igep2_enable_dvi,
461 .platform_disable = igep2_disable_dvi,
462 .i2c_bus_num = 3,
463}; 450};
464 451
465static struct omap_dss_device igep2_dvi_device = { 452static struct omap_dss_device igep2_dvi_device = {
466 .type = OMAP_DISPLAY_TYPE_DPI, 453 .type = OMAP_DISPLAY_TYPE_DPI,
467 .name = "dvi", 454 .name = "dvi",
468 .driver_name = "dvi", 455 .driver_name = "tfp410",
469 .data = &dvi_panel, 456 .data = &dvi_panel,
470 .phy.dpi.data_lines = 24, 457 .phy.dpi.data_lines = 24,
471}; 458};
@@ -480,14 +467,6 @@ static struct omap_dss_board_info igep2_dss_data = {
480 .default_device = &igep2_dvi_device, 467 .default_device = &igep2_dvi_device,
481}; 468};
482 469
483static void __init igep2_display_init(void)
484{
485 int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH,
486 "GPIO_DVI_PUP");
487 if (err)
488 pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n");
489}
490
491static struct platform_device *igep_devices[] __initdata = { 470static struct platform_device *igep_devices[] __initdata = {
492 &igep_vwlan_device, 471 &igep_vwlan_device,
493}; 472};
@@ -668,7 +647,6 @@ static void __init igep_init(void)
668 647
669 if (machine_is_igep0020()) { 648 if (machine_is_igep0020()) {
670 omap_display_init(&igep2_dss_data); 649 omap_display_init(&igep2_dss_data);
671 igep2_display_init();
672 igep2_init_smsc911x(); 650 igep2_init_smsc911x();
673 usbhs_init(&igep2_usbhs_bdata); 651 usbhs_init(&igep2_usbhs_bdata);
674 } else { 652 } else {
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7be8d659d91..8ede8d20d7b 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -42,7 +42,7 @@
42#include <plat/board.h> 42#include <plat/board.h>
43#include "common.h" 43#include "common.h"
44#include <video/omapdss.h> 44#include <video/omapdss.h>
45#include <video/omap-panel-dvi.h> 45#include <video/omap-panel-tfp410.h>
46#include <plat/gpmc.h> 46#include <plat/gpmc.h>
47#include <plat/nand.h> 47#include <plat/nand.h>
48#include <plat/usb.h> 48#include <plat/usb.h>
@@ -189,33 +189,17 @@ static struct mtd_partition omap3beagle_nand_partitions[] = {
189 189
190/* DSS */ 190/* DSS */
191 191
192static int beagle_enable_dvi(struct omap_dss_device *dssdev) 192static struct tfp410_platform_data dvi_panel = {
193{
194 if (gpio_is_valid(dssdev->reset_gpio))
195 gpio_set_value(dssdev->reset_gpio, 1);
196
197 return 0;
198}
199
200static void beagle_disable_dvi(struct omap_dss_device *dssdev)
201{
202 if (gpio_is_valid(dssdev->reset_gpio))
203 gpio_set_value(dssdev->reset_gpio, 0);
204}
205
206static struct panel_dvi_platform_data dvi_panel = {
207 .platform_enable = beagle_enable_dvi,
208 .platform_disable = beagle_disable_dvi,
209 .i2c_bus_num = 3, 193 .i2c_bus_num = 3,
194 .power_down_gpio = -1,
210}; 195};
211 196
212static struct omap_dss_device beagle_dvi_device = { 197static struct omap_dss_device beagle_dvi_device = {
213 .type = OMAP_DISPLAY_TYPE_DPI, 198 .type = OMAP_DISPLAY_TYPE_DPI,
214 .name = "dvi", 199 .name = "dvi",
215 .driver_name = "dvi", 200 .driver_name = "tfp410",
216 .data = &dvi_panel, 201 .data = &dvi_panel,
217 .phy.dpi.data_lines = 24, 202 .phy.dpi.data_lines = 24,
218 .reset_gpio = -EINVAL,
219}; 203};
220 204
221static struct omap_dss_device beagle_tv_device = { 205static struct omap_dss_device beagle_tv_device = {
@@ -236,16 +220,6 @@ static struct omap_dss_board_info beagle_dss_data = {
236 .default_device = &beagle_dvi_device, 220 .default_device = &beagle_dvi_device,
237}; 221};
238 222
239static void __init beagle_display_init(void)
240{
241 int r;
242
243 r = gpio_request_one(beagle_dvi_device.reset_gpio, GPIOF_OUT_INIT_LOW,
244 "DVI reset");
245 if (r < 0)
246 printk(KERN_ERR "Unable to get DVI reset GPIO\n");
247}
248
249#include "sdram-micron-mt46h32m32lf-6.h" 223#include "sdram-micron-mt46h32m32lf-6.h"
250 224
251static struct omap2_hsmmc_info mmc[] = { 225static struct omap2_hsmmc_info mmc[] = {
@@ -309,7 +283,7 @@ static int beagle_twl_gpio_setup(struct device *dev,
309 if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC")) 283 if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
310 pr_err("%s: unable to configure EHCI_nOC\n", __func__); 284 pr_err("%s: unable to configure EHCI_nOC\n", __func__);
311 } 285 }
312 beagle_dvi_device.reset_gpio = beagle_config.reset_gpio; 286 dvi_panel.power_down_gpio = beagle_config.reset_gpio;
313 287
314 gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level, 288 gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
315 "nEN_USB_PWR"); 289 "nEN_USB_PWR");
@@ -552,7 +526,6 @@ static void __init omap3_beagle_init(void)
552 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); 526 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
553 omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); 527 omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
554 528
555 beagle_display_init();
556 beagle_opp_init(); 529 beagle_opp_init();
557} 530}
558 531
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 49df12735b4..ace3c675e9c 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -46,7 +46,7 @@
46#include "common.h" 46#include "common.h"
47#include <plat/mcspi.h> 47#include <plat/mcspi.h>
48#include <video/omapdss.h> 48#include <video/omapdss.h>
49#include <video/omap-panel-dvi.h> 49#include <video/omap-panel-tfp410.h>
50 50
51#include "mux.h" 51#include "mux.h"
52#include "sdram-micron-mt46h32m32lf-6.h" 52#include "sdram-micron-mt46h32m32lf-6.h"
@@ -219,35 +219,14 @@ static struct omap_dss_device omap3_evm_tv_device = {
219 .platform_disable = omap3_evm_disable_tv, 219 .platform_disable = omap3_evm_disable_tv,
220}; 220};
221 221
222static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev) 222static struct tfp410_platform_data dvi_panel = {
223{ 223 .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO,
224 if (lcd_enabled) {
225 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
226 return -EINVAL;
227 }
228
229 gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
230
231 dvi_enabled = 1;
232 return 0;
233}
234
235static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
236{
237 gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
238
239 dvi_enabled = 0;
240}
241
242static struct panel_dvi_platform_data dvi_panel = {
243 .platform_enable = omap3_evm_enable_dvi,
244 .platform_disable = omap3_evm_disable_dvi,
245}; 224};
246 225
247static struct omap_dss_device omap3_evm_dvi_device = { 226static struct omap_dss_device omap3_evm_dvi_device = {
248 .name = "dvi", 227 .name = "dvi",
249 .type = OMAP_DISPLAY_TYPE_DPI, 228 .type = OMAP_DISPLAY_TYPE_DPI,
250 .driver_name = "dvi", 229 .driver_name = "tfp410",
251 .data = &dvi_panel, 230 .data = &dvi_panel,
252 .phy.dpi.data_lines = 24, 231 .phy.dpi.data_lines = 24,
253}; 232};
@@ -630,13 +609,13 @@ static struct regulator_consumer_supply dummy_supplies[] = {
630 609
631static void __init omap3_evm_init(void) 610static void __init omap3_evm_init(void)
632{ 611{
612 struct omap_board_mux *obm;
613
633 omap3_evm_get_revision(); 614 omap3_evm_get_revision();
634 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 615 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
635 616
636 if (cpu_is_omap3630()) 617 obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
637 omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB); 618 omap3_mux_init(obm, OMAP_PACKAGE_CBB);
638 else
639 omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
640 619
641 omap_board_config = omap3_evm_config; 620 omap_board_config = omap3_evm_config;
642 omap_board_config_size = ARRAY_SIZE(omap3_evm_config); 621 omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 4dffc95bddd..4396bae9167 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -42,7 +42,7 @@
42#include <plat/usb.h> 42#include <plat/usb.h>
43#include <video/omapdss.h> 43#include <video/omapdss.h>
44#include <video/omap-panel-generic-dpi.h> 44#include <video/omap-panel-generic-dpi.h>
45#include <video/omap-panel-dvi.h> 45#include <video/omap-panel-tfp410.h>
46 46
47#include <plat/mcspi.h> 47#include <plat/mcspi.h>
48#include <linux/input/matrix_keypad.h> 48#include <linux/input/matrix_keypad.h>
@@ -92,9 +92,6 @@ static inline void __init omap3stalker_init_eth(void)
92#define LCD_PANEL_BKLIGHT_GPIO 210 92#define LCD_PANEL_BKLIGHT_GPIO 210
93#define ENABLE_VPLL2_DEV_GRP 0xE0 93#define ENABLE_VPLL2_DEV_GRP 0xE0
94 94
95static int lcd_enabled;
96static int dvi_enabled;
97
98static void __init omap3_stalker_display_init(void) 95static void __init omap3_stalker_display_init(void)
99{ 96{
100 return; 97 return;
@@ -122,32 +119,14 @@ static struct omap_dss_device omap3_stalker_tv_device = {
122 .platform_disable = omap3_stalker_disable_tv, 119 .platform_disable = omap3_stalker_disable_tv,
123}; 120};
124 121
125static int omap3_stalker_enable_dvi(struct omap_dss_device *dssdev) 122static struct tfp410_platform_data dvi_panel = {
126{ 123 .power_down_gpio = DSS_ENABLE_GPIO,
127 if (lcd_enabled) {
128 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
129 return -EINVAL;
130 }
131 gpio_set_value(DSS_ENABLE_GPIO, 1);
132 dvi_enabled = 1;
133 return 0;
134}
135
136static void omap3_stalker_disable_dvi(struct omap_dss_device *dssdev)
137{
138 gpio_set_value(DSS_ENABLE_GPIO, 0);
139 dvi_enabled = 0;
140}
141
142static struct panel_dvi_platform_data dvi_panel = {
143 .platform_enable = omap3_stalker_enable_dvi,
144 .platform_disable = omap3_stalker_disable_dvi,
145}; 124};
146 125
147static struct omap_dss_device omap3_stalker_dvi_device = { 126static struct omap_dss_device omap3_stalker_dvi_device = {
148 .name = "dvi", 127 .name = "dvi",
149 .type = OMAP_DISPLAY_TYPE_DPI, 128 .type = OMAP_DISPLAY_TYPE_DPI,
150 .driver_name = "dvi", 129 .driver_name = "tfp410",
151 .data = &dvi_panel, 130 .data = &dvi_panel,
152 .phy.dpi.data_lines = 24, 131 .phy.dpi.data_lines = 24,
153}; 132};
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 1b782ba5343..59dd8b7f5b4 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -42,7 +42,7 @@
42#include "common.h" 42#include "common.h"
43#include <plat/usb.h> 43#include <plat/usb.h>
44#include <plat/mmc.h> 44#include <plat/mmc.h>
45#include <video/omap-panel-dvi.h> 45#include <video/omap-panel-tfp410.h>
46 46
47#include "hsmmc.h" 47#include "hsmmc.h"
48#include "control.h" 48#include "control.h"
@@ -231,7 +231,7 @@ static struct platform_device omap_vwlan_device = {
231 }, 231 },
232}; 232};
233 233
234struct wl12xx_platform_data omap_panda_wlan_data __initdata = { 234static struct wl12xx_platform_data omap_panda_wlan_data __initdata = {
235 /* PANDA ref clock is 38.4 MHz */ 235 /* PANDA ref clock is 38.4 MHz */
236 .board_ref_clock = 2, 236 .board_ref_clock = 2,
237}; 237};
@@ -420,47 +420,22 @@ static struct omap_board_mux board_mux[] __initdata = {
420/* Display DVI */ 420/* Display DVI */
421#define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0 421#define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0
422 422
423static int omap4_panda_enable_dvi(struct omap_dss_device *dssdev)
424{
425 gpio_set_value(dssdev->reset_gpio, 1);
426 return 0;
427}
428
429static void omap4_panda_disable_dvi(struct omap_dss_device *dssdev)
430{
431 gpio_set_value(dssdev->reset_gpio, 0);
432}
433
434/* Using generic display panel */ 423/* Using generic display panel */
435static struct panel_dvi_platform_data omap4_dvi_panel = { 424static struct tfp410_platform_data omap4_dvi_panel = {
436 .platform_enable = omap4_panda_enable_dvi, 425 .i2c_bus_num = 3,
437 .platform_disable = omap4_panda_disable_dvi, 426 .power_down_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
438 .i2c_bus_num = 3,
439}; 427};
440 428
441struct omap_dss_device omap4_panda_dvi_device = { 429static struct omap_dss_device omap4_panda_dvi_device = {
442 .type = OMAP_DISPLAY_TYPE_DPI, 430 .type = OMAP_DISPLAY_TYPE_DPI,
443 .name = "dvi", 431 .name = "dvi",
444 .driver_name = "dvi", 432 .driver_name = "tfp410",
445 .data = &omap4_dvi_panel, 433 .data = &omap4_dvi_panel,
446 .phy.dpi.data_lines = 24, 434 .phy.dpi.data_lines = 24,
447 .reset_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, 435 .reset_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
448 .channel = OMAP_DSS_CHANNEL_LCD2, 436 .channel = OMAP_DSS_CHANNEL_LCD2,
449}; 437};
450 438
451int __init omap4_panda_dvi_init(void)
452{
453 int r;
454
455 /* Requesting TFP410 DVI GPIO and disabling it, at bootup */
456 r = gpio_request_one(omap4_panda_dvi_device.reset_gpio,
457 GPIOF_OUT_INIT_LOW, "DVI PD");
458 if (r)
459 pr_err("Failed to get DVI powerdown GPIO\n");
460
461 return r;
462}
463
464static struct gpio panda_hdmi_gpios[] = { 439static struct gpio panda_hdmi_gpios[] = {
465 { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, 440 { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" },
466 { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, 441 { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
@@ -509,13 +484,8 @@ static struct omap_dss_board_info omap4_panda_dss_data = {
509 .default_device = &omap4_panda_dvi_device, 484 .default_device = &omap4_panda_dvi_device,
510}; 485};
511 486
512void __init omap4_panda_display_init(void) 487static void __init omap4_panda_display_init(void)
513{ 488{
514 int r;
515
516 r = omap4_panda_dvi_init();
517 if (r)
518 pr_err("error initializing panda DVI\n");
519 489
520 omap_display_init(&omap4_panda_dss_data); 490 omap_display_init(&omap4_panda_dss_data);
521 491
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 33aa3910b09..5527c1979a1 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -46,7 +46,7 @@
46#include "common.h" 46#include "common.h"
47#include <video/omapdss.h> 47#include <video/omapdss.h>
48#include <video/omap-panel-generic-dpi.h> 48#include <video/omap-panel-generic-dpi.h>
49#include <video/omap-panel-dvi.h> 49#include <video/omap-panel-tfp410.h>
50#include <plat/gpmc.h> 50#include <plat/gpmc.h>
51#include <mach/hardware.h> 51#include <mach/hardware.h>
52#include <plat/nand.h> 52#include <plat/nand.h>
@@ -167,32 +167,15 @@ static void __init overo_display_init(void)
167 gpio_export(OVERO_GPIO_LCD_BL, 0); 167 gpio_export(OVERO_GPIO_LCD_BL, 0);
168} 168}
169 169
170static int overo_panel_enable_dvi(struct omap_dss_device *dssdev) 170static struct tfp410_platform_data dvi_panel = {
171{
172 if (lcd_enabled) {
173 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
174 return -EINVAL;
175 }
176 dvi_enabled = 1;
177
178 return 0;
179}
180
181static void overo_panel_disable_dvi(struct omap_dss_device *dssdev)
182{
183 dvi_enabled = 0;
184}
185
186static struct panel_dvi_platform_data dvi_panel = {
187 .platform_enable = overo_panel_enable_dvi,
188 .platform_disable = overo_panel_disable_dvi,
189 .i2c_bus_num = 3, 171 .i2c_bus_num = 3,
172 .power_down_gpio = -1,
190}; 173};
191 174
192static struct omap_dss_device overo_dvi_device = { 175static struct omap_dss_device overo_dvi_device = {
193 .name = "dvi", 176 .name = "dvi",
194 .type = OMAP_DISPLAY_TYPE_DPI, 177 .type = OMAP_DISPLAY_TYPE_DPI,
195 .driver_name = "dvi", 178 .driver_name = "tfp410",
196 .data = &dvi_panel, 179 .data = &dvi_panel,
197 .phy.dpi.data_lines = 24, 180 .phy.dpi.data_lines = 24,
198}; 181};
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index d87ee061209..ae957c92081 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -872,11 +872,11 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
872 .resource_config = twl4030_rconfig, 872 .resource_config = twl4030_rconfig,
873}; 873};
874 874
875struct twl4030_vibra_data rx51_vibra_data __initdata = { 875static struct twl4030_vibra_data rx51_vibra_data __initdata = {
876 .coexist = 0, 876 .coexist = 0,
877}; 877};
878 878
879struct twl4030_audio_data rx51_audio_data __initdata = { 879static struct twl4030_audio_data rx51_audio_data __initdata = {
880 .audio_mclk = 26000000, 880 .audio_mclk = 26000000,
881 .vibra = &rx51_vibra_data, 881 .vibra = &rx51_vibra_data,
882}; 882};
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 27f01f051df..2da92a6ba40 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -59,25 +59,24 @@ static struct platform_device leds_gpio = {
59}; 59};
60 60
61/* 61/*
62 * cpuidle C-states definition override from the default values. 62 * cpuidle C-states definition for rx51.
63 * The 'exit_latency' field is the sum of sleep and wake-up latencies. 63 *
64 */ 64 * The 'exit_latency' field is the sum of sleep
65static struct cpuidle_params rx51_cpuidle_params[] = { 65 * and wake-up latencies.
66 /* C1 */ 66
67 {110 + 162, 5 , 1}, 67 ---------------------------------------------
68 /* C2 */ 68 | state | exit_latency | target_residency |
69 {106 + 180, 309, 1}, 69 ---------------------------------------------
70 /* C3 */ 70 | C1 | 110 + 162 | 5 |
71 {107 + 410, 46057, 0}, 71 | C2 | 106 + 180 | 309 |
72 /* C4 */ 72 | C3 | 107 + 410 | 46057 |
73 {121 + 3374, 46057, 0}, 73 | C4 | 121 + 3374 | 46057 |
74 /* C5 */ 74 | C5 | 855 + 1146 | 46057 |
75 {855 + 1146, 46057, 1}, 75 | C6 | 7580 + 4134 | 484329 |
76 /* C6 */ 76 | C7 | 7505 + 15274 | 484329 |
77 {7580 + 4134, 484329, 0}, 77 ---------------------------------------------
78 /* C7 */ 78
79 {7505 + 15274, 484329, 1}, 79*/
80};
81 80
82extern void __init rx51_peripherals_init(void); 81extern void __init rx51_peripherals_init(void);
83 82
@@ -98,7 +97,6 @@ static void __init rx51_init(void)
98 struct omap_sdrc_params *sdrc_params; 97 struct omap_sdrc_params *sdrc_params;
99 98
100 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 99 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
101 omap3_pm_init_cpuidle(rx51_cpuidle_params);
102 omap_serial_init(); 100 omap_serial_init();
103 101
104 sdrc_params = nokia_get_sdram_timings(); 102 sdrc_params = nokia_get_sdram_timings();
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index a43a765dd09..28187f134ff 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -16,6 +16,7 @@
16#include <linux/spi/spi.h> 16#include <linux/spi/spi.h>
17#include <plat/mcspi.h> 17#include <plat/mcspi.h>
18#include <video/omapdss.h> 18#include <video/omapdss.h>
19#include <mach/board-zoom.h>
19 20
20#define LCD_PANEL_RESET_GPIO_PROD 96 21#define LCD_PANEL_RESET_GPIO_PROD 96
21#define LCD_PANEL_RESET_GPIO_PILOT 55 22#define LCD_PANEL_RESET_GPIO_PILOT 55
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 57da7f406e2..0e95efccd2d 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -134,8 +134,6 @@ void omap4_map_io(void);
134void ti81xx_map_io(void); 134void ti81xx_map_io(void);
135void omap_barriers_init(void); 135void omap_barriers_init(void);
136 136
137extern void __init omap_init_consistent_dma_size(void);
138
139/** 137/**
140 * omap_test_timeout - busy-loop, testing a condition 138 * omap_test_timeout - busy-loop, testing a condition
141 * @cond: condition to test until it evaluates to true 139 * @cond: condition to test until it evaluates to true
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 535866489ce..207bc1c7759 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -38,40 +38,44 @@
38 38
39#ifdef CONFIG_CPU_IDLE 39#ifdef CONFIG_CPU_IDLE
40 40
41/*
42 * The latencies/thresholds for various C states have
43 * to be configured from the respective board files.
44 * These are some default values (which might not provide
45 * the best power savings) used on boards which do not
46 * pass these details from the board file.
47 */
48static struct cpuidle_params cpuidle_params_table[] = {
49 /* C1 */
50 {2 + 2, 5, 1},
51 /* C2 */
52 {10 + 10, 30, 1},
53 /* C3 */
54 {50 + 50, 300, 1},
55 /* C4 */
56 {1500 + 1800, 4000, 1},
57 /* C5 */
58 {2500 + 7500, 12000, 1},
59 /* C6 */
60 {3000 + 8500, 15000, 1},
61 /* C7 */
62 {10000 + 30000, 300000, 1},
63};
64#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
65
66/* Mach specific information to be recorded in the C-state driver_data */ 41/* Mach specific information to be recorded in the C-state driver_data */
67struct omap3_idle_statedata { 42struct omap3_idle_statedata {
68 u32 mpu_state; 43 u32 mpu_state;
69 u32 core_state; 44 u32 core_state;
70 u8 valid;
71}; 45};
72struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
73 46
74struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; 47static struct omap3_idle_statedata omap3_idle_data[] = {
48 {
49 .mpu_state = PWRDM_POWER_ON,
50 .core_state = PWRDM_POWER_ON,
51 },
52 {
53 .mpu_state = PWRDM_POWER_ON,
54 .core_state = PWRDM_POWER_ON,
55 },
56 {
57 .mpu_state = PWRDM_POWER_RET,
58 .core_state = PWRDM_POWER_ON,
59 },
60 {
61 .mpu_state = PWRDM_POWER_OFF,
62 .core_state = PWRDM_POWER_ON,
63 },
64 {
65 .mpu_state = PWRDM_POWER_RET,
66 .core_state = PWRDM_POWER_RET,
67 },
68 {
69 .mpu_state = PWRDM_POWER_OFF,
70 .core_state = PWRDM_POWER_RET,
71 },
72 {
73 .mpu_state = PWRDM_POWER_OFF,
74 .core_state = PWRDM_POWER_OFF,
75 },
76};
77
78static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
75 79
76static int _cpuidle_allow_idle(struct powerdomain *pwrdm, 80static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
77 struct clockdomain *clkdm) 81 struct clockdomain *clkdm)
@@ -91,8 +95,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
91 struct cpuidle_driver *drv, 95 struct cpuidle_driver *drv,
92 int index) 96 int index)
93{ 97{
94 struct omap3_idle_statedata *cx = 98 struct omap3_idle_statedata *cx = &omap3_idle_data[index];
95 cpuidle_get_statedata(&dev->states_usage[index]);
96 u32 mpu_state = cx->mpu_state, core_state = cx->core_state; 99 u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
97 100
98 local_fiq_disable(); 101 local_fiq_disable();
@@ -169,14 +172,12 @@ static inline int omap3_enter_idle(struct cpuidle_device *dev,
169 * if it satisfies the enable_off_mode condition. 172 * if it satisfies the enable_off_mode condition.
170 */ 173 */
171static int next_valid_state(struct cpuidle_device *dev, 174static int next_valid_state(struct cpuidle_device *dev,
172 struct cpuidle_driver *drv, 175 struct cpuidle_driver *drv, int index)
173 int index)
174{ 176{
175 struct cpuidle_state_usage *curr_usage = &dev->states_usage[index]; 177 struct omap3_idle_statedata *cx = &omap3_idle_data[index];
176 struct cpuidle_state *curr = &drv->states[index];
177 struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
178 u32 mpu_deepest_state = PWRDM_POWER_RET; 178 u32 mpu_deepest_state = PWRDM_POWER_RET;
179 u32 core_deepest_state = PWRDM_POWER_RET; 179 u32 core_deepest_state = PWRDM_POWER_RET;
180 int idx;
180 int next_index = -1; 181 int next_index = -1;
181 182
182 if (enable_off_mode) { 183 if (enable_off_mode) {
@@ -191,45 +192,29 @@ static int next_valid_state(struct cpuidle_device *dev,
191 } 192 }
192 193
193 /* Check if current state is valid */ 194 /* Check if current state is valid */
194 if ((cx->valid) && 195 if ((cx->mpu_state >= mpu_deepest_state) &&
195 (cx->mpu_state >= mpu_deepest_state) && 196 (cx->core_state >= core_deepest_state))
196 (cx->core_state >= core_deepest_state)) {
197 return index; 197 return index;
198 } else {
199 int idx = OMAP3_NUM_STATES - 1;
200
201 /* Reach the current state starting at highest C-state */
202 for (; idx >= 0; idx--) {
203 if (&drv->states[idx] == curr) {
204 next_index = idx;
205 break;
206 }
207 }
208
209 /* Should never hit this condition */
210 WARN_ON(next_index == -1);
211 198
212 /* 199 /*
213 * Drop to next valid state. 200 * Drop to next valid state.
214 * Start search from the next (lower) state. 201 * Start search from the next (lower) state.
215 */ 202 */
216 idx--; 203 for (idx = index - 1; idx >= 0; idx--) {
217 for (; idx >= 0; idx--) { 204 cx = &omap3_idle_data[idx];
218 cx = cpuidle_get_statedata(&dev->states_usage[idx]); 205 if ((cx->mpu_state >= mpu_deepest_state) &&
219 if ((cx->valid) && 206 (cx->core_state >= core_deepest_state)) {
220 (cx->mpu_state >= mpu_deepest_state) && 207 next_index = idx;
221 (cx->core_state >= core_deepest_state)) { 208 break;
222 next_index = idx;
223 break;
224 }
225 } 209 }
226 /*
227 * C1 is always valid.
228 * So, no need to check for 'next_index == -1' outside
229 * this loop.
230 */
231 } 210 }
232 211
212 /*
213 * C1 is always valid.
214 * So, no need to check for 'next_index == -1' outside
215 * this loop.
216 */
217
233 return next_index; 218 return next_index;
234} 219}
235 220
@@ -273,7 +258,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
273 * Prevent PER off if CORE is not in retention or off as this 258 * Prevent PER off if CORE is not in retention or off as this
274 * would disable PER wakeups completely. 259 * would disable PER wakeups completely.
275 */ 260 */
276 cx = cpuidle_get_statedata(&dev->states_usage[index]); 261 cx = &omap3_idle_data[index];
277 core_next_state = cx->core_state; 262 core_next_state = cx->core_state;
278 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); 263 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
279 if ((per_next_state == PWRDM_POWER_OFF) && 264 if ((per_next_state == PWRDM_POWER_OFF) &&
@@ -298,57 +283,71 @@ select_state:
298 283
299DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); 284DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
300 285
301void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
302{
303 int i;
304
305 if (!cpuidle_board_params)
306 return;
307
308 for (i = 0; i < OMAP3_NUM_STATES; i++) {
309 cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
310 cpuidle_params_table[i].exit_latency =
311 cpuidle_board_params[i].exit_latency;
312 cpuidle_params_table[i].target_residency =
313 cpuidle_board_params[i].target_residency;
314 }
315 return;
316}
317
318struct cpuidle_driver omap3_idle_driver = { 286struct cpuidle_driver omap3_idle_driver = {
319 .name = "omap3_idle", 287 .name = "omap3_idle",
320 .owner = THIS_MODULE, 288 .owner = THIS_MODULE,
289 .states = {
290 {
291 .enter = omap3_enter_idle,
292 .exit_latency = 2 + 2,
293 .target_residency = 5,
294 .flags = CPUIDLE_FLAG_TIME_VALID,
295 .name = "C1",
296 .desc = "MPU ON + CORE ON",
297 },
298 {
299 .enter = omap3_enter_idle_bm,
300 .exit_latency = 10 + 10,
301 .target_residency = 30,
302 .flags = CPUIDLE_FLAG_TIME_VALID,
303 .name = "C2",
304 .desc = "MPU ON + CORE ON",
305 },
306 {
307 .enter = omap3_enter_idle_bm,
308 .exit_latency = 50 + 50,
309 .target_residency = 300,
310 .flags = CPUIDLE_FLAG_TIME_VALID,
311 .name = "C3",
312 .desc = "MPU RET + CORE ON",
313 },
314 {
315 .enter = omap3_enter_idle_bm,
316 .exit_latency = 1500 + 1800,
317 .target_residency = 4000,
318 .flags = CPUIDLE_FLAG_TIME_VALID,
319 .name = "C4",
320 .desc = "MPU OFF + CORE ON",
321 },
322 {
323 .enter = omap3_enter_idle_bm,
324 .exit_latency = 2500 + 7500,
325 .target_residency = 12000,
326 .flags = CPUIDLE_FLAG_TIME_VALID,
327 .name = "C5",
328 .desc = "MPU RET + CORE RET",
329 },
330 {
331 .enter = omap3_enter_idle_bm,
332 .exit_latency = 3000 + 8500,
333 .target_residency = 15000,
334 .flags = CPUIDLE_FLAG_TIME_VALID,
335 .name = "C6",
336 .desc = "MPU OFF + CORE RET",
337 },
338 {
339 .enter = omap3_enter_idle_bm,
340 .exit_latency = 10000 + 30000,
341 .target_residency = 30000,
342 .flags = CPUIDLE_FLAG_TIME_VALID,
343 .name = "C7",
344 .desc = "MPU OFF + CORE OFF",
345 },
346 },
347 .state_count = ARRAY_SIZE(omap3_idle_data),
348 .safe_state_index = 0,
321}; 349};
322 350
323/* Helper to fill the C-state common data*/
324static inline void _fill_cstate(struct cpuidle_driver *drv,
325 int idx, const char *descr)
326{
327 struct cpuidle_state *state = &drv->states[idx];
328
329 state->exit_latency = cpuidle_params_table[idx].exit_latency;
330 state->target_residency = cpuidle_params_table[idx].target_residency;
331 state->flags = CPUIDLE_FLAG_TIME_VALID;
332 state->enter = omap3_enter_idle_bm;
333 sprintf(state->name, "C%d", idx + 1);
334 strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
335
336}
337
338/* Helper to register the driver_data */
339static inline struct omap3_idle_statedata *_fill_cstate_usage(
340 struct cpuidle_device *dev,
341 int idx)
342{
343 struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
344 struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
345
346 cx->valid = cpuidle_params_table[idx].valid;
347 cpuidle_set_statedata(state_usage, cx);
348
349 return cx;
350}
351
352/** 351/**
353 * omap3_idle_init - Init routine for OMAP3 idle 352 * omap3_idle_init - Init routine for OMAP3 idle
354 * 353 *
@@ -358,77 +357,20 @@ static inline struct omap3_idle_statedata *_fill_cstate_usage(
358int __init omap3_idle_init(void) 357int __init omap3_idle_init(void)
359{ 358{
360 struct cpuidle_device *dev; 359 struct cpuidle_device *dev;
361 struct cpuidle_driver *drv = &omap3_idle_driver;
362 struct omap3_idle_statedata *cx;
363 360
364 mpu_pd = pwrdm_lookup("mpu_pwrdm"); 361 mpu_pd = pwrdm_lookup("mpu_pwrdm");
365 core_pd = pwrdm_lookup("core_pwrdm"); 362 core_pd = pwrdm_lookup("core_pwrdm");
366 per_pd = pwrdm_lookup("per_pwrdm"); 363 per_pd = pwrdm_lookup("per_pwrdm");
367 cam_pd = pwrdm_lookup("cam_pwrdm"); 364 cam_pd = pwrdm_lookup("cam_pwrdm");
368 365
366 if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
367 return -ENODEV;
369 368
370 drv->safe_state_index = -1;
371 dev = &per_cpu(omap3_idle_dev, smp_processor_id());
372
373 /* C1 . MPU WFI + Core active */
374 _fill_cstate(drv, 0, "MPU ON + CORE ON");
375 (&drv->states[0])->enter = omap3_enter_idle;
376 drv->safe_state_index = 0;
377 cx = _fill_cstate_usage(dev, 0);
378 cx->valid = 1; /* C1 is always valid */
379 cx->mpu_state = PWRDM_POWER_ON;
380 cx->core_state = PWRDM_POWER_ON;
381
382 /* C2 . MPU WFI + Core inactive */
383 _fill_cstate(drv, 1, "MPU ON + CORE ON");
384 cx = _fill_cstate_usage(dev, 1);
385 cx->mpu_state = PWRDM_POWER_ON;
386 cx->core_state = PWRDM_POWER_ON;
387
388 /* C3 . MPU CSWR + Core inactive */
389 _fill_cstate(drv, 2, "MPU RET + CORE ON");
390 cx = _fill_cstate_usage(dev, 2);
391 cx->mpu_state = PWRDM_POWER_RET;
392 cx->core_state = PWRDM_POWER_ON;
393
394 /* C4 . MPU OFF + Core inactive */
395 _fill_cstate(drv, 3, "MPU OFF + CORE ON");
396 cx = _fill_cstate_usage(dev, 3);
397 cx->mpu_state = PWRDM_POWER_OFF;
398 cx->core_state = PWRDM_POWER_ON;
399
400 /* C5 . MPU RET + Core RET */
401 _fill_cstate(drv, 4, "MPU RET + CORE RET");
402 cx = _fill_cstate_usage(dev, 4);
403 cx->mpu_state = PWRDM_POWER_RET;
404 cx->core_state = PWRDM_POWER_RET;
405
406 /* C6 . MPU OFF + Core RET */
407 _fill_cstate(drv, 5, "MPU OFF + CORE RET");
408 cx = _fill_cstate_usage(dev, 5);
409 cx->mpu_state = PWRDM_POWER_OFF;
410 cx->core_state = PWRDM_POWER_RET;
411
412 /* C7 . MPU OFF + Core OFF */
413 _fill_cstate(drv, 6, "MPU OFF + CORE OFF");
414 cx = _fill_cstate_usage(dev, 6);
415 /*
416 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
417 * enable OFF mode in a stable form for previous revisions.
418 * We disable C7 state as a result.
419 */
420 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
421 cx->valid = 0;
422 pr_warn("%s: core off state C7 disabled due to i583\n",
423 __func__);
424 }
425 cx->mpu_state = PWRDM_POWER_OFF;
426 cx->core_state = PWRDM_POWER_OFF;
427
428 drv->state_count = OMAP3_NUM_STATES;
429 cpuidle_register_driver(&omap3_idle_driver); 369 cpuidle_register_driver(&omap3_idle_driver);
430 370
431 dev->state_count = OMAP3_NUM_STATES; 371 dev = &per_cpu(omap3_idle_dev, smp_processor_id());
372 dev->cpu = 0;
373
432 if (cpuidle_register_device(dev)) { 374 if (cpuidle_register_device(dev)) {
433 printk(KERN_ERR "%s: CPUidle register device failed\n", 375 printk(KERN_ERR "%s: CPUidle register device failed\n",
434 __func__); 376 __func__);
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index f386cbe9c88..be1617ca84b 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -24,26 +24,31 @@
24 24
25#ifdef CONFIG_CPU_IDLE 25#ifdef CONFIG_CPU_IDLE
26 26
27/* Machine specific information to be recorded in the C-state driver_data */ 27/* Machine specific information */
28struct omap4_idle_statedata { 28struct omap4_idle_statedata {
29 u32 cpu_state; 29 u32 cpu_state;
30 u32 mpu_logic_state; 30 u32 mpu_logic_state;
31 u32 mpu_state; 31 u32 mpu_state;
32 u8 valid;
33}; 32};
34 33
35static struct cpuidle_params cpuidle_params_table[] = { 34static struct omap4_idle_statedata omap4_idle_data[] = {
36 /* C1 - CPU0 ON + CPU1 ON + MPU ON */ 35 {
37 {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1}, 36 .cpu_state = PWRDM_POWER_ON,
38 /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */ 37 .mpu_state = PWRDM_POWER_ON,
39 {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1}, 38 .mpu_logic_state = PWRDM_POWER_RET,
40 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ 39 },
41 {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1}, 40 {
41 .cpu_state = PWRDM_POWER_OFF,
42 .mpu_state = PWRDM_POWER_RET,
43 .mpu_logic_state = PWRDM_POWER_RET,
44 },
45 {
46 .cpu_state = PWRDM_POWER_OFF,
47 .mpu_state = PWRDM_POWER_RET,
48 .mpu_logic_state = PWRDM_POWER_OFF,
49 },
42}; 50};
43 51
44#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
45
46struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
47static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd; 52static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
48 53
49/** 54/**
@@ -60,8 +65,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
60 struct cpuidle_driver *drv, 65 struct cpuidle_driver *drv,
61 int index) 66 int index)
62{ 67{
63 struct omap4_idle_statedata *cx = 68 struct omap4_idle_statedata *cx = &omap4_idle_data[index];
64 cpuidle_get_statedata(&dev->states_usage[index]);
65 u32 cpu1_state; 69 u32 cpu1_state;
66 int cpu_id = smp_processor_id(); 70 int cpu_id = smp_processor_id();
67 71
@@ -78,7 +82,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
78 cpu1_state = pwrdm_read_pwrst(cpu1_pd); 82 cpu1_state = pwrdm_read_pwrst(cpu1_pd);
79 if (cpu1_state != PWRDM_POWER_OFF) { 83 if (cpu1_state != PWRDM_POWER_OFF) {
80 index = drv->safe_state_index; 84 index = drv->safe_state_index;
81 cx = cpuidle_get_statedata(&dev->states_usage[index]); 85 cx = &omap4_idle_data[index];
82 } 86 }
83 87
84 if (index > 0) 88 if (index > 0)
@@ -133,36 +137,39 @@ struct cpuidle_driver omap4_idle_driver = {
133 .name = "omap4_idle", 137 .name = "omap4_idle",
134 .owner = THIS_MODULE, 138 .owner = THIS_MODULE,
135 .en_core_tk_irqen = 1, 139 .en_core_tk_irqen = 1,
140 .states = {
141 {
142 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
143 .exit_latency = 2 + 2,
144 .target_residency = 5,
145 .flags = CPUIDLE_FLAG_TIME_VALID,
146 .enter = omap4_enter_idle,
147 .name = "C1",
148 .desc = "MPUSS ON"
149 },
150 {
151 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
152 .exit_latency = 328 + 440,
153 .target_residency = 960,
154 .flags = CPUIDLE_FLAG_TIME_VALID,
155 .enter = omap4_enter_idle,
156 .name = "C2",
157 .desc = "MPUSS CSWR",
158 },
159 {
160 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
161 .exit_latency = 460 + 518,
162 .target_residency = 1100,
163 .flags = CPUIDLE_FLAG_TIME_VALID,
164 .enter = omap4_enter_idle,
165 .name = "C3",
166 .desc = "MPUSS OSWR",
167 },
168 },
169 .state_count = ARRAY_SIZE(omap4_idle_data),
170 .safe_state_index = 0,
136}; 171};
137 172
138static inline void _fill_cstate(struct cpuidle_driver *drv,
139 int idx, const char *descr)
140{
141 struct cpuidle_state *state = &drv->states[idx];
142
143 state->exit_latency = cpuidle_params_table[idx].exit_latency;
144 state->target_residency = cpuidle_params_table[idx].target_residency;
145 state->flags = CPUIDLE_FLAG_TIME_VALID;
146 state->enter = omap4_enter_idle;
147 sprintf(state->name, "C%d", idx + 1);
148 strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
149}
150
151static inline struct omap4_idle_statedata *_fill_cstate_usage(
152 struct cpuidle_device *dev,
153 int idx)
154{
155 struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
156 struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
157
158 cx->valid = cpuidle_params_table[idx].valid;
159 cpuidle_set_statedata(state_usage, cx);
160
161 return cx;
162}
163
164
165
166/** 173/**
167 * omap4_idle_init - Init routine for OMAP4 idle 174 * omap4_idle_init - Init routine for OMAP4 idle
168 * 175 *
@@ -171,9 +178,7 @@ static inline struct omap4_idle_statedata *_fill_cstate_usage(
171 */ 178 */
172int __init omap4_idle_init(void) 179int __init omap4_idle_init(void)
173{ 180{
174 struct omap4_idle_statedata *cx;
175 struct cpuidle_device *dev; 181 struct cpuidle_device *dev;
176 struct cpuidle_driver *drv = &omap4_idle_driver;
177 unsigned int cpu_id = 0; 182 unsigned int cpu_id = 0;
178 183
179 mpu_pd = pwrdm_lookup("mpu_pwrdm"); 184 mpu_pd = pwrdm_lookup("mpu_pwrdm");
@@ -182,42 +187,15 @@ int __init omap4_idle_init(void)
182 if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd)) 187 if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
183 return -ENODEV; 188 return -ENODEV;
184 189
185
186 drv->safe_state_index = -1;
187 dev = &per_cpu(omap4_idle_dev, cpu_id); 190 dev = &per_cpu(omap4_idle_dev, cpu_id);
188 dev->cpu = cpu_id; 191 dev->cpu = cpu_id;
189 192
190 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
191 _fill_cstate(drv, 0, "MPUSS ON");
192 drv->safe_state_index = 0;
193 cx = _fill_cstate_usage(dev, 0);
194 cx->valid = 1; /* C1 is always valid */
195 cx->cpu_state = PWRDM_POWER_ON;
196 cx->mpu_state = PWRDM_POWER_ON;
197 cx->mpu_logic_state = PWRDM_POWER_RET;
198
199 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
200 _fill_cstate(drv, 1, "MPUSS CSWR");
201 cx = _fill_cstate_usage(dev, 1);
202 cx->cpu_state = PWRDM_POWER_OFF;
203 cx->mpu_state = PWRDM_POWER_RET;
204 cx->mpu_logic_state = PWRDM_POWER_RET;
205
206 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
207 _fill_cstate(drv, 2, "MPUSS OSWR");
208 cx = _fill_cstate_usage(dev, 2);
209 cx->cpu_state = PWRDM_POWER_OFF;
210 cx->mpu_state = PWRDM_POWER_RET;
211 cx->mpu_logic_state = PWRDM_POWER_OFF;
212
213 drv->state_count = OMAP4_NUM_STATES;
214 cpuidle_register_driver(&omap4_idle_driver); 193 cpuidle_register_driver(&omap4_idle_driver);
215 194
216 dev->state_count = OMAP4_NUM_STATES;
217 if (cpuidle_register_device(dev)) { 195 if (cpuidle_register_device(dev)) {
218 pr_err("%s: CPUidle register device failed\n", __func__); 196 pr_err("%s: CPUidle register device failed\n", __func__);
219 return -EIO; 197 return -EIO;
220 } 198 }
221 199
222 return 0; 200 return 0;
223} 201}
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index e4336035c0e..f3953a49928 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -42,7 +42,6 @@
42 42
43static int __init omap3_l3_init(void) 43static int __init omap3_l3_init(void)
44{ 44{
45 int l;
46 struct omap_hwmod *oh; 45 struct omap_hwmod *oh;
47 struct platform_device *pdev; 46 struct platform_device *pdev;
48 char oh_name[L3_MODULES_MAX_LEN]; 47 char oh_name[L3_MODULES_MAX_LEN];
@@ -54,7 +53,7 @@ static int __init omap3_l3_init(void)
54 if (!(cpu_is_omap34xx())) 53 if (!(cpu_is_omap34xx()))
55 return -ENODEV; 54 return -ENODEV;
56 55
57 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); 56 snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
58 57
59 oh = omap_hwmod_lookup(oh_name); 58 oh = omap_hwmod_lookup(oh_name);
60 59
@@ -72,7 +71,7 @@ postcore_initcall(omap3_l3_init);
72 71
73static int __init omap4_l3_init(void) 72static int __init omap4_l3_init(void)
74{ 73{
75 int l, i; 74 int i;
76 struct omap_hwmod *oh[3]; 75 struct omap_hwmod *oh[3];
77 struct platform_device *pdev; 76 struct platform_device *pdev;
78 char oh_name[L3_MODULES_MAX_LEN]; 77 char oh_name[L3_MODULES_MAX_LEN];
@@ -89,7 +88,7 @@ static int __init omap4_l3_init(void)
89 return -ENODEV; 88 return -ENODEV;
90 89
91 for (i = 0; i < L3_MODULES; i++) { 90 for (i = 0; i < L3_MODULES; i++) {
92 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1); 91 snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
93 92
94 oh[i] = omap_hwmod_lookup(oh_name); 93 oh[i] = omap_hwmod_lookup(oh_name);
95 if (!(oh[i])) 94 if (!(oh[i]))
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 2f994e5194e..064cab03d2b 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -58,7 +58,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
58 pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1); 58 pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
59 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 59 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
60 pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL); 60 pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
61 if (!pdata) { 61 if (!pdata->regs) {
62 pr_err("gpio%d: Memory allocation failed\n", id); 62 pr_err("gpio%d: Memory allocation failed\n", id);
63 return -ENOMEM; 63 return -ENOMEM;
64 } 64 }
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 385b3e02c4a..a0fa9bb2bda 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -176,7 +176,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
176 const int t_wpl = 40; 176 const int t_wpl = 40;
177 const int t_wph = 30; 177 const int t_wph = 30;
178 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; 178 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
179 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; 179 int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
180 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; 180 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
181 int err, ticks_cez; 181 int err, ticks_cez;
182 int cs = cfg->cs, freq = *freq_ptr; 182 int cs = cfg->cs, freq = *freq_ptr;
@@ -240,7 +240,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
240 break; 240 break;
241 } 241 }
242 242
243 tick_ns = gpmc_ticks_to_ns(1);
244 div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period); 243 div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
245 gpmc_clk_ns = gpmc_ticks_to_ns(div); 244 gpmc_clk_ns = gpmc_ticks_to_ns(div);
246 if (gpmc_clk_ns < 15) /* >66Mhz */ 245 if (gpmc_clk_ns < 15) /* >66Mhz */
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 00d510858e2..580e684e882 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -755,8 +755,7 @@ static int __init gpmc_init(void)
755 irq++; 755 irq++;
756 } 756 }
757 757
758 ret = request_irq(gpmc_irq, 758 ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
759 gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
760 if (ret) 759 if (ret)
761 pr_err("gpmc: irq-%d could not claim: err %d\n", 760 pr_err("gpmc: irq-%d could not claim: err %d\n",
762 gpmc_irq, ret); 761 gpmc_irq, ret);
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 454dfce125c..8763c8520dc 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -28,7 +28,7 @@ static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = {
28 .base_id = 0, 28 .base_id = 0,
29}; 29};
30 30
31int __init hwspinlocks_init(void) 31static int __init hwspinlocks_init(void)
32{ 32{
33 int retval = 0; 33 int retval = 0;
34 struct omap_hwmod *oh; 34 struct omap_hwmod *oh;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 065bd768987..2d5a57669a7 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -31,6 +31,7 @@
31#include <plat/omap-pm.h> 31#include <plat/omap-pm.h>
32#include <plat/omap_hwmod.h> 32#include <plat/omap_hwmod.h>
33#include <plat/multi.h> 33#include <plat/multi.h>
34#include <plat/dma.h>
34 35
35#include "iomap.h" 36#include "iomap.h"
36#include "voltage.h" 37#include "voltage.h"
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 65f0d2571c9..80f3ced0bd1 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -25,6 +25,7 @@
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26 26
27#include "iomap.h" 27#include "iomap.h"
28#include "common.h"
28 29
29/* selected INTC register offsets */ 30/* selected INTC register offsets */
30 31
@@ -334,7 +335,7 @@ void omap_intc_restore_context(void)
334void omap3_intc_suspend(void) 335void omap3_intc_suspend(void)
335{ 336{
336 /* A pending interrupt would prevent OMAP from entering suspend */ 337 /* A pending interrupt would prevent OMAP from entering suspend */
337 omap_ack_irq(0); 338 omap_ack_irq(NULL);
338} 339}
339 340
340void omap3_intc_prepare_idle(void) 341void omap3_intc_prepare_idle(void)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 65c33911341..3268ee24ead 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -247,7 +247,7 @@ int __init omap_mux_init_signal(const char *muxname, int val)
247 int mux_mode; 247 int mux_mode;
248 248
249 mux_mode = omap_mux_get_by_name(muxname, &partition, &mux); 249 mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
250 if (mux_mode < 0) 250 if (mux_mode < 0 || !mux)
251 return mux_mode; 251 return mux_mode;
252 252
253 old_mode = omap_mux_read(partition, mux->reg_offset); 253 old_mode = omap_mux_read(partition, mux->reg_offset);
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index d8f8ef40290..d9ae4a53d81 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -18,6 +18,7 @@
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/memblock.h> 19#include <asm/memblock.h>
20 20
21#include <plat/omap-secure.h>
21#include <mach/omap-secure.h> 22#include <mach/omap-secure.h>
22 23
23static phys_addr_t omap_secure_memblock_base; 24static phys_addr_t omap_secure_memblock_base;
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 42cd7fb5241..d811c779035 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -259,7 +259,7 @@ static void irq_save_context(void)
259/* 259/*
260 * Clear WakeupGen SAR backup status. 260 * Clear WakeupGen SAR backup status.
261 */ 261 */
262void irq_sar_clear(void) 262static void irq_sar_clear(void)
263{ 263{
264 u32 val; 264 u32 val;
265 val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET); 265 val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7144ae651d3..bf86f7e8f91 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2,7 +2,7 @@
2 * omap_hwmod implementation for OMAP2/3/4 2 * omap_hwmod implementation for OMAP2/3/4
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2011 Texas Instruments, Inc. 5 * Copyright (C) 2011-2012 Texas Instruments, Inc.
6 * 6 *
7 * Paul Walmsley, Benoît Cousson, Kevin Hilman 7 * Paul Walmsley, Benoît Cousson, Kevin Hilman
8 * 8 *
@@ -137,6 +137,7 @@
137#include <linux/mutex.h> 137#include <linux/mutex.h>
138#include <linux/spinlock.h> 138#include <linux/spinlock.h>
139#include <linux/slab.h> 139#include <linux/slab.h>
140#include <linux/bootmem.h>
140 141
141#include "common.h" 142#include "common.h"
142#include <plat/cpu.h> 143#include <plat/cpu.h>
@@ -159,16 +160,58 @@
159/* Name of the OMAP hwmod for the MPU */ 160/* Name of the OMAP hwmod for the MPU */
160#define MPU_INITIATOR_NAME "mpu" 161#define MPU_INITIATOR_NAME "mpu"
161 162
163/*
164 * Number of struct omap_hwmod_link records per struct
165 * omap_hwmod_ocp_if record (master->slave and slave->master)
166 */
167#define LINKS_PER_OCP_IF 2
168
162/* omap_hwmod_list contains all registered struct omap_hwmods */ 169/* omap_hwmod_list contains all registered struct omap_hwmods */
163static LIST_HEAD(omap_hwmod_list); 170static LIST_HEAD(omap_hwmod_list);
164 171
165/* mpu_oh: used to add/remove MPU initiator from sleepdep list */ 172/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
166static struct omap_hwmod *mpu_oh; 173static struct omap_hwmod *mpu_oh;
167 174
175/*
176 * linkspace: ptr to a buffer that struct omap_hwmod_link records are
177 * allocated from - used to reduce the number of small memory
178 * allocations, which has a significant impact on performance
179 */
180static struct omap_hwmod_link *linkspace;
181
182/*
183 * free_ls, max_ls: array indexes into linkspace; representing the
184 * next free struct omap_hwmod_link index, and the maximum number of
185 * struct omap_hwmod_link records allocated (respectively)
186 */
187static unsigned short free_ls, max_ls, ls_supp;
168 188
169/* Private functions */ 189/* Private functions */
170 190
171/** 191/**
192 * _fetch_next_ocp_if - return the next OCP interface in a list
193 * @p: ptr to a ptr to the list_head inside the ocp_if to return
194 * @i: pointer to the index of the element pointed to by @p in the list
195 *
196 * Return a pointer to the struct omap_hwmod_ocp_if record
197 * containing the struct list_head pointed to by @p, and increment
198 * @p such that a future call to this routine will return the next
199 * record.
200 */
201static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p,
202 int *i)
203{
204 struct omap_hwmod_ocp_if *oi;
205
206 oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if;
207 *p = (*p)->next;
208
209 *i = *i + 1;
210
211 return oi;
212}
213
214/**
172 * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy 215 * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
173 * @oh: struct omap_hwmod * 216 * @oh: struct omap_hwmod *
174 * 217 *
@@ -582,16 +625,16 @@ static int _init_main_clk(struct omap_hwmod *oh)
582 */ 625 */
583static int _init_interface_clks(struct omap_hwmod *oh) 626static int _init_interface_clks(struct omap_hwmod *oh)
584{ 627{
628 struct omap_hwmod_ocp_if *os;
629 struct list_head *p;
585 struct clk *c; 630 struct clk *c;
586 int i; 631 int i = 0;
587 int ret = 0; 632 int ret = 0;
588 633
589 if (oh->slaves_cnt == 0) 634 p = oh->slave_ports.next;
590 return 0;
591
592 for (i = 0; i < oh->slaves_cnt; i++) {
593 struct omap_hwmod_ocp_if *os = oh->slaves[i];
594 635
636 while (i < oh->slaves_cnt) {
637 os = _fetch_next_ocp_if(&p, &i);
595 if (!os->clk) 638 if (!os->clk)
596 continue; 639 continue;
597 640
@@ -643,21 +686,22 @@ static int _init_opt_clks(struct omap_hwmod *oh)
643 */ 686 */
644static int _enable_clocks(struct omap_hwmod *oh) 687static int _enable_clocks(struct omap_hwmod *oh)
645{ 688{
646 int i; 689 struct omap_hwmod_ocp_if *os;
690 struct list_head *p;
691 int i = 0;
647 692
648 pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); 693 pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
649 694
650 if (oh->_clk) 695 if (oh->_clk)
651 clk_enable(oh->_clk); 696 clk_enable(oh->_clk);
652 697
653 if (oh->slaves_cnt > 0) { 698 p = oh->slave_ports.next;
654 for (i = 0; i < oh->slaves_cnt; i++) {
655 struct omap_hwmod_ocp_if *os = oh->slaves[i];
656 struct clk *c = os->_clk;
657 699
658 if (c && (os->flags & OCPIF_SWSUP_IDLE)) 700 while (i < oh->slaves_cnt) {
659 clk_enable(c); 701 os = _fetch_next_ocp_if(&p, &i);
660 } 702
703 if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
704 clk_enable(os->_clk);
661 } 705 }
662 706
663 /* The opt clocks are controlled by the device driver. */ 707 /* The opt clocks are controlled by the device driver. */
@@ -673,21 +717,22 @@ static int _enable_clocks(struct omap_hwmod *oh)
673 */ 717 */
674static int _disable_clocks(struct omap_hwmod *oh) 718static int _disable_clocks(struct omap_hwmod *oh)
675{ 719{
676 int i; 720 struct omap_hwmod_ocp_if *os;
721 struct list_head *p;
722 int i = 0;
677 723
678 pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); 724 pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
679 725
680 if (oh->_clk) 726 if (oh->_clk)
681 clk_disable(oh->_clk); 727 clk_disable(oh->_clk);
682 728
683 if (oh->slaves_cnt > 0) { 729 p = oh->slave_ports.next;
684 for (i = 0; i < oh->slaves_cnt; i++) {
685 struct omap_hwmod_ocp_if *os = oh->slaves[i];
686 struct clk *c = os->_clk;
687 730
688 if (c && (os->flags & OCPIF_SWSUP_IDLE)) 731 while (i < oh->slaves_cnt) {
689 clk_disable(c); 732 os = _fetch_next_ocp_if(&p, &i);
690 } 733
734 if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
735 clk_disable(os->_clk);
691 } 736 }
692 737
693 /* The opt clocks are controlled by the device driver. */ 738 /* The opt clocks are controlled by the device driver. */
@@ -781,39 +826,6 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh)
781} 826}
782 827
783/** 828/**
784 * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
785 * @oh: struct omap_hwmod *
786 *
787 * Disable the PRCM module mode related to the hwmod @oh.
788 * Return EINVAL if the modulemode is not supported and 0 in case of success.
789 */
790static int _omap4_disable_module(struct omap_hwmod *oh)
791{
792 int v;
793
794 /* The module mode does not exist prior OMAP4 */
795 if (!cpu_is_omap44xx())
796 return -EINVAL;
797
798 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
799 return -EINVAL;
800
801 pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
802
803 omap4_cminst_module_disable(oh->clkdm->prcm_partition,
804 oh->clkdm->cm_inst,
805 oh->clkdm->clkdm_offs,
806 oh->prcm.omap4.clkctrl_offs);
807
808 v = _omap4_wait_target_disable(oh);
809 if (v)
810 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
811 oh->name);
812
813 return 0;
814}
815
816/**
817 * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh 829 * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
818 * @oh: struct omap_hwmod *oh 830 * @oh: struct omap_hwmod *oh
819 * 831 *
@@ -883,59 +895,220 @@ static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
883} 895}
884 896
885/** 897/**
886 * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use 898 * _get_mpu_irq_by_name - fetch MPU interrupt line number by name
887 * @oh: struct omap_hwmod * 899 * @oh: struct omap_hwmod * to operate on
900 * @name: pointer to the name of the MPU interrupt number to fetch (optional)
901 * @irq: pointer to an unsigned int to store the MPU IRQ number to
888 * 902 *
889 * Returns the array index of the OCP slave port that the MPU 903 * Retrieve a MPU hardware IRQ line number named by @name associated
890 * addresses the device on, or -EINVAL upon error or not found. 904 * with the IP block pointed to by @oh. The IRQ number will be filled
905 * into the address pointed to by @dma. When @name is non-null, the
906 * IRQ line number associated with the named entry will be returned.
907 * If @name is null, the first matching entry will be returned. Data
908 * order is not meaningful in hwmod data, so callers are strongly
909 * encouraged to use a non-null @name whenever possible to avoid
910 * unpredictable effects if hwmod data is later added that causes data
911 * ordering to change. Returns 0 upon success or a negative error
912 * code upon error.
891 */ 913 */
892static int __init _find_mpu_port_index(struct omap_hwmod *oh) 914static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name,
915 unsigned int *irq)
893{ 916{
894 int i; 917 int i;
895 int found = 0; 918 bool found = false;
896 919
897 if (!oh || oh->slaves_cnt == 0) 920 if (!oh->mpu_irqs)
898 return -EINVAL; 921 return -ENOENT;
899 922
900 for (i = 0; i < oh->slaves_cnt; i++) { 923 i = 0;
901 struct omap_hwmod_ocp_if *os = oh->slaves[i]; 924 while (oh->mpu_irqs[i].irq != -1) {
925 if (name == oh->mpu_irqs[i].name ||
926 !strcmp(name, oh->mpu_irqs[i].name)) {
927 found = true;
928 break;
929 }
930 i++;
931 }
902 932
903 if (os->user & OCP_USER_MPU) { 933 if (!found)
904 found = 1; 934 return -ENOENT;
935
936 *irq = oh->mpu_irqs[i].irq;
937
938 return 0;
939}
940
941/**
942 * _get_sdma_req_by_name - fetch SDMA request line ID by name
943 * @oh: struct omap_hwmod * to operate on
944 * @name: pointer to the name of the SDMA request line to fetch (optional)
945 * @dma: pointer to an unsigned int to store the request line ID to
946 *
947 * Retrieve an SDMA request line ID named by @name on the IP block
948 * pointed to by @oh. The ID will be filled into the address pointed
949 * to by @dma. When @name is non-null, the request line ID associated
950 * with the named entry will be returned. If @name is null, the first
951 * matching entry will be returned. Data order is not meaningful in
952 * hwmod data, so callers are strongly encouraged to use a non-null
953 * @name whenever possible to avoid unpredictable effects if hwmod
954 * data is later added that causes data ordering to change. Returns 0
955 * upon success or a negative error code upon error.
956 */
957static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name,
958 unsigned int *dma)
959{
960 int i;
961 bool found = false;
962
963 if (!oh->sdma_reqs)
964 return -ENOENT;
965
966 i = 0;
967 while (oh->sdma_reqs[i].dma_req != -1) {
968 if (name == oh->sdma_reqs[i].name ||
969 !strcmp(name, oh->sdma_reqs[i].name)) {
970 found = true;
905 break; 971 break;
906 } 972 }
973 i++;
907 } 974 }
908 975
909 if (found) 976 if (!found)
910 pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n", 977 return -ENOENT;
911 oh->name, i); 978
912 else 979 *dma = oh->sdma_reqs[i].dma_req;
913 pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n",
914 oh->name);
915 980
916 return (found) ? i : -EINVAL; 981 return 0;
917} 982}
918 983
919/** 984/**
920 * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU 985 * _get_addr_space_by_name - fetch address space start & end by name
921 * @oh: struct omap_hwmod * 986 * @oh: struct omap_hwmod * to operate on
987 * @name: pointer to the name of the address space to fetch (optional)
988 * @pa_start: pointer to a u32 to store the starting address to
989 * @pa_end: pointer to a u32 to store the ending address to
922 * 990 *
923 * Return the virtual address of the base of the register target of 991 * Retrieve address space start and end addresses for the IP block
924 * device @oh, or NULL on error. 992 * pointed to by @oh. The data will be filled into the addresses
993 * pointed to by @pa_start and @pa_end. When @name is non-null, the
994 * address space data associated with the named entry will be
995 * returned. If @name is null, the first matching entry will be
996 * returned. Data order is not meaningful in hwmod data, so callers
997 * are strongly encouraged to use a non-null @name whenever possible
998 * to avoid unpredictable effects if hwmod data is later added that
999 * causes data ordering to change. Returns 0 upon success or a
1000 * negative error code upon error.
925 */ 1001 */
926static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) 1002static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
1003 u32 *pa_start, u32 *pa_end)
927{ 1004{
1005 int i, j;
928 struct omap_hwmod_ocp_if *os; 1006 struct omap_hwmod_ocp_if *os;
929 struct omap_hwmod_addr_space *mem; 1007 struct list_head *p = NULL;
930 int i = 0, found = 0; 1008 bool found = false;
931 void __iomem *va_start; 1009
1010 p = oh->slave_ports.next;
1011
1012 i = 0;
1013 while (i < oh->slaves_cnt) {
1014 os = _fetch_next_ocp_if(&p, &i);
1015
1016 if (!os->addr)
1017 return -ENOENT;
1018
1019 j = 0;
1020 while (os->addr[j].pa_start != os->addr[j].pa_end) {
1021 if (name == os->addr[j].name ||
1022 !strcmp(name, os->addr[j].name)) {
1023 found = true;
1024 break;
1025 }
1026 j++;
1027 }
1028
1029 if (found)
1030 break;
1031 }
1032
1033 if (!found)
1034 return -ENOENT;
1035
1036 *pa_start = os->addr[j].pa_start;
1037 *pa_end = os->addr[j].pa_end;
1038
1039 return 0;
1040}
1041
1042/**
1043 * _save_mpu_port_index - find and save the index to @oh's MPU port
1044 * @oh: struct omap_hwmod *
1045 *
1046 * Determines the array index of the OCP slave port that the MPU uses
1047 * to address the device, and saves it into the struct omap_hwmod.
1048 * Intended to be called during hwmod registration only. No return
1049 * value.
1050 */
1051static void __init _save_mpu_port_index(struct omap_hwmod *oh)
1052{
1053 struct omap_hwmod_ocp_if *os = NULL;
1054 struct list_head *p;
1055 int i = 0;
1056
1057 if (!oh)
1058 return;
932 1059
933 if (!oh || oh->slaves_cnt == 0) 1060 oh->_int_flags |= _HWMOD_NO_MPU_PORT;
1061
1062 p = oh->slave_ports.next;
1063
1064 while (i < oh->slaves_cnt) {
1065 os = _fetch_next_ocp_if(&p, &i);
1066 if (os->user & OCP_USER_MPU) {
1067 oh->_mpu_port = os;
1068 oh->_int_flags &= ~_HWMOD_NO_MPU_PORT;
1069 break;
1070 }
1071 }
1072
1073 return;
1074}
1075
1076/**
1077 * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU
1078 * @oh: struct omap_hwmod *
1079 *
1080 * Given a pointer to a struct omap_hwmod record @oh, return a pointer
1081 * to the struct omap_hwmod_ocp_if record that is used by the MPU to
1082 * communicate with the IP block. This interface need not be directly
1083 * connected to the MPU (and almost certainly is not), but is directly
1084 * connected to the IP block represented by @oh. Returns a pointer
1085 * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon
1086 * error or if there does not appear to be a path from the MPU to this
1087 * IP block.
1088 */
1089static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh)
1090{
1091 if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
934 return NULL; 1092 return NULL;
935 1093
936 os = oh->slaves[index]; 1094 return oh->_mpu_port;
1095};
1096
1097/**
1098 * _find_mpu_rt_addr_space - return MPU register target address space for @oh
1099 * @oh: struct omap_hwmod *
1100 *
1101 * Returns a pointer to the struct omap_hwmod_addr_space record representing
1102 * the register target MPU address space; or returns NULL upon error.
1103 */
1104static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh)
1105{
1106 struct omap_hwmod_ocp_if *os;
1107 struct omap_hwmod_addr_space *mem;
1108 int found = 0, i = 0;
937 1109
938 if (!os->addr) 1110 os = _find_mpu_rt_port(oh);
1111 if (!os || !os->addr)
939 return NULL; 1112 return NULL;
940 1113
941 do { 1114 do {
@@ -944,20 +1117,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
944 found = 1; 1117 found = 1;
945 } while (!found && mem->pa_start != mem->pa_end); 1118 } while (!found && mem->pa_start != mem->pa_end);
946 1119
947 if (found) { 1120 return (found) ? mem : NULL;
948 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
949 if (!va_start) {
950 pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
951 return NULL;
952 }
953 pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
954 oh->name, va_start);
955 } else {
956 pr_debug("omap_hwmod: %s: no MPU register target found\n",
957 oh->name);
958 }
959
960 return (found) ? va_start : NULL;
961} 1121}
962 1122
963/** 1123/**
@@ -1205,12 +1365,11 @@ static int _wait_target_ready(struct omap_hwmod *oh)
1205 if (!oh) 1365 if (!oh)
1206 return -EINVAL; 1366 return -EINVAL;
1207 1367
1208 if (oh->_int_flags & _HWMOD_NO_MPU_PORT) 1368 if (oh->flags & HWMOD_NO_IDLEST)
1209 return 0; 1369 return 0;
1210 1370
1211 os = oh->slaves[oh->_mpu_port_index]; 1371 os = _find_mpu_rt_port(oh);
1212 1372 if (!os)
1213 if (oh->flags & HWMOD_NO_IDLEST)
1214 return 0; 1373 return 0;
1215 1374
1216 /* XXX check module SIDLEMODE */ 1375 /* XXX check module SIDLEMODE */
@@ -1378,13 +1537,73 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
1378} 1537}
1379 1538
1380/** 1539/**
1540 * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset
1541 * @oh: struct omap_hwmod *
1542 *
1543 * If any hardreset line associated with @oh is asserted, then return true.
1544 * Otherwise, if @oh has no hardreset lines associated with it, or if
1545 * no hardreset lines associated with @oh are asserted, then return false.
1546 * This function is used to avoid executing some parts of the IP block
1547 * enable/disable sequence if a hardreset line is set.
1548 */
1549static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
1550{
1551 int i;
1552
1553 if (oh->rst_lines_cnt == 0)
1554 return false;
1555
1556 for (i = 0; i < oh->rst_lines_cnt; i++)
1557 if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
1558 return true;
1559
1560 return false;
1561}
1562
1563/**
1564 * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
1565 * @oh: struct omap_hwmod *
1566 *
1567 * Disable the PRCM module mode related to the hwmod @oh.
1568 * Return EINVAL if the modulemode is not supported and 0 in case of success.
1569 */
1570static int _omap4_disable_module(struct omap_hwmod *oh)
1571{
1572 int v;
1573
1574 /* The module mode does not exist prior OMAP4 */
1575 if (!cpu_is_omap44xx())
1576 return -EINVAL;
1577
1578 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
1579 return -EINVAL;
1580
1581 pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
1582
1583 omap4_cminst_module_disable(oh->clkdm->prcm_partition,
1584 oh->clkdm->cm_inst,
1585 oh->clkdm->clkdm_offs,
1586 oh->prcm.omap4.clkctrl_offs);
1587
1588 if (_are_any_hardreset_lines_asserted(oh))
1589 return 0;
1590
1591 v = _omap4_wait_target_disable(oh);
1592 if (v)
1593 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
1594 oh->name);
1595
1596 return 0;
1597}
1598
1599/**
1381 * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit 1600 * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
1382 * @oh: struct omap_hwmod * 1601 * @oh: struct omap_hwmod *
1383 * 1602 *
1384 * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be 1603 * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be
1385 * enabled for this to work. Returns -EINVAL if the hwmod cannot be 1604 * enabled for this to work. Returns -ENOENT if the hwmod cannot be
1386 * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if 1605 * reset this way, -EINVAL if the hwmod is in the wrong state,
1387 * the module did not reset in time, or 0 upon success. 1606 * -ETIMEDOUT if the module did not reset in time, or 0 upon success.
1388 * 1607 *
1389 * In OMAP3 a specific SYSSTATUS register is used to get the reset status. 1608 * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
1390 * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead 1609 * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
@@ -1401,7 +1620,7 @@ static int _ocp_softreset(struct omap_hwmod *oh)
1401 1620
1402 if (!oh->class->sysc || 1621 if (!oh->class->sysc ||
1403 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) 1622 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
1404 return -EINVAL; 1623 return -ENOENT;
1405 1624
1406 /* clocks must be on for this operation */ 1625 /* clocks must be on for this operation */
1407 if (oh->_state != _HWMOD_STATE_ENABLED) { 1626 if (oh->_state != _HWMOD_STATE_ENABLED) {
@@ -1462,32 +1681,60 @@ dis_opt_clks:
1462 * _reset - reset an omap_hwmod 1681 * _reset - reset an omap_hwmod
1463 * @oh: struct omap_hwmod * 1682 * @oh: struct omap_hwmod *
1464 * 1683 *
1465 * Resets an omap_hwmod @oh. The default software reset mechanism for 1684 * Resets an omap_hwmod @oh. If the module has a custom reset
1466 * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET 1685 * function pointer defined, then call it to reset the IP block, and
1467 * bit. However, some hwmods cannot be reset via this method: some 1686 * pass along its return value to the caller. Otherwise, if the IP
1468 * are not targets and therefore have no OCP header registers to 1687 * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield
1469 * access; others (like the IVA) have idiosyncratic reset sequences. 1688 * associated with it, call a function to reset the IP block via that
1470 * So for these relatively rare cases, custom reset code can be 1689 * method, and pass along the return value to the caller. Finally, if
1471 * supplied in the struct omap_hwmod_class .reset function pointer. 1690 * the IP block has some hardreset lines associated with it, assert
1472 * Passes along the return value from either _reset() or the custom 1691 * all of those, but do _not_ deassert them. (This is because driver
1473 * reset function - these must return -EINVAL if the hwmod cannot be 1692 * authors have expressed an apparent requirement to control the
1474 * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if 1693 * deassertion of the hardreset lines themselves.)
1475 * the module did not reset in time, or 0 upon success. 1694 *
1695 * The default software reset mechanism for most OMAP IP blocks is
1696 * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some
1697 * hwmods cannot be reset via this method. Some are not targets and
1698 * therefore have no OCP header registers to access. Others (like the
1699 * IVA) have idiosyncratic reset sequences. So for these relatively
1700 * rare cases, custom reset code can be supplied in the struct
1701 * omap_hwmod_class .reset function pointer. Passes along the return
1702 * value from either _ocp_softreset() or the custom reset function -
1703 * these must return -EINVAL if the hwmod cannot be reset this way or
1704 * if the hwmod is in the wrong state, -ETIMEDOUT if the module did
1705 * not reset in time, or 0 upon success.
1476 */ 1706 */
1477static int _reset(struct omap_hwmod *oh) 1707static int _reset(struct omap_hwmod *oh)
1478{ 1708{
1479 int ret; 1709 int i, r;
1480 1710
1481 pr_debug("omap_hwmod: %s: resetting\n", oh->name); 1711 pr_debug("omap_hwmod: %s: resetting\n", oh->name);
1482 1712
1483 ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh); 1713 if (oh->class->reset) {
1714 r = oh->class->reset(oh);
1715 } else {
1716 if (oh->rst_lines_cnt > 0) {
1717 for (i = 0; i < oh->rst_lines_cnt; i++)
1718 _assert_hardreset(oh, oh->rst_lines[i].name);
1719 return 0;
1720 } else {
1721 r = _ocp_softreset(oh);
1722 if (r == -ENOENT)
1723 r = 0;
1724 }
1725 }
1484 1726
1727 /*
1728 * OCP_SYSCONFIG bits need to be reprogrammed after a
1729 * softreset. The _enable() function should be split to avoid
1730 * the rewrite of the OCP_SYSCONFIG register.
1731 */
1485 if (oh->class->sysc) { 1732 if (oh->class->sysc) {
1486 _update_sysc_cache(oh); 1733 _update_sysc_cache(oh);
1487 _enable_sysc(oh); 1734 _enable_sysc(oh);
1488 } 1735 }
1489 1736
1490 return ret; 1737 return r;
1491} 1738}
1492 1739
1493/** 1740/**
@@ -1506,10 +1753,9 @@ static int _enable(struct omap_hwmod *oh)
1506 pr_debug("omap_hwmod: %s: enabling\n", oh->name); 1753 pr_debug("omap_hwmod: %s: enabling\n", oh->name);
1507 1754
1508 /* 1755 /*
1509 * hwmods with HWMOD_INIT_NO_IDLE flag set are left 1756 * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled
1510 * in enabled state at init. 1757 * state at init. Now that someone is really trying to enable
1511 * Now that someone is really trying to enable them, 1758 * them, just ensure that the hwmod mux is set.
1512 * just ensure that the hwmod mux is set.
1513 */ 1759 */
1514 if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { 1760 if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
1515 /* 1761 /*
@@ -1532,15 +1778,17 @@ static int _enable(struct omap_hwmod *oh)
1532 return -EINVAL; 1778 return -EINVAL;
1533 } 1779 }
1534 1780
1535
1536 /* 1781 /*
1537 * If an IP contains only one HW reset line, then de-assert it in order 1782 * If an IP block contains HW reset lines and any of them are
1538 * to allow the module state transition. Otherwise the PRCM will return 1783 * asserted, we let integration code associated with that
1539 * Intransition status, and the init will failed. 1784 * block handle the enable. We've received very little
1785 * information on what those driver authors need, and until
1786 * detailed information is provided and the driver code is
1787 * posted to the public lists, this is probably the best we
1788 * can do.
1540 */ 1789 */
1541 if ((oh->_state == _HWMOD_STATE_INITIALIZED || 1790 if (_are_any_hardreset_lines_asserted(oh))
1542 oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) 1791 return 0;
1543 _deassert_hardreset(oh, oh->rst_lines[0].name);
1544 1792
1545 /* Mux pins for device runtime if populated */ 1793 /* Mux pins for device runtime if populated */
1546 if (oh->mux && (!oh->mux->enabled || 1794 if (oh->mux && (!oh->mux->enabled ||
@@ -1615,6 +1863,9 @@ static int _idle(struct omap_hwmod *oh)
1615 return -EINVAL; 1863 return -EINVAL;
1616 } 1864 }
1617 1865
1866 if (_are_any_hardreset_lines_asserted(oh))
1867 return 0;
1868
1618 if (oh->class->sysc) 1869 if (oh->class->sysc)
1619 _idle_sysc(oh); 1870 _idle_sysc(oh);
1620 _del_initiator_dep(oh, mpu_oh); 1871 _del_initiator_dep(oh, mpu_oh);
@@ -1687,7 +1938,7 @@ int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
1687 */ 1938 */
1688static int _shutdown(struct omap_hwmod *oh) 1939static int _shutdown(struct omap_hwmod *oh)
1689{ 1940{
1690 int ret; 1941 int ret, i;
1691 u8 prev_state; 1942 u8 prev_state;
1692 1943
1693 if (oh->_state != _HWMOD_STATE_IDLE && 1944 if (oh->_state != _HWMOD_STATE_IDLE &&
@@ -1697,6 +1948,9 @@ static int _shutdown(struct omap_hwmod *oh)
1697 return -EINVAL; 1948 return -EINVAL;
1698 } 1949 }
1699 1950
1951 if (_are_any_hardreset_lines_asserted(oh))
1952 return 0;
1953
1700 pr_debug("omap_hwmod: %s: disabling\n", oh->name); 1954 pr_debug("omap_hwmod: %s: disabling\n", oh->name);
1701 1955
1702 if (oh->class->pre_shutdown) { 1956 if (oh->class->pre_shutdown) {
@@ -1728,12 +1982,8 @@ static int _shutdown(struct omap_hwmod *oh)
1728 } 1982 }
1729 /* XXX Should this code also force-disable the optional clocks? */ 1983 /* XXX Should this code also force-disable the optional clocks? */
1730 1984
1731 /* 1985 for (i = 0; i < oh->rst_lines_cnt; i++)
1732 * If an IP contains only one HW reset line, then assert it 1986 _assert_hardreset(oh, oh->rst_lines[i].name);
1733 * after disabling the clocks and before shutting down the IP.
1734 */
1735 if (oh->rst_lines_cnt == 1)
1736 _assert_hardreset(oh, oh->rst_lines[0].name);
1737 1987
1738 /* Mux pins to safe mode or use populated off mode values */ 1988 /* Mux pins to safe mode or use populated off mode values */
1739 if (oh->mux) 1989 if (oh->mux)
@@ -1745,59 +1995,186 @@ static int _shutdown(struct omap_hwmod *oh)
1745} 1995}
1746 1996
1747/** 1997/**
1748 * _setup - do initial configuration of omap_hwmod 1998 * _init_mpu_rt_base - populate the virtual address for a hwmod
1749 * @oh: struct omap_hwmod * 1999 * @oh: struct omap_hwmod * to locate the virtual address
1750 * 2000 *
1751 * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh 2001 * Cache the virtual address used by the MPU to access this IP block's
1752 * OCP_SYSCONFIG register. Returns 0. 2002 * registers. This address is needed early so the OCP registers that
2003 * are part of the device's address space can be ioremapped properly.
2004 * No return value.
1753 */ 2005 */
1754static int _setup(struct omap_hwmod *oh, void *data) 2006static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
1755{ 2007{
1756 int i, r; 2008 struct omap_hwmod_addr_space *mem;
1757 u8 postsetup_state; 2009 void __iomem *va_start;
2010
2011 if (!oh)
2012 return;
2013
2014 _save_mpu_port_index(oh);
1758 2015
1759 if (oh->_state != _HWMOD_STATE_CLKS_INITED) 2016 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
2017 return;
2018
2019 mem = _find_mpu_rt_addr_space(oh);
2020 if (!mem) {
2021 pr_debug("omap_hwmod: %s: no MPU register target found\n",
2022 oh->name);
2023 return;
2024 }
2025
2026 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
2027 if (!va_start) {
2028 pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
2029 return;
2030 }
2031
2032 pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
2033 oh->name, va_start);
2034
2035 oh->_mpu_rt_va = va_start;
2036}
2037
2038/**
2039 * _init - initialize internal data for the hwmod @oh
2040 * @oh: struct omap_hwmod *
2041 * @n: (unused)
2042 *
2043 * Look up the clocks and the address space used by the MPU to access
2044 * registers belonging to the hwmod @oh. @oh must already be
2045 * registered at this point. This is the first of two phases for
2046 * hwmod initialization. Code called here does not touch any hardware
2047 * registers, it simply prepares internal data structures. Returns 0
2048 * upon success or if the hwmod isn't registered, or -EINVAL upon
2049 * failure.
2050 */
2051static int __init _init(struct omap_hwmod *oh, void *data)
2052{
2053 int r;
2054
2055 if (oh->_state != _HWMOD_STATE_REGISTERED)
1760 return 0; 2056 return 0;
1761 2057
1762 /* Set iclk autoidle mode */ 2058 _init_mpu_rt_base(oh, NULL);
1763 if (oh->slaves_cnt > 0) {
1764 for (i = 0; i < oh->slaves_cnt; i++) {
1765 struct omap_hwmod_ocp_if *os = oh->slaves[i];
1766 struct clk *c = os->_clk;
1767 2059
1768 if (!c) 2060 r = _init_clocks(oh, NULL);
1769 continue; 2061 if (IS_ERR_VALUE(r)) {
2062 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
2063 return -EINVAL;
2064 }
1770 2065
1771 if (os->flags & OCPIF_SWSUP_IDLE) { 2066 oh->_state = _HWMOD_STATE_INITIALIZED;
1772 /* XXX omap_iclk_deny_idle(c); */ 2067
1773 } else { 2068 return 0;
1774 /* XXX omap_iclk_allow_idle(c); */ 2069}
1775 clk_enable(c); 2070
1776 } 2071/**
2072 * _setup_iclk_autoidle - configure an IP block's interface clocks
2073 * @oh: struct omap_hwmod *
2074 *
2075 * Set up the module's interface clocks. XXX This function is still mostly
2076 * a stub; implementing this properly requires iclk autoidle usecounting in
2077 * the clock code. No return value.
2078 */
2079static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
2080{
2081 struct omap_hwmod_ocp_if *os;
2082 struct list_head *p;
2083 int i = 0;
2084 if (oh->_state != _HWMOD_STATE_INITIALIZED)
2085 return;
2086
2087 p = oh->slave_ports.next;
2088
2089 while (i < oh->slaves_cnt) {
2090 os = _fetch_next_ocp_if(&p, &i);
2091 if (!os->_clk)
2092 continue;
2093
2094 if (os->flags & OCPIF_SWSUP_IDLE) {
2095 /* XXX omap_iclk_deny_idle(c); */
2096 } else {
2097 /* XXX omap_iclk_allow_idle(c); */
2098 clk_enable(os->_clk);
1777 } 2099 }
1778 } 2100 }
1779 2101
1780 oh->_state = _HWMOD_STATE_INITIALIZED; 2102 return;
2103}
1781 2104
1782 /* 2105/**
1783 * In the case of hwmod with hardreset that should not be 2106 * _setup_reset - reset an IP block during the setup process
1784 * de-assert at boot time, we have to keep the module 2107 * @oh: struct omap_hwmod *
1785 * initialized, because we cannot enable it properly with the 2108 *
1786 * reset asserted. Exit without warning because that behavior is 2109 * Reset the IP block corresponding to the hwmod @oh during the setup
1787 * expected. 2110 * process. The IP block is first enabled so it can be successfully
1788 */ 2111 * reset. Returns 0 upon success or a negative error code upon
1789 if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) 2112 * failure.
1790 return 0; 2113 */
2114static int __init _setup_reset(struct omap_hwmod *oh)
2115{
2116 int r;
1791 2117
1792 r = _enable(oh); 2118 if (oh->_state != _HWMOD_STATE_INITIALIZED)
1793 if (r) { 2119 return -EINVAL;
1794 pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", 2120
1795 oh->name, oh->_state); 2121 if (oh->rst_lines_cnt == 0) {
1796 return 0; 2122 r = _enable(oh);
2123 if (r) {
2124 pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n",
2125 oh->name, oh->_state);
2126 return -EINVAL;
2127 }
1797 } 2128 }
1798 2129
1799 if (!(oh->flags & HWMOD_INIT_NO_RESET)) 2130 if (!(oh->flags & HWMOD_INIT_NO_RESET))
1800 _reset(oh); 2131 r = _reset(oh);
2132
2133 return r;
2134}
2135
2136/**
2137 * _setup_postsetup - transition to the appropriate state after _setup
2138 * @oh: struct omap_hwmod *
2139 *
2140 * Place an IP block represented by @oh into a "post-setup" state --
2141 * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that
2142 * this function is called at the end of _setup().) The postsetup
2143 * state for an IP block can be changed by calling
2144 * omap_hwmod_enter_postsetup_state() early in the boot process,
2145 * before one of the omap_hwmod_setup*() functions are called for the
2146 * IP block.
2147 *
2148 * The IP block stays in this state until a PM runtime-based driver is
2149 * loaded for that IP block. A post-setup state of IDLE is
2150 * appropriate for almost all IP blocks with runtime PM-enabled
2151 * drivers, since those drivers are able to enable the IP block. A
2152 * post-setup state of ENABLED is appropriate for kernels with PM
2153 * runtime disabled. The DISABLED state is appropriate for unusual IP
2154 * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers
2155 * included, since the WDTIMER starts running on reset and will reset
2156 * the MPU if left active.
2157 *
2158 * This post-setup mechanism is deprecated. Once all of the OMAP
2159 * drivers have been converted to use PM runtime, and all of the IP
2160 * block data and interconnect data is available to the hwmod code, it
2161 * should be possible to replace this mechanism with a "lazy reset"
2162 * arrangement. In a "lazy reset" setup, each IP block is enabled
2163 * when the driver first probes, then all remaining IP blocks without
2164 * drivers are either shut down or enabled after the drivers have
2165 * loaded. However, this cannot take place until the above
2166 * preconditions have been met, since otherwise the late reset code
2167 * has no way of knowing which IP blocks are in use by drivers, and
2168 * which ones are unused.
2169 *
2170 * No return value.
2171 */
2172static void __init _setup_postsetup(struct omap_hwmod *oh)
2173{
2174 u8 postsetup_state;
2175
2176 if (oh->rst_lines_cnt > 0)
2177 return;
1801 2178
1802 postsetup_state = oh->_postsetup_state; 2179 postsetup_state = oh->_postsetup_state;
1803 if (postsetup_state == _HWMOD_STATE_UNKNOWN) 2180 if (postsetup_state == _HWMOD_STATE_UNKNOWN)
@@ -1821,6 +2198,35 @@ static int _setup(struct omap_hwmod *oh, void *data)
1821 WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", 2198 WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
1822 oh->name, postsetup_state); 2199 oh->name, postsetup_state);
1823 2200
2201 return;
2202}
2203
2204/**
2205 * _setup - prepare IP block hardware for use
2206 * @oh: struct omap_hwmod *
2207 * @n: (unused, pass NULL)
2208 *
2209 * Configure the IP block represented by @oh. This may include
2210 * enabling the IP block, resetting it, and placing it into a
2211 * post-setup state, depending on the type of IP block and applicable
2212 * flags. IP blocks are reset to prevent any previous configuration
2213 * by the bootloader or previous operating system from interfering
2214 * with power management or other parts of the system. The reset can
2215 * be avoided; see omap_hwmod_no_setup_reset(). This is the second of
2216 * two phases for hwmod initialization. Code called here generally
2217 * affects the IP block hardware, or system integration hardware
2218 * associated with the IP block. Returns 0.
2219 */
2220static int __init _setup(struct omap_hwmod *oh, void *data)
2221{
2222 if (oh->_state != _HWMOD_STATE_INITIALIZED)
2223 return 0;
2224
2225 _setup_iclk_autoidle(oh);
2226
2227 if (!_setup_reset(oh))
2228 _setup_postsetup(oh);
2229
1824 return 0; 2230 return 0;
1825} 2231}
1826 2232
@@ -1843,8 +2249,6 @@ static int _setup(struct omap_hwmod *oh, void *data)
1843 */ 2249 */
1844static int __init _register(struct omap_hwmod *oh) 2250static int __init _register(struct omap_hwmod *oh)
1845{ 2251{
1846 int ms_id;
1847
1848 if (!oh || !oh->name || !oh->class || !oh->class->name || 2252 if (!oh || !oh->name || !oh->class || !oh->class->name ||
1849 (oh->_state != _HWMOD_STATE_UNKNOWN)) 2253 (oh->_state != _HWMOD_STATE_UNKNOWN))
1850 return -EINVAL; 2254 return -EINVAL;
@@ -1854,14 +2258,10 @@ static int __init _register(struct omap_hwmod *oh)
1854 if (_lookup(oh->name)) 2258 if (_lookup(oh->name))
1855 return -EEXIST; 2259 return -EEXIST;
1856 2260
1857 ms_id = _find_mpu_port_index(oh);
1858 if (!IS_ERR_VALUE(ms_id))
1859 oh->_mpu_port_index = ms_id;
1860 else
1861 oh->_int_flags |= _HWMOD_NO_MPU_PORT;
1862
1863 list_add_tail(&oh->node, &omap_hwmod_list); 2261 list_add_tail(&oh->node, &omap_hwmod_list);
1864 2262
2263 INIT_LIST_HEAD(&oh->master_ports);
2264 INIT_LIST_HEAD(&oh->slave_ports);
1865 spin_lock_init(&oh->_lock); 2265 spin_lock_init(&oh->_lock);
1866 2266
1867 oh->_state = _HWMOD_STATE_REGISTERED; 2267 oh->_state = _HWMOD_STATE_REGISTERED;
@@ -1876,6 +2276,160 @@ static int __init _register(struct omap_hwmod *oh)
1876 return 0; 2276 return 0;
1877} 2277}
1878 2278
2279/**
2280 * _alloc_links - return allocated memory for hwmod links
2281 * @ml: pointer to a struct omap_hwmod_link * for the master link
2282 * @sl: pointer to a struct omap_hwmod_link * for the slave link
2283 *
2284 * Return pointers to two struct omap_hwmod_link records, via the
2285 * addresses pointed to by @ml and @sl. Will first attempt to return
2286 * memory allocated as part of a large initial block, but if that has
2287 * been exhausted, will allocate memory itself. Since ideally this
2288 * second allocation path will never occur, the number of these
2289 * 'supplemental' allocations will be logged when debugging is
2290 * enabled. Returns 0.
2291 */
2292static int __init _alloc_links(struct omap_hwmod_link **ml,
2293 struct omap_hwmod_link **sl)
2294{
2295 unsigned int sz;
2296
2297 if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) {
2298 *ml = &linkspace[free_ls++];
2299 *sl = &linkspace[free_ls++];
2300 return 0;
2301 }
2302
2303 sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF;
2304
2305 *sl = NULL;
2306 *ml = alloc_bootmem(sz);
2307
2308 memset(*ml, 0, sz);
2309
2310 *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link);
2311
2312 ls_supp++;
2313 pr_debug("omap_hwmod: supplemental link allocations needed: %d\n",
2314 ls_supp * LINKS_PER_OCP_IF);
2315
2316 return 0;
2317};
2318
2319/**
2320 * _add_link - add an interconnect between two IP blocks
2321 * @oi: pointer to a struct omap_hwmod_ocp_if record
2322 *
2323 * Add struct omap_hwmod_link records connecting the master IP block
2324 * specified in @oi->master to @oi, and connecting the slave IP block
2325 * specified in @oi->slave to @oi. This code is assumed to run before
2326 * preemption or SMP has been enabled, thus avoiding the need for
2327 * locking in this code. Changes to this assumption will require
2328 * additional locking. Returns 0.
2329 */
2330static int __init _add_link(struct omap_hwmod_ocp_if *oi)
2331{
2332 struct omap_hwmod_link *ml, *sl;
2333
2334 pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name,
2335 oi->slave->name);
2336
2337 _alloc_links(&ml, &sl);
2338
2339 ml->ocp_if = oi;
2340 INIT_LIST_HEAD(&ml->node);
2341 list_add(&ml->node, &oi->master->master_ports);
2342 oi->master->masters_cnt++;
2343
2344 sl->ocp_if = oi;
2345 INIT_LIST_HEAD(&sl->node);
2346 list_add(&sl->node, &oi->slave->slave_ports);
2347 oi->slave->slaves_cnt++;
2348
2349 return 0;
2350}
2351
2352/**
2353 * _register_link - register a struct omap_hwmod_ocp_if
2354 * @oi: struct omap_hwmod_ocp_if *
2355 *
2356 * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it
2357 * has already been registered; -EINVAL if @oi is NULL or if the
2358 * record pointed to by @oi is missing required fields; or 0 upon
2359 * success.
2360 *
2361 * XXX The data should be copied into bootmem, so the original data
2362 * should be marked __initdata and freed after init. This would allow
2363 * unneeded omap_hwmods to be freed on multi-OMAP configurations.
2364 */
2365static int __init _register_link(struct omap_hwmod_ocp_if *oi)
2366{
2367 if (!oi || !oi->master || !oi->slave || !oi->user)
2368 return -EINVAL;
2369
2370 if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED)
2371 return -EEXIST;
2372
2373 pr_debug("omap_hwmod: registering link from %s to %s\n",
2374 oi->master->name, oi->slave->name);
2375
2376 /*
2377 * Register the connected hwmods, if they haven't been
2378 * registered already
2379 */
2380 if (oi->master->_state != _HWMOD_STATE_REGISTERED)
2381 _register(oi->master);
2382
2383 if (oi->slave->_state != _HWMOD_STATE_REGISTERED)
2384 _register(oi->slave);
2385
2386 _add_link(oi);
2387
2388 oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED;
2389
2390 return 0;
2391}
2392
2393/**
2394 * _alloc_linkspace - allocate large block of hwmod links
2395 * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count
2396 *
2397 * Allocate a large block of struct omap_hwmod_link records. This
2398 * improves boot time significantly by avoiding the need to allocate
2399 * individual records one by one. If the number of records to
2400 * allocate in the block hasn't been manually specified, this function
2401 * will count the number of struct omap_hwmod_ocp_if records in @ois
2402 * and use that to determine the allocation size. For SoC families
2403 * that require multiple list registrations, such as OMAP3xxx, this
2404 * estimation process isn't optimal, so manual estimation is advised
2405 * in those cases. Returns -EEXIST if the allocation has already occurred
2406 * or 0 upon success.
2407 */
2408static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
2409{
2410 unsigned int i = 0;
2411 unsigned int sz;
2412
2413 if (linkspace) {
2414 WARN(1, "linkspace already allocated\n");
2415 return -EEXIST;
2416 }
2417
2418 if (max_ls == 0)
2419 while (ois[i++])
2420 max_ls += LINKS_PER_OCP_IF;
2421
2422 sz = sizeof(struct omap_hwmod_link) * max_ls;
2423
2424 pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n",
2425 __func__, sz, max_ls);
2426
2427 linkspace = alloc_bootmem(sz);
2428
2429 memset(linkspace, 0, sz);
2430
2431 return 0;
2432}
1879 2433
1880/* Public functions */ 2434/* Public functions */
1881 2435
@@ -2004,120 +2558,101 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
2004} 2558}
2005 2559
2006/** 2560/**
2007 * omap_hwmod_register - register an array of hwmods 2561 * omap_hwmod_register_links - register an array of hwmod links
2008 * @ohs: pointer to an array of omap_hwmods to register 2562 * @ois: pointer to an array of omap_hwmod_ocp_if to register
2009 * 2563 *
2010 * Intended to be called early in boot before the clock framework is 2564 * Intended to be called early in boot before the clock framework is
2011 * initialized. If @ohs is not null, will register all omap_hwmods 2565 * initialized. If @ois is not null, will register all omap_hwmods
2012 * listed in @ohs that are valid for this chip. Returns 0. 2566 * listed in @ois that are valid for this chip. Returns 0.
2013 */ 2567 */
2014int __init omap_hwmod_register(struct omap_hwmod **ohs) 2568int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
2015{ 2569{
2016 int r, i; 2570 int r, i;
2017 2571
2018 if (!ohs) 2572 if (!ois)
2019 return 0; 2573 return 0;
2020 2574
2575 if (!linkspace) {
2576 if (_alloc_linkspace(ois)) {
2577 pr_err("omap_hwmod: could not allocate link space\n");
2578 return -ENOMEM;
2579 }
2580 }
2581
2021 i = 0; 2582 i = 0;
2022 do { 2583 do {
2023 r = _register(ohs[i]); 2584 r = _register_link(ois[i]);
2024 WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name, 2585 WARN(r && r != -EEXIST,
2025 r); 2586 "omap_hwmod: _register_link(%s -> %s) returned %d\n",
2026 } while (ohs[++i]); 2587 ois[i]->master->name, ois[i]->slave->name, r);
2588 } while (ois[++i]);
2027 2589
2028 return 0; 2590 return 0;
2029} 2591}
2030 2592
2031/* 2593/**
2032 * _populate_mpu_rt_base - populate the virtual address for a hwmod 2594 * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up
2595 * @oh: pointer to the hwmod currently being set up (usually not the MPU)
2033 * 2596 *
2034 * Must be called only from omap_hwmod_setup_*() so ioremap works properly. 2597 * If the hwmod data corresponding to the MPU subsystem IP block
2035 * Assumes the caller takes care of locking if needed. 2598 * hasn't been initialized and set up yet, do so now. This must be
2599 * done first since sleep dependencies may be added from other hwmods
2600 * to the MPU. Intended to be called only by omap_hwmod_setup*(). No
2601 * return value.
2036 */ 2602 */
2037static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) 2603static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh)
2038{ 2604{
2039 if (oh->_state != _HWMOD_STATE_REGISTERED) 2605 if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN)
2040 return 0; 2606 pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
2041 2607 __func__, MPU_INITIATOR_NAME);
2042 if (oh->_int_flags & _HWMOD_NO_MPU_PORT) 2608 else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
2043 return 0; 2609 omap_hwmod_setup_one(MPU_INITIATOR_NAME);
2044
2045 oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
2046
2047 return 0;
2048} 2610}
2049 2611
2050/** 2612/**
2051 * omap_hwmod_setup_one - set up a single hwmod 2613 * omap_hwmod_setup_one - set up a single hwmod
2052 * @oh_name: const char * name of the already-registered hwmod to set up 2614 * @oh_name: const char * name of the already-registered hwmod to set up
2053 * 2615 *
2054 * Must be called after omap2_clk_init(). Resolves the struct clk 2616 * Initialize and set up a single hwmod. Intended to be used for a
2055 * names to struct clk pointers for each registered omap_hwmod. Also 2617 * small number of early devices, such as the timer IP blocks used for
2056 * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon 2618 * the scheduler clock. Must be called after omap2_clk_init().
2057 * success. 2619 * Resolves the struct clk names to struct clk pointers for each
2620 * registered omap_hwmod. Also calls _setup() on each hwmod. Returns
2621 * -EINVAL upon error or 0 upon success.
2058 */ 2622 */
2059int __init omap_hwmod_setup_one(const char *oh_name) 2623int __init omap_hwmod_setup_one(const char *oh_name)
2060{ 2624{
2061 struct omap_hwmod *oh; 2625 struct omap_hwmod *oh;
2062 int r;
2063 2626
2064 pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); 2627 pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
2065 2628
2066 if (!mpu_oh) {
2067 pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
2068 oh_name, MPU_INITIATOR_NAME);
2069 return -EINVAL;
2070 }
2071
2072 oh = _lookup(oh_name); 2629 oh = _lookup(oh_name);
2073 if (!oh) { 2630 if (!oh) {
2074 WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); 2631 WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
2075 return -EINVAL; 2632 return -EINVAL;
2076 } 2633 }
2077 2634
2078 if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) 2635 _ensure_mpu_hwmod_is_setup(oh);
2079 omap_hwmod_setup_one(MPU_INITIATOR_NAME);
2080
2081 r = _populate_mpu_rt_base(oh, NULL);
2082 if (IS_ERR_VALUE(r)) {
2083 WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
2084 return -EINVAL;
2085 }
2086
2087 r = _init_clocks(oh, NULL);
2088 if (IS_ERR_VALUE(r)) {
2089 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
2090 return -EINVAL;
2091 }
2092 2636
2637 _init(oh, NULL);
2093 _setup(oh, NULL); 2638 _setup(oh, NULL);
2094 2639
2095 return 0; 2640 return 0;
2096} 2641}
2097 2642
2098/** 2643/**
2099 * omap_hwmod_setup - do some post-clock framework initialization 2644 * omap_hwmod_setup_all - set up all registered IP blocks
2100 * 2645 *
2101 * Must be called after omap2_clk_init(). Resolves the struct clk names 2646 * Initialize and set up all IP blocks registered with the hwmod code.
2102 * to struct clk pointers for each registered omap_hwmod. Also calls 2647 * Must be called after omap2_clk_init(). Resolves the struct clk
2103 * _setup() on each hwmod. Returns 0 upon success. 2648 * names to struct clk pointers for each registered omap_hwmod. Also
2649 * calls _setup() on each hwmod. Returns 0 upon success.
2104 */ 2650 */
2105static int __init omap_hwmod_setup_all(void) 2651static int __init omap_hwmod_setup_all(void)
2106{ 2652{
2107 int r; 2653 _ensure_mpu_hwmod_is_setup(NULL);
2108
2109 if (!mpu_oh) {
2110 pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
2111 __func__, MPU_INITIATOR_NAME);
2112 return -EINVAL;
2113 }
2114
2115 r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
2116
2117 r = omap_hwmod_for_each(_init_clocks, NULL);
2118 WARN(IS_ERR_VALUE(r),
2119 "omap_hwmod: %s: _init_clocks failed\n", __func__);
2120 2654
2655 omap_hwmod_for_each(_init, NULL);
2121 omap_hwmod_for_each(_setup, NULL); 2656 omap_hwmod_for_each(_setup, NULL);
2122 2657
2123 return 0; 2658 return 0;
@@ -2274,6 +2809,10 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
2274 return r; 2809 return r;
2275} 2810}
2276 2811
2812/*
2813 * IP block data retrieval functions
2814 */
2815
2277/** 2816/**
2278 * omap_hwmod_count_resources - count number of struct resources needed by hwmod 2817 * omap_hwmod_count_resources - count number of struct resources needed by hwmod
2279 * @oh: struct omap_hwmod * 2818 * @oh: struct omap_hwmod *
@@ -2292,12 +2831,19 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
2292 */ 2831 */
2293int omap_hwmod_count_resources(struct omap_hwmod *oh) 2832int omap_hwmod_count_resources(struct omap_hwmod *oh)
2294{ 2833{
2295 int ret, i; 2834 struct omap_hwmod_ocp_if *os;
2835 struct list_head *p;
2836 int ret;
2837 int i = 0;
2296 2838
2297 ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); 2839 ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
2298 2840
2299 for (i = 0; i < oh->slaves_cnt; i++) 2841 p = oh->slave_ports.next;
2300 ret += _count_ocp_if_addr_spaces(oh->slaves[i]); 2842
2843 while (i < oh->slaves_cnt) {
2844 os = _fetch_next_ocp_if(&p, &i);
2845 ret += _count_ocp_if_addr_spaces(os);
2846 }
2301 2847
2302 return ret; 2848 return ret;
2303} 2849}
@@ -2314,7 +2860,9 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
2314 */ 2860 */
2315int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) 2861int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
2316{ 2862{
2317 int i, j, mpu_irqs_cnt, sdma_reqs_cnt; 2863 struct omap_hwmod_ocp_if *os;
2864 struct list_head *p;
2865 int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt;
2318 int r = 0; 2866 int r = 0;
2319 2867
2320 /* For each IRQ, DMA, memory area, fill in array.*/ 2868 /* For each IRQ, DMA, memory area, fill in array.*/
@@ -2337,11 +2885,11 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
2337 r++; 2885 r++;
2338 } 2886 }
2339 2887
2340 for (i = 0; i < oh->slaves_cnt; i++) { 2888 p = oh->slave_ports.next;
2341 struct omap_hwmod_ocp_if *os;
2342 int addr_cnt;
2343 2889
2344 os = oh->slaves[i]; 2890 i = 0;
2891 while (i < oh->slaves_cnt) {
2892 os = _fetch_next_ocp_if(&p, &i);
2345 addr_cnt = _count_ocp_if_addr_spaces(os); 2893 addr_cnt = _count_ocp_if_addr_spaces(os);
2346 2894
2347 for (j = 0; j < addr_cnt; j++) { 2895 for (j = 0; j < addr_cnt; j++) {
@@ -2357,6 +2905,69 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
2357} 2905}
2358 2906
2359/** 2907/**
2908 * omap_hwmod_get_resource_byname - fetch IP block integration data by name
2909 * @oh: struct omap_hwmod * to operate on
2910 * @type: one of the IORESOURCE_* constants from include/linux/ioport.h
2911 * @name: pointer to the name of the data to fetch (optional)
2912 * @rsrc: pointer to a struct resource, allocated by the caller
2913 *
2914 * Retrieve MPU IRQ, SDMA request line, or address space start/end
2915 * data for the IP block pointed to by @oh. The data will be filled
2916 * into a struct resource record pointed to by @rsrc. The struct
2917 * resource must be allocated by the caller. When @name is non-null,
2918 * the data associated with the matching entry in the IRQ/SDMA/address
2919 * space hwmod data arrays will be returned. If @name is null, the
2920 * first array entry will be returned. Data order is not meaningful
2921 * in hwmod data, so callers are strongly encouraged to use a non-null
2922 * @name whenever possible to avoid unpredictable effects if hwmod
2923 * data is later added that causes data ordering to change. This
2924 * function is only intended for use by OMAP core code. Device
2925 * drivers should not call this function - the appropriate bus-related
2926 * data accessor functions should be used instead. Returns 0 upon
2927 * success or a negative error code upon error.
2928 */
2929int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
2930 const char *name, struct resource *rsrc)
2931{
2932 int r;
2933 unsigned int irq, dma;
2934 u32 pa_start, pa_end;
2935
2936 if (!oh || !rsrc)
2937 return -EINVAL;
2938
2939 if (type == IORESOURCE_IRQ) {
2940 r = _get_mpu_irq_by_name(oh, name, &irq);
2941 if (r)
2942 return r;
2943
2944 rsrc->start = irq;
2945 rsrc->end = irq;
2946 } else if (type == IORESOURCE_DMA) {
2947 r = _get_sdma_req_by_name(oh, name, &dma);
2948 if (r)
2949 return r;
2950
2951 rsrc->start = dma;
2952 rsrc->end = dma;
2953 } else if (type == IORESOURCE_MEM) {
2954 r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end);
2955 if (r)
2956 return r;
2957
2958 rsrc->start = pa_start;
2959 rsrc->end = pa_end;
2960 } else {
2961 return -EINVAL;
2962 }
2963
2964 rsrc->flags = type;
2965 rsrc->name = name;
2966
2967 return 0;
2968}
2969
2970/**
2360 * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain 2971 * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
2361 * @oh: struct omap_hwmod * 2972 * @oh: struct omap_hwmod *
2362 * 2973 *
@@ -2370,6 +2981,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
2370struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) 2981struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
2371{ 2982{
2372 struct clk *c; 2983 struct clk *c;
2984 struct omap_hwmod_ocp_if *oi;
2373 2985
2374 if (!oh) 2986 if (!oh)
2375 return NULL; 2987 return NULL;
@@ -2377,9 +2989,10 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
2377 if (oh->_clk) { 2989 if (oh->_clk) {
2378 c = oh->_clk; 2990 c = oh->_clk;
2379 } else { 2991 } else {
2380 if (oh->_int_flags & _HWMOD_NO_MPU_PORT) 2992 oi = _find_mpu_rt_port(oh);
2993 if (!oi)
2381 return NULL; 2994 return NULL;
2382 c = oh->slaves[oh->_mpu_port_index]->_clk; 2995 c = oi->_clk;
2383 } 2996 }
2384 2997
2385 if (!c->clkdm) 2998 if (!c->clkdm)
@@ -2653,10 +3266,10 @@ int omap_hwmod_for_each_by_class(const char *classname,
2653 * @state: state that _setup() should leave the hwmod in 3266 * @state: state that _setup() should leave the hwmod in
2654 * 3267 *
2655 * Sets the hwmod state that @oh will enter at the end of _setup() 3268 * Sets the hwmod state that @oh will enter at the end of _setup()
2656 * (called by omap_hwmod_setup_*()). Only valid to call between 3269 * (called by omap_hwmod_setup_*()). See also the documentation
2657 * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns 3270 * for _setup_postsetup(), above. Returns 0 upon success or
2658 * 0 upon success or -EINVAL if there is a problem with the arguments 3271 * -EINVAL if there is a problem with the arguments or if the hwmod is
2659 * or if the hwmod is in the wrong state. 3272 * in the wrong state.
2660 */ 3273 */
2661int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) 3274int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
2662{ 3275{
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a6bde34e443..2c087ffc6a9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -2,6 +2,7 @@
2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips 2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -32,707 +33,268 @@
32/* 33/*
33 * OMAP2420 hardware module integration data 34 * OMAP2420 hardware module integration data
34 * 35 *
35 * ALl of the data in this section should be autogeneratable from the 36 * All of the data in this section should be autogeneratable from the
36 * TI hardware database or other technical documentation. Data that 37 * TI hardware database or other technical documentation. Data that
37 * is driver-specific or driver-kernel integration-specific belongs 38 * is driver-specific or driver-kernel integration-specific belongs
38 * elsewhere. 39 * elsewhere.
39 */ 40 */
40 41
41static struct omap_hwmod omap2420_mpu_hwmod;
42static struct omap_hwmod omap2420_iva_hwmod;
43static struct omap_hwmod omap2420_l3_main_hwmod;
44static struct omap_hwmod omap2420_l4_core_hwmod;
45static struct omap_hwmod omap2420_dss_core_hwmod;
46static struct omap_hwmod omap2420_dss_dispc_hwmod;
47static struct omap_hwmod omap2420_dss_rfbi_hwmod;
48static struct omap_hwmod omap2420_dss_venc_hwmod;
49static struct omap_hwmod omap2420_wd_timer2_hwmod;
50static struct omap_hwmod omap2420_gpio1_hwmod;
51static struct omap_hwmod omap2420_gpio2_hwmod;
52static struct omap_hwmod omap2420_gpio3_hwmod;
53static struct omap_hwmod omap2420_gpio4_hwmod;
54static struct omap_hwmod omap2420_dma_system_hwmod;
55static struct omap_hwmod omap2420_mcspi1_hwmod;
56static struct omap_hwmod omap2420_mcspi2_hwmod;
57
58/* L3 -> L4_CORE interface */
59static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
60 .master = &omap2420_l3_main_hwmod,
61 .slave = &omap2420_l4_core_hwmod,
62 .user = OCP_USER_MPU | OCP_USER_SDMA,
63};
64
65/* MPU -> L3 interface */
66static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
67 .master = &omap2420_mpu_hwmod,
68 .slave = &omap2420_l3_main_hwmod,
69 .user = OCP_USER_MPU,
70};
71
72/* Slave interfaces on the L3 interconnect */
73static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
74 &omap2420_mpu__l3_main,
75};
76
77/* DSS -> l3 */
78static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
79 .master = &omap2420_dss_core_hwmod,
80 .slave = &omap2420_l3_main_hwmod,
81 .fw = {
82 .omap2 = {
83 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
84 .flags = OMAP_FIREWALL_L3,
85 }
86 },
87 .user = OCP_USER_MPU | OCP_USER_SDMA,
88};
89
90/* Master interfaces on the L3 interconnect */
91static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
92 &omap2420_l3_main__l4_core,
93};
94
95/* L3 */
96static struct omap_hwmod omap2420_l3_main_hwmod = {
97 .name = "l3_main",
98 .class = &l3_hwmod_class,
99 .masters = omap2420_l3_main_masters,
100 .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters),
101 .slaves = omap2420_l3_main_slaves,
102 .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves),
103 .flags = HWMOD_NO_IDLEST,
104};
105
106static struct omap_hwmod omap2420_l4_wkup_hwmod;
107static struct omap_hwmod omap2420_uart1_hwmod;
108static struct omap_hwmod omap2420_uart2_hwmod;
109static struct omap_hwmod omap2420_uart3_hwmod;
110static struct omap_hwmod omap2420_i2c1_hwmod;
111static struct omap_hwmod omap2420_i2c2_hwmod;
112static struct omap_hwmod omap2420_mcbsp1_hwmod;
113static struct omap_hwmod omap2420_mcbsp2_hwmod;
114
115/* l4 core -> mcspi1 interface */
116static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
117 .master = &omap2420_l4_core_hwmod,
118 .slave = &omap2420_mcspi1_hwmod,
119 .clk = "mcspi1_ick",
120 .addr = omap2_mcspi1_addr_space,
121 .user = OCP_USER_MPU | OCP_USER_SDMA,
122};
123
124/* l4 core -> mcspi2 interface */
125static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
126 .master = &omap2420_l4_core_hwmod,
127 .slave = &omap2420_mcspi2_hwmod,
128 .clk = "mcspi2_ick",
129 .addr = omap2_mcspi2_addr_space,
130 .user = OCP_USER_MPU | OCP_USER_SDMA,
131};
132
133/* L4_CORE -> L4_WKUP interface */
134static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
135 .master = &omap2420_l4_core_hwmod,
136 .slave = &omap2420_l4_wkup_hwmod,
137 .user = OCP_USER_MPU | OCP_USER_SDMA,
138};
139
140/* L4 CORE -> UART1 interface */
141static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
142 .master = &omap2420_l4_core_hwmod,
143 .slave = &omap2420_uart1_hwmod,
144 .clk = "uart1_ick",
145 .addr = omap2xxx_uart1_addr_space,
146 .user = OCP_USER_MPU | OCP_USER_SDMA,
147};
148
149/* L4 CORE -> UART2 interface */
150static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
151 .master = &omap2420_l4_core_hwmod,
152 .slave = &omap2420_uart2_hwmod,
153 .clk = "uart2_ick",
154 .addr = omap2xxx_uart2_addr_space,
155 .user = OCP_USER_MPU | OCP_USER_SDMA,
156};
157
158/* L4 PER -> UART3 interface */
159static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
160 .master = &omap2420_l4_core_hwmod,
161 .slave = &omap2420_uart3_hwmod,
162 .clk = "uart3_ick",
163 .addr = omap2xxx_uart3_addr_space,
164 .user = OCP_USER_MPU | OCP_USER_SDMA,
165};
166
167/* L4 CORE -> I2C1 interface */
168static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
169 .master = &omap2420_l4_core_hwmod,
170 .slave = &omap2420_i2c1_hwmod,
171 .clk = "i2c1_ick",
172 .addr = omap2_i2c1_addr_space,
173 .user = OCP_USER_MPU | OCP_USER_SDMA,
174};
175
176/* L4 CORE -> I2C2 interface */
177static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
178 .master = &omap2420_l4_core_hwmod,
179 .slave = &omap2420_i2c2_hwmod,
180 .clk = "i2c2_ick",
181 .addr = omap2_i2c2_addr_space,
182 .user = OCP_USER_MPU | OCP_USER_SDMA,
183};
184
185/* Slave interfaces on the L4_CORE interconnect */
186static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
187 &omap2420_l3_main__l4_core,
188};
189
190/* Master interfaces on the L4_CORE interconnect */
191static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
192 &omap2420_l4_core__l4_wkup,
193 &omap2_l4_core__uart1,
194 &omap2_l4_core__uart2,
195 &omap2_l4_core__uart3,
196 &omap2420_l4_core__i2c1,
197 &omap2420_l4_core__i2c2
198};
199
200/* L4 CORE */
201static struct omap_hwmod omap2420_l4_core_hwmod = {
202 .name = "l4_core",
203 .class = &l4_hwmod_class,
204 .masters = omap2420_l4_core_masters,
205 .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
206 .slaves = omap2420_l4_core_slaves,
207 .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves),
208 .flags = HWMOD_NO_IDLEST,
209};
210
211/* Slave interfaces on the L4_WKUP interconnect */
212static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
213 &omap2420_l4_core__l4_wkup,
214};
215
216/* Master interfaces on the L4_WKUP interconnect */
217static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
218};
219
220/* L4 WKUP */
221static struct omap_hwmod omap2420_l4_wkup_hwmod = {
222 .name = "l4_wkup",
223 .class = &l4_hwmod_class,
224 .masters = omap2420_l4_wkup_masters,
225 .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
226 .slaves = omap2420_l4_wkup_slaves,
227 .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves),
228 .flags = HWMOD_NO_IDLEST,
229};
230
231/* Master interfaces on the MPU device */
232static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
233 &omap2420_mpu__l3_main,
234};
235
236/* MPU */
237static struct omap_hwmod omap2420_mpu_hwmod = {
238 .name = "mpu",
239 .class = &mpu_hwmod_class,
240 .main_clk = "mpu_ck",
241 .masters = omap2420_mpu_masters,
242 .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters),
243};
244
245/* 42/*
246 * IVA1 interface data 43 * IP blocks
247 */ 44 */
248 45
249/* IVA <- L3 interface */ 46/* IVA1 (IVA1) */
250static struct omap_hwmod_ocp_if omap2420_l3__iva = { 47static struct omap_hwmod_class iva1_hwmod_class = {
251 .master = &omap2420_l3_main_hwmod, 48 .name = "iva1",
252 .slave = &omap2420_iva_hwmod,
253 .clk = "iva1_ifck",
254 .user = OCP_USER_MPU | OCP_USER_SDMA,
255}; 49};
256 50
257static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { 51static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
258 &omap2420_l3__iva, 52 { .name = "iva", .rst_shift = 8 },
259}; 53};
260 54
261/*
262 * IVA2 (IVA2)
263 */
264
265static struct omap_hwmod omap2420_iva_hwmod = { 55static struct omap_hwmod omap2420_iva_hwmod = {
266 .name = "iva", 56 .name = "iva",
267 .class = &iva_hwmod_class, 57 .class = &iva1_hwmod_class,
268 .masters = omap2420_iva_masters, 58 .clkdm_name = "iva1_clkdm",
269 .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), 59 .rst_lines = omap2420_iva_resets,
60 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
61 .main_clk = "iva1_ifck",
270}; 62};
271 63
272/* always-on timers dev attribute */ 64/* DSP */
273static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 65static struct omap_hwmod_class dsp_hwmod_class = {
274 .timer_capability = OMAP_TIMER_ALWON, 66 .name = "dsp",
275};
276
277/* pwm timers dev attribute */
278static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
279 .timer_capability = OMAP_TIMER_HAS_PWM,
280};
281
282/* timer1 */
283static struct omap_hwmod omap2420_timer1_hwmod;
284
285static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
286 {
287 .pa_start = 0x48028000,
288 .pa_end = 0x48028000 + SZ_1K - 1,
289 .flags = ADDR_TYPE_RT
290 },
291 { }
292}; 67};
293 68
294/* l4_wkup -> timer1 */ 69static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
295static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { 70 { .name = "logic", .rst_shift = 0 },
296 .master = &omap2420_l4_wkup_hwmod, 71 { .name = "mmu", .rst_shift = 1 },
297 .slave = &omap2420_timer1_hwmod,
298 .clk = "gpt1_ick",
299 .addr = omap2420_timer1_addrs,
300 .user = OCP_USER_MPU | OCP_USER_SDMA,
301}; 72};
302 73
303/* timer1 slave port */ 74static struct omap_hwmod omap2420_dsp_hwmod = {
304static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { 75 .name = "dsp",
305 &omap2420_l4_wkup__timer1, 76 .class = &dsp_hwmod_class,
77 .clkdm_name = "dsp_clkdm",
78 .rst_lines = omap2420_dsp_resets,
79 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
80 .main_clk = "dsp_fck",
306}; 81};
307 82
308/* timer1 hwmod */ 83/* I2C common */
309static struct omap_hwmod omap2420_timer1_hwmod = { 84static struct omap_hwmod_class_sysconfig i2c_sysc = {
310 .name = "timer1", 85 .rev_offs = 0x00,
311 .mpu_irqs = omap2_timer1_mpu_irqs, 86 .sysc_offs = 0x20,
312 .main_clk = "gpt1_fck", 87 .syss_offs = 0x10,
313 .prcm = { 88 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
314 .omap2 = { 89 .sysc_fields = &omap_hwmod_sysc_type1,
315 .prcm_reg_id = 1,
316 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
317 .module_offs = WKUP_MOD,
318 .idlest_reg_id = 1,
319 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
320 },
321 },
322 .dev_attr = &capability_alwon_dev_attr,
323 .slaves = omap2420_timer1_slaves,
324 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
325 .class = &omap2xxx_timer_hwmod_class,
326}; 90};
327 91
328/* timer2 */ 92static struct omap_hwmod_class i2c_class = {
329static struct omap_hwmod omap2420_timer2_hwmod; 93 .name = "i2c",
330 94 .sysc = &i2c_sysc,
331/* l4_core -> timer2 */ 95 .rev = OMAP_I2C_IP_VERSION_1,
332static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { 96 .reset = &omap_i2c_reset,
333 .master = &omap2420_l4_core_hwmod,
334 .slave = &omap2420_timer2_hwmod,
335 .clk = "gpt2_ick",
336 .addr = omap2xxx_timer2_addrs,
337 .user = OCP_USER_MPU | OCP_USER_SDMA,
338}; 97};
339 98
340/* timer2 slave port */ 99static struct omap_i2c_dev_attr i2c_dev_attr = {
341static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { 100 .flags = OMAP_I2C_FLAG_NO_FIFO |
342 &omap2420_l4_core__timer2, 101 OMAP_I2C_FLAG_SIMPLE_CLOCK |
102 OMAP_I2C_FLAG_16BIT_DATA_REG |
103 OMAP_I2C_FLAG_BUS_SHIFT_2,
343}; 104};
344 105
345/* timer2 hwmod */ 106/* I2C1 */
346static struct omap_hwmod omap2420_timer2_hwmod = { 107static struct omap_hwmod omap2420_i2c1_hwmod = {
347 .name = "timer2", 108 .name = "i2c1",
348 .mpu_irqs = omap2_timer2_mpu_irqs, 109 .mpu_irqs = omap2_i2c1_mpu_irqs,
349 .main_clk = "gpt2_fck", 110 .sdma_reqs = omap2_i2c1_sdma_reqs,
111 .main_clk = "i2c1_fck",
350 .prcm = { 112 .prcm = {
351 .omap2 = { 113 .omap2 = {
352 .prcm_reg_id = 1,
353 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
354 .module_offs = CORE_MOD, 114 .module_offs = CORE_MOD,
355 .idlest_reg_id = 1,
356 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
357 },
358 },
359 .dev_attr = &capability_alwon_dev_attr,
360 .slaves = omap2420_timer2_slaves,
361 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
362 .class = &omap2xxx_timer_hwmod_class,
363};
364
365/* timer3 */
366static struct omap_hwmod omap2420_timer3_hwmod;
367
368/* l4_core -> timer3 */
369static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
370 .master = &omap2420_l4_core_hwmod,
371 .slave = &omap2420_timer3_hwmod,
372 .clk = "gpt3_ick",
373 .addr = omap2xxx_timer3_addrs,
374 .user = OCP_USER_MPU | OCP_USER_SDMA,
375};
376
377/* timer3 slave port */
378static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
379 &omap2420_l4_core__timer3,
380};
381
382/* timer3 hwmod */
383static struct omap_hwmod omap2420_timer3_hwmod = {
384 .name = "timer3",
385 .mpu_irqs = omap2_timer3_mpu_irqs,
386 .main_clk = "gpt3_fck",
387 .prcm = {
388 .omap2 = {
389 .prcm_reg_id = 1, 115 .prcm_reg_id = 1,
390 .module_bit = OMAP24XX_EN_GPT3_SHIFT, 116 .module_bit = OMAP2420_EN_I2C1_SHIFT,
391 .module_offs = CORE_MOD,
392 .idlest_reg_id = 1, 117 .idlest_reg_id = 1,
393 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, 118 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
394 }, 119 },
395 }, 120 },
396 .dev_attr = &capability_alwon_dev_attr, 121 .class = &i2c_class,
397 .slaves = omap2420_timer3_slaves, 122 .dev_attr = &i2c_dev_attr,
398 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), 123 .flags = HWMOD_16BIT_REG,
399 .class = &omap2xxx_timer_hwmod_class,
400};
401
402/* timer4 */
403static struct omap_hwmod omap2420_timer4_hwmod;
404
405/* l4_core -> timer4 */
406static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
407 .master = &omap2420_l4_core_hwmod,
408 .slave = &omap2420_timer4_hwmod,
409 .clk = "gpt4_ick",
410 .addr = omap2xxx_timer4_addrs,
411 .user = OCP_USER_MPU | OCP_USER_SDMA,
412};
413
414/* timer4 slave port */
415static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
416 &omap2420_l4_core__timer4,
417}; 124};
418 125
419/* timer4 hwmod */ 126/* I2C2 */
420static struct omap_hwmod omap2420_timer4_hwmod = { 127static struct omap_hwmod omap2420_i2c2_hwmod = {
421 .name = "timer4", 128 .name = "i2c2",
422 .mpu_irqs = omap2_timer4_mpu_irqs, 129 .mpu_irqs = omap2_i2c2_mpu_irqs,
423 .main_clk = "gpt4_fck", 130 .sdma_reqs = omap2_i2c2_sdma_reqs,
131 .main_clk = "i2c2_fck",
424 .prcm = { 132 .prcm = {
425 .omap2 = { 133 .omap2 = {
426 .prcm_reg_id = 1,
427 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
428 .module_offs = CORE_MOD, 134 .module_offs = CORE_MOD,
429 .idlest_reg_id = 1,
430 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
431 },
432 },
433 .dev_attr = &capability_alwon_dev_attr,
434 .slaves = omap2420_timer4_slaves,
435 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
436 .class = &omap2xxx_timer_hwmod_class,
437};
438
439/* timer5 */
440static struct omap_hwmod omap2420_timer5_hwmod;
441
442/* l4_core -> timer5 */
443static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
444 .master = &omap2420_l4_core_hwmod,
445 .slave = &omap2420_timer5_hwmod,
446 .clk = "gpt5_ick",
447 .addr = omap2xxx_timer5_addrs,
448 .user = OCP_USER_MPU | OCP_USER_SDMA,
449};
450
451/* timer5 slave port */
452static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
453 &omap2420_l4_core__timer5,
454};
455
456/* timer5 hwmod */
457static struct omap_hwmod omap2420_timer5_hwmod = {
458 .name = "timer5",
459 .mpu_irqs = omap2_timer5_mpu_irqs,
460 .main_clk = "gpt5_fck",
461 .prcm = {
462 .omap2 = {
463 .prcm_reg_id = 1, 135 .prcm_reg_id = 1,
464 .module_bit = OMAP24XX_EN_GPT5_SHIFT, 136 .module_bit = OMAP2420_EN_I2C2_SHIFT,
465 .module_offs = CORE_MOD,
466 .idlest_reg_id = 1, 137 .idlest_reg_id = 1,
467 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, 138 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
468 }, 139 },
469 }, 140 },
470 .dev_attr = &capability_alwon_dev_attr, 141 .class = &i2c_class,
471 .slaves = omap2420_timer5_slaves, 142 .dev_attr = &i2c_dev_attr,
472 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), 143 .flags = HWMOD_16BIT_REG,
473 .class = &omap2xxx_timer_hwmod_class,
474};
475
476
477/* timer6 */
478static struct omap_hwmod omap2420_timer6_hwmod;
479
480/* l4_core -> timer6 */
481static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
482 .master = &omap2420_l4_core_hwmod,
483 .slave = &omap2420_timer6_hwmod,
484 .clk = "gpt6_ick",
485 .addr = omap2xxx_timer6_addrs,
486 .user = OCP_USER_MPU | OCP_USER_SDMA,
487};
488
489/* timer6 slave port */
490static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
491 &omap2420_l4_core__timer6,
492}; 144};
493 145
494/* timer6 hwmod */ 146/* dma attributes */
495static struct omap_hwmod omap2420_timer6_hwmod = { 147static struct omap_dma_dev_attr dma_dev_attr = {
496 .name = "timer6", 148 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
497 .mpu_irqs = omap2_timer6_mpu_irqs, 149 IS_CSSA_32 | IS_CDSA_32,
498 .main_clk = "gpt6_fck", 150 .lch_count = 32,
499 .prcm = {
500 .omap2 = {
501 .prcm_reg_id = 1,
502 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
503 .module_offs = CORE_MOD,
504 .idlest_reg_id = 1,
505 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
506 },
507 },
508 .dev_attr = &capability_alwon_dev_attr,
509 .slaves = omap2420_timer6_slaves,
510 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
511 .class = &omap2xxx_timer_hwmod_class,
512}; 151};
513 152
514/* timer7 */ 153static struct omap_hwmod omap2420_dma_system_hwmod = {
515static struct omap_hwmod omap2420_timer7_hwmod; 154 .name = "dma",
516 155 .class = &omap2xxx_dma_hwmod_class,
517/* l4_core -> timer7 */ 156 .mpu_irqs = omap2_dma_system_irqs,
518static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { 157 .main_clk = "core_l3_ck",
519 .master = &omap2420_l4_core_hwmod, 158 .dev_attr = &dma_dev_attr,
520 .slave = &omap2420_timer7_hwmod, 159 .flags = HWMOD_NO_IDLEST,
521 .clk = "gpt7_ick",
522 .addr = omap2xxx_timer7_addrs,
523 .user = OCP_USER_MPU | OCP_USER_SDMA,
524}; 160};
525 161
526/* timer7 slave port */ 162/* mailbox */
527static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { 163static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
528 &omap2420_l4_core__timer7, 164 { .name = "dsp", .irq = 26 },
165 { .name = "iva", .irq = 34 },
166 { .irq = -1 }
529}; 167};
530 168
531/* timer7 hwmod */ 169static struct omap_hwmod omap2420_mailbox_hwmod = {
532static struct omap_hwmod omap2420_timer7_hwmod = { 170 .name = "mailbox",
533 .name = "timer7", 171 .class = &omap2xxx_mailbox_hwmod_class,
534 .mpu_irqs = omap2_timer7_mpu_irqs, 172 .mpu_irqs = omap2420_mailbox_irqs,
535 .main_clk = "gpt7_fck", 173 .main_clk = "mailboxes_ick",
536 .prcm = { 174 .prcm = {
537 .omap2 = { 175 .omap2 = {
538 .prcm_reg_id = 1, 176 .prcm_reg_id = 1,
539 .module_bit = OMAP24XX_EN_GPT7_SHIFT, 177 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
540 .module_offs = CORE_MOD, 178 .module_offs = CORE_MOD,
541 .idlest_reg_id = 1, 179 .idlest_reg_id = 1,
542 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, 180 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
543 }, 181 },
544 }, 182 },
545 .dev_attr = &capability_alwon_dev_attr,
546 .slaves = omap2420_timer7_slaves,
547 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
548 .class = &omap2xxx_timer_hwmod_class,
549}; 183};
550 184
551/* timer8 */ 185/*
552static struct omap_hwmod omap2420_timer8_hwmod; 186 * 'mcbsp' class
187 * multi channel buffered serial port controller
188 */
553 189
554/* l4_core -> timer8 */ 190static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
555static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { 191 .name = "mcbsp",
556 .master = &omap2420_l4_core_hwmod,
557 .slave = &omap2420_timer8_hwmod,
558 .clk = "gpt8_ick",
559 .addr = omap2xxx_timer8_addrs,
560 .user = OCP_USER_MPU | OCP_USER_SDMA,
561}; 192};
562 193
563/* timer8 slave port */ 194/* mcbsp1 */
564static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { 195static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
565 &omap2420_l4_core__timer8, 196 { .name = "tx", .irq = 59 },
197 { .name = "rx", .irq = 60 },
198 { .irq = -1 }
566}; 199};
567 200
568/* timer8 hwmod */ 201static struct omap_hwmod omap2420_mcbsp1_hwmod = {
569static struct omap_hwmod omap2420_timer8_hwmod = { 202 .name = "mcbsp1",
570 .name = "timer8", 203 .class = &omap2420_mcbsp_hwmod_class,
571 .mpu_irqs = omap2_timer8_mpu_irqs, 204 .mpu_irqs = omap2420_mcbsp1_irqs,
572 .main_clk = "gpt8_fck", 205 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
206 .main_clk = "mcbsp1_fck",
573 .prcm = { 207 .prcm = {
574 .omap2 = { 208 .omap2 = {
575 .prcm_reg_id = 1, 209 .prcm_reg_id = 1,
576 .module_bit = OMAP24XX_EN_GPT8_SHIFT, 210 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
577 .module_offs = CORE_MOD, 211 .module_offs = CORE_MOD,
578 .idlest_reg_id = 1, 212 .idlest_reg_id = 1,
579 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, 213 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
580 }, 214 },
581 }, 215 },
582 .dev_attr = &capability_alwon_dev_attr,
583 .slaves = omap2420_timer8_slaves,
584 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
585 .class = &omap2xxx_timer_hwmod_class,
586};
587
588/* timer9 */
589static struct omap_hwmod omap2420_timer9_hwmod;
590
591/* l4_core -> timer9 */
592static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
593 .master = &omap2420_l4_core_hwmod,
594 .slave = &omap2420_timer9_hwmod,
595 .clk = "gpt9_ick",
596 .addr = omap2xxx_timer9_addrs,
597 .user = OCP_USER_MPU | OCP_USER_SDMA,
598}; 216};
599 217
600/* timer9 slave port */ 218/* mcbsp2 */
601static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { 219static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
602 &omap2420_l4_core__timer9, 220 { .name = "tx", .irq = 62 },
221 { .name = "rx", .irq = 63 },
222 { .irq = -1 }
603}; 223};
604 224
605/* timer9 hwmod */ 225static struct omap_hwmod omap2420_mcbsp2_hwmod = {
606static struct omap_hwmod omap2420_timer9_hwmod = { 226 .name = "mcbsp2",
607 .name = "timer9", 227 .class = &omap2420_mcbsp_hwmod_class,
608 .mpu_irqs = omap2_timer9_mpu_irqs, 228 .mpu_irqs = omap2420_mcbsp2_irqs,
609 .main_clk = "gpt9_fck", 229 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
230 .main_clk = "mcbsp2_fck",
610 .prcm = { 231 .prcm = {
611 .omap2 = { 232 .omap2 = {
612 .prcm_reg_id = 1, 233 .prcm_reg_id = 1,
613 .module_bit = OMAP24XX_EN_GPT9_SHIFT, 234 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
614 .module_offs = CORE_MOD, 235 .module_offs = CORE_MOD,
615 .idlest_reg_id = 1, 236 .idlest_reg_id = 1,
616 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, 237 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
617 }, 238 },
618 }, 239 },
619 .dev_attr = &capability_pwm_dev_attr,
620 .slaves = omap2420_timer9_slaves,
621 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
622 .class = &omap2xxx_timer_hwmod_class,
623}; 240};
624 241
625/* timer10 */ 242/*
626static struct omap_hwmod omap2420_timer10_hwmod; 243 * interfaces
244 */
627 245
628/* l4_core -> timer10 */ 246/* L4 CORE -> I2C1 interface */
629static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { 247static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
630 .master = &omap2420_l4_core_hwmod, 248 .master = &omap2xxx_l4_core_hwmod,
631 .slave = &omap2420_timer10_hwmod, 249 .slave = &omap2420_i2c1_hwmod,
632 .clk = "gpt10_ick", 250 .clk = "i2c1_ick",
633 .addr = omap2_timer10_addrs, 251 .addr = omap2_i2c1_addr_space,
634 .user = OCP_USER_MPU | OCP_USER_SDMA, 252 .user = OCP_USER_MPU | OCP_USER_SDMA,
635}; 253};
636 254
637/* timer10 slave port */ 255/* L4 CORE -> I2C2 interface */
638static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { 256static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
639 &omap2420_l4_core__timer10, 257 .master = &omap2xxx_l4_core_hwmod,
640}; 258 .slave = &omap2420_i2c2_hwmod,
641 259 .clk = "i2c2_ick",
642/* timer10 hwmod */ 260 .addr = omap2_i2c2_addr_space,
643static struct omap_hwmod omap2420_timer10_hwmod = { 261 .user = OCP_USER_MPU | OCP_USER_SDMA,
644 .name = "timer10",
645 .mpu_irqs = omap2_timer10_mpu_irqs,
646 .main_clk = "gpt10_fck",
647 .prcm = {
648 .omap2 = {
649 .prcm_reg_id = 1,
650 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
651 .module_offs = CORE_MOD,
652 .idlest_reg_id = 1,
653 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
654 },
655 },
656 .dev_attr = &capability_pwm_dev_attr,
657 .slaves = omap2420_timer10_slaves,
658 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
659 .class = &omap2xxx_timer_hwmod_class,
660}; 262};
661 263
662/* timer11 */ 264/* IVA <- L3 interface */
663static struct omap_hwmod omap2420_timer11_hwmod; 265static struct omap_hwmod_ocp_if omap2420_l3__iva = {
664 266 .master = &omap2xxx_l3_main_hwmod,
665/* l4_core -> timer11 */ 267 .slave = &omap2420_iva_hwmod,
666static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { 268 .clk = "core_l3_ck",
667 .master = &omap2420_l4_core_hwmod,
668 .slave = &omap2420_timer11_hwmod,
669 .clk = "gpt11_ick",
670 .addr = omap2_timer11_addrs,
671 .user = OCP_USER_MPU | OCP_USER_SDMA, 269 .user = OCP_USER_MPU | OCP_USER_SDMA,
672}; 270};
673 271
674/* timer11 slave port */ 272/* DSP <- L3 interface */
675static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { 273static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
676 &omap2420_l4_core__timer11, 274 .master = &omap2xxx_l3_main_hwmod,
275 .slave = &omap2420_dsp_hwmod,
276 .clk = "dsp_ick",
277 .user = OCP_USER_MPU | OCP_USER_SDMA,
677}; 278};
678 279
679/* timer11 hwmod */ 280static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
680static struct omap_hwmod omap2420_timer11_hwmod = { 281 {
681 .name = "timer11", 282 .pa_start = 0x48028000,
682 .mpu_irqs = omap2_timer11_mpu_irqs, 283 .pa_end = 0x48028000 + SZ_1K - 1,
683 .main_clk = "gpt11_fck", 284 .flags = ADDR_TYPE_RT
684 .prcm = {
685 .omap2 = {
686 .prcm_reg_id = 1,
687 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
688 .module_offs = CORE_MOD,
689 .idlest_reg_id = 1,
690 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
691 },
692 }, 285 },
693 .dev_attr = &capability_pwm_dev_attr, 286 { }
694 .slaves = omap2420_timer11_slaves,
695 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
696 .class = &omap2xxx_timer_hwmod_class,
697}; 287};
698 288
699/* timer12 */ 289/* l4_wkup -> timer1 */
700static struct omap_hwmod omap2420_timer12_hwmod; 290static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
701 291 .master = &omap2xxx_l4_wkup_hwmod,
702/* l4_core -> timer12 */ 292 .slave = &omap2xxx_timer1_hwmod,
703static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { 293 .clk = "gpt1_ick",
704 .master = &omap2420_l4_core_hwmod, 294 .addr = omap2420_timer1_addrs,
705 .slave = &omap2420_timer12_hwmod,
706 .clk = "gpt12_ick",
707 .addr = omap2xxx_timer12_addrs,
708 .user = OCP_USER_MPU | OCP_USER_SDMA, 295 .user = OCP_USER_MPU | OCP_USER_SDMA,
709}; 296};
710 297
711/* timer12 slave port */
712static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
713 &omap2420_l4_core__timer12,
714};
715
716/* timer12 hwmod */
717static struct omap_hwmod omap2420_timer12_hwmod = {
718 .name = "timer12",
719 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
720 .main_clk = "gpt12_fck",
721 .prcm = {
722 .omap2 = {
723 .prcm_reg_id = 1,
724 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
725 .module_offs = CORE_MOD,
726 .idlest_reg_id = 1,
727 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
728 },
729 },
730 .dev_attr = &capability_pwm_dev_attr,
731 .slaves = omap2420_timer12_slaves,
732 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
733 .class = &omap2xxx_timer_hwmod_class,
734};
735
736/* l4_wkup -> wd_timer2 */ 298/* l4_wkup -> wd_timer2 */
737static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { 299static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
738 { 300 {
@@ -744,363 +306,13 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
744}; 306};
745 307
746static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 308static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
747 .master = &omap2420_l4_wkup_hwmod, 309 .master = &omap2xxx_l4_wkup_hwmod,
748 .slave = &omap2420_wd_timer2_hwmod, 310 .slave = &omap2xxx_wd_timer2_hwmod,
749 .clk = "mpu_wdt_ick", 311 .clk = "mpu_wdt_ick",
750 .addr = omap2420_wd_timer2_addrs, 312 .addr = omap2420_wd_timer2_addrs,
751 .user = OCP_USER_MPU | OCP_USER_SDMA, 313 .user = OCP_USER_MPU | OCP_USER_SDMA,
752}; 314};
753 315
754/* wd_timer2 */
755static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
756 &omap2420_l4_wkup__wd_timer2,
757};
758
759static struct omap_hwmod omap2420_wd_timer2_hwmod = {
760 .name = "wd_timer2",
761 .class = &omap2xxx_wd_timer_hwmod_class,
762 .main_clk = "mpu_wdt_fck",
763 .prcm = {
764 .omap2 = {
765 .prcm_reg_id = 1,
766 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
767 .module_offs = WKUP_MOD,
768 .idlest_reg_id = 1,
769 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
770 },
771 },
772 .slaves = omap2420_wd_timer2_slaves,
773 .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves),
774};
775
776/* UART1 */
777
778static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
779 &omap2_l4_core__uart1,
780};
781
782static struct omap_hwmod omap2420_uart1_hwmod = {
783 .name = "uart1",
784 .mpu_irqs = omap2_uart1_mpu_irqs,
785 .sdma_reqs = omap2_uart1_sdma_reqs,
786 .main_clk = "uart1_fck",
787 .prcm = {
788 .omap2 = {
789 .module_offs = CORE_MOD,
790 .prcm_reg_id = 1,
791 .module_bit = OMAP24XX_EN_UART1_SHIFT,
792 .idlest_reg_id = 1,
793 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
794 },
795 },
796 .slaves = omap2420_uart1_slaves,
797 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
798 .class = &omap2_uart_class,
799};
800
801/* UART2 */
802
803static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
804 &omap2_l4_core__uart2,
805};
806
807static struct omap_hwmod omap2420_uart2_hwmod = {
808 .name = "uart2",
809 .mpu_irqs = omap2_uart2_mpu_irqs,
810 .sdma_reqs = omap2_uart2_sdma_reqs,
811 .main_clk = "uart2_fck",
812 .prcm = {
813 .omap2 = {
814 .module_offs = CORE_MOD,
815 .prcm_reg_id = 1,
816 .module_bit = OMAP24XX_EN_UART2_SHIFT,
817 .idlest_reg_id = 1,
818 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
819 },
820 },
821 .slaves = omap2420_uart2_slaves,
822 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
823 .class = &omap2_uart_class,
824};
825
826/* UART3 */
827
828static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
829 &omap2_l4_core__uart3,
830};
831
832static struct omap_hwmod omap2420_uart3_hwmod = {
833 .name = "uart3",
834 .mpu_irqs = omap2_uart3_mpu_irqs,
835 .sdma_reqs = omap2_uart3_sdma_reqs,
836 .main_clk = "uart3_fck",
837 .prcm = {
838 .omap2 = {
839 .module_offs = CORE_MOD,
840 .prcm_reg_id = 2,
841 .module_bit = OMAP24XX_EN_UART3_SHIFT,
842 .idlest_reg_id = 2,
843 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
844 },
845 },
846 .slaves = omap2420_uart3_slaves,
847 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
848 .class = &omap2_uart_class,
849};
850
851/* dss */
852/* dss master ports */
853static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
854 &omap2420_dss__l3,
855};
856
857/* l4_core -> dss */
858static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
859 .master = &omap2420_l4_core_hwmod,
860 .slave = &omap2420_dss_core_hwmod,
861 .clk = "dss_ick",
862 .addr = omap2_dss_addrs,
863 .fw = {
864 .omap2 = {
865 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
866 .flags = OMAP_FIREWALL_L4,
867 }
868 },
869 .user = OCP_USER_MPU | OCP_USER_SDMA,
870};
871
872/* dss slave ports */
873static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
874 &omap2420_l4_core__dss,
875};
876
877static struct omap_hwmod_opt_clk dss_opt_clks[] = {
878 /*
879 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
880 * driver does not use these clocks.
881 */
882 { .role = "tv_clk", .clk = "dss_54m_fck" },
883 { .role = "sys_clk", .clk = "dss2_fck" },
884};
885
886static struct omap_hwmod omap2420_dss_core_hwmod = {
887 .name = "dss_core",
888 .class = &omap2_dss_hwmod_class,
889 .main_clk = "dss1_fck", /* instead of dss_fck */
890 .sdma_reqs = omap2xxx_dss_sdma_chs,
891 .prcm = {
892 .omap2 = {
893 .prcm_reg_id = 1,
894 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
895 .module_offs = CORE_MOD,
896 .idlest_reg_id = 1,
897 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
898 },
899 },
900 .opt_clks = dss_opt_clks,
901 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
902 .slaves = omap2420_dss_slaves,
903 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
904 .masters = omap2420_dss_masters,
905 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
906 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
907};
908
909/* l4_core -> dss_dispc */
910static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
911 .master = &omap2420_l4_core_hwmod,
912 .slave = &omap2420_dss_dispc_hwmod,
913 .clk = "dss_ick",
914 .addr = omap2_dss_dispc_addrs,
915 .fw = {
916 .omap2 = {
917 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
918 .flags = OMAP_FIREWALL_L4,
919 }
920 },
921 .user = OCP_USER_MPU | OCP_USER_SDMA,
922};
923
924/* dss_dispc slave ports */
925static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
926 &omap2420_l4_core__dss_dispc,
927};
928
929static struct omap_hwmod omap2420_dss_dispc_hwmod = {
930 .name = "dss_dispc",
931 .class = &omap2_dispc_hwmod_class,
932 .mpu_irqs = omap2_dispc_irqs,
933 .main_clk = "dss1_fck",
934 .prcm = {
935 .omap2 = {
936 .prcm_reg_id = 1,
937 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
938 .module_offs = CORE_MOD,
939 .idlest_reg_id = 1,
940 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
941 },
942 },
943 .slaves = omap2420_dss_dispc_slaves,
944 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
945 .flags = HWMOD_NO_IDLEST,
946 .dev_attr = &omap2_3_dss_dispc_dev_attr
947};
948
949/* l4_core -> dss_rfbi */
950static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
951 .master = &omap2420_l4_core_hwmod,
952 .slave = &omap2420_dss_rfbi_hwmod,
953 .clk = "dss_ick",
954 .addr = omap2_dss_rfbi_addrs,
955 .fw = {
956 .omap2 = {
957 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
958 .flags = OMAP_FIREWALL_L4,
959 }
960 },
961 .user = OCP_USER_MPU | OCP_USER_SDMA,
962};
963
964/* dss_rfbi slave ports */
965static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
966 &omap2420_l4_core__dss_rfbi,
967};
968
969static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
970 { .role = "ick", .clk = "dss_ick" },
971};
972
973static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
974 .name = "dss_rfbi",
975 .class = &omap2_rfbi_hwmod_class,
976 .main_clk = "dss1_fck",
977 .prcm = {
978 .omap2 = {
979 .prcm_reg_id = 1,
980 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
981 .module_offs = CORE_MOD,
982 },
983 },
984 .opt_clks = dss_rfbi_opt_clks,
985 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
986 .slaves = omap2420_dss_rfbi_slaves,
987 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
988 .flags = HWMOD_NO_IDLEST,
989};
990
991/* l4_core -> dss_venc */
992static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
993 .master = &omap2420_l4_core_hwmod,
994 .slave = &omap2420_dss_venc_hwmod,
995 .clk = "dss_ick",
996 .addr = omap2_dss_venc_addrs,
997 .fw = {
998 .omap2 = {
999 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
1000 .flags = OMAP_FIREWALL_L4,
1001 }
1002 },
1003 .user = OCP_USER_MPU | OCP_USER_SDMA,
1004};
1005
1006/* dss_venc slave ports */
1007static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1008 &omap2420_l4_core__dss_venc,
1009};
1010
1011static struct omap_hwmod omap2420_dss_venc_hwmod = {
1012 .name = "dss_venc",
1013 .class = &omap2_venc_hwmod_class,
1014 .main_clk = "dss_54m_fck",
1015 .prcm = {
1016 .omap2 = {
1017 .prcm_reg_id = 1,
1018 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1019 .module_offs = CORE_MOD,
1020 },
1021 },
1022 .slaves = omap2420_dss_venc_slaves,
1023 .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves),
1024 .flags = HWMOD_NO_IDLEST,
1025};
1026
1027/* I2C common */
1028static struct omap_hwmod_class_sysconfig i2c_sysc = {
1029 .rev_offs = 0x00,
1030 .sysc_offs = 0x20,
1031 .syss_offs = 0x10,
1032 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1033 .sysc_fields = &omap_hwmod_sysc_type1,
1034};
1035
1036static struct omap_hwmod_class i2c_class = {
1037 .name = "i2c",
1038 .sysc = &i2c_sysc,
1039 .rev = OMAP_I2C_IP_VERSION_1,
1040 .reset = &omap_i2c_reset,
1041};
1042
1043static struct omap_i2c_dev_attr i2c_dev_attr = {
1044 .flags = OMAP_I2C_FLAG_NO_FIFO |
1045 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1046 OMAP_I2C_FLAG_16BIT_DATA_REG |
1047 OMAP_I2C_FLAG_BUS_SHIFT_2,
1048};
1049
1050/* I2C1 */
1051
1052static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1053 &omap2420_l4_core__i2c1,
1054};
1055
1056static struct omap_hwmod omap2420_i2c1_hwmod = {
1057 .name = "i2c1",
1058 .mpu_irqs = omap2_i2c1_mpu_irqs,
1059 .sdma_reqs = omap2_i2c1_sdma_reqs,
1060 .main_clk = "i2c1_fck",
1061 .prcm = {
1062 .omap2 = {
1063 .module_offs = CORE_MOD,
1064 .prcm_reg_id = 1,
1065 .module_bit = OMAP2420_EN_I2C1_SHIFT,
1066 .idlest_reg_id = 1,
1067 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
1068 },
1069 },
1070 .slaves = omap2420_i2c1_slaves,
1071 .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves),
1072 .class = &i2c_class,
1073 .dev_attr = &i2c_dev_attr,
1074 .flags = HWMOD_16BIT_REG,
1075};
1076
1077/* I2C2 */
1078
1079static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1080 &omap2420_l4_core__i2c2,
1081};
1082
1083static struct omap_hwmod omap2420_i2c2_hwmod = {
1084 .name = "i2c2",
1085 .mpu_irqs = omap2_i2c2_mpu_irqs,
1086 .sdma_reqs = omap2_i2c2_sdma_reqs,
1087 .main_clk = "i2c2_fck",
1088 .prcm = {
1089 .omap2 = {
1090 .module_offs = CORE_MOD,
1091 .prcm_reg_id = 1,
1092 .module_bit = OMAP2420_EN_I2C2_SHIFT,
1093 .idlest_reg_id = 1,
1094 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
1095 },
1096 },
1097 .slaves = omap2420_i2c2_slaves,
1098 .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves),
1099 .class = &i2c_class,
1100 .dev_attr = &i2c_dev_attr,
1101 .flags = HWMOD_16BIT_REG,
1102};
1103
1104/* l4_wkup -> gpio1 */ 316/* l4_wkup -> gpio1 */
1105static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { 317static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1106 { 318 {
@@ -1112,8 +324,8 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1112}; 324};
1113 325
1114static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { 326static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1115 .master = &omap2420_l4_wkup_hwmod, 327 .master = &omap2xxx_l4_wkup_hwmod,
1116 .slave = &omap2420_gpio1_hwmod, 328 .slave = &omap2xxx_gpio1_hwmod,
1117 .clk = "gpios_ick", 329 .clk = "gpios_ick",
1118 .addr = omap2420_gpio1_addr_space, 330 .addr = omap2420_gpio1_addr_space,
1119 .user = OCP_USER_MPU | OCP_USER_SDMA, 331 .user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1130,8 +342,8 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1130}; 342};
1131 343
1132static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { 344static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1133 .master = &omap2420_l4_wkup_hwmod, 345 .master = &omap2xxx_l4_wkup_hwmod,
1134 .slave = &omap2420_gpio2_hwmod, 346 .slave = &omap2xxx_gpio2_hwmod,
1135 .clk = "gpios_ick", 347 .clk = "gpios_ick",
1136 .addr = omap2420_gpio2_addr_space, 348 .addr = omap2420_gpio2_addr_space,
1137 .user = OCP_USER_MPU | OCP_USER_SDMA, 349 .user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1148,8 +360,8 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1148}; 360};
1149 361
1150static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { 362static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1151 .master = &omap2420_l4_wkup_hwmod, 363 .master = &omap2xxx_l4_wkup_hwmod,
1152 .slave = &omap2420_gpio3_hwmod, 364 .slave = &omap2xxx_gpio3_hwmod,
1153 .clk = "gpios_ick", 365 .clk = "gpios_ick",
1154 .addr = omap2420_gpio3_addr_space, 366 .addr = omap2420_gpio3_addr_space,
1155 .user = OCP_USER_MPU | OCP_USER_SDMA, 367 .user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1166,408 +378,100 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1166}; 378};
1167 379
1168static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { 380static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1169 .master = &omap2420_l4_wkup_hwmod, 381 .master = &omap2xxx_l4_wkup_hwmod,
1170 .slave = &omap2420_gpio4_hwmod, 382 .slave = &omap2xxx_gpio4_hwmod,
1171 .clk = "gpios_ick", 383 .clk = "gpios_ick",
1172 .addr = omap2420_gpio4_addr_space, 384 .addr = omap2420_gpio4_addr_space,
1173 .user = OCP_USER_MPU | OCP_USER_SDMA, 385 .user = OCP_USER_MPU | OCP_USER_SDMA,
1174}; 386};
1175 387
1176/* gpio dev_attr */
1177static struct omap_gpio_dev_attr gpio_dev_attr = {
1178 .bank_width = 32,
1179 .dbck_flag = false,
1180};
1181
1182/* gpio1 */
1183static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1184 &omap2420_l4_wkup__gpio1,
1185};
1186
1187static struct omap_hwmod omap2420_gpio1_hwmod = {
1188 .name = "gpio1",
1189 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1190 .mpu_irqs = omap2_gpio1_irqs,
1191 .main_clk = "gpios_fck",
1192 .prcm = {
1193 .omap2 = {
1194 .prcm_reg_id = 1,
1195 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1196 .module_offs = WKUP_MOD,
1197 .idlest_reg_id = 1,
1198 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1199 },
1200 },
1201 .slaves = omap2420_gpio1_slaves,
1202 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
1203 .class = &omap2xxx_gpio_hwmod_class,
1204 .dev_attr = &gpio_dev_attr,
1205};
1206
1207/* gpio2 */
1208static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1209 &omap2420_l4_wkup__gpio2,
1210};
1211
1212static struct omap_hwmod omap2420_gpio2_hwmod = {
1213 .name = "gpio2",
1214 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1215 .mpu_irqs = omap2_gpio2_irqs,
1216 .main_clk = "gpios_fck",
1217 .prcm = {
1218 .omap2 = {
1219 .prcm_reg_id = 1,
1220 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1221 .module_offs = WKUP_MOD,
1222 .idlest_reg_id = 1,
1223 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1224 },
1225 },
1226 .slaves = omap2420_gpio2_slaves,
1227 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
1228 .class = &omap2xxx_gpio_hwmod_class,
1229 .dev_attr = &gpio_dev_attr,
1230};
1231
1232/* gpio3 */
1233static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1234 &omap2420_l4_wkup__gpio3,
1235};
1236
1237static struct omap_hwmod omap2420_gpio3_hwmod = {
1238 .name = "gpio3",
1239 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1240 .mpu_irqs = omap2_gpio3_irqs,
1241 .main_clk = "gpios_fck",
1242 .prcm = {
1243 .omap2 = {
1244 .prcm_reg_id = 1,
1245 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1246 .module_offs = WKUP_MOD,
1247 .idlest_reg_id = 1,
1248 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1249 },
1250 },
1251 .slaves = omap2420_gpio3_slaves,
1252 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
1253 .class = &omap2xxx_gpio_hwmod_class,
1254 .dev_attr = &gpio_dev_attr,
1255};
1256
1257/* gpio4 */
1258static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1259 &omap2420_l4_wkup__gpio4,
1260};
1261
1262static struct omap_hwmod omap2420_gpio4_hwmod = {
1263 .name = "gpio4",
1264 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1265 .mpu_irqs = omap2_gpio4_irqs,
1266 .main_clk = "gpios_fck",
1267 .prcm = {
1268 .omap2 = {
1269 .prcm_reg_id = 1,
1270 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1271 .module_offs = WKUP_MOD,
1272 .idlest_reg_id = 1,
1273 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1274 },
1275 },
1276 .slaves = omap2420_gpio4_slaves,
1277 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
1278 .class = &omap2xxx_gpio_hwmod_class,
1279 .dev_attr = &gpio_dev_attr,
1280};
1281
1282/* dma attributes */
1283static struct omap_dma_dev_attr dma_dev_attr = {
1284 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1285 IS_CSSA_32 | IS_CDSA_32,
1286 .lch_count = 32,
1287};
1288
1289/* dma_system -> L3 */ 388/* dma_system -> L3 */
1290static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { 389static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1291 .master = &omap2420_dma_system_hwmod, 390 .master = &omap2420_dma_system_hwmod,
1292 .slave = &omap2420_l3_main_hwmod, 391 .slave = &omap2xxx_l3_main_hwmod,
1293 .clk = "core_l3_ck", 392 .clk = "core_l3_ck",
1294 .user = OCP_USER_MPU | OCP_USER_SDMA, 393 .user = OCP_USER_MPU | OCP_USER_SDMA,
1295}; 394};
1296 395
1297/* dma_system master ports */
1298static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
1299 &omap2420_dma_system__l3,
1300};
1301
1302/* l4_core -> dma_system */ 396/* l4_core -> dma_system */
1303static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { 397static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1304 .master = &omap2420_l4_core_hwmod, 398 .master = &omap2xxx_l4_core_hwmod,
1305 .slave = &omap2420_dma_system_hwmod, 399 .slave = &omap2420_dma_system_hwmod,
1306 .clk = "sdma_ick", 400 .clk = "sdma_ick",
1307 .addr = omap2_dma_system_addrs, 401 .addr = omap2_dma_system_addrs,
1308 .user = OCP_USER_MPU | OCP_USER_SDMA, 402 .user = OCP_USER_MPU | OCP_USER_SDMA,
1309}; 403};
1310 404
1311/* dma_system slave ports */
1312static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1313 &omap2420_l4_core__dma_system,
1314};
1315
1316static struct omap_hwmod omap2420_dma_system_hwmod = {
1317 .name = "dma",
1318 .class = &omap2xxx_dma_hwmod_class,
1319 .mpu_irqs = omap2_dma_system_irqs,
1320 .main_clk = "core_l3_ck",
1321 .slaves = omap2420_dma_system_slaves,
1322 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
1323 .masters = omap2420_dma_system_masters,
1324 .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters),
1325 .dev_attr = &dma_dev_attr,
1326 .flags = HWMOD_NO_IDLEST,
1327};
1328
1329/* mailbox */
1330static struct omap_hwmod omap2420_mailbox_hwmod;
1331static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1332 { .name = "dsp", .irq = 26 },
1333 { .name = "iva", .irq = 34 },
1334 { .irq = -1 }
1335};
1336
1337/* l4_core -> mailbox */ 405/* l4_core -> mailbox */
1338static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { 406static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1339 .master = &omap2420_l4_core_hwmod, 407 .master = &omap2xxx_l4_core_hwmod,
1340 .slave = &omap2420_mailbox_hwmod, 408 .slave = &omap2420_mailbox_hwmod,
1341 .addr = omap2_mailbox_addrs, 409 .addr = omap2_mailbox_addrs,
1342 .user = OCP_USER_MPU | OCP_USER_SDMA, 410 .user = OCP_USER_MPU | OCP_USER_SDMA,
1343}; 411};
1344 412
1345/* mailbox slave ports */
1346static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1347 &omap2420_l4_core__mailbox,
1348};
1349
1350static struct omap_hwmod omap2420_mailbox_hwmod = {
1351 .name = "mailbox",
1352 .class = &omap2xxx_mailbox_hwmod_class,
1353 .mpu_irqs = omap2420_mailbox_irqs,
1354 .main_clk = "mailboxes_ick",
1355 .prcm = {
1356 .omap2 = {
1357 .prcm_reg_id = 1,
1358 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1359 .module_offs = CORE_MOD,
1360 .idlest_reg_id = 1,
1361 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1362 },
1363 },
1364 .slaves = omap2420_mailbox_slaves,
1365 .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
1366};
1367
1368/* mcspi1 */
1369static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1370 &omap2420_l4_core__mcspi1,
1371};
1372
1373static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1374 .num_chipselect = 4,
1375};
1376
1377static struct omap_hwmod omap2420_mcspi1_hwmod = {
1378 .name = "mcspi1_hwmod",
1379 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1380 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1381 .main_clk = "mcspi1_fck",
1382 .prcm = {
1383 .omap2 = {
1384 .module_offs = CORE_MOD,
1385 .prcm_reg_id = 1,
1386 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1387 .idlest_reg_id = 1,
1388 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1389 },
1390 },
1391 .slaves = omap2420_mcspi1_slaves,
1392 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
1393 .class = &omap2xxx_mcspi_class,
1394 .dev_attr = &omap_mcspi1_dev_attr,
1395};
1396
1397/* mcspi2 */
1398static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1399 &omap2420_l4_core__mcspi2,
1400};
1401
1402static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1403 .num_chipselect = 2,
1404};
1405
1406static struct omap_hwmod omap2420_mcspi2_hwmod = {
1407 .name = "mcspi2_hwmod",
1408 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1409 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1410 .main_clk = "mcspi2_fck",
1411 .prcm = {
1412 .omap2 = {
1413 .module_offs = CORE_MOD,
1414 .prcm_reg_id = 1,
1415 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1416 .idlest_reg_id = 1,
1417 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1418 },
1419 },
1420 .slaves = omap2420_mcspi2_slaves,
1421 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
1422 .class = &omap2xxx_mcspi_class,
1423 .dev_attr = &omap_mcspi2_dev_attr,
1424};
1425
1426/*
1427 * 'mcbsp' class
1428 * multi channel buffered serial port controller
1429 */
1430
1431static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
1432 .name = "mcbsp",
1433};
1434
1435/* mcbsp1 */
1436static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
1437 { .name = "tx", .irq = 59 },
1438 { .name = "rx", .irq = 60 },
1439 { .irq = -1 }
1440};
1441
1442/* l4_core -> mcbsp1 */ 413/* l4_core -> mcbsp1 */
1443static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { 414static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
1444 .master = &omap2420_l4_core_hwmod, 415 .master = &omap2xxx_l4_core_hwmod,
1445 .slave = &omap2420_mcbsp1_hwmod, 416 .slave = &omap2420_mcbsp1_hwmod,
1446 .clk = "mcbsp1_ick", 417 .clk = "mcbsp1_ick",
1447 .addr = omap2_mcbsp1_addrs, 418 .addr = omap2_mcbsp1_addrs,
1448 .user = OCP_USER_MPU | OCP_USER_SDMA, 419 .user = OCP_USER_MPU | OCP_USER_SDMA,
1449}; 420};
1450 421
1451/* mcbsp1 slave ports */
1452static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
1453 &omap2420_l4_core__mcbsp1,
1454};
1455
1456static struct omap_hwmod omap2420_mcbsp1_hwmod = {
1457 .name = "mcbsp1",
1458 .class = &omap2420_mcbsp_hwmod_class,
1459 .mpu_irqs = omap2420_mcbsp1_irqs,
1460 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1461 .main_clk = "mcbsp1_fck",
1462 .prcm = {
1463 .omap2 = {
1464 .prcm_reg_id = 1,
1465 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1466 .module_offs = CORE_MOD,
1467 .idlest_reg_id = 1,
1468 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1469 },
1470 },
1471 .slaves = omap2420_mcbsp1_slaves,
1472 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves),
1473};
1474
1475/* mcbsp2 */
1476static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
1477 { .name = "tx", .irq = 62 },
1478 { .name = "rx", .irq = 63 },
1479 { .irq = -1 }
1480};
1481
1482/* l4_core -> mcbsp2 */ 422/* l4_core -> mcbsp2 */
1483static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { 423static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
1484 .master = &omap2420_l4_core_hwmod, 424 .master = &omap2xxx_l4_core_hwmod,
1485 .slave = &omap2420_mcbsp2_hwmod, 425 .slave = &omap2420_mcbsp2_hwmod,
1486 .clk = "mcbsp2_ick", 426 .clk = "mcbsp2_ick",
1487 .addr = omap2xxx_mcbsp2_addrs, 427 .addr = omap2xxx_mcbsp2_addrs,
1488 .user = OCP_USER_MPU | OCP_USER_SDMA, 428 .user = OCP_USER_MPU | OCP_USER_SDMA,
1489}; 429};
1490 430
1491/* mcbsp2 slave ports */ 431static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
1492static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { 432 &omap2xxx_l3_main__l4_core,
433 &omap2xxx_mpu__l3_main,
434 &omap2xxx_dss__l3,
435 &omap2xxx_l4_core__mcspi1,
436 &omap2xxx_l4_core__mcspi2,
437 &omap2xxx_l4_core__l4_wkup,
438 &omap2_l4_core__uart1,
439 &omap2_l4_core__uart2,
440 &omap2_l4_core__uart3,
441 &omap2420_l4_core__i2c1,
442 &omap2420_l4_core__i2c2,
443 &omap2420_l3__iva,
444 &omap2420_l3__dsp,
445 &omap2420_l4_wkup__timer1,
446 &omap2xxx_l4_core__timer2,
447 &omap2xxx_l4_core__timer3,
448 &omap2xxx_l4_core__timer4,
449 &omap2xxx_l4_core__timer5,
450 &omap2xxx_l4_core__timer6,
451 &omap2xxx_l4_core__timer7,
452 &omap2xxx_l4_core__timer8,
453 &omap2xxx_l4_core__timer9,
454 &omap2xxx_l4_core__timer10,
455 &omap2xxx_l4_core__timer11,
456 &omap2xxx_l4_core__timer12,
457 &omap2420_l4_wkup__wd_timer2,
458 &omap2xxx_l4_core__dss,
459 &omap2xxx_l4_core__dss_dispc,
460 &omap2xxx_l4_core__dss_rfbi,
461 &omap2xxx_l4_core__dss_venc,
462 &omap2420_l4_wkup__gpio1,
463 &omap2420_l4_wkup__gpio2,
464 &omap2420_l4_wkup__gpio3,
465 &omap2420_l4_wkup__gpio4,
466 &omap2420_dma_system__l3,
467 &omap2420_l4_core__dma_system,
468 &omap2420_l4_core__mailbox,
469 &omap2420_l4_core__mcbsp1,
1493 &omap2420_l4_core__mcbsp2, 470 &omap2420_l4_core__mcbsp2,
1494};
1495
1496static struct omap_hwmod omap2420_mcbsp2_hwmod = {
1497 .name = "mcbsp2",
1498 .class = &omap2420_mcbsp_hwmod_class,
1499 .mpu_irqs = omap2420_mcbsp2_irqs,
1500 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1501 .main_clk = "mcbsp2_fck",
1502 .prcm = {
1503 .omap2 = {
1504 .prcm_reg_id = 1,
1505 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1506 .module_offs = CORE_MOD,
1507 .idlest_reg_id = 1,
1508 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1509 },
1510 },
1511 .slaves = omap2420_mcbsp2_slaves,
1512 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves),
1513};
1514
1515static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1516 &omap2420_l3_main_hwmod,
1517 &omap2420_l4_core_hwmod,
1518 &omap2420_l4_wkup_hwmod,
1519 &omap2420_mpu_hwmod,
1520 &omap2420_iva_hwmod,
1521
1522 &omap2420_timer1_hwmod,
1523 &omap2420_timer2_hwmod,
1524 &omap2420_timer3_hwmod,
1525 &omap2420_timer4_hwmod,
1526 &omap2420_timer5_hwmod,
1527 &omap2420_timer6_hwmod,
1528 &omap2420_timer7_hwmod,
1529 &omap2420_timer8_hwmod,
1530 &omap2420_timer9_hwmod,
1531 &omap2420_timer10_hwmod,
1532 &omap2420_timer11_hwmod,
1533 &omap2420_timer12_hwmod,
1534
1535 &omap2420_wd_timer2_hwmod,
1536 &omap2420_uart1_hwmod,
1537 &omap2420_uart2_hwmod,
1538 &omap2420_uart3_hwmod,
1539 /* dss class */
1540 &omap2420_dss_core_hwmod,
1541 &omap2420_dss_dispc_hwmod,
1542 &omap2420_dss_rfbi_hwmod,
1543 &omap2420_dss_venc_hwmod,
1544 /* i2c class */
1545 &omap2420_i2c1_hwmod,
1546 &omap2420_i2c2_hwmod,
1547
1548 /* gpio class */
1549 &omap2420_gpio1_hwmod,
1550 &omap2420_gpio2_hwmod,
1551 &omap2420_gpio3_hwmod,
1552 &omap2420_gpio4_hwmod,
1553
1554 /* dma_system class*/
1555 &omap2420_dma_system_hwmod,
1556
1557 /* mailbox class */
1558 &omap2420_mailbox_hwmod,
1559
1560 /* mcbsp class */
1561 &omap2420_mcbsp1_hwmod,
1562 &omap2420_mcbsp2_hwmod,
1563
1564 /* mcspi class */
1565 &omap2420_mcspi1_hwmod,
1566 &omap2420_mcspi2_hwmod,
1567 NULL, 471 NULL,
1568}; 472};
1569 473
1570int __init omap2420_hwmod_init(void) 474int __init omap2420_hwmod_init(void)
1571{ 475{
1572 return omap_hwmod_register(omap2420_hwmods); 476 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
1573} 477}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 04a3885f447..71d9f8824f9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -2,6 +2,7 @@
2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips 2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -33,1044 +34,29 @@
33/* 34/*
34 * OMAP2430 hardware module integration data 35 * OMAP2430 hardware module integration data
35 * 36 *
36 * ALl of the data in this section should be autogeneratable from the 37 * All of the data in this section should be autogeneratable from the
37 * TI hardware database or other technical documentation. Data that 38 * TI hardware database or other technical documentation. Data that
38 * is driver-specific or driver-kernel integration-specific belongs 39 * is driver-specific or driver-kernel integration-specific belongs
39 * elsewhere. 40 * elsewhere.
40 */ 41 */
41 42
42static struct omap_hwmod omap2430_mpu_hwmod;
43static struct omap_hwmod omap2430_iva_hwmod;
44static struct omap_hwmod omap2430_l3_main_hwmod;
45static struct omap_hwmod omap2430_l4_core_hwmod;
46static struct omap_hwmod omap2430_dss_core_hwmod;
47static struct omap_hwmod omap2430_dss_dispc_hwmod;
48static struct omap_hwmod omap2430_dss_rfbi_hwmod;
49static struct omap_hwmod omap2430_dss_venc_hwmod;
50static struct omap_hwmod omap2430_wd_timer2_hwmod;
51static struct omap_hwmod omap2430_gpio1_hwmod;
52static struct omap_hwmod omap2430_gpio2_hwmod;
53static struct omap_hwmod omap2430_gpio3_hwmod;
54static struct omap_hwmod omap2430_gpio4_hwmod;
55static struct omap_hwmod omap2430_gpio5_hwmod;
56static struct omap_hwmod omap2430_dma_system_hwmod;
57static struct omap_hwmod omap2430_mcbsp1_hwmod;
58static struct omap_hwmod omap2430_mcbsp2_hwmod;
59static struct omap_hwmod omap2430_mcbsp3_hwmod;
60static struct omap_hwmod omap2430_mcbsp4_hwmod;
61static struct omap_hwmod omap2430_mcbsp5_hwmod;
62static struct omap_hwmod omap2430_mcspi1_hwmod;
63static struct omap_hwmod omap2430_mcspi2_hwmod;
64static struct omap_hwmod omap2430_mcspi3_hwmod;
65static struct omap_hwmod omap2430_mmc1_hwmod;
66static struct omap_hwmod omap2430_mmc2_hwmod;
67
68/* L3 -> L4_CORE interface */
69static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
70 .master = &omap2430_l3_main_hwmod,
71 .slave = &omap2430_l4_core_hwmod,
72 .user = OCP_USER_MPU | OCP_USER_SDMA,
73};
74
75/* MPU -> L3 interface */
76static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
77 .master = &omap2430_mpu_hwmod,
78 .slave = &omap2430_l3_main_hwmod,
79 .user = OCP_USER_MPU,
80};
81
82/* Slave interfaces on the L3 interconnect */
83static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
84 &omap2430_mpu__l3_main,
85};
86
87/* DSS -> l3 */
88static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
89 .master = &omap2430_dss_core_hwmod,
90 .slave = &omap2430_l3_main_hwmod,
91 .fw = {
92 .omap2 = {
93 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
94 .flags = OMAP_FIREWALL_L3,
95 }
96 },
97 .user = OCP_USER_MPU | OCP_USER_SDMA,
98};
99
100/* Master interfaces on the L3 interconnect */
101static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
102 &omap2430_l3_main__l4_core,
103};
104
105/* L3 */
106static struct omap_hwmod omap2430_l3_main_hwmod = {
107 .name = "l3_main",
108 .class = &l3_hwmod_class,
109 .masters = omap2430_l3_main_masters,
110 .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters),
111 .slaves = omap2430_l3_main_slaves,
112 .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves),
113 .flags = HWMOD_NO_IDLEST,
114};
115
116static struct omap_hwmod omap2430_l4_wkup_hwmod;
117static struct omap_hwmod omap2430_uart1_hwmod;
118static struct omap_hwmod omap2430_uart2_hwmod;
119static struct omap_hwmod omap2430_uart3_hwmod;
120static struct omap_hwmod omap2430_i2c1_hwmod;
121static struct omap_hwmod omap2430_i2c2_hwmod;
122
123static struct omap_hwmod omap2430_usbhsotg_hwmod;
124
125/* l3_core -> usbhsotg interface */
126static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
127 .master = &omap2430_usbhsotg_hwmod,
128 .slave = &omap2430_l3_main_hwmod,
129 .clk = "core_l3_ck",
130 .user = OCP_USER_MPU,
131};
132
133/* L4 CORE -> I2C1 interface */
134static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
135 .master = &omap2430_l4_core_hwmod,
136 .slave = &omap2430_i2c1_hwmod,
137 .clk = "i2c1_ick",
138 .addr = omap2_i2c1_addr_space,
139 .user = OCP_USER_MPU | OCP_USER_SDMA,
140};
141
142/* L4 CORE -> I2C2 interface */
143static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
144 .master = &omap2430_l4_core_hwmod,
145 .slave = &omap2430_i2c2_hwmod,
146 .clk = "i2c2_ick",
147 .addr = omap2_i2c2_addr_space,
148 .user = OCP_USER_MPU | OCP_USER_SDMA,
149};
150
151/* L4_CORE -> L4_WKUP interface */
152static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
153 .master = &omap2430_l4_core_hwmod,
154 .slave = &omap2430_l4_wkup_hwmod,
155 .user = OCP_USER_MPU | OCP_USER_SDMA,
156};
157
158/* L4 CORE -> UART1 interface */
159static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
160 .master = &omap2430_l4_core_hwmod,
161 .slave = &omap2430_uart1_hwmod,
162 .clk = "uart1_ick",
163 .addr = omap2xxx_uart1_addr_space,
164 .user = OCP_USER_MPU | OCP_USER_SDMA,
165};
166
167/* L4 CORE -> UART2 interface */
168static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
169 .master = &omap2430_l4_core_hwmod,
170 .slave = &omap2430_uart2_hwmod,
171 .clk = "uart2_ick",
172 .addr = omap2xxx_uart2_addr_space,
173 .user = OCP_USER_MPU | OCP_USER_SDMA,
174};
175
176/* L4 PER -> UART3 interface */
177static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
178 .master = &omap2430_l4_core_hwmod,
179 .slave = &omap2430_uart3_hwmod,
180 .clk = "uart3_ick",
181 .addr = omap2xxx_uart3_addr_space,
182 .user = OCP_USER_MPU | OCP_USER_SDMA,
183};
184
185/* 43/*
186* usbhsotg interface data 44 * IP blocks
187*/
188static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
189 {
190 .pa_start = OMAP243X_HS_BASE,
191 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
192 .flags = ADDR_TYPE_RT
193 },
194 { }
195};
196
197/* l4_core ->usbhsotg interface */
198static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
199 .master = &omap2430_l4_core_hwmod,
200 .slave = &omap2430_usbhsotg_hwmod,
201 .clk = "usb_l4_ick",
202 .addr = omap2430_usbhsotg_addrs,
203 .user = OCP_USER_MPU,
204};
205
206static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
207 &omap2430_usbhsotg__l3,
208};
209
210static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
211 &omap2430_l4_core__usbhsotg,
212};
213
214/* L4 CORE -> MMC1 interface */
215static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
216 .master = &omap2430_l4_core_hwmod,
217 .slave = &omap2430_mmc1_hwmod,
218 .clk = "mmchs1_ick",
219 .addr = omap2430_mmc1_addr_space,
220 .user = OCP_USER_MPU | OCP_USER_SDMA,
221};
222
223/* L4 CORE -> MMC2 interface */
224static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
225 .master = &omap2430_l4_core_hwmod,
226 .slave = &omap2430_mmc2_hwmod,
227 .clk = "mmchs2_ick",
228 .addr = omap2430_mmc2_addr_space,
229 .user = OCP_USER_MPU | OCP_USER_SDMA,
230};
231
232/* Slave interfaces on the L4_CORE interconnect */
233static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
234 &omap2430_l3_main__l4_core,
235};
236
237/* Master interfaces on the L4_CORE interconnect */
238static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
239 &omap2430_l4_core__l4_wkup,
240 &omap2430_l4_core__mmc1,
241 &omap2430_l4_core__mmc2,
242};
243
244/* L4 CORE */
245static struct omap_hwmod omap2430_l4_core_hwmod = {
246 .name = "l4_core",
247 .class = &l4_hwmod_class,
248 .masters = omap2430_l4_core_masters,
249 .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
250 .slaves = omap2430_l4_core_slaves,
251 .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves),
252 .flags = HWMOD_NO_IDLEST,
253};
254
255/* Slave interfaces on the L4_WKUP interconnect */
256static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
257 &omap2430_l4_core__l4_wkup,
258 &omap2_l4_core__uart1,
259 &omap2_l4_core__uart2,
260 &omap2_l4_core__uart3,
261};
262
263/* Master interfaces on the L4_WKUP interconnect */
264static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
265};
266
267/* l4 core -> mcspi1 interface */
268static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
269 .master = &omap2430_l4_core_hwmod,
270 .slave = &omap2430_mcspi1_hwmod,
271 .clk = "mcspi1_ick",
272 .addr = omap2_mcspi1_addr_space,
273 .user = OCP_USER_MPU | OCP_USER_SDMA,
274};
275
276/* l4 core -> mcspi2 interface */
277static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
278 .master = &omap2430_l4_core_hwmod,
279 .slave = &omap2430_mcspi2_hwmod,
280 .clk = "mcspi2_ick",
281 .addr = omap2_mcspi2_addr_space,
282 .user = OCP_USER_MPU | OCP_USER_SDMA,
283};
284
285/* l4 core -> mcspi3 interface */
286static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
287 .master = &omap2430_l4_core_hwmod,
288 .slave = &omap2430_mcspi3_hwmod,
289 .clk = "mcspi3_ick",
290 .addr = omap2430_mcspi3_addr_space,
291 .user = OCP_USER_MPU | OCP_USER_SDMA,
292};
293
294/* L4 WKUP */
295static struct omap_hwmod omap2430_l4_wkup_hwmod = {
296 .name = "l4_wkup",
297 .class = &l4_hwmod_class,
298 .masters = omap2430_l4_wkup_masters,
299 .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
300 .slaves = omap2430_l4_wkup_slaves,
301 .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves),
302 .flags = HWMOD_NO_IDLEST,
303};
304
305/* Master interfaces on the MPU device */
306static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
307 &omap2430_mpu__l3_main,
308};
309
310/* MPU */
311static struct omap_hwmod omap2430_mpu_hwmod = {
312 .name = "mpu",
313 .class = &mpu_hwmod_class,
314 .main_clk = "mpu_ck",
315 .masters = omap2430_mpu_masters,
316 .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters),
317};
318
319/*
320 * IVA2_1 interface data
321 */ 45 */
322 46
323/* IVA2 <- L3 interface */ 47/* IVA2 (IVA2) */
324static struct omap_hwmod_ocp_if omap2430_l3__iva = { 48static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
325 .master = &omap2430_l3_main_hwmod, 49 { .name = "logic", .rst_shift = 0 },
326 .slave = &omap2430_iva_hwmod, 50 { .name = "mmu", .rst_shift = 1 },
327 .clk = "dsp_fck",
328 .user = OCP_USER_MPU | OCP_USER_SDMA,
329};
330
331static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
332 &omap2430_l3__iva,
333}; 51};
334 52
335/*
336 * IVA2 (IVA2)
337 */
338
339static struct omap_hwmod omap2430_iva_hwmod = { 53static struct omap_hwmod omap2430_iva_hwmod = {
340 .name = "iva", 54 .name = "iva",
341 .class = &iva_hwmod_class, 55 .class = &iva_hwmod_class,
342 .masters = omap2430_iva_masters, 56 .clkdm_name = "dsp_clkdm",
343 .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), 57 .rst_lines = omap2430_iva_resets,
344}; 58 .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
345 59 .main_clk = "dsp_fck",
346/* always-on timers dev attribute */
347static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
348 .timer_capability = OMAP_TIMER_ALWON,
349};
350
351/* pwm timers dev attribute */
352static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
353 .timer_capability = OMAP_TIMER_HAS_PWM,
354};
355
356/* timer1 */
357static struct omap_hwmod omap2430_timer1_hwmod;
358
359static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
360 {
361 .pa_start = 0x49018000,
362 .pa_end = 0x49018000 + SZ_1K - 1,
363 .flags = ADDR_TYPE_RT
364 },
365 { }
366};
367
368/* l4_wkup -> timer1 */
369static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
370 .master = &omap2430_l4_wkup_hwmod,
371 .slave = &omap2430_timer1_hwmod,
372 .clk = "gpt1_ick",
373 .addr = omap2430_timer1_addrs,
374 .user = OCP_USER_MPU | OCP_USER_SDMA,
375};
376
377/* timer1 slave port */
378static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
379 &omap2430_l4_wkup__timer1,
380};
381
382/* timer1 hwmod */
383static struct omap_hwmod omap2430_timer1_hwmod = {
384 .name = "timer1",
385 .mpu_irqs = omap2_timer1_mpu_irqs,
386 .main_clk = "gpt1_fck",
387 .prcm = {
388 .omap2 = {
389 .prcm_reg_id = 1,
390 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
391 .module_offs = WKUP_MOD,
392 .idlest_reg_id = 1,
393 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
394 },
395 },
396 .dev_attr = &capability_alwon_dev_attr,
397 .slaves = omap2430_timer1_slaves,
398 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
399 .class = &omap2xxx_timer_hwmod_class,
400};
401
402/* timer2 */
403static struct omap_hwmod omap2430_timer2_hwmod;
404
405/* l4_core -> timer2 */
406static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
407 .master = &omap2430_l4_core_hwmod,
408 .slave = &omap2430_timer2_hwmod,
409 .clk = "gpt2_ick",
410 .addr = omap2xxx_timer2_addrs,
411 .user = OCP_USER_MPU | OCP_USER_SDMA,
412};
413
414/* timer2 slave port */
415static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
416 &omap2430_l4_core__timer2,
417};
418
419/* timer2 hwmod */
420static struct omap_hwmod omap2430_timer2_hwmod = {
421 .name = "timer2",
422 .mpu_irqs = omap2_timer2_mpu_irqs,
423 .main_clk = "gpt2_fck",
424 .prcm = {
425 .omap2 = {
426 .prcm_reg_id = 1,
427 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
428 .module_offs = CORE_MOD,
429 .idlest_reg_id = 1,
430 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
431 },
432 },
433 .dev_attr = &capability_alwon_dev_attr,
434 .slaves = omap2430_timer2_slaves,
435 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
436 .class = &omap2xxx_timer_hwmod_class,
437};
438
439/* timer3 */
440static struct omap_hwmod omap2430_timer3_hwmod;
441
442/* l4_core -> timer3 */
443static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
444 .master = &omap2430_l4_core_hwmod,
445 .slave = &omap2430_timer3_hwmod,
446 .clk = "gpt3_ick",
447 .addr = omap2xxx_timer3_addrs,
448 .user = OCP_USER_MPU | OCP_USER_SDMA,
449};
450
451/* timer3 slave port */
452static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
453 &omap2430_l4_core__timer3,
454};
455
456/* timer3 hwmod */
457static struct omap_hwmod omap2430_timer3_hwmod = {
458 .name = "timer3",
459 .mpu_irqs = omap2_timer3_mpu_irqs,
460 .main_clk = "gpt3_fck",
461 .prcm = {
462 .omap2 = {
463 .prcm_reg_id = 1,
464 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
465 .module_offs = CORE_MOD,
466 .idlest_reg_id = 1,
467 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
468 },
469 },
470 .dev_attr = &capability_alwon_dev_attr,
471 .slaves = omap2430_timer3_slaves,
472 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
473 .class = &omap2xxx_timer_hwmod_class,
474};
475
476/* timer4 */
477static struct omap_hwmod omap2430_timer4_hwmod;
478
479/* l4_core -> timer4 */
480static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
481 .master = &omap2430_l4_core_hwmod,
482 .slave = &omap2430_timer4_hwmod,
483 .clk = "gpt4_ick",
484 .addr = omap2xxx_timer4_addrs,
485 .user = OCP_USER_MPU | OCP_USER_SDMA,
486};
487
488/* timer4 slave port */
489static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
490 &omap2430_l4_core__timer4,
491};
492
493/* timer4 hwmod */
494static struct omap_hwmod omap2430_timer4_hwmod = {
495 .name = "timer4",
496 .mpu_irqs = omap2_timer4_mpu_irqs,
497 .main_clk = "gpt4_fck",
498 .prcm = {
499 .omap2 = {
500 .prcm_reg_id = 1,
501 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
502 .module_offs = CORE_MOD,
503 .idlest_reg_id = 1,
504 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
505 },
506 },
507 .dev_attr = &capability_alwon_dev_attr,
508 .slaves = omap2430_timer4_slaves,
509 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
510 .class = &omap2xxx_timer_hwmod_class,
511};
512
513/* timer5 */
514static struct omap_hwmod omap2430_timer5_hwmod;
515
516/* l4_core -> timer5 */
517static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
518 .master = &omap2430_l4_core_hwmod,
519 .slave = &omap2430_timer5_hwmod,
520 .clk = "gpt5_ick",
521 .addr = omap2xxx_timer5_addrs,
522 .user = OCP_USER_MPU | OCP_USER_SDMA,
523};
524
525/* timer5 slave port */
526static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
527 &omap2430_l4_core__timer5,
528};
529
530/* timer5 hwmod */
531static struct omap_hwmod omap2430_timer5_hwmod = {
532 .name = "timer5",
533 .mpu_irqs = omap2_timer5_mpu_irqs,
534 .main_clk = "gpt5_fck",
535 .prcm = {
536 .omap2 = {
537 .prcm_reg_id = 1,
538 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
539 .module_offs = CORE_MOD,
540 .idlest_reg_id = 1,
541 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
542 },
543 },
544 .dev_attr = &capability_alwon_dev_attr,
545 .slaves = omap2430_timer5_slaves,
546 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
547 .class = &omap2xxx_timer_hwmod_class,
548};
549
550/* timer6 */
551static struct omap_hwmod omap2430_timer6_hwmod;
552
553/* l4_core -> timer6 */
554static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
555 .master = &omap2430_l4_core_hwmod,
556 .slave = &omap2430_timer6_hwmod,
557 .clk = "gpt6_ick",
558 .addr = omap2xxx_timer6_addrs,
559 .user = OCP_USER_MPU | OCP_USER_SDMA,
560};
561
562/* timer6 slave port */
563static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
564 &omap2430_l4_core__timer6,
565};
566
567/* timer6 hwmod */
568static struct omap_hwmod omap2430_timer6_hwmod = {
569 .name = "timer6",
570 .mpu_irqs = omap2_timer6_mpu_irqs,
571 .main_clk = "gpt6_fck",
572 .prcm = {
573 .omap2 = {
574 .prcm_reg_id = 1,
575 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
576 .module_offs = CORE_MOD,
577 .idlest_reg_id = 1,
578 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
579 },
580 },
581 .dev_attr = &capability_alwon_dev_attr,
582 .slaves = omap2430_timer6_slaves,
583 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
584 .class = &omap2xxx_timer_hwmod_class,
585};
586
587/* timer7 */
588static struct omap_hwmod omap2430_timer7_hwmod;
589
590/* l4_core -> timer7 */
591static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
592 .master = &omap2430_l4_core_hwmod,
593 .slave = &omap2430_timer7_hwmod,
594 .clk = "gpt7_ick",
595 .addr = omap2xxx_timer7_addrs,
596 .user = OCP_USER_MPU | OCP_USER_SDMA,
597};
598
599/* timer7 slave port */
600static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
601 &omap2430_l4_core__timer7,
602};
603
604/* timer7 hwmod */
605static struct omap_hwmod omap2430_timer7_hwmod = {
606 .name = "timer7",
607 .mpu_irqs = omap2_timer7_mpu_irqs,
608 .main_clk = "gpt7_fck",
609 .prcm = {
610 .omap2 = {
611 .prcm_reg_id = 1,
612 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
613 .module_offs = CORE_MOD,
614 .idlest_reg_id = 1,
615 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
616 },
617 },
618 .dev_attr = &capability_alwon_dev_attr,
619 .slaves = omap2430_timer7_slaves,
620 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
621 .class = &omap2xxx_timer_hwmod_class,
622};
623
624/* timer8 */
625static struct omap_hwmod omap2430_timer8_hwmod;
626
627/* l4_core -> timer8 */
628static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
629 .master = &omap2430_l4_core_hwmod,
630 .slave = &omap2430_timer8_hwmod,
631 .clk = "gpt8_ick",
632 .addr = omap2xxx_timer8_addrs,
633 .user = OCP_USER_MPU | OCP_USER_SDMA,
634};
635
636/* timer8 slave port */
637static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
638 &omap2430_l4_core__timer8,
639};
640
641/* timer8 hwmod */
642static struct omap_hwmod omap2430_timer8_hwmod = {
643 .name = "timer8",
644 .mpu_irqs = omap2_timer8_mpu_irqs,
645 .main_clk = "gpt8_fck",
646 .prcm = {
647 .omap2 = {
648 .prcm_reg_id = 1,
649 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
650 .module_offs = CORE_MOD,
651 .idlest_reg_id = 1,
652 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
653 },
654 },
655 .dev_attr = &capability_alwon_dev_attr,
656 .slaves = omap2430_timer8_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
658 .class = &omap2xxx_timer_hwmod_class,
659};
660
661/* timer9 */
662static struct omap_hwmod omap2430_timer9_hwmod;
663
664/* l4_core -> timer9 */
665static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
666 .master = &omap2430_l4_core_hwmod,
667 .slave = &omap2430_timer9_hwmod,
668 .clk = "gpt9_ick",
669 .addr = omap2xxx_timer9_addrs,
670 .user = OCP_USER_MPU | OCP_USER_SDMA,
671};
672
673/* timer9 slave port */
674static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
675 &omap2430_l4_core__timer9,
676};
677
678/* timer9 hwmod */
679static struct omap_hwmod omap2430_timer9_hwmod = {
680 .name = "timer9",
681 .mpu_irqs = omap2_timer9_mpu_irqs,
682 .main_clk = "gpt9_fck",
683 .prcm = {
684 .omap2 = {
685 .prcm_reg_id = 1,
686 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
687 .module_offs = CORE_MOD,
688 .idlest_reg_id = 1,
689 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
690 },
691 },
692 .dev_attr = &capability_pwm_dev_attr,
693 .slaves = omap2430_timer9_slaves,
694 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
695 .class = &omap2xxx_timer_hwmod_class,
696};
697
698/* timer10 */
699static struct omap_hwmod omap2430_timer10_hwmod;
700
701/* l4_core -> timer10 */
702static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
703 .master = &omap2430_l4_core_hwmod,
704 .slave = &omap2430_timer10_hwmod,
705 .clk = "gpt10_ick",
706 .addr = omap2_timer10_addrs,
707 .user = OCP_USER_MPU | OCP_USER_SDMA,
708};
709
710/* timer10 slave port */
711static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
712 &omap2430_l4_core__timer10,
713};
714
715/* timer10 hwmod */
716static struct omap_hwmod omap2430_timer10_hwmod = {
717 .name = "timer10",
718 .mpu_irqs = omap2_timer10_mpu_irqs,
719 .main_clk = "gpt10_fck",
720 .prcm = {
721 .omap2 = {
722 .prcm_reg_id = 1,
723 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
724 .module_offs = CORE_MOD,
725 .idlest_reg_id = 1,
726 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
727 },
728 },
729 .dev_attr = &capability_pwm_dev_attr,
730 .slaves = omap2430_timer10_slaves,
731 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
732 .class = &omap2xxx_timer_hwmod_class,
733};
734
735/* timer11 */
736static struct omap_hwmod omap2430_timer11_hwmod;
737
738/* l4_core -> timer11 */
739static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
740 .master = &omap2430_l4_core_hwmod,
741 .slave = &omap2430_timer11_hwmod,
742 .clk = "gpt11_ick",
743 .addr = omap2_timer11_addrs,
744 .user = OCP_USER_MPU | OCP_USER_SDMA,
745};
746
747/* timer11 slave port */
748static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
749 &omap2430_l4_core__timer11,
750};
751
752/* timer11 hwmod */
753static struct omap_hwmod omap2430_timer11_hwmod = {
754 .name = "timer11",
755 .mpu_irqs = omap2_timer11_mpu_irqs,
756 .main_clk = "gpt11_fck",
757 .prcm = {
758 .omap2 = {
759 .prcm_reg_id = 1,
760 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
761 .module_offs = CORE_MOD,
762 .idlest_reg_id = 1,
763 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
764 },
765 },
766 .dev_attr = &capability_pwm_dev_attr,
767 .slaves = omap2430_timer11_slaves,
768 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
769 .class = &omap2xxx_timer_hwmod_class,
770};
771
772/* timer12 */
773static struct omap_hwmod omap2430_timer12_hwmod;
774
775/* l4_core -> timer12 */
776static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
777 .master = &omap2430_l4_core_hwmod,
778 .slave = &omap2430_timer12_hwmod,
779 .clk = "gpt12_ick",
780 .addr = omap2xxx_timer12_addrs,
781 .user = OCP_USER_MPU | OCP_USER_SDMA,
782};
783
784/* timer12 slave port */
785static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
786 &omap2430_l4_core__timer12,
787};
788
789/* timer12 hwmod */
790static struct omap_hwmod omap2430_timer12_hwmod = {
791 .name = "timer12",
792 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
793 .main_clk = "gpt12_fck",
794 .prcm = {
795 .omap2 = {
796 .prcm_reg_id = 1,
797 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
798 .module_offs = CORE_MOD,
799 .idlest_reg_id = 1,
800 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
801 },
802 },
803 .dev_attr = &capability_pwm_dev_attr,
804 .slaves = omap2430_timer12_slaves,
805 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
806 .class = &omap2xxx_timer_hwmod_class,
807};
808
809/* l4_wkup -> wd_timer2 */
810static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
811 {
812 .pa_start = 0x49016000,
813 .pa_end = 0x4901607f,
814 .flags = ADDR_TYPE_RT
815 },
816 { }
817};
818
819static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
820 .master = &omap2430_l4_wkup_hwmod,
821 .slave = &omap2430_wd_timer2_hwmod,
822 .clk = "mpu_wdt_ick",
823 .addr = omap2430_wd_timer2_addrs,
824 .user = OCP_USER_MPU | OCP_USER_SDMA,
825};
826
827/* wd_timer2 */
828static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
829 &omap2430_l4_wkup__wd_timer2,
830};
831
832static struct omap_hwmod omap2430_wd_timer2_hwmod = {
833 .name = "wd_timer2",
834 .class = &omap2xxx_wd_timer_hwmod_class,
835 .main_clk = "mpu_wdt_fck",
836 .prcm = {
837 .omap2 = {
838 .prcm_reg_id = 1,
839 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
840 .module_offs = WKUP_MOD,
841 .idlest_reg_id = 1,
842 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
843 },
844 },
845 .slaves = omap2430_wd_timer2_slaves,
846 .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves),
847};
848
849/* UART1 */
850
851static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
852 &omap2_l4_core__uart1,
853};
854
855static struct omap_hwmod omap2430_uart1_hwmod = {
856 .name = "uart1",
857 .mpu_irqs = omap2_uart1_mpu_irqs,
858 .sdma_reqs = omap2_uart1_sdma_reqs,
859 .main_clk = "uart1_fck",
860 .prcm = {
861 .omap2 = {
862 .module_offs = CORE_MOD,
863 .prcm_reg_id = 1,
864 .module_bit = OMAP24XX_EN_UART1_SHIFT,
865 .idlest_reg_id = 1,
866 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
867 },
868 },
869 .slaves = omap2430_uart1_slaves,
870 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
871 .class = &omap2_uart_class,
872};
873
874/* UART2 */
875
876static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
877 &omap2_l4_core__uart2,
878};
879
880static struct omap_hwmod omap2430_uart2_hwmod = {
881 .name = "uart2",
882 .mpu_irqs = omap2_uart2_mpu_irqs,
883 .sdma_reqs = omap2_uart2_sdma_reqs,
884 .main_clk = "uart2_fck",
885 .prcm = {
886 .omap2 = {
887 .module_offs = CORE_MOD,
888 .prcm_reg_id = 1,
889 .module_bit = OMAP24XX_EN_UART2_SHIFT,
890 .idlest_reg_id = 1,
891 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
892 },
893 },
894 .slaves = omap2430_uart2_slaves,
895 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
896 .class = &omap2_uart_class,
897};
898
899/* UART3 */
900
901static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
902 &omap2_l4_core__uart3,
903};
904
905static struct omap_hwmod omap2430_uart3_hwmod = {
906 .name = "uart3",
907 .mpu_irqs = omap2_uart3_mpu_irqs,
908 .sdma_reqs = omap2_uart3_sdma_reqs,
909 .main_clk = "uart3_fck",
910 .prcm = {
911 .omap2 = {
912 .module_offs = CORE_MOD,
913 .prcm_reg_id = 2,
914 .module_bit = OMAP24XX_EN_UART3_SHIFT,
915 .idlest_reg_id = 2,
916 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
917 },
918 },
919 .slaves = omap2430_uart3_slaves,
920 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
921 .class = &omap2_uart_class,
922};
923
924/* dss */
925/* dss master ports */
926static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
927 &omap2430_dss__l3,
928};
929
930/* l4_core -> dss */
931static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
932 .master = &omap2430_l4_core_hwmod,
933 .slave = &omap2430_dss_core_hwmod,
934 .clk = "dss_ick",
935 .addr = omap2_dss_addrs,
936 .user = OCP_USER_MPU | OCP_USER_SDMA,
937};
938
939/* dss slave ports */
940static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
941 &omap2430_l4_core__dss,
942};
943
944static struct omap_hwmod_opt_clk dss_opt_clks[] = {
945 /*
946 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
947 * driver does not use these clocks.
948 */
949 { .role = "tv_clk", .clk = "dss_54m_fck" },
950 { .role = "sys_clk", .clk = "dss2_fck" },
951};
952
953static struct omap_hwmod omap2430_dss_core_hwmod = {
954 .name = "dss_core",
955 .class = &omap2_dss_hwmod_class,
956 .main_clk = "dss1_fck", /* instead of dss_fck */
957 .sdma_reqs = omap2xxx_dss_sdma_chs,
958 .prcm = {
959 .omap2 = {
960 .prcm_reg_id = 1,
961 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
962 .module_offs = CORE_MOD,
963 .idlest_reg_id = 1,
964 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
965 },
966 },
967 .opt_clks = dss_opt_clks,
968 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
969 .slaves = omap2430_dss_slaves,
970 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
971 .masters = omap2430_dss_masters,
972 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
973 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
974};
975
976/* l4_core -> dss_dispc */
977static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
978 .master = &omap2430_l4_core_hwmod,
979 .slave = &omap2430_dss_dispc_hwmod,
980 .clk = "dss_ick",
981 .addr = omap2_dss_dispc_addrs,
982 .user = OCP_USER_MPU | OCP_USER_SDMA,
983};
984
985/* dss_dispc slave ports */
986static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
987 &omap2430_l4_core__dss_dispc,
988};
989
990static struct omap_hwmod omap2430_dss_dispc_hwmod = {
991 .name = "dss_dispc",
992 .class = &omap2_dispc_hwmod_class,
993 .mpu_irqs = omap2_dispc_irqs,
994 .main_clk = "dss1_fck",
995 .prcm = {
996 .omap2 = {
997 .prcm_reg_id = 1,
998 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
999 .module_offs = CORE_MOD,
1000 .idlest_reg_id = 1,
1001 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1002 },
1003 },
1004 .slaves = omap2430_dss_dispc_slaves,
1005 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1006 .flags = HWMOD_NO_IDLEST,
1007 .dev_attr = &omap2_3_dss_dispc_dev_attr
1008};
1009
1010/* l4_core -> dss_rfbi */
1011static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1012 .master = &omap2430_l4_core_hwmod,
1013 .slave = &omap2430_dss_rfbi_hwmod,
1014 .clk = "dss_ick",
1015 .addr = omap2_dss_rfbi_addrs,
1016 .user = OCP_USER_MPU | OCP_USER_SDMA,
1017};
1018
1019/* dss_rfbi slave ports */
1020static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1021 &omap2430_l4_core__dss_rfbi,
1022};
1023
1024static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1025 { .role = "ick", .clk = "dss_ick" },
1026};
1027
1028static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1029 .name = "dss_rfbi",
1030 .class = &omap2_rfbi_hwmod_class,
1031 .main_clk = "dss1_fck",
1032 .prcm = {
1033 .omap2 = {
1034 .prcm_reg_id = 1,
1035 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1036 .module_offs = CORE_MOD,
1037 },
1038 },
1039 .opt_clks = dss_rfbi_opt_clks,
1040 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1041 .slaves = omap2430_dss_rfbi_slaves,
1042 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1043 .flags = HWMOD_NO_IDLEST,
1044};
1045
1046/* l4_core -> dss_venc */
1047static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1048 .master = &omap2430_l4_core_hwmod,
1049 .slave = &omap2430_dss_venc_hwmod,
1050 .clk = "dss_ick",
1051 .addr = omap2_dss_venc_addrs,
1052 .user = OCP_USER_MPU | OCP_USER_SDMA,
1053};
1054
1055/* dss_venc slave ports */
1056static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1057 &omap2430_l4_core__dss_venc,
1058};
1059
1060static struct omap_hwmod omap2430_dss_venc_hwmod = {
1061 .name = "dss_venc",
1062 .class = &omap2_venc_hwmod_class,
1063 .main_clk = "dss_54m_fck",
1064 .prcm = {
1065 .omap2 = {
1066 .prcm_reg_id = 1,
1067 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1068 .module_offs = CORE_MOD,
1069 },
1070 },
1071 .slaves = omap2430_dss_venc_slaves,
1072 .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves),
1073 .flags = HWMOD_NO_IDLEST,
1074}; 60};
1075 61
1076/* I2C common */ 62/* I2C common */
@@ -1098,11 +84,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
1098}; 84};
1099 85
1100/* I2C1 */ 86/* I2C1 */
1101
1102static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1103 &omap2430_l4_core__i2c1,
1104};
1105
1106static struct omap_hwmod omap2430_i2c1_hwmod = { 87static struct omap_hwmod omap2430_i2c1_hwmod = {
1107 .name = "i2c1", 88 .name = "i2c1",
1108 .flags = HWMOD_16BIT_REG, 89 .flags = HWMOD_16BIT_REG,
@@ -1126,18 +107,11 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
1126 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, 107 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1127 }, 108 },
1128 }, 109 },
1129 .slaves = omap2430_i2c1_slaves,
1130 .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
1131 .class = &i2c_class, 110 .class = &i2c_class,
1132 .dev_attr = &i2c_dev_attr, 111 .dev_attr = &i2c_dev_attr,
1133}; 112};
1134 113
1135/* I2C2 */ 114/* I2C2 */
1136
1137static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1138 &omap2430_l4_core__i2c2,
1139};
1140
1141static struct omap_hwmod omap2430_i2c2_hwmod = { 115static struct omap_hwmod omap2430_i2c2_hwmod = {
1142 .name = "i2c2", 116 .name = "i2c2",
1143 .flags = HWMOD_16BIT_REG, 117 .flags = HWMOD_16BIT_REG,
@@ -1153,218 +127,16 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
1153 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, 127 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1154 }, 128 },
1155 }, 129 },
1156 .slaves = omap2430_i2c2_slaves,
1157 .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
1158 .class = &i2c_class, 130 .class = &i2c_class,
1159 .dev_attr = &i2c_dev_attr, 131 .dev_attr = &i2c_dev_attr,
1160}; 132};
1161 133
1162/* l4_wkup -> gpio1 */
1163static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1164 {
1165 .pa_start = 0x4900C000,
1166 .pa_end = 0x4900C1ff,
1167 .flags = ADDR_TYPE_RT
1168 },
1169 { }
1170};
1171
1172static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1173 .master = &omap2430_l4_wkup_hwmod,
1174 .slave = &omap2430_gpio1_hwmod,
1175 .clk = "gpios_ick",
1176 .addr = omap2430_gpio1_addr_space,
1177 .user = OCP_USER_MPU | OCP_USER_SDMA,
1178};
1179
1180/* l4_wkup -> gpio2 */
1181static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1182 {
1183 .pa_start = 0x4900E000,
1184 .pa_end = 0x4900E1ff,
1185 .flags = ADDR_TYPE_RT
1186 },
1187 { }
1188};
1189
1190static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1191 .master = &omap2430_l4_wkup_hwmod,
1192 .slave = &omap2430_gpio2_hwmod,
1193 .clk = "gpios_ick",
1194 .addr = omap2430_gpio2_addr_space,
1195 .user = OCP_USER_MPU | OCP_USER_SDMA,
1196};
1197
1198/* l4_wkup -> gpio3 */
1199static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1200 {
1201 .pa_start = 0x49010000,
1202 .pa_end = 0x490101ff,
1203 .flags = ADDR_TYPE_RT
1204 },
1205 { }
1206};
1207
1208static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1209 .master = &omap2430_l4_wkup_hwmod,
1210 .slave = &omap2430_gpio3_hwmod,
1211 .clk = "gpios_ick",
1212 .addr = omap2430_gpio3_addr_space,
1213 .user = OCP_USER_MPU | OCP_USER_SDMA,
1214};
1215
1216/* l4_wkup -> gpio4 */
1217static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1218 {
1219 .pa_start = 0x49012000,
1220 .pa_end = 0x490121ff,
1221 .flags = ADDR_TYPE_RT
1222 },
1223 { }
1224};
1225
1226static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1227 .master = &omap2430_l4_wkup_hwmod,
1228 .slave = &omap2430_gpio4_hwmod,
1229 .clk = "gpios_ick",
1230 .addr = omap2430_gpio4_addr_space,
1231 .user = OCP_USER_MPU | OCP_USER_SDMA,
1232};
1233
1234/* l4_core -> gpio5 */
1235static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1236 {
1237 .pa_start = 0x480B6000,
1238 .pa_end = 0x480B61ff,
1239 .flags = ADDR_TYPE_RT
1240 },
1241 { }
1242};
1243
1244static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1245 .master = &omap2430_l4_core_hwmod,
1246 .slave = &omap2430_gpio5_hwmod,
1247 .clk = "gpio5_ick",
1248 .addr = omap2430_gpio5_addr_space,
1249 .user = OCP_USER_MPU | OCP_USER_SDMA,
1250};
1251
1252/* gpio dev_attr */
1253static struct omap_gpio_dev_attr gpio_dev_attr = {
1254 .bank_width = 32,
1255 .dbck_flag = false,
1256};
1257
1258/* gpio1 */
1259static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1260 &omap2430_l4_wkup__gpio1,
1261};
1262
1263static struct omap_hwmod omap2430_gpio1_hwmod = {
1264 .name = "gpio1",
1265 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1266 .mpu_irqs = omap2_gpio1_irqs,
1267 .main_clk = "gpios_fck",
1268 .prcm = {
1269 .omap2 = {
1270 .prcm_reg_id = 1,
1271 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1272 .module_offs = WKUP_MOD,
1273 .idlest_reg_id = 1,
1274 .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1275 },
1276 },
1277 .slaves = omap2430_gpio1_slaves,
1278 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
1279 .class = &omap2xxx_gpio_hwmod_class,
1280 .dev_attr = &gpio_dev_attr,
1281};
1282
1283/* gpio2 */
1284static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1285 &omap2430_l4_wkup__gpio2,
1286};
1287
1288static struct omap_hwmod omap2430_gpio2_hwmod = {
1289 .name = "gpio2",
1290 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1291 .mpu_irqs = omap2_gpio2_irqs,
1292 .main_clk = "gpios_fck",
1293 .prcm = {
1294 .omap2 = {
1295 .prcm_reg_id = 1,
1296 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1297 .module_offs = WKUP_MOD,
1298 .idlest_reg_id = 1,
1299 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1300 },
1301 },
1302 .slaves = omap2430_gpio2_slaves,
1303 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
1304 .class = &omap2xxx_gpio_hwmod_class,
1305 .dev_attr = &gpio_dev_attr,
1306};
1307
1308/* gpio3 */
1309static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1310 &omap2430_l4_wkup__gpio3,
1311};
1312
1313static struct omap_hwmod omap2430_gpio3_hwmod = {
1314 .name = "gpio3",
1315 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1316 .mpu_irqs = omap2_gpio3_irqs,
1317 .main_clk = "gpios_fck",
1318 .prcm = {
1319 .omap2 = {
1320 .prcm_reg_id = 1,
1321 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1322 .module_offs = WKUP_MOD,
1323 .idlest_reg_id = 1,
1324 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1325 },
1326 },
1327 .slaves = omap2430_gpio3_slaves,
1328 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
1329 .class = &omap2xxx_gpio_hwmod_class,
1330 .dev_attr = &gpio_dev_attr,
1331};
1332
1333/* gpio4 */
1334static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1335 &omap2430_l4_wkup__gpio4,
1336};
1337
1338static struct omap_hwmod omap2430_gpio4_hwmod = {
1339 .name = "gpio4",
1340 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1341 .mpu_irqs = omap2_gpio4_irqs,
1342 .main_clk = "gpios_fck",
1343 .prcm = {
1344 .omap2 = {
1345 .prcm_reg_id = 1,
1346 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1347 .module_offs = WKUP_MOD,
1348 .idlest_reg_id = 1,
1349 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1350 },
1351 },
1352 .slaves = omap2430_gpio4_slaves,
1353 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
1354 .class = &omap2xxx_gpio_hwmod_class,
1355 .dev_attr = &gpio_dev_attr,
1356};
1357
1358/* gpio5 */ 134/* gpio5 */
1359static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { 135static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1360 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ 136 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1361 { .irq = -1 } 137 { .irq = -1 }
1362}; 138};
1363 139
1364static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1365 &omap2430_l4_core__gpio5,
1366};
1367
1368static struct omap_hwmod omap2430_gpio5_hwmod = { 140static struct omap_hwmod omap2430_gpio5_hwmod = {
1369 .name = "gpio5", 141 .name = "gpio5",
1370 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 142 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1379,10 +151,8 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
1379 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, 151 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1380 }, 152 },
1381 }, 153 },
1382 .slaves = omap2430_gpio5_slaves,
1383 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
1384 .class = &omap2xxx_gpio_hwmod_class, 154 .class = &omap2xxx_gpio_hwmod_class,
1385 .dev_attr = &gpio_dev_attr, 155 .dev_attr = &omap2xxx_gpio_dev_attr,
1386}; 156};
1387 157
1388/* dma attributes */ 158/* dma attributes */
@@ -1392,66 +162,21 @@ static struct omap_dma_dev_attr dma_dev_attr = {
1392 .lch_count = 32, 162 .lch_count = 32,
1393}; 163};
1394 164
1395/* dma_system -> L3 */
1396static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1397 .master = &omap2430_dma_system_hwmod,
1398 .slave = &omap2430_l3_main_hwmod,
1399 .clk = "core_l3_ck",
1400 .user = OCP_USER_MPU | OCP_USER_SDMA,
1401};
1402
1403/* dma_system master ports */
1404static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1405 &omap2430_dma_system__l3,
1406};
1407
1408/* l4_core -> dma_system */
1409static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1410 .master = &omap2430_l4_core_hwmod,
1411 .slave = &omap2430_dma_system_hwmod,
1412 .clk = "sdma_ick",
1413 .addr = omap2_dma_system_addrs,
1414 .user = OCP_USER_MPU | OCP_USER_SDMA,
1415};
1416
1417/* dma_system slave ports */
1418static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1419 &omap2430_l4_core__dma_system,
1420};
1421
1422static struct omap_hwmod omap2430_dma_system_hwmod = { 165static struct omap_hwmod omap2430_dma_system_hwmod = {
1423 .name = "dma", 166 .name = "dma",
1424 .class = &omap2xxx_dma_hwmod_class, 167 .class = &omap2xxx_dma_hwmod_class,
1425 .mpu_irqs = omap2_dma_system_irqs, 168 .mpu_irqs = omap2_dma_system_irqs,
1426 .main_clk = "core_l3_ck", 169 .main_clk = "core_l3_ck",
1427 .slaves = omap2430_dma_system_slaves,
1428 .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
1429 .masters = omap2430_dma_system_masters,
1430 .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters),
1431 .dev_attr = &dma_dev_attr, 170 .dev_attr = &dma_dev_attr,
1432 .flags = HWMOD_NO_IDLEST, 171 .flags = HWMOD_NO_IDLEST,
1433}; 172};
1434 173
1435/* mailbox */ 174/* mailbox */
1436static struct omap_hwmod omap2430_mailbox_hwmod;
1437static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { 175static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1438 { .irq = 26 }, 176 { .irq = 26 },
1439 { .irq = -1 } 177 { .irq = -1 }
1440}; 178};
1441 179
1442/* l4_core -> mailbox */
1443static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
1444 .master = &omap2430_l4_core_hwmod,
1445 .slave = &omap2430_mailbox_hwmod,
1446 .addr = omap2_mailbox_addrs,
1447 .user = OCP_USER_MPU | OCP_USER_SDMA,
1448};
1449
1450/* mailbox slave ports */
1451static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
1452 &omap2430_l4_core__mailbox,
1453};
1454
1455static struct omap_hwmod omap2430_mailbox_hwmod = { 180static struct omap_hwmod omap2430_mailbox_hwmod = {
1456 .name = "mailbox", 181 .name = "mailbox",
1457 .class = &omap2xxx_mailbox_hwmod_class, 182 .class = &omap2xxx_mailbox_hwmod_class,
@@ -1466,66 +191,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
1466 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 191 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1467 }, 192 },
1468 }, 193 },
1469 .slaves = omap2430_mailbox_slaves,
1470 .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
1471};
1472
1473/* mcspi1 */
1474static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1475 &omap2430_l4_core__mcspi1,
1476};
1477
1478static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1479 .num_chipselect = 4,
1480};
1481
1482static struct omap_hwmod omap2430_mcspi1_hwmod = {
1483 .name = "mcspi1_hwmod",
1484 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1485 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1486 .main_clk = "mcspi1_fck",
1487 .prcm = {
1488 .omap2 = {
1489 .module_offs = CORE_MOD,
1490 .prcm_reg_id = 1,
1491 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1492 .idlest_reg_id = 1,
1493 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1494 },
1495 },
1496 .slaves = omap2430_mcspi1_slaves,
1497 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
1498 .class = &omap2xxx_mcspi_class,
1499 .dev_attr = &omap_mcspi1_dev_attr,
1500};
1501
1502/* mcspi2 */
1503static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
1504 &omap2430_l4_core__mcspi2,
1505};
1506
1507static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1508 .num_chipselect = 2,
1509};
1510
1511static struct omap_hwmod omap2430_mcspi2_hwmod = {
1512 .name = "mcspi2_hwmod",
1513 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1514 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1515 .main_clk = "mcspi2_fck",
1516 .prcm = {
1517 .omap2 = {
1518 .module_offs = CORE_MOD,
1519 .prcm_reg_id = 1,
1520 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1521 .idlest_reg_id = 1,
1522 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1523 },
1524 },
1525 .slaves = omap2430_mcspi2_slaves,
1526 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
1527 .class = &omap2xxx_mcspi_class,
1528 .dev_attr = &omap_mcspi2_dev_attr,
1529}; 194};
1530 195
1531/* mcspi3 */ 196/* mcspi3 */
@@ -1542,16 +207,12 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
1542 { .dma_req = -1 } 207 { .dma_req = -1 }
1543}; 208};
1544 209
1545static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
1546 &omap2430_l4_core__mcspi3,
1547};
1548
1549static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 210static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1550 .num_chipselect = 2, 211 .num_chipselect = 2,
1551}; 212};
1552 213
1553static struct omap_hwmod omap2430_mcspi3_hwmod = { 214static struct omap_hwmod omap2430_mcspi3_hwmod = {
1554 .name = "mcspi3_hwmod", 215 .name = "mcspi3",
1555 .mpu_irqs = omap2430_mcspi3_mpu_irqs, 216 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
1556 .sdma_reqs = omap2430_mcspi3_sdma_reqs, 217 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
1557 .main_clk = "mcspi3_fck", 218 .main_clk = "mcspi3_fck",
@@ -1564,15 +225,11 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
1564 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, 225 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
1565 }, 226 },
1566 }, 227 },
1567 .slaves = omap2430_mcspi3_slaves,
1568 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
1569 .class = &omap2xxx_mcspi_class, 228 .class = &omap2xxx_mcspi_class,
1570 .dev_attr = &omap_mcspi3_dev_attr, 229 .dev_attr = &omap_mcspi3_dev_attr,
1571}; 230};
1572 231
1573/* 232/* usbhsotg */
1574 * usbhsotg
1575 */
1576static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { 233static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
1577 .rev_offs = 0x0400, 234 .rev_offs = 0x0400,
1578 .sysc_offs = 0x0404, 235 .sysc_offs = 0x0404,
@@ -1611,10 +268,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
1611 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, 268 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
1612 }, 269 },
1613 }, 270 },
1614 .masters = omap2430_usbhsotg_masters,
1615 .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters),
1616 .slaves = omap2430_usbhsotg_slaves,
1617 .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves),
1618 .class = &usbotg_class, 271 .class = &usbotg_class,
1619 /* 272 /*
1620 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 273 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
@@ -1652,20 +305,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
1652 { .irq = -1 } 305 { .irq = -1 }
1653}; 306};
1654 307
1655/* l4_core -> mcbsp1 */
1656static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
1657 .master = &omap2430_l4_core_hwmod,
1658 .slave = &omap2430_mcbsp1_hwmod,
1659 .clk = "mcbsp1_ick",
1660 .addr = omap2_mcbsp1_addrs,
1661 .user = OCP_USER_MPU | OCP_USER_SDMA,
1662};
1663
1664/* mcbsp1 slave ports */
1665static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
1666 &omap2430_l4_core__mcbsp1,
1667};
1668
1669static struct omap_hwmod omap2430_mcbsp1_hwmod = { 308static struct omap_hwmod omap2430_mcbsp1_hwmod = {
1670 .name = "mcbsp1", 309 .name = "mcbsp1",
1671 .class = &omap2430_mcbsp_hwmod_class, 310 .class = &omap2430_mcbsp_hwmod_class,
@@ -1681,8 +320,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
1681 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 320 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1682 }, 321 },
1683 }, 322 },
1684 .slaves = omap2430_mcbsp1_slaves,
1685 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves),
1686}; 323};
1687 324
1688/* mcbsp2 */ 325/* mcbsp2 */
@@ -1693,20 +330,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
1693 { .irq = -1 } 330 { .irq = -1 }
1694}; 331};
1695 332
1696/* l4_core -> mcbsp2 */
1697static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
1698 .master = &omap2430_l4_core_hwmod,
1699 .slave = &omap2430_mcbsp2_hwmod,
1700 .clk = "mcbsp2_ick",
1701 .addr = omap2xxx_mcbsp2_addrs,
1702 .user = OCP_USER_MPU | OCP_USER_SDMA,
1703};
1704
1705/* mcbsp2 slave ports */
1706static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
1707 &omap2430_l4_core__mcbsp2,
1708};
1709
1710static struct omap_hwmod omap2430_mcbsp2_hwmod = { 333static struct omap_hwmod omap2430_mcbsp2_hwmod = {
1711 .name = "mcbsp2", 334 .name = "mcbsp2",
1712 .class = &omap2430_mcbsp_hwmod_class, 335 .class = &omap2430_mcbsp_hwmod_class,
@@ -1722,8 +345,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
1722 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 345 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1723 }, 346 },
1724 }, 347 },
1725 .slaves = omap2430_mcbsp2_slaves,
1726 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves),
1727}; 348};
1728 349
1729/* mcbsp3 */ 350/* mcbsp3 */
@@ -1734,30 +355,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
1734 { .irq = -1 } 355 { .irq = -1 }
1735}; 356};
1736 357
1737static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
1738 {
1739 .name = "mpu",
1740 .pa_start = 0x4808C000,
1741 .pa_end = 0x4808C0ff,
1742 .flags = ADDR_TYPE_RT
1743 },
1744 { }
1745};
1746
1747/* l4_core -> mcbsp3 */
1748static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
1749 .master = &omap2430_l4_core_hwmod,
1750 .slave = &omap2430_mcbsp3_hwmod,
1751 .clk = "mcbsp3_ick",
1752 .addr = omap2430_mcbsp3_addrs,
1753 .user = OCP_USER_MPU | OCP_USER_SDMA,
1754};
1755
1756/* mcbsp3 slave ports */
1757static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
1758 &omap2430_l4_core__mcbsp3,
1759};
1760
1761static struct omap_hwmod omap2430_mcbsp3_hwmod = { 358static struct omap_hwmod omap2430_mcbsp3_hwmod = {
1762 .name = "mcbsp3", 359 .name = "mcbsp3",
1763 .class = &omap2430_mcbsp_hwmod_class, 360 .class = &omap2430_mcbsp_hwmod_class,
@@ -1773,8 +370,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
1773 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, 370 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
1774 }, 371 },
1775 }, 372 },
1776 .slaves = omap2430_mcbsp3_slaves,
1777 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves),
1778}; 373};
1779 374
1780/* mcbsp4 */ 375/* mcbsp4 */
@@ -1791,30 +386,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
1791 { .dma_req = -1 } 386 { .dma_req = -1 }
1792}; 387};
1793 388
1794static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
1795 {
1796 .name = "mpu",
1797 .pa_start = 0x4808E000,
1798 .pa_end = 0x4808E0ff,
1799 .flags = ADDR_TYPE_RT
1800 },
1801 { }
1802};
1803
1804/* l4_core -> mcbsp4 */
1805static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
1806 .master = &omap2430_l4_core_hwmod,
1807 .slave = &omap2430_mcbsp4_hwmod,
1808 .clk = "mcbsp4_ick",
1809 .addr = omap2430_mcbsp4_addrs,
1810 .user = OCP_USER_MPU | OCP_USER_SDMA,
1811};
1812
1813/* mcbsp4 slave ports */
1814static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
1815 &omap2430_l4_core__mcbsp4,
1816};
1817
1818static struct omap_hwmod omap2430_mcbsp4_hwmod = { 389static struct omap_hwmod omap2430_mcbsp4_hwmod = {
1819 .name = "mcbsp4", 390 .name = "mcbsp4",
1820 .class = &omap2430_mcbsp_hwmod_class, 391 .class = &omap2430_mcbsp_hwmod_class,
@@ -1830,8 +401,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
1830 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, 401 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
1831 }, 402 },
1832 }, 403 },
1833 .slaves = omap2430_mcbsp4_slaves,
1834 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves),
1835}; 404};
1836 405
1837/* mcbsp5 */ 406/* mcbsp5 */
@@ -1848,30 +417,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
1848 { .dma_req = -1 } 417 { .dma_req = -1 }
1849}; 418};
1850 419
1851static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
1852 {
1853 .name = "mpu",
1854 .pa_start = 0x48096000,
1855 .pa_end = 0x480960ff,
1856 .flags = ADDR_TYPE_RT
1857 },
1858 { }
1859};
1860
1861/* l4_core -> mcbsp5 */
1862static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
1863 .master = &omap2430_l4_core_hwmod,
1864 .slave = &omap2430_mcbsp5_hwmod,
1865 .clk = "mcbsp5_ick",
1866 .addr = omap2430_mcbsp5_addrs,
1867 .user = OCP_USER_MPU | OCP_USER_SDMA,
1868};
1869
1870/* mcbsp5 slave ports */
1871static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
1872 &omap2430_l4_core__mcbsp5,
1873};
1874
1875static struct omap_hwmod omap2430_mcbsp5_hwmod = { 420static struct omap_hwmod omap2430_mcbsp5_hwmod = {
1876 .name = "mcbsp5", 421 .name = "mcbsp5",
1877 .class = &omap2430_mcbsp_hwmod_class, 422 .class = &omap2430_mcbsp_hwmod_class,
@@ -1887,12 +432,9 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
1887 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, 432 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
1888 }, 433 },
1889 }, 434 },
1890 .slaves = omap2430_mcbsp5_slaves,
1891 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves),
1892}; 435};
1893 436
1894/* MMC/SD/SDIO common */ 437/* MMC/SD/SDIO common */
1895
1896static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { 438static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
1897 .rev_offs = 0x1fc, 439 .rev_offs = 0x1fc,
1898 .sysc_offs = 0x10, 440 .sysc_offs = 0x10,
@@ -1910,7 +452,6 @@ static struct omap_hwmod_class omap2430_mmc_class = {
1910}; 452};
1911 453
1912/* MMC/SD/SDIO1 */ 454/* MMC/SD/SDIO1 */
1913
1914static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { 455static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
1915 { .irq = 83 }, 456 { .irq = 83 },
1916 { .irq = -1 } 457 { .irq = -1 }
@@ -1926,10 +467,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
1926 { .role = "dbck", .clk = "mmchsdb1_fck" }, 467 { .role = "dbck", .clk = "mmchsdb1_fck" },
1927}; 468};
1928 469
1929static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
1930 &omap2430_l4_core__mmc1,
1931};
1932
1933static struct omap_mmc_dev_attr mmc1_dev_attr = { 470static struct omap_mmc_dev_attr mmc1_dev_attr = {
1934 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 471 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1935}; 472};
@@ -1952,13 +489,10 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
1952 }, 489 },
1953 }, 490 },
1954 .dev_attr = &mmc1_dev_attr, 491 .dev_attr = &mmc1_dev_attr,
1955 .slaves = omap2430_mmc1_slaves,
1956 .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
1957 .class = &omap2430_mmc_class, 492 .class = &omap2430_mmc_class,
1958}; 493};
1959 494
1960/* MMC/SD/SDIO2 */ 495/* MMC/SD/SDIO2 */
1961
1962static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { 496static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
1963 { .irq = 86 }, 497 { .irq = 86 },
1964 { .irq = -1 } 498 { .irq = -1 }
@@ -1974,10 +508,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
1974 { .role = "dbck", .clk = "mmchsdb2_fck" }, 508 { .role = "dbck", .clk = "mmchsdb2_fck" },
1975}; 509};
1976 510
1977static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
1978 &omap2430_l4_core__mmc2,
1979};
1980
1981static struct omap_hwmod omap2430_mmc2_hwmod = { 511static struct omap_hwmod omap2430_mmc2_hwmod = {
1982 .name = "mmc2", 512 .name = "mmc2",
1983 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 513 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1995,78 +525,371 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
1995 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, 525 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
1996 }, 526 },
1997 }, 527 },
1998 .slaves = omap2430_mmc2_slaves,
1999 .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves),
2000 .class = &omap2430_mmc_class, 528 .class = &omap2430_mmc_class,
2001}; 529};
2002 530
2003static __initdata struct omap_hwmod *omap2430_hwmods[] = { 531/*
2004 &omap2430_l3_main_hwmod, 532 * interfaces
2005 &omap2430_l4_core_hwmod, 533 */
2006 &omap2430_l4_wkup_hwmod, 534
2007 &omap2430_mpu_hwmod, 535/* L3 -> L4_CORE interface */
2008 &omap2430_iva_hwmod, 536/* l3_core -> usbhsotg interface */
2009 537static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
2010 &omap2430_timer1_hwmod, 538 .master = &omap2430_usbhsotg_hwmod,
2011 &omap2430_timer2_hwmod, 539 .slave = &omap2xxx_l3_main_hwmod,
2012 &omap2430_timer3_hwmod, 540 .clk = "core_l3_ck",
2013 &omap2430_timer4_hwmod, 541 .user = OCP_USER_MPU,
2014 &omap2430_timer5_hwmod, 542};
2015 &omap2430_timer6_hwmod, 543
2016 &omap2430_timer7_hwmod, 544/* L4 CORE -> I2C1 interface */
2017 &omap2430_timer8_hwmod, 545static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
2018 &omap2430_timer9_hwmod, 546 .master = &omap2xxx_l4_core_hwmod,
2019 &omap2430_timer10_hwmod, 547 .slave = &omap2430_i2c1_hwmod,
2020 &omap2430_timer11_hwmod, 548 .clk = "i2c1_ick",
2021 &omap2430_timer12_hwmod, 549 .addr = omap2_i2c1_addr_space,
2022 550 .user = OCP_USER_MPU | OCP_USER_SDMA,
2023 &omap2430_wd_timer2_hwmod, 551};
2024 &omap2430_uart1_hwmod, 552
2025 &omap2430_uart2_hwmod, 553/* L4 CORE -> I2C2 interface */
2026 &omap2430_uart3_hwmod, 554static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
2027 /* dss class */ 555 .master = &omap2xxx_l4_core_hwmod,
2028 &omap2430_dss_core_hwmod, 556 .slave = &omap2430_i2c2_hwmod,
2029 &omap2430_dss_dispc_hwmod, 557 .clk = "i2c2_ick",
2030 &omap2430_dss_rfbi_hwmod, 558 .addr = omap2_i2c2_addr_space,
2031 &omap2430_dss_venc_hwmod, 559 .user = OCP_USER_MPU | OCP_USER_SDMA,
2032 /* i2c class */ 560};
2033 &omap2430_i2c1_hwmod, 561
2034 &omap2430_i2c2_hwmod, 562static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
2035 &omap2430_mmc1_hwmod, 563 {
2036 &omap2430_mmc2_hwmod, 564 .pa_start = OMAP243X_HS_BASE,
2037 565 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
2038 /* gpio class */ 566 .flags = ADDR_TYPE_RT
2039 &omap2430_gpio1_hwmod, 567 },
2040 &omap2430_gpio2_hwmod, 568 { }
2041 &omap2430_gpio3_hwmod, 569};
2042 &omap2430_gpio4_hwmod, 570
2043 &omap2430_gpio5_hwmod, 571/* l4_core ->usbhsotg interface */
2044 572static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
2045 /* dma_system class*/ 573 .master = &omap2xxx_l4_core_hwmod,
2046 &omap2430_dma_system_hwmod, 574 .slave = &omap2430_usbhsotg_hwmod,
2047 575 .clk = "usb_l4_ick",
2048 /* mcbsp class */ 576 .addr = omap2430_usbhsotg_addrs,
2049 &omap2430_mcbsp1_hwmod, 577 .user = OCP_USER_MPU,
2050 &omap2430_mcbsp2_hwmod, 578};
2051 &omap2430_mcbsp3_hwmod, 579
2052 &omap2430_mcbsp4_hwmod, 580/* L4 CORE -> MMC1 interface */
2053 &omap2430_mcbsp5_hwmod, 581static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
2054 582 .master = &omap2xxx_l4_core_hwmod,
2055 /* mailbox class */ 583 .slave = &omap2430_mmc1_hwmod,
2056 &omap2430_mailbox_hwmod, 584 .clk = "mmchs1_ick",
2057 585 .addr = omap2430_mmc1_addr_space,
2058 /* mcspi class */ 586 .user = OCP_USER_MPU | OCP_USER_SDMA,
2059 &omap2430_mcspi1_hwmod, 587};
2060 &omap2430_mcspi2_hwmod, 588
2061 &omap2430_mcspi3_hwmod, 589/* L4 CORE -> MMC2 interface */
2062 590static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
2063 /* usbotg class*/ 591 .master = &omap2xxx_l4_core_hwmod,
2064 &omap2430_usbhsotg_hwmod, 592 .slave = &omap2430_mmc2_hwmod,
593 .clk = "mmchs2_ick",
594 .addr = omap2430_mmc2_addr_space,
595 .user = OCP_USER_MPU | OCP_USER_SDMA,
596};
597
598/* l4 core -> mcspi3 interface */
599static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
600 .master = &omap2xxx_l4_core_hwmod,
601 .slave = &omap2430_mcspi3_hwmod,
602 .clk = "mcspi3_ick",
603 .addr = omap2430_mcspi3_addr_space,
604 .user = OCP_USER_MPU | OCP_USER_SDMA,
605};
606
607/* IVA2 <- L3 interface */
608static struct omap_hwmod_ocp_if omap2430_l3__iva = {
609 .master = &omap2xxx_l3_main_hwmod,
610 .slave = &omap2430_iva_hwmod,
611 .clk = "core_l3_ck",
612 .user = OCP_USER_MPU | OCP_USER_SDMA,
613};
614
615static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
616 {
617 .pa_start = 0x49018000,
618 .pa_end = 0x49018000 + SZ_1K - 1,
619 .flags = ADDR_TYPE_RT
620 },
621 { }
622};
623
624/* l4_wkup -> timer1 */
625static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
626 .master = &omap2xxx_l4_wkup_hwmod,
627 .slave = &omap2xxx_timer1_hwmod,
628 .clk = "gpt1_ick",
629 .addr = omap2430_timer1_addrs,
630 .user = OCP_USER_MPU | OCP_USER_SDMA,
631};
2065 632
633/* l4_wkup -> wd_timer2 */
634static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
635 {
636 .pa_start = 0x49016000,
637 .pa_end = 0x4901607f,
638 .flags = ADDR_TYPE_RT
639 },
640 { }
641};
642
643static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
644 .master = &omap2xxx_l4_wkup_hwmod,
645 .slave = &omap2xxx_wd_timer2_hwmod,
646 .clk = "mpu_wdt_ick",
647 .addr = omap2430_wd_timer2_addrs,
648 .user = OCP_USER_MPU | OCP_USER_SDMA,
649};
650
651/* l4_wkup -> gpio1 */
652static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
653 {
654 .pa_start = 0x4900C000,
655 .pa_end = 0x4900C1ff,
656 .flags = ADDR_TYPE_RT
657 },
658 { }
659};
660
661static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
662 .master = &omap2xxx_l4_wkup_hwmod,
663 .slave = &omap2xxx_gpio1_hwmod,
664 .clk = "gpios_ick",
665 .addr = omap2430_gpio1_addr_space,
666 .user = OCP_USER_MPU | OCP_USER_SDMA,
667};
668
669/* l4_wkup -> gpio2 */
670static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
671 {
672 .pa_start = 0x4900E000,
673 .pa_end = 0x4900E1ff,
674 .flags = ADDR_TYPE_RT
675 },
676 { }
677};
678
679static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
680 .master = &omap2xxx_l4_wkup_hwmod,
681 .slave = &omap2xxx_gpio2_hwmod,
682 .clk = "gpios_ick",
683 .addr = omap2430_gpio2_addr_space,
684 .user = OCP_USER_MPU | OCP_USER_SDMA,
685};
686
687/* l4_wkup -> gpio3 */
688static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
689 {
690 .pa_start = 0x49010000,
691 .pa_end = 0x490101ff,
692 .flags = ADDR_TYPE_RT
693 },
694 { }
695};
696
697static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
698 .master = &omap2xxx_l4_wkup_hwmod,
699 .slave = &omap2xxx_gpio3_hwmod,
700 .clk = "gpios_ick",
701 .addr = omap2430_gpio3_addr_space,
702 .user = OCP_USER_MPU | OCP_USER_SDMA,
703};
704
705/* l4_wkup -> gpio4 */
706static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
707 {
708 .pa_start = 0x49012000,
709 .pa_end = 0x490121ff,
710 .flags = ADDR_TYPE_RT
711 },
712 { }
713};
714
715static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
716 .master = &omap2xxx_l4_wkup_hwmod,
717 .slave = &omap2xxx_gpio4_hwmod,
718 .clk = "gpios_ick",
719 .addr = omap2430_gpio4_addr_space,
720 .user = OCP_USER_MPU | OCP_USER_SDMA,
721};
722
723/* l4_core -> gpio5 */
724static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
725 {
726 .pa_start = 0x480B6000,
727 .pa_end = 0x480B61ff,
728 .flags = ADDR_TYPE_RT
729 },
730 { }
731};
732
733static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
734 .master = &omap2xxx_l4_core_hwmod,
735 .slave = &omap2430_gpio5_hwmod,
736 .clk = "gpio5_ick",
737 .addr = omap2430_gpio5_addr_space,
738 .user = OCP_USER_MPU | OCP_USER_SDMA,
739};
740
741/* dma_system -> L3 */
742static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
743 .master = &omap2430_dma_system_hwmod,
744 .slave = &omap2xxx_l3_main_hwmod,
745 .clk = "core_l3_ck",
746 .user = OCP_USER_MPU | OCP_USER_SDMA,
747};
748
749/* l4_core -> dma_system */
750static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
751 .master = &omap2xxx_l4_core_hwmod,
752 .slave = &omap2430_dma_system_hwmod,
753 .clk = "sdma_ick",
754 .addr = omap2_dma_system_addrs,
755 .user = OCP_USER_MPU | OCP_USER_SDMA,
756};
757
758/* l4_core -> mailbox */
759static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
760 .master = &omap2xxx_l4_core_hwmod,
761 .slave = &omap2430_mailbox_hwmod,
762 .addr = omap2_mailbox_addrs,
763 .user = OCP_USER_MPU | OCP_USER_SDMA,
764};
765
766/* l4_core -> mcbsp1 */
767static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
768 .master = &omap2xxx_l4_core_hwmod,
769 .slave = &omap2430_mcbsp1_hwmod,
770 .clk = "mcbsp1_ick",
771 .addr = omap2_mcbsp1_addrs,
772 .user = OCP_USER_MPU | OCP_USER_SDMA,
773};
774
775/* l4_core -> mcbsp2 */
776static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
777 .master = &omap2xxx_l4_core_hwmod,
778 .slave = &omap2430_mcbsp2_hwmod,
779 .clk = "mcbsp2_ick",
780 .addr = omap2xxx_mcbsp2_addrs,
781 .user = OCP_USER_MPU | OCP_USER_SDMA,
782};
783
784static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
785 {
786 .name = "mpu",
787 .pa_start = 0x4808C000,
788 .pa_end = 0x4808C0ff,
789 .flags = ADDR_TYPE_RT
790 },
791 { }
792};
793
794/* l4_core -> mcbsp3 */
795static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
796 .master = &omap2xxx_l4_core_hwmod,
797 .slave = &omap2430_mcbsp3_hwmod,
798 .clk = "mcbsp3_ick",
799 .addr = omap2430_mcbsp3_addrs,
800 .user = OCP_USER_MPU | OCP_USER_SDMA,
801};
802
803static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
804 {
805 .name = "mpu",
806 .pa_start = 0x4808E000,
807 .pa_end = 0x4808E0ff,
808 .flags = ADDR_TYPE_RT
809 },
810 { }
811};
812
813/* l4_core -> mcbsp4 */
814static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
815 .master = &omap2xxx_l4_core_hwmod,
816 .slave = &omap2430_mcbsp4_hwmod,
817 .clk = "mcbsp4_ick",
818 .addr = omap2430_mcbsp4_addrs,
819 .user = OCP_USER_MPU | OCP_USER_SDMA,
820};
821
822static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
823 {
824 .name = "mpu",
825 .pa_start = 0x48096000,
826 .pa_end = 0x480960ff,
827 .flags = ADDR_TYPE_RT
828 },
829 { }
830};
831
832/* l4_core -> mcbsp5 */
833static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
834 .master = &omap2xxx_l4_core_hwmod,
835 .slave = &omap2430_mcbsp5_hwmod,
836 .clk = "mcbsp5_ick",
837 .addr = omap2430_mcbsp5_addrs,
838 .user = OCP_USER_MPU | OCP_USER_SDMA,
839};
840
841static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
842 &omap2xxx_l3_main__l4_core,
843 &omap2xxx_mpu__l3_main,
844 &omap2xxx_dss__l3,
845 &omap2430_usbhsotg__l3,
846 &omap2430_l4_core__i2c1,
847 &omap2430_l4_core__i2c2,
848 &omap2xxx_l4_core__l4_wkup,
849 &omap2_l4_core__uart1,
850 &omap2_l4_core__uart2,
851 &omap2_l4_core__uart3,
852 &omap2430_l4_core__usbhsotg,
853 &omap2430_l4_core__mmc1,
854 &omap2430_l4_core__mmc2,
855 &omap2xxx_l4_core__mcspi1,
856 &omap2xxx_l4_core__mcspi2,
857 &omap2430_l4_core__mcspi3,
858 &omap2430_l3__iva,
859 &omap2430_l4_wkup__timer1,
860 &omap2xxx_l4_core__timer2,
861 &omap2xxx_l4_core__timer3,
862 &omap2xxx_l4_core__timer4,
863 &omap2xxx_l4_core__timer5,
864 &omap2xxx_l4_core__timer6,
865 &omap2xxx_l4_core__timer7,
866 &omap2xxx_l4_core__timer8,
867 &omap2xxx_l4_core__timer9,
868 &omap2xxx_l4_core__timer10,
869 &omap2xxx_l4_core__timer11,
870 &omap2xxx_l4_core__timer12,
871 &omap2430_l4_wkup__wd_timer2,
872 &omap2xxx_l4_core__dss,
873 &omap2xxx_l4_core__dss_dispc,
874 &omap2xxx_l4_core__dss_rfbi,
875 &omap2xxx_l4_core__dss_venc,
876 &omap2430_l4_wkup__gpio1,
877 &omap2430_l4_wkup__gpio2,
878 &omap2430_l4_wkup__gpio3,
879 &omap2430_l4_wkup__gpio4,
880 &omap2430_l4_core__gpio5,
881 &omap2430_dma_system__l3,
882 &omap2430_l4_core__dma_system,
883 &omap2430_l4_core__mailbox,
884 &omap2430_l4_core__mcbsp1,
885 &omap2430_l4_core__mcbsp2,
886 &omap2430_l4_core__mcbsp3,
887 &omap2430_l4_core__mcbsp4,
888 &omap2430_l4_core__mcbsp5,
2066 NULL, 889 NULL,
2067}; 890};
2068 891
2069int __init omap2430_hwmod_init(void) 892int __init omap2430_hwmod_init(void)
2070{ 893{
2071 return omap_hwmod_register(omap2430_hwmods); 894 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
2072} 895}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 4f3547c2a49..5178e40e84f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -15,10 +15,12 @@
15 15
16#include <plat/omap_hwmod.h> 16#include <plat/omap_hwmod.h>
17#include <plat/serial.h> 17#include <plat/serial.h>
18#include <plat/l3_2xxx.h>
19#include <plat/l4_2xxx.h>
18 20
19#include "omap_hwmod_common_data.h" 21#include "omap_hwmod_common_data.h"
20 22
21struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { 23static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
22 { 24 {
23 .pa_start = OMAP2_UART1_BASE, 25 .pa_start = OMAP2_UART1_BASE,
24 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, 26 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
@@ -27,7 +29,7 @@ struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
27 { } 29 { }
28}; 30};
29 31
30struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { 32static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
31 { 33 {
32 .pa_start = OMAP2_UART2_BASE, 34 .pa_start = OMAP2_UART2_BASE,
33 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, 35 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
@@ -36,7 +38,7 @@ struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
36 { } 38 { }
37}; 39};
38 40
39struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { 41static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
40 { 42 {
41 .pa_start = OMAP2_UART3_BASE, 43 .pa_start = OMAP2_UART3_BASE,
42 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, 44 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
@@ -45,7 +47,7 @@ struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
45 { } 47 { }
46}; 48};
47 49
48struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { 50static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
49 { 51 {
50 .pa_start = 0x4802a000, 52 .pa_start = 0x4802a000,
51 .pa_end = 0x4802a000 + SZ_1K - 1, 53 .pa_end = 0x4802a000 + SZ_1K - 1,
@@ -54,7 +56,7 @@ struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
54 { } 56 { }
55}; 57};
56 58
57struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { 59static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
58 { 60 {
59 .pa_start = 0x48078000, 61 .pa_start = 0x48078000,
60 .pa_end = 0x48078000 + SZ_1K - 1, 62 .pa_end = 0x48078000 + SZ_1K - 1,
@@ -63,7 +65,7 @@ struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
63 { } 65 { }
64}; 66};
65 67
66struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { 68static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
67 { 69 {
68 .pa_start = 0x4807a000, 70 .pa_start = 0x4807a000,
69 .pa_end = 0x4807a000 + SZ_1K - 1, 71 .pa_end = 0x4807a000 + SZ_1K - 1,
@@ -72,7 +74,7 @@ struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
72 { } 74 { }
73}; 75};
74 76
75struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { 77static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
76 { 78 {
77 .pa_start = 0x4807c000, 79 .pa_start = 0x4807c000,
78 .pa_end = 0x4807c000 + SZ_1K - 1, 80 .pa_end = 0x4807c000 + SZ_1K - 1,
@@ -81,7 +83,7 @@ struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
81 { } 83 { }
82}; 84};
83 85
84struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { 86static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
85 { 87 {
86 .pa_start = 0x4807e000, 88 .pa_start = 0x4807e000,
87 .pa_end = 0x4807e000 + SZ_1K - 1, 89 .pa_end = 0x4807e000 + SZ_1K - 1,
@@ -90,7 +92,7 @@ struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
90 { } 92 { }
91}; 93};
92 94
93struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { 95static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
94 { 96 {
95 .pa_start = 0x48080000, 97 .pa_start = 0x48080000,
96 .pa_end = 0x48080000 + SZ_1K - 1, 98 .pa_end = 0x48080000 + SZ_1K - 1,
@@ -99,7 +101,7 @@ struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
99 { } 101 { }
100}; 102};
101 103
102struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { 104static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
103 { 105 {
104 .pa_start = 0x48082000, 106 .pa_start = 0x48082000,
105 .pa_end = 0x48082000 + SZ_1K - 1, 107 .pa_end = 0x48082000 + SZ_1K - 1,
@@ -108,7 +110,7 @@ struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
108 { } 110 { }
109}; 111};
110 112
111struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = { 113static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
112 { 114 {
113 .pa_start = 0x48084000, 115 .pa_start = 0x48084000,
114 .pa_end = 0x48084000 + SZ_1K - 1, 116 .pa_end = 0x48084000 + SZ_1K - 1,
@@ -127,4 +129,246 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
127 { } 129 { }
128}; 130};
129 131
132/*
133 * Common interconnect data
134 */
135
136/* L3 -> L4_CORE interface */
137struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
138 .master = &omap2xxx_l3_main_hwmod,
139 .slave = &omap2xxx_l4_core_hwmod,
140 .user = OCP_USER_MPU | OCP_USER_SDMA,
141};
142
143/* MPU -> L3 interface */
144struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
145 .master = &omap2xxx_mpu_hwmod,
146 .slave = &omap2xxx_l3_main_hwmod,
147 .user = OCP_USER_MPU,
148};
149
150/* DSS -> l3 */
151struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
152 .master = &omap2xxx_dss_core_hwmod,
153 .slave = &omap2xxx_l3_main_hwmod,
154 .fw = {
155 .omap2 = {
156 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
157 .flags = OMAP_FIREWALL_L3,
158 }
159 },
160 .user = OCP_USER_MPU | OCP_USER_SDMA,
161};
162
163/* L4_CORE -> L4_WKUP interface */
164struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
165 .master = &omap2xxx_l4_core_hwmod,
166 .slave = &omap2xxx_l4_wkup_hwmod,
167 .user = OCP_USER_MPU | OCP_USER_SDMA,
168};
169
170/* L4 CORE -> UART1 interface */
171struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
172 .master = &omap2xxx_l4_core_hwmod,
173 .slave = &omap2xxx_uart1_hwmod,
174 .clk = "uart1_ick",
175 .addr = omap2xxx_uart1_addr_space,
176 .user = OCP_USER_MPU | OCP_USER_SDMA,
177};
178
179/* L4 CORE -> UART2 interface */
180struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
181 .master = &omap2xxx_l4_core_hwmod,
182 .slave = &omap2xxx_uart2_hwmod,
183 .clk = "uart2_ick",
184 .addr = omap2xxx_uart2_addr_space,
185 .user = OCP_USER_MPU | OCP_USER_SDMA,
186};
187
188/* L4 PER -> UART3 interface */
189struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
190 .master = &omap2xxx_l4_core_hwmod,
191 .slave = &omap2xxx_uart3_hwmod,
192 .clk = "uart3_ick",
193 .addr = omap2xxx_uart3_addr_space,
194 .user = OCP_USER_MPU | OCP_USER_SDMA,
195};
196
197/* l4 core -> mcspi1 interface */
198struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
199 .master = &omap2xxx_l4_core_hwmod,
200 .slave = &omap2xxx_mcspi1_hwmod,
201 .clk = "mcspi1_ick",
202 .addr = omap2_mcspi1_addr_space,
203 .user = OCP_USER_MPU | OCP_USER_SDMA,
204};
205
206/* l4 core -> mcspi2 interface */
207struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
208 .master = &omap2xxx_l4_core_hwmod,
209 .slave = &omap2xxx_mcspi2_hwmod,
210 .clk = "mcspi2_ick",
211 .addr = omap2_mcspi2_addr_space,
212 .user = OCP_USER_MPU | OCP_USER_SDMA,
213};
214
215/* l4_core -> timer2 */
216struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
217 .master = &omap2xxx_l4_core_hwmod,
218 .slave = &omap2xxx_timer2_hwmod,
219 .clk = "gpt2_ick",
220 .addr = omap2xxx_timer2_addrs,
221 .user = OCP_USER_MPU | OCP_USER_SDMA,
222};
223
224/* l4_core -> timer3 */
225struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
226 .master = &omap2xxx_l4_core_hwmod,
227 .slave = &omap2xxx_timer3_hwmod,
228 .clk = "gpt3_ick",
229 .addr = omap2xxx_timer3_addrs,
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231};
232
233/* l4_core -> timer4 */
234struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
235 .master = &omap2xxx_l4_core_hwmod,
236 .slave = &omap2xxx_timer4_hwmod,
237 .clk = "gpt4_ick",
238 .addr = omap2xxx_timer4_addrs,
239 .user = OCP_USER_MPU | OCP_USER_SDMA,
240};
241
242/* l4_core -> timer5 */
243struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
244 .master = &omap2xxx_l4_core_hwmod,
245 .slave = &omap2xxx_timer5_hwmod,
246 .clk = "gpt5_ick",
247 .addr = omap2xxx_timer5_addrs,
248 .user = OCP_USER_MPU | OCP_USER_SDMA,
249};
250
251/* l4_core -> timer6 */
252struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
253 .master = &omap2xxx_l4_core_hwmod,
254 .slave = &omap2xxx_timer6_hwmod,
255 .clk = "gpt6_ick",
256 .addr = omap2xxx_timer6_addrs,
257 .user = OCP_USER_MPU | OCP_USER_SDMA,
258};
259
260/* l4_core -> timer7 */
261struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
262 .master = &omap2xxx_l4_core_hwmod,
263 .slave = &omap2xxx_timer7_hwmod,
264 .clk = "gpt7_ick",
265 .addr = omap2xxx_timer7_addrs,
266 .user = OCP_USER_MPU | OCP_USER_SDMA,
267};
268
269/* l4_core -> timer8 */
270struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
271 .master = &omap2xxx_l4_core_hwmod,
272 .slave = &omap2xxx_timer8_hwmod,
273 .clk = "gpt8_ick",
274 .addr = omap2xxx_timer8_addrs,
275 .user = OCP_USER_MPU | OCP_USER_SDMA,
276};
277
278/* l4_core -> timer9 */
279struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
280 .master = &omap2xxx_l4_core_hwmod,
281 .slave = &omap2xxx_timer9_hwmod,
282 .clk = "gpt9_ick",
283 .addr = omap2xxx_timer9_addrs,
284 .user = OCP_USER_MPU | OCP_USER_SDMA,
285};
286
287/* l4_core -> timer10 */
288struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
289 .master = &omap2xxx_l4_core_hwmod,
290 .slave = &omap2xxx_timer10_hwmod,
291 .clk = "gpt10_ick",
292 .addr = omap2_timer10_addrs,
293 .user = OCP_USER_MPU | OCP_USER_SDMA,
294};
295
296/* l4_core -> timer11 */
297struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
298 .master = &omap2xxx_l4_core_hwmod,
299 .slave = &omap2xxx_timer11_hwmod,
300 .clk = "gpt11_ick",
301 .addr = omap2_timer11_addrs,
302 .user = OCP_USER_MPU | OCP_USER_SDMA,
303};
304
305/* l4_core -> timer12 */
306struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
307 .master = &omap2xxx_l4_core_hwmod,
308 .slave = &omap2xxx_timer12_hwmod,
309 .clk = "gpt12_ick",
310 .addr = omap2xxx_timer12_addrs,
311 .user = OCP_USER_MPU | OCP_USER_SDMA,
312};
313
314/* l4_core -> dss */
315struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
316 .master = &omap2xxx_l4_core_hwmod,
317 .slave = &omap2xxx_dss_core_hwmod,
318 .clk = "dss_ick",
319 .addr = omap2_dss_addrs,
320 .fw = {
321 .omap2 = {
322 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
323 .flags = OMAP_FIREWALL_L4,
324 }
325 },
326 .user = OCP_USER_MPU | OCP_USER_SDMA,
327};
328
329/* l4_core -> dss_dispc */
330struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
331 .master = &omap2xxx_l4_core_hwmod,
332 .slave = &omap2xxx_dss_dispc_hwmod,
333 .clk = "dss_ick",
334 .addr = omap2_dss_dispc_addrs,
335 .fw = {
336 .omap2 = {
337 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
338 .flags = OMAP_FIREWALL_L4,
339 }
340 },
341 .user = OCP_USER_MPU | OCP_USER_SDMA,
342};
343
344/* l4_core -> dss_rfbi */
345struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
346 .master = &omap2xxx_l4_core_hwmod,
347 .slave = &omap2xxx_dss_rfbi_hwmod,
348 .clk = "dss_ick",
349 .addr = omap2_dss_rfbi_addrs,
350 .fw = {
351 .omap2 = {
352 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
353 .flags = OMAP_FIREWALL_L4,
354 }
355 },
356 .user = OCP_USER_MPU | OCP_USER_SDMA,
357};
358
359/* l4_core -> dss_venc */
360struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
361 .master = &omap2xxx_l4_core_hwmod,
362 .slave = &omap2xxx_dss_venc_hwmod,
363 .clk = "dss_ick",
364 .addr = omap2_dss_venc_addrs,
365 .fw = {
366 .omap2 = {
367 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
368 .flags = OMAP_FIREWALL_L4,
369 }
370 },
371 .flags = OCPIF_SWSUP_IDLE,
372 .user = OCP_USER_MPU | OCP_USER_SDMA,
373};
130 374
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 2a6729741b0..45aaa07e302 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -10,6 +10,7 @@
10 */ 10 */
11#include <plat/omap_hwmod.h> 11#include <plat/omap_hwmod.h>
12#include <plat/serial.h> 12#include <plat/serial.h>
13#include <plat/gpio.h>
13#include <plat/dma.h> 14#include <plat/dma.h>
14#include <plat/dmtimer.h> 15#include <plat/dmtimer.h>
15#include <plat/mcspi.h> 16#include <plat/mcspi.h>
@@ -17,6 +18,8 @@
17#include <mach/irqs.h> 18#include <mach/irqs.h>
18 19
19#include "omap_hwmod_common_data.h" 20#include "omap_hwmod_common_data.h"
21#include "cm-regbits-24xx.h"
22#include "prm-regbits-24xx.h"
20#include "wd_timer.h" 23#include "wd_timer.h"
21 24
22struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { 25struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
@@ -170,3 +173,562 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
170 .sysc = &omap2xxx_mcspi_sysc, 173 .sysc = &omap2xxx_mcspi_sysc,
171 .rev = OMAP2_MCSPI_REV, 174 .rev = OMAP2_MCSPI_REV,
172}; 175};
176
177/*
178 * IP blocks
179 */
180
181/* L3 */
182struct omap_hwmod omap2xxx_l3_main_hwmod = {
183 .name = "l3_main",
184 .class = &l3_hwmod_class,
185 .flags = HWMOD_NO_IDLEST,
186};
187
188/* L4 CORE */
189struct omap_hwmod omap2xxx_l4_core_hwmod = {
190 .name = "l4_core",
191 .class = &l4_hwmod_class,
192 .flags = HWMOD_NO_IDLEST,
193};
194
195/* L4 WKUP */
196struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
197 .name = "l4_wkup",
198 .class = &l4_hwmod_class,
199 .flags = HWMOD_NO_IDLEST,
200};
201
202/* MPU */
203struct omap_hwmod omap2xxx_mpu_hwmod = {
204 .name = "mpu",
205 .class = &mpu_hwmod_class,
206 .main_clk = "mpu_ck",
207};
208
209/* IVA2 */
210struct omap_hwmod omap2xxx_iva_hwmod = {
211 .name = "iva",
212 .class = &iva_hwmod_class,
213};
214
215/* always-on timers dev attribute */
216static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
217 .timer_capability = OMAP_TIMER_ALWON,
218};
219
220/* pwm timers dev attribute */
221static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
222 .timer_capability = OMAP_TIMER_HAS_PWM,
223};
224
225/* timer1 */
226
227struct omap_hwmod omap2xxx_timer1_hwmod = {
228 .name = "timer1",
229 .mpu_irqs = omap2_timer1_mpu_irqs,
230 .main_clk = "gpt1_fck",
231 .prcm = {
232 .omap2 = {
233 .prcm_reg_id = 1,
234 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
235 .module_offs = WKUP_MOD,
236 .idlest_reg_id = 1,
237 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
238 },
239 },
240 .dev_attr = &capability_alwon_dev_attr,
241 .class = &omap2xxx_timer_hwmod_class,
242};
243
244/* timer2 */
245
246struct omap_hwmod omap2xxx_timer2_hwmod = {
247 .name = "timer2",
248 .mpu_irqs = omap2_timer2_mpu_irqs,
249 .main_clk = "gpt2_fck",
250 .prcm = {
251 .omap2 = {
252 .prcm_reg_id = 1,
253 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
254 .module_offs = CORE_MOD,
255 .idlest_reg_id = 1,
256 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
257 },
258 },
259 .dev_attr = &capability_alwon_dev_attr,
260 .class = &omap2xxx_timer_hwmod_class,
261};
262
263/* timer3 */
264
265struct omap_hwmod omap2xxx_timer3_hwmod = {
266 .name = "timer3",
267 .mpu_irqs = omap2_timer3_mpu_irqs,
268 .main_clk = "gpt3_fck",
269 .prcm = {
270 .omap2 = {
271 .prcm_reg_id = 1,
272 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
273 .module_offs = CORE_MOD,
274 .idlest_reg_id = 1,
275 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
276 },
277 },
278 .dev_attr = &capability_alwon_dev_attr,
279 .class = &omap2xxx_timer_hwmod_class,
280};
281
282/* timer4 */
283
284struct omap_hwmod omap2xxx_timer4_hwmod = {
285 .name = "timer4",
286 .mpu_irqs = omap2_timer4_mpu_irqs,
287 .main_clk = "gpt4_fck",
288 .prcm = {
289 .omap2 = {
290 .prcm_reg_id = 1,
291 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
292 .module_offs = CORE_MOD,
293 .idlest_reg_id = 1,
294 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
295 },
296 },
297 .dev_attr = &capability_alwon_dev_attr,
298 .class = &omap2xxx_timer_hwmod_class,
299};
300
301/* timer5 */
302
303struct omap_hwmod omap2xxx_timer5_hwmod = {
304 .name = "timer5",
305 .mpu_irqs = omap2_timer5_mpu_irqs,
306 .main_clk = "gpt5_fck",
307 .prcm = {
308 .omap2 = {
309 .prcm_reg_id = 1,
310 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
311 .module_offs = CORE_MOD,
312 .idlest_reg_id = 1,
313 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
314 },
315 },
316 .dev_attr = &capability_alwon_dev_attr,
317 .class = &omap2xxx_timer_hwmod_class,
318};
319
320/* timer6 */
321
322struct omap_hwmod omap2xxx_timer6_hwmod = {
323 .name = "timer6",
324 .mpu_irqs = omap2_timer6_mpu_irqs,
325 .main_clk = "gpt6_fck",
326 .prcm = {
327 .omap2 = {
328 .prcm_reg_id = 1,
329 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
330 .module_offs = CORE_MOD,
331 .idlest_reg_id = 1,
332 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
333 },
334 },
335 .dev_attr = &capability_alwon_dev_attr,
336 .class = &omap2xxx_timer_hwmod_class,
337};
338
339/* timer7 */
340
341struct omap_hwmod omap2xxx_timer7_hwmod = {
342 .name = "timer7",
343 .mpu_irqs = omap2_timer7_mpu_irqs,
344 .main_clk = "gpt7_fck",
345 .prcm = {
346 .omap2 = {
347 .prcm_reg_id = 1,
348 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
349 .module_offs = CORE_MOD,
350 .idlest_reg_id = 1,
351 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
352 },
353 },
354 .dev_attr = &capability_alwon_dev_attr,
355 .class = &omap2xxx_timer_hwmod_class,
356};
357
358/* timer8 */
359
360struct omap_hwmod omap2xxx_timer8_hwmod = {
361 .name = "timer8",
362 .mpu_irqs = omap2_timer8_mpu_irqs,
363 .main_clk = "gpt8_fck",
364 .prcm = {
365 .omap2 = {
366 .prcm_reg_id = 1,
367 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
368 .module_offs = CORE_MOD,
369 .idlest_reg_id = 1,
370 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
371 },
372 },
373 .dev_attr = &capability_alwon_dev_attr,
374 .class = &omap2xxx_timer_hwmod_class,
375};
376
377/* timer9 */
378
379struct omap_hwmod omap2xxx_timer9_hwmod = {
380 .name = "timer9",
381 .mpu_irqs = omap2_timer9_mpu_irqs,
382 .main_clk = "gpt9_fck",
383 .prcm = {
384 .omap2 = {
385 .prcm_reg_id = 1,
386 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
387 .module_offs = CORE_MOD,
388 .idlest_reg_id = 1,
389 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
390 },
391 },
392 .dev_attr = &capability_pwm_dev_attr,
393 .class = &omap2xxx_timer_hwmod_class,
394};
395
396/* timer10 */
397
398struct omap_hwmod omap2xxx_timer10_hwmod = {
399 .name = "timer10",
400 .mpu_irqs = omap2_timer10_mpu_irqs,
401 .main_clk = "gpt10_fck",
402 .prcm = {
403 .omap2 = {
404 .prcm_reg_id = 1,
405 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
406 .module_offs = CORE_MOD,
407 .idlest_reg_id = 1,
408 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
409 },
410 },
411 .dev_attr = &capability_pwm_dev_attr,
412 .class = &omap2xxx_timer_hwmod_class,
413};
414
415/* timer11 */
416
417struct omap_hwmod omap2xxx_timer11_hwmod = {
418 .name = "timer11",
419 .mpu_irqs = omap2_timer11_mpu_irqs,
420 .main_clk = "gpt11_fck",
421 .prcm = {
422 .omap2 = {
423 .prcm_reg_id = 1,
424 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
425 .module_offs = CORE_MOD,
426 .idlest_reg_id = 1,
427 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
428 },
429 },
430 .dev_attr = &capability_pwm_dev_attr,
431 .class = &omap2xxx_timer_hwmod_class,
432};
433
434/* timer12 */
435
436struct omap_hwmod omap2xxx_timer12_hwmod = {
437 .name = "timer12",
438 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
439 .main_clk = "gpt12_fck",
440 .prcm = {
441 .omap2 = {
442 .prcm_reg_id = 1,
443 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
444 .module_offs = CORE_MOD,
445 .idlest_reg_id = 1,
446 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
447 },
448 },
449 .dev_attr = &capability_pwm_dev_attr,
450 .class = &omap2xxx_timer_hwmod_class,
451};
452
453/* wd_timer2 */
454struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
455 .name = "wd_timer2",
456 .class = &omap2xxx_wd_timer_hwmod_class,
457 .main_clk = "mpu_wdt_fck",
458 .prcm = {
459 .omap2 = {
460 .prcm_reg_id = 1,
461 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
462 .module_offs = WKUP_MOD,
463 .idlest_reg_id = 1,
464 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
465 },
466 },
467};
468
469/* UART1 */
470
471struct omap_hwmod omap2xxx_uart1_hwmod = {
472 .name = "uart1",
473 .mpu_irqs = omap2_uart1_mpu_irqs,
474 .sdma_reqs = omap2_uart1_sdma_reqs,
475 .main_clk = "uart1_fck",
476 .prcm = {
477 .omap2 = {
478 .module_offs = CORE_MOD,
479 .prcm_reg_id = 1,
480 .module_bit = OMAP24XX_EN_UART1_SHIFT,
481 .idlest_reg_id = 1,
482 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
483 },
484 },
485 .class = &omap2_uart_class,
486};
487
488/* UART2 */
489
490struct omap_hwmod omap2xxx_uart2_hwmod = {
491 .name = "uart2",
492 .mpu_irqs = omap2_uart2_mpu_irqs,
493 .sdma_reqs = omap2_uart2_sdma_reqs,
494 .main_clk = "uart2_fck",
495 .prcm = {
496 .omap2 = {
497 .module_offs = CORE_MOD,
498 .prcm_reg_id = 1,
499 .module_bit = OMAP24XX_EN_UART2_SHIFT,
500 .idlest_reg_id = 1,
501 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
502 },
503 },
504 .class = &omap2_uart_class,
505};
506
507/* UART3 */
508
509struct omap_hwmod omap2xxx_uart3_hwmod = {
510 .name = "uart3",
511 .mpu_irqs = omap2_uart3_mpu_irqs,
512 .sdma_reqs = omap2_uart3_sdma_reqs,
513 .main_clk = "uart3_fck",
514 .prcm = {
515 .omap2 = {
516 .module_offs = CORE_MOD,
517 .prcm_reg_id = 2,
518 .module_bit = OMAP24XX_EN_UART3_SHIFT,
519 .idlest_reg_id = 2,
520 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
521 },
522 },
523 .class = &omap2_uart_class,
524};
525
526/* dss */
527
528static struct omap_hwmod_opt_clk dss_opt_clks[] = {
529 /*
530 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
531 * driver does not use these clocks.
532 */
533 { .role = "tv_clk", .clk = "dss_54m_fck" },
534 { .role = "sys_clk", .clk = "dss2_fck" },
535};
536
537struct omap_hwmod omap2xxx_dss_core_hwmod = {
538 .name = "dss_core",
539 .class = &omap2_dss_hwmod_class,
540 .main_clk = "dss1_fck", /* instead of dss_fck */
541 .sdma_reqs = omap2xxx_dss_sdma_chs,
542 .prcm = {
543 .omap2 = {
544 .prcm_reg_id = 1,
545 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
546 .module_offs = CORE_MOD,
547 .idlest_reg_id = 1,
548 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
549 },
550 },
551 .opt_clks = dss_opt_clks,
552 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
553 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
554};
555
556struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
557 .name = "dss_dispc",
558 .class = &omap2_dispc_hwmod_class,
559 .mpu_irqs = omap2_dispc_irqs,
560 .main_clk = "dss1_fck",
561 .prcm = {
562 .omap2 = {
563 .prcm_reg_id = 1,
564 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
565 .module_offs = CORE_MOD,
566 .idlest_reg_id = 1,
567 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
568 },
569 },
570 .flags = HWMOD_NO_IDLEST,
571 .dev_attr = &omap2_3_dss_dispc_dev_attr
572};
573
574static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
575 { .role = "ick", .clk = "dss_ick" },
576};
577
578struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
579 .name = "dss_rfbi",
580 .class = &omap2_rfbi_hwmod_class,
581 .main_clk = "dss1_fck",
582 .prcm = {
583 .omap2 = {
584 .prcm_reg_id = 1,
585 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
586 .module_offs = CORE_MOD,
587 },
588 },
589 .opt_clks = dss_rfbi_opt_clks,
590 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
591 .flags = HWMOD_NO_IDLEST,
592};
593
594struct omap_hwmod omap2xxx_dss_venc_hwmod = {
595 .name = "dss_venc",
596 .class = &omap2_venc_hwmod_class,
597 .main_clk = "dss_54m_fck",
598 .prcm = {
599 .omap2 = {
600 .prcm_reg_id = 1,
601 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
602 .module_offs = CORE_MOD,
603 },
604 },
605 .flags = HWMOD_NO_IDLEST,
606};
607
608/* gpio dev_attr */
609struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
610 .bank_width = 32,
611 .dbck_flag = false,
612};
613
614/* gpio1 */
615struct omap_hwmod omap2xxx_gpio1_hwmod = {
616 .name = "gpio1",
617 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
618 .mpu_irqs = omap2_gpio1_irqs,
619 .main_clk = "gpios_fck",
620 .prcm = {
621 .omap2 = {
622 .prcm_reg_id = 1,
623 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
624 .module_offs = WKUP_MOD,
625 .idlest_reg_id = 1,
626 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
627 },
628 },
629 .class = &omap2xxx_gpio_hwmod_class,
630 .dev_attr = &omap2xxx_gpio_dev_attr,
631};
632
633/* gpio2 */
634struct omap_hwmod omap2xxx_gpio2_hwmod = {
635 .name = "gpio2",
636 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
637 .mpu_irqs = omap2_gpio2_irqs,
638 .main_clk = "gpios_fck",
639 .prcm = {
640 .omap2 = {
641 .prcm_reg_id = 1,
642 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
643 .module_offs = WKUP_MOD,
644 .idlest_reg_id = 1,
645 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
646 },
647 },
648 .class = &omap2xxx_gpio_hwmod_class,
649 .dev_attr = &omap2xxx_gpio_dev_attr,
650};
651
652/* gpio3 */
653struct omap_hwmod omap2xxx_gpio3_hwmod = {
654 .name = "gpio3",
655 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
656 .mpu_irqs = omap2_gpio3_irqs,
657 .main_clk = "gpios_fck",
658 .prcm = {
659 .omap2 = {
660 .prcm_reg_id = 1,
661 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
662 .module_offs = WKUP_MOD,
663 .idlest_reg_id = 1,
664 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
665 },
666 },
667 .class = &omap2xxx_gpio_hwmod_class,
668 .dev_attr = &omap2xxx_gpio_dev_attr,
669};
670
671/* gpio4 */
672struct omap_hwmod omap2xxx_gpio4_hwmod = {
673 .name = "gpio4",
674 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
675 .mpu_irqs = omap2_gpio4_irqs,
676 .main_clk = "gpios_fck",
677 .prcm = {
678 .omap2 = {
679 .prcm_reg_id = 1,
680 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
681 .module_offs = WKUP_MOD,
682 .idlest_reg_id = 1,
683 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
684 },
685 },
686 .class = &omap2xxx_gpio_hwmod_class,
687 .dev_attr = &omap2xxx_gpio_dev_attr,
688};
689
690/* mcspi1 */
691static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
692 .num_chipselect = 4,
693};
694
695struct omap_hwmod omap2xxx_mcspi1_hwmod = {
696 .name = "mcspi1",
697 .mpu_irqs = omap2_mcspi1_mpu_irqs,
698 .sdma_reqs = omap2_mcspi1_sdma_reqs,
699 .main_clk = "mcspi1_fck",
700 .prcm = {
701 .omap2 = {
702 .module_offs = CORE_MOD,
703 .prcm_reg_id = 1,
704 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
705 .idlest_reg_id = 1,
706 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
707 },
708 },
709 .class = &omap2xxx_mcspi_class,
710 .dev_attr = &omap_mcspi1_dev_attr,
711};
712
713/* mcspi2 */
714static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
715 .num_chipselect = 2,
716};
717
718struct omap_hwmod omap2xxx_mcspi2_hwmod = {
719 .name = "mcspi2",
720 .mpu_irqs = omap2_mcspi2_mpu_irqs,
721 .sdma_reqs = omap2_mcspi2_sdma_reqs,
722 .main_clk = "mcspi2_fck",
723 .prcm = {
724 .omap2 = {
725 .module_offs = CORE_MOD,
726 .prcm_reg_id = 1,
727 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
728 .idlest_reg_id = 1,
729 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
730 },
731 },
732 .class = &omap2xxx_mcspi_class,
733 .dev_attr = &omap_mcspi2_dev_attr,
734};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index db86ce90c69..0c65079c2b6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2,6 +2,7 @@
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -38,491 +39,56 @@
38/* 39/*
39 * OMAP3xxx hardware module integration data 40 * OMAP3xxx hardware module integration data
40 * 41 *
41 * ALl of the data in this section should be autogeneratable from the 42 * All of the data in this section should be autogeneratable from the
42 * TI hardware database or other technical documentation. Data that 43 * TI hardware database or other technical documentation. Data that
43 * is driver-specific or driver-kernel integration-specific belongs 44 * is driver-specific or driver-kernel integration-specific belongs
44 * elsewhere. 45 * elsewhere.
45 */ 46 */
46 47
47static struct omap_hwmod omap3xxx_mpu_hwmod; 48/*
48static struct omap_hwmod omap3xxx_iva_hwmod; 49 * IP blocks
49static struct omap_hwmod omap3xxx_l3_main_hwmod; 50 */
50static struct omap_hwmod omap3xxx_l4_core_hwmod;
51static struct omap_hwmod omap3xxx_l4_per_hwmod;
52static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
53static struct omap_hwmod omap3430es1_dss_core_hwmod;
54static struct omap_hwmod omap3xxx_dss_core_hwmod;
55static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
56static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
57static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
58static struct omap_hwmod omap3xxx_dss_venc_hwmod;
59static struct omap_hwmod omap3xxx_i2c1_hwmod;
60static struct omap_hwmod omap3xxx_i2c2_hwmod;
61static struct omap_hwmod omap3xxx_i2c3_hwmod;
62static struct omap_hwmod omap3xxx_gpio1_hwmod;
63static struct omap_hwmod omap3xxx_gpio2_hwmod;
64static struct omap_hwmod omap3xxx_gpio3_hwmod;
65static struct omap_hwmod omap3xxx_gpio4_hwmod;
66static struct omap_hwmod omap3xxx_gpio5_hwmod;
67static struct omap_hwmod omap3xxx_gpio6_hwmod;
68static struct omap_hwmod omap34xx_sr1_hwmod;
69static struct omap_hwmod omap34xx_sr2_hwmod;
70static struct omap_hwmod omap34xx_mcspi1;
71static struct omap_hwmod omap34xx_mcspi2;
72static struct omap_hwmod omap34xx_mcspi3;
73static struct omap_hwmod omap34xx_mcspi4;
74static struct omap_hwmod omap3xxx_mmc1_hwmod;
75static struct omap_hwmod omap3xxx_mmc2_hwmod;
76static struct omap_hwmod omap3xxx_mmc3_hwmod;
77static struct omap_hwmod am35xx_usbhsotg_hwmod;
78
79static struct omap_hwmod omap3xxx_dma_system_hwmod;
80
81static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
82static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
83static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
84static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
85static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
86static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
87static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
89static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
90
91/* L3 -> L4_CORE interface */
92static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
93 .master = &omap3xxx_l3_main_hwmod,
94 .slave = &omap3xxx_l4_core_hwmod,
95 .user = OCP_USER_MPU | OCP_USER_SDMA,
96};
97
98/* L3 -> L4_PER interface */
99static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
100 .master = &omap3xxx_l3_main_hwmod,
101 .slave = &omap3xxx_l4_per_hwmod,
102 .user = OCP_USER_MPU | OCP_USER_SDMA,
103};
104 51
105/* L3 taret configuration and error log registers */ 52/* L3 */
106static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { 53static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
107 { .irq = INT_34XX_L3_DBG_IRQ }, 54 { .irq = INT_34XX_L3_DBG_IRQ },
108 { .irq = INT_34XX_L3_APP_IRQ }, 55 { .irq = INT_34XX_L3_APP_IRQ },
109 { .irq = -1 } 56 { .irq = -1 }
110}; 57};
111 58
112static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
113 {
114 .pa_start = 0x68000000,
115 .pa_end = 0x6800ffff,
116 .flags = ADDR_TYPE_RT,
117 },
118 { }
119};
120
121/* MPU -> L3 interface */
122static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
123 .master = &omap3xxx_mpu_hwmod,
124 .slave = &omap3xxx_l3_main_hwmod,
125 .addr = omap3xxx_l3_main_addrs,
126 .user = OCP_USER_MPU,
127};
128
129/* Slave interfaces on the L3 interconnect */
130static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
131 &omap3xxx_mpu__l3_main,
132};
133
134/* DSS -> l3 */
135static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
136 .master = &omap3xxx_dss_core_hwmod,
137 .slave = &omap3xxx_l3_main_hwmod,
138 .fw = {
139 .omap2 = {
140 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
141 .flags = OMAP_FIREWALL_L3,
142 }
143 },
144 .user = OCP_USER_MPU | OCP_USER_SDMA,
145};
146
147/* Master interfaces on the L3 interconnect */
148static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
149 &omap3xxx_l3_main__l4_core,
150 &omap3xxx_l3_main__l4_per,
151};
152
153/* L3 */
154static struct omap_hwmod omap3xxx_l3_main_hwmod = { 59static struct omap_hwmod omap3xxx_l3_main_hwmod = {
155 .name = "l3_main", 60 .name = "l3_main",
156 .class = &l3_hwmod_class, 61 .class = &l3_hwmod_class,
157 .mpu_irqs = omap3xxx_l3_main_irqs, 62 .mpu_irqs = omap3xxx_l3_main_irqs,
158 .masters = omap3xxx_l3_main_masters,
159 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
160 .slaves = omap3xxx_l3_main_slaves,
161 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
162 .flags = HWMOD_NO_IDLEST, 63 .flags = HWMOD_NO_IDLEST,
163}; 64};
164 65
165static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
166static struct omap_hwmod omap3xxx_uart1_hwmod;
167static struct omap_hwmod omap3xxx_uart2_hwmod;
168static struct omap_hwmod omap3xxx_uart3_hwmod;
169static struct omap_hwmod omap3xxx_uart4_hwmod;
170static struct omap_hwmod am35xx_uart4_hwmod;
171static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
172
173/* l3_core -> usbhsotg interface */
174static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
175 .master = &omap3xxx_usbhsotg_hwmod,
176 .slave = &omap3xxx_l3_main_hwmod,
177 .clk = "core_l3_ick",
178 .user = OCP_USER_MPU,
179};
180
181/* l3_core -> am35xx_usbhsotg interface */
182static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
183 .master = &am35xx_usbhsotg_hwmod,
184 .slave = &omap3xxx_l3_main_hwmod,
185 .clk = "core_l3_ick",
186 .user = OCP_USER_MPU,
187};
188/* L4_CORE -> L4_WKUP interface */
189static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
190 .master = &omap3xxx_l4_core_hwmod,
191 .slave = &omap3xxx_l4_wkup_hwmod,
192 .user = OCP_USER_MPU | OCP_USER_SDMA,
193};
194
195/* L4 CORE -> MMC1 interface */
196static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
197 .master = &omap3xxx_l4_core_hwmod,
198 .slave = &omap3xxx_mmc1_hwmod,
199 .clk = "mmchs1_ick",
200 .addr = omap2430_mmc1_addr_space,
201 .user = OCP_USER_MPU | OCP_USER_SDMA,
202 .flags = OMAP_FIREWALL_L4
203};
204
205/* L4 CORE -> MMC2 interface */
206static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
207 .master = &omap3xxx_l4_core_hwmod,
208 .slave = &omap3xxx_mmc2_hwmod,
209 .clk = "mmchs2_ick",
210 .addr = omap2430_mmc2_addr_space,
211 .user = OCP_USER_MPU | OCP_USER_SDMA,
212 .flags = OMAP_FIREWALL_L4
213};
214
215/* L4 CORE -> MMC3 interface */
216static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
217 {
218 .pa_start = 0x480ad000,
219 .pa_end = 0x480ad1ff,
220 .flags = ADDR_TYPE_RT,
221 },
222 { }
223};
224
225static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
226 .master = &omap3xxx_l4_core_hwmod,
227 .slave = &omap3xxx_mmc3_hwmod,
228 .clk = "mmchs3_ick",
229 .addr = omap3xxx_mmc3_addr_space,
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231 .flags = OMAP_FIREWALL_L4
232};
233
234/* L4 CORE -> UART1 interface */
235static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
236 {
237 .pa_start = OMAP3_UART1_BASE,
238 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
239 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
240 },
241 { }
242};
243
244static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
245 .master = &omap3xxx_l4_core_hwmod,
246 .slave = &omap3xxx_uart1_hwmod,
247 .clk = "uart1_ick",
248 .addr = omap3xxx_uart1_addr_space,
249 .user = OCP_USER_MPU | OCP_USER_SDMA,
250};
251
252/* L4 CORE -> UART2 interface */
253static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
254 {
255 .pa_start = OMAP3_UART2_BASE,
256 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
257 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
258 },
259 { }
260};
261
262static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
263 .master = &omap3xxx_l4_core_hwmod,
264 .slave = &omap3xxx_uart2_hwmod,
265 .clk = "uart2_ick",
266 .addr = omap3xxx_uart2_addr_space,
267 .user = OCP_USER_MPU | OCP_USER_SDMA,
268};
269
270/* L4 PER -> UART3 interface */
271static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
272 {
273 .pa_start = OMAP3_UART3_BASE,
274 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
275 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
276 },
277 { }
278};
279
280static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
281 .master = &omap3xxx_l4_per_hwmod,
282 .slave = &omap3xxx_uart3_hwmod,
283 .clk = "uart3_ick",
284 .addr = omap3xxx_uart3_addr_space,
285 .user = OCP_USER_MPU | OCP_USER_SDMA,
286};
287
288/* L4 PER -> UART4 interface */
289static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
290 {
291 .pa_start = OMAP3_UART4_BASE,
292 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
293 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
294 },
295 { }
296};
297
298static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
299 .master = &omap3xxx_l4_per_hwmod,
300 .slave = &omap3xxx_uart4_hwmod,
301 .clk = "uart4_ick",
302 .addr = omap3xxx_uart4_addr_space,
303 .user = OCP_USER_MPU | OCP_USER_SDMA,
304};
305
306/* AM35xx: L4 CORE -> UART4 interface */
307static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
308 {
309 .pa_start = OMAP3_UART4_AM35XX_BASE,
310 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
311 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
312 },
313};
314
315static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
316 .master = &omap3xxx_l4_core_hwmod,
317 .slave = &am35xx_uart4_hwmod,
318 .clk = "uart4_ick",
319 .addr = am35xx_uart4_addr_space,
320 .user = OCP_USER_MPU | OCP_USER_SDMA,
321};
322
323/* L4 CORE -> I2C1 interface */
324static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
325 .master = &omap3xxx_l4_core_hwmod,
326 .slave = &omap3xxx_i2c1_hwmod,
327 .clk = "i2c1_ick",
328 .addr = omap2_i2c1_addr_space,
329 .fw = {
330 .omap2 = {
331 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
332 .l4_prot_group = 7,
333 .flags = OMAP_FIREWALL_L4,
334 }
335 },
336 .user = OCP_USER_MPU | OCP_USER_SDMA,
337};
338
339/* L4 CORE -> I2C2 interface */
340static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
341 .master = &omap3xxx_l4_core_hwmod,
342 .slave = &omap3xxx_i2c2_hwmod,
343 .clk = "i2c2_ick",
344 .addr = omap2_i2c2_addr_space,
345 .fw = {
346 .omap2 = {
347 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
348 .l4_prot_group = 7,
349 .flags = OMAP_FIREWALL_L4,
350 }
351 },
352 .user = OCP_USER_MPU | OCP_USER_SDMA,
353};
354
355/* L4 CORE -> I2C3 interface */
356static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
357 {
358 .pa_start = 0x48060000,
359 .pa_end = 0x48060000 + SZ_128 - 1,
360 .flags = ADDR_TYPE_RT,
361 },
362 { }
363};
364
365static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
366 .master = &omap3xxx_l4_core_hwmod,
367 .slave = &omap3xxx_i2c3_hwmod,
368 .clk = "i2c3_ick",
369 .addr = omap3xxx_i2c3_addr_space,
370 .fw = {
371 .omap2 = {
372 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
373 .l4_prot_group = 7,
374 .flags = OMAP_FIREWALL_L4,
375 }
376 },
377 .user = OCP_USER_MPU | OCP_USER_SDMA,
378};
379
380static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
381 { .irq = 18},
382 { .irq = -1 }
383};
384
385static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
386 { .irq = 19},
387 { .irq = -1 }
388};
389
390/* L4 CORE -> SR1 interface */
391static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
392 {
393 .pa_start = OMAP34XX_SR1_BASE,
394 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
395 .flags = ADDR_TYPE_RT,
396 },
397 { }
398};
399
400static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
401 .master = &omap3xxx_l4_core_hwmod,
402 .slave = &omap34xx_sr1_hwmod,
403 .clk = "sr_l4_ick",
404 .addr = omap3_sr1_addr_space,
405 .user = OCP_USER_MPU,
406};
407
408/* L4 CORE -> SR1 interface */
409static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
410 {
411 .pa_start = OMAP34XX_SR2_BASE,
412 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
413 .flags = ADDR_TYPE_RT,
414 },
415 { }
416};
417
418static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
419 .master = &omap3xxx_l4_core_hwmod,
420 .slave = &omap34xx_sr2_hwmod,
421 .clk = "sr_l4_ick",
422 .addr = omap3_sr2_addr_space,
423 .user = OCP_USER_MPU,
424};
425
426/*
427* usbhsotg interface data
428*/
429
430static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
431 {
432 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
433 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
434 .flags = ADDR_TYPE_RT
435 },
436 { }
437};
438
439/* l4_core -> usbhsotg */
440static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
441 .master = &omap3xxx_l4_core_hwmod,
442 .slave = &omap3xxx_usbhsotg_hwmod,
443 .clk = "l4_ick",
444 .addr = omap3xxx_usbhsotg_addrs,
445 .user = OCP_USER_MPU,
446};
447
448static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
449 &omap3xxx_usbhsotg__l3,
450};
451
452static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
453 &omap3xxx_l4_core__usbhsotg,
454};
455
456static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
457 {
458 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
459 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
460 .flags = ADDR_TYPE_RT
461 },
462 { }
463};
464
465/* l4_core -> usbhsotg */
466static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
467 .master = &omap3xxx_l4_core_hwmod,
468 .slave = &am35xx_usbhsotg_hwmod,
469 .clk = "l4_ick",
470 .addr = am35xx_usbhsotg_addrs,
471 .user = OCP_USER_MPU,
472};
473
474static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
475 &am35xx_usbhsotg__l3,
476};
477
478static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
479 &am35xx_l4_core__usbhsotg,
480};
481/* Slave interfaces on the L4_CORE interconnect */
482static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
483 &omap3xxx_l3_main__l4_core,
484};
485
486/* L4 CORE */ 66/* L4 CORE */
487static struct omap_hwmod omap3xxx_l4_core_hwmod = { 67static struct omap_hwmod omap3xxx_l4_core_hwmod = {
488 .name = "l4_core", 68 .name = "l4_core",
489 .class = &l4_hwmod_class, 69 .class = &l4_hwmod_class,
490 .slaves = omap3xxx_l4_core_slaves,
491 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
492 .flags = HWMOD_NO_IDLEST, 70 .flags = HWMOD_NO_IDLEST,
493}; 71};
494 72
495/* Slave interfaces on the L4_PER interconnect */
496static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
497 &omap3xxx_l3_main__l4_per,
498};
499
500/* L4 PER */ 73/* L4 PER */
501static struct omap_hwmod omap3xxx_l4_per_hwmod = { 74static struct omap_hwmod omap3xxx_l4_per_hwmod = {
502 .name = "l4_per", 75 .name = "l4_per",
503 .class = &l4_hwmod_class, 76 .class = &l4_hwmod_class,
504 .slaves = omap3xxx_l4_per_slaves,
505 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
506 .flags = HWMOD_NO_IDLEST, 77 .flags = HWMOD_NO_IDLEST,
507}; 78};
508 79
509/* Slave interfaces on the L4_WKUP interconnect */
510static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
511 &omap3xxx_l4_core__l4_wkup,
512};
513
514/* L4 WKUP */ 80/* L4 WKUP */
515static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 81static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
516 .name = "l4_wkup", 82 .name = "l4_wkup",
517 .class = &l4_hwmod_class, 83 .class = &l4_hwmod_class,
518 .slaves = omap3xxx_l4_wkup_slaves,
519 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
520 .flags = HWMOD_NO_IDLEST, 84 .flags = HWMOD_NO_IDLEST,
521}; 85};
522 86
523/* Master interfaces on the MPU device */ 87/* L4 SEC */
524static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { 88static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
525 &omap3xxx_mpu__l3_main, 89 .name = "l4_sec",
90 .class = &l4_hwmod_class,
91 .flags = HWMOD_NO_IDLEST,
526}; 92};
527 93
528/* MPU */ 94/* MPU */
@@ -530,35 +96,22 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
530 .name = "mpu", 96 .name = "mpu",
531 .class = &mpu_hwmod_class, 97 .class = &mpu_hwmod_class,
532 .main_clk = "arm_fck", 98 .main_clk = "arm_fck",
533 .masters = omap3xxx_mpu_masters,
534 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
535}; 99};
536 100
537/* 101/* IVA2 (IVA2) */
538 * IVA2_2 interface data 102static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
539 */ 103 { .name = "logic", .rst_shift = 0 },
540 104 { .name = "seq0", .rst_shift = 1 },
541/* IVA2 <- L3 interface */ 105 { .name = "seq1", .rst_shift = 2 },
542static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
543 .master = &omap3xxx_l3_main_hwmod,
544 .slave = &omap3xxx_iva_hwmod,
545 .clk = "iva2_ck",
546 .user = OCP_USER_MPU | OCP_USER_SDMA,
547}; 106};
548 107
549static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
550 &omap3xxx_l3__iva,
551};
552
553/*
554 * IVA2 (IVA2)
555 */
556
557static struct omap_hwmod omap3xxx_iva_hwmod = { 108static struct omap_hwmod omap3xxx_iva_hwmod = {
558 .name = "iva", 109 .name = "iva",
559 .class = &iva_hwmod_class, 110 .class = &iva_hwmod_class,
560 .masters = omap3xxx_iva_masters, 111 .clkdm_name = "iva2_clkdm",
561 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), 112 .rst_lines = omap3xxx_iva_resets,
113 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
114 .main_clk = "iva2_ck",
562}; 115};
563 116
564/* timer class */ 117/* timer class */
@@ -597,46 +150,20 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
597 150
598/* secure timers dev attribute */ 151/* secure timers dev attribute */
599static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { 152static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
600 .timer_capability = OMAP_TIMER_SECURE, 153 .timer_capability = OMAP_TIMER_SECURE,
601}; 154};
602 155
603/* always-on timers dev attribute */ 156/* always-on timers dev attribute */
604static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 157static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
605 .timer_capability = OMAP_TIMER_ALWON, 158 .timer_capability = OMAP_TIMER_ALWON,
606}; 159};
607 160
608/* pwm timers dev attribute */ 161/* pwm timers dev attribute */
609static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 162static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
610 .timer_capability = OMAP_TIMER_HAS_PWM, 163 .timer_capability = OMAP_TIMER_HAS_PWM,
611}; 164};
612 165
613/* timer1 */ 166/* timer1 */
614static struct omap_hwmod omap3xxx_timer1_hwmod;
615
616static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
617 {
618 .pa_start = 0x48318000,
619 .pa_end = 0x48318000 + SZ_1K - 1,
620 .flags = ADDR_TYPE_RT
621 },
622 { }
623};
624
625/* l4_wkup -> timer1 */
626static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
627 .master = &omap3xxx_l4_wkup_hwmod,
628 .slave = &omap3xxx_timer1_hwmod,
629 .clk = "gpt1_ick",
630 .addr = omap3xxx_timer1_addrs,
631 .user = OCP_USER_MPU | OCP_USER_SDMA,
632};
633
634/* timer1 slave port */
635static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
636 &omap3xxx_l4_wkup__timer1,
637};
638
639/* timer1 hwmod */
640static struct omap_hwmod omap3xxx_timer1_hwmod = { 167static struct omap_hwmod omap3xxx_timer1_hwmod = {
641 .name = "timer1", 168 .name = "timer1",
642 .mpu_irqs = omap2_timer1_mpu_irqs, 169 .mpu_irqs = omap2_timer1_mpu_irqs,
@@ -651,38 +178,10 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
651 }, 178 },
652 }, 179 },
653 .dev_attr = &capability_alwon_dev_attr, 180 .dev_attr = &capability_alwon_dev_attr,
654 .slaves = omap3xxx_timer1_slaves,
655 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
656 .class = &omap3xxx_timer_1ms_hwmod_class, 181 .class = &omap3xxx_timer_1ms_hwmod_class,
657}; 182};
658 183
659/* timer2 */ 184/* timer2 */
660static struct omap_hwmod omap3xxx_timer2_hwmod;
661
662static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
663 {
664 .pa_start = 0x49032000,
665 .pa_end = 0x49032000 + SZ_1K - 1,
666 .flags = ADDR_TYPE_RT
667 },
668 { }
669};
670
671/* l4_per -> timer2 */
672static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
673 .master = &omap3xxx_l4_per_hwmod,
674 .slave = &omap3xxx_timer2_hwmod,
675 .clk = "gpt2_ick",
676 .addr = omap3xxx_timer2_addrs,
677 .user = OCP_USER_MPU | OCP_USER_SDMA,
678};
679
680/* timer2 slave port */
681static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
682 &omap3xxx_l4_per__timer2,
683};
684
685/* timer2 hwmod */
686static struct omap_hwmod omap3xxx_timer2_hwmod = { 185static struct omap_hwmod omap3xxx_timer2_hwmod = {
687 .name = "timer2", 186 .name = "timer2",
688 .mpu_irqs = omap2_timer2_mpu_irqs, 187 .mpu_irqs = omap2_timer2_mpu_irqs,
@@ -697,38 +196,10 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
697 }, 196 },
698 }, 197 },
699 .dev_attr = &capability_alwon_dev_attr, 198 .dev_attr = &capability_alwon_dev_attr,
700 .slaves = omap3xxx_timer2_slaves,
701 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
702 .class = &omap3xxx_timer_1ms_hwmod_class, 199 .class = &omap3xxx_timer_1ms_hwmod_class,
703}; 200};
704 201
705/* timer3 */ 202/* timer3 */
706static struct omap_hwmod omap3xxx_timer3_hwmod;
707
708static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
709 {
710 .pa_start = 0x49034000,
711 .pa_end = 0x49034000 + SZ_1K - 1,
712 .flags = ADDR_TYPE_RT
713 },
714 { }
715};
716
717/* l4_per -> timer3 */
718static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
719 .master = &omap3xxx_l4_per_hwmod,
720 .slave = &omap3xxx_timer3_hwmod,
721 .clk = "gpt3_ick",
722 .addr = omap3xxx_timer3_addrs,
723 .user = OCP_USER_MPU | OCP_USER_SDMA,
724};
725
726/* timer3 slave port */
727static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
728 &omap3xxx_l4_per__timer3,
729};
730
731/* timer3 hwmod */
732static struct omap_hwmod omap3xxx_timer3_hwmod = { 203static struct omap_hwmod omap3xxx_timer3_hwmod = {
733 .name = "timer3", 204 .name = "timer3",
734 .mpu_irqs = omap2_timer3_mpu_irqs, 205 .mpu_irqs = omap2_timer3_mpu_irqs,
@@ -743,38 +214,10 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
743 }, 214 },
744 }, 215 },
745 .dev_attr = &capability_alwon_dev_attr, 216 .dev_attr = &capability_alwon_dev_attr,
746 .slaves = omap3xxx_timer3_slaves,
747 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
748 .class = &omap3xxx_timer_hwmod_class, 217 .class = &omap3xxx_timer_hwmod_class,
749}; 218};
750 219
751/* timer4 */ 220/* timer4 */
752static struct omap_hwmod omap3xxx_timer4_hwmod;
753
754static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
755 {
756 .pa_start = 0x49036000,
757 .pa_end = 0x49036000 + SZ_1K - 1,
758 .flags = ADDR_TYPE_RT
759 },
760 { }
761};
762
763/* l4_per -> timer4 */
764static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
765 .master = &omap3xxx_l4_per_hwmod,
766 .slave = &omap3xxx_timer4_hwmod,
767 .clk = "gpt4_ick",
768 .addr = omap3xxx_timer4_addrs,
769 .user = OCP_USER_MPU | OCP_USER_SDMA,
770};
771
772/* timer4 slave port */
773static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
774 &omap3xxx_l4_per__timer4,
775};
776
777/* timer4 hwmod */
778static struct omap_hwmod omap3xxx_timer4_hwmod = { 221static struct omap_hwmod omap3xxx_timer4_hwmod = {
779 .name = "timer4", 222 .name = "timer4",
780 .mpu_irqs = omap2_timer4_mpu_irqs, 223 .mpu_irqs = omap2_timer4_mpu_irqs,
@@ -789,38 +232,10 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
789 }, 232 },
790 }, 233 },
791 .dev_attr = &capability_alwon_dev_attr, 234 .dev_attr = &capability_alwon_dev_attr,
792 .slaves = omap3xxx_timer4_slaves,
793 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
794 .class = &omap3xxx_timer_hwmod_class, 235 .class = &omap3xxx_timer_hwmod_class,
795}; 236};
796 237
797/* timer5 */ 238/* timer5 */
798static struct omap_hwmod omap3xxx_timer5_hwmod;
799
800static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
801 {
802 .pa_start = 0x49038000,
803 .pa_end = 0x49038000 + SZ_1K - 1,
804 .flags = ADDR_TYPE_RT
805 },
806 { }
807};
808
809/* l4_per -> timer5 */
810static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
811 .master = &omap3xxx_l4_per_hwmod,
812 .slave = &omap3xxx_timer5_hwmod,
813 .clk = "gpt5_ick",
814 .addr = omap3xxx_timer5_addrs,
815 .user = OCP_USER_MPU | OCP_USER_SDMA,
816};
817
818/* timer5 slave port */
819static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
820 &omap3xxx_l4_per__timer5,
821};
822
823/* timer5 hwmod */
824static struct omap_hwmod omap3xxx_timer5_hwmod = { 239static struct omap_hwmod omap3xxx_timer5_hwmod = {
825 .name = "timer5", 240 .name = "timer5",
826 .mpu_irqs = omap2_timer5_mpu_irqs, 241 .mpu_irqs = omap2_timer5_mpu_irqs,
@@ -835,38 +250,10 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
835 }, 250 },
836 }, 251 },
837 .dev_attr = &capability_alwon_dev_attr, 252 .dev_attr = &capability_alwon_dev_attr,
838 .slaves = omap3xxx_timer5_slaves,
839 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
840 .class = &omap3xxx_timer_hwmod_class, 253 .class = &omap3xxx_timer_hwmod_class,
841}; 254};
842 255
843/* timer6 */ 256/* timer6 */
844static struct omap_hwmod omap3xxx_timer6_hwmod;
845
846static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
847 {
848 .pa_start = 0x4903A000,
849 .pa_end = 0x4903A000 + SZ_1K - 1,
850 .flags = ADDR_TYPE_RT
851 },
852 { }
853};
854
855/* l4_per -> timer6 */
856static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
857 .master = &omap3xxx_l4_per_hwmod,
858 .slave = &omap3xxx_timer6_hwmod,
859 .clk = "gpt6_ick",
860 .addr = omap3xxx_timer6_addrs,
861 .user = OCP_USER_MPU | OCP_USER_SDMA,
862};
863
864/* timer6 slave port */
865static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
866 &omap3xxx_l4_per__timer6,
867};
868
869/* timer6 hwmod */
870static struct omap_hwmod omap3xxx_timer6_hwmod = { 257static struct omap_hwmod omap3xxx_timer6_hwmod = {
871 .name = "timer6", 258 .name = "timer6",
872 .mpu_irqs = omap2_timer6_mpu_irqs, 259 .mpu_irqs = omap2_timer6_mpu_irqs,
@@ -881,38 +268,10 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
881 }, 268 },
882 }, 269 },
883 .dev_attr = &capability_alwon_dev_attr, 270 .dev_attr = &capability_alwon_dev_attr,
884 .slaves = omap3xxx_timer6_slaves,
885 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
886 .class = &omap3xxx_timer_hwmod_class, 271 .class = &omap3xxx_timer_hwmod_class,
887}; 272};
888 273
889/* timer7 */ 274/* timer7 */
890static struct omap_hwmod omap3xxx_timer7_hwmod;
891
892static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
893 {
894 .pa_start = 0x4903C000,
895 .pa_end = 0x4903C000 + SZ_1K - 1,
896 .flags = ADDR_TYPE_RT
897 },
898 { }
899};
900
901/* l4_per -> timer7 */
902static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
903 .master = &omap3xxx_l4_per_hwmod,
904 .slave = &omap3xxx_timer7_hwmod,
905 .clk = "gpt7_ick",
906 .addr = omap3xxx_timer7_addrs,
907 .user = OCP_USER_MPU | OCP_USER_SDMA,
908};
909
910/* timer7 slave port */
911static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
912 &omap3xxx_l4_per__timer7,
913};
914
915/* timer7 hwmod */
916static struct omap_hwmod omap3xxx_timer7_hwmod = { 275static struct omap_hwmod omap3xxx_timer7_hwmod = {
917 .name = "timer7", 276 .name = "timer7",
918 .mpu_irqs = omap2_timer7_mpu_irqs, 277 .mpu_irqs = omap2_timer7_mpu_irqs,
@@ -927,38 +286,10 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
927 }, 286 },
928 }, 287 },
929 .dev_attr = &capability_alwon_dev_attr, 288 .dev_attr = &capability_alwon_dev_attr,
930 .slaves = omap3xxx_timer7_slaves,
931 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
932 .class = &omap3xxx_timer_hwmod_class, 289 .class = &omap3xxx_timer_hwmod_class,
933}; 290};
934 291
935/* timer8 */ 292/* timer8 */
936static struct omap_hwmod omap3xxx_timer8_hwmod;
937
938static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
939 {
940 .pa_start = 0x4903E000,
941 .pa_end = 0x4903E000 + SZ_1K - 1,
942 .flags = ADDR_TYPE_RT
943 },
944 { }
945};
946
947/* l4_per -> timer8 */
948static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
949 .master = &omap3xxx_l4_per_hwmod,
950 .slave = &omap3xxx_timer8_hwmod,
951 .clk = "gpt8_ick",
952 .addr = omap3xxx_timer8_addrs,
953 .user = OCP_USER_MPU | OCP_USER_SDMA,
954};
955
956/* timer8 slave port */
957static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
958 &omap3xxx_l4_per__timer8,
959};
960
961/* timer8 hwmod */
962static struct omap_hwmod omap3xxx_timer8_hwmod = { 293static struct omap_hwmod omap3xxx_timer8_hwmod = {
963 .name = "timer8", 294 .name = "timer8",
964 .mpu_irqs = omap2_timer8_mpu_irqs, 295 .mpu_irqs = omap2_timer8_mpu_irqs,
@@ -973,38 +304,10 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
973 }, 304 },
974 }, 305 },
975 .dev_attr = &capability_pwm_dev_attr, 306 .dev_attr = &capability_pwm_dev_attr,
976 .slaves = omap3xxx_timer8_slaves,
977 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
978 .class = &omap3xxx_timer_hwmod_class, 307 .class = &omap3xxx_timer_hwmod_class,
979}; 308};
980 309
981/* timer9 */ 310/* timer9 */
982static struct omap_hwmod omap3xxx_timer9_hwmod;
983
984static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
985 {
986 .pa_start = 0x49040000,
987 .pa_end = 0x49040000 + SZ_1K - 1,
988 .flags = ADDR_TYPE_RT
989 },
990 { }
991};
992
993/* l4_per -> timer9 */
994static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
995 .master = &omap3xxx_l4_per_hwmod,
996 .slave = &omap3xxx_timer9_hwmod,
997 .clk = "gpt9_ick",
998 .addr = omap3xxx_timer9_addrs,
999 .user = OCP_USER_MPU | OCP_USER_SDMA,
1000};
1001
1002/* timer9 slave port */
1003static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1004 &omap3xxx_l4_per__timer9,
1005};
1006
1007/* timer9 hwmod */
1008static struct omap_hwmod omap3xxx_timer9_hwmod = { 311static struct omap_hwmod omap3xxx_timer9_hwmod = {
1009 .name = "timer9", 312 .name = "timer9",
1010 .mpu_irqs = omap2_timer9_mpu_irqs, 313 .mpu_irqs = omap2_timer9_mpu_irqs,
@@ -1019,29 +322,10 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
1019 }, 322 },
1020 }, 323 },
1021 .dev_attr = &capability_pwm_dev_attr, 324 .dev_attr = &capability_pwm_dev_attr,
1022 .slaves = omap3xxx_timer9_slaves,
1023 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1024 .class = &omap3xxx_timer_hwmod_class, 325 .class = &omap3xxx_timer_hwmod_class,
1025}; 326};
1026 327
1027/* timer10 */ 328/* timer10 */
1028static struct omap_hwmod omap3xxx_timer10_hwmod;
1029
1030/* l4_core -> timer10 */
1031static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1032 .master = &omap3xxx_l4_core_hwmod,
1033 .slave = &omap3xxx_timer10_hwmod,
1034 .clk = "gpt10_ick",
1035 .addr = omap2_timer10_addrs,
1036 .user = OCP_USER_MPU | OCP_USER_SDMA,
1037};
1038
1039/* timer10 slave port */
1040static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1041 &omap3xxx_l4_core__timer10,
1042};
1043
1044/* timer10 hwmod */
1045static struct omap_hwmod omap3xxx_timer10_hwmod = { 329static struct omap_hwmod omap3xxx_timer10_hwmod = {
1046 .name = "timer10", 330 .name = "timer10",
1047 .mpu_irqs = omap2_timer10_mpu_irqs, 331 .mpu_irqs = omap2_timer10_mpu_irqs,
@@ -1056,29 +340,10 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
1056 }, 340 },
1057 }, 341 },
1058 .dev_attr = &capability_pwm_dev_attr, 342 .dev_attr = &capability_pwm_dev_attr,
1059 .slaves = omap3xxx_timer10_slaves,
1060 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1061 .class = &omap3xxx_timer_1ms_hwmod_class, 343 .class = &omap3xxx_timer_1ms_hwmod_class,
1062}; 344};
1063 345
1064/* timer11 */ 346/* timer11 */
1065static struct omap_hwmod omap3xxx_timer11_hwmod;
1066
1067/* l4_core -> timer11 */
1068static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1069 .master = &omap3xxx_l4_core_hwmod,
1070 .slave = &omap3xxx_timer11_hwmod,
1071 .clk = "gpt11_ick",
1072 .addr = omap2_timer11_addrs,
1073 .user = OCP_USER_MPU | OCP_USER_SDMA,
1074};
1075
1076/* timer11 slave port */
1077static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1078 &omap3xxx_l4_core__timer11,
1079};
1080
1081/* timer11 hwmod */
1082static struct omap_hwmod omap3xxx_timer11_hwmod = { 347static struct omap_hwmod omap3xxx_timer11_hwmod = {
1083 .name = "timer11", 348 .name = "timer11",
1084 .mpu_irqs = omap2_timer11_mpu_irqs, 349 .mpu_irqs = omap2_timer11_mpu_irqs,
@@ -1093,42 +358,15 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
1093 }, 358 },
1094 }, 359 },
1095 .dev_attr = &capability_pwm_dev_attr, 360 .dev_attr = &capability_pwm_dev_attr,
1096 .slaves = omap3xxx_timer11_slaves,
1097 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1098 .class = &omap3xxx_timer_hwmod_class, 361 .class = &omap3xxx_timer_hwmod_class,
1099}; 362};
1100 363
1101/* timer12*/ 364/* timer12 */
1102static struct omap_hwmod omap3xxx_timer12_hwmod;
1103static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { 365static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1104 { .irq = 95, }, 366 { .irq = 95, },
1105 { .irq = -1 } 367 { .irq = -1 }
1106}; 368};
1107 369
1108static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1109 {
1110 .pa_start = 0x48304000,
1111 .pa_end = 0x48304000 + SZ_1K - 1,
1112 .flags = ADDR_TYPE_RT
1113 },
1114 { }
1115};
1116
1117/* l4_core -> timer12 */
1118static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1119 .master = &omap3xxx_l4_core_hwmod,
1120 .slave = &omap3xxx_timer12_hwmod,
1121 .clk = "gpt12_ick",
1122 .addr = omap3xxx_timer12_addrs,
1123 .user = OCP_USER_MPU | OCP_USER_SDMA,
1124};
1125
1126/* timer12 slave port */
1127static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1128 &omap3xxx_l4_core__timer12,
1129};
1130
1131/* timer12 hwmod */
1132static struct omap_hwmod omap3xxx_timer12_hwmod = { 370static struct omap_hwmod omap3xxx_timer12_hwmod = {
1133 .name = "timer12", 371 .name = "timer12",
1134 .mpu_irqs = omap3xxx_timer12_mpu_irqs, 372 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
@@ -1143,29 +381,9 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
1143 }, 381 },
1144 }, 382 },
1145 .dev_attr = &capability_secure_dev_attr, 383 .dev_attr = &capability_secure_dev_attr,
1146 .slaves = omap3xxx_timer12_slaves,
1147 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1148 .class = &omap3xxx_timer_hwmod_class, 384 .class = &omap3xxx_timer_hwmod_class,
1149}; 385};
1150 386
1151/* l4_wkup -> wd_timer2 */
1152static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1153 {
1154 .pa_start = 0x48314000,
1155 .pa_end = 0x4831407f,
1156 .flags = ADDR_TYPE_RT
1157 },
1158 { }
1159};
1160
1161static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1162 .master = &omap3xxx_l4_wkup_hwmod,
1163 .slave = &omap3xxx_wd_timer2_hwmod,
1164 .clk = "wdt2_ick",
1165 .addr = omap3xxx_wd_timer2_addrs,
1166 .user = OCP_USER_MPU | OCP_USER_SDMA,
1167};
1168
1169/* 387/*
1170 * 'wd_timer' class 388 * 'wd_timer' class
1171 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 389 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
@@ -1203,11 +421,6 @@ static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1203 .pre_shutdown = &omap2_wd_timer_disable 421 .pre_shutdown = &omap2_wd_timer_disable
1204}; 422};
1205 423
1206/* wd_timer2 */
1207static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1208 &omap3xxx_l4_wkup__wd_timer2,
1209};
1210
1211static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { 424static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1212 .name = "wd_timer2", 425 .name = "wd_timer2",
1213 .class = &omap3xxx_wd_timer_hwmod_class, 426 .class = &omap3xxx_wd_timer_hwmod_class,
@@ -1221,8 +434,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1221 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, 434 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1222 }, 435 },
1223 }, 436 },
1224 .slaves = omap3xxx_wd_timer2_slaves,
1225 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1226 /* 437 /*
1227 * XXX: Use software supervised mode, HW supervised smartidle seems to 438 * XXX: Use software supervised mode, HW supervised smartidle seems to
1228 * block CORE power domain idle transitions. Maybe a HW bug in wdt2? 439 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
@@ -1231,11 +442,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1231}; 442};
1232 443
1233/* UART1 */ 444/* UART1 */
1234
1235static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1236 &omap3_l4_core__uart1,
1237};
1238
1239static struct omap_hwmod omap3xxx_uart1_hwmod = { 445static struct omap_hwmod omap3xxx_uart1_hwmod = {
1240 .name = "uart1", 446 .name = "uart1",
1241 .mpu_irqs = omap2_uart1_mpu_irqs, 447 .mpu_irqs = omap2_uart1_mpu_irqs,
@@ -1250,17 +456,10 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
1250 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, 456 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1251 }, 457 },
1252 }, 458 },
1253 .slaves = omap3xxx_uart1_slaves,
1254 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1255 .class = &omap2_uart_class, 459 .class = &omap2_uart_class,
1256}; 460};
1257 461
1258/* UART2 */ 462/* UART2 */
1259
1260static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1261 &omap3_l4_core__uart2,
1262};
1263
1264static struct omap_hwmod omap3xxx_uart2_hwmod = { 463static struct omap_hwmod omap3xxx_uart2_hwmod = {
1265 .name = "uart2", 464 .name = "uart2",
1266 .mpu_irqs = omap2_uart2_mpu_irqs, 465 .mpu_irqs = omap2_uart2_mpu_irqs,
@@ -1275,17 +474,10 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
1275 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, 474 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1276 }, 475 },
1277 }, 476 },
1278 .slaves = omap3xxx_uart2_slaves,
1279 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1280 .class = &omap2_uart_class, 477 .class = &omap2_uart_class,
1281}; 478};
1282 479
1283/* UART3 */ 480/* UART3 */
1284
1285static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1286 &omap3_l4_per__uart3,
1287};
1288
1289static struct omap_hwmod omap3xxx_uart3_hwmod = { 481static struct omap_hwmod omap3xxx_uart3_hwmod = {
1290 .name = "uart3", 482 .name = "uart3",
1291 .mpu_irqs = omap2_uart3_mpu_irqs, 483 .mpu_irqs = omap2_uart3_mpu_irqs,
@@ -1300,13 +492,10 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
1300 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, 492 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1301 }, 493 },
1302 }, 494 },
1303 .slaves = omap3xxx_uart3_slaves,
1304 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1305 .class = &omap2_uart_class, 495 .class = &omap2_uart_class,
1306}; 496};
1307 497
1308/* UART4 */ 498/* UART4 */
1309
1310static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { 499static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1311 { .irq = INT_36XX_UART4_IRQ, }, 500 { .irq = INT_36XX_UART4_IRQ, },
1312 { .irq = -1 } 501 { .irq = -1 }
@@ -1318,11 +507,7 @@ static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1318 { .dma_req = -1 } 507 { .dma_req = -1 }
1319}; 508};
1320 509
1321static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { 510static struct omap_hwmod omap36xx_uart4_hwmod = {
1322 &omap3_l4_per__uart4,
1323};
1324
1325static struct omap_hwmod omap3xxx_uart4_hwmod = {
1326 .name = "uart4", 511 .name = "uart4",
1327 .mpu_irqs = uart4_mpu_irqs, 512 .mpu_irqs = uart4_mpu_irqs,
1328 .sdma_reqs = uart4_sdma_reqs, 513 .sdma_reqs = uart4_sdma_reqs,
@@ -1336,8 +521,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
1336 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, 521 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1337 }, 522 },
1338 }, 523 },
1339 .slaves = omap3xxx_uart4_slaves,
1340 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1341 .class = &omap2_uart_class, 524 .class = &omap2_uart_class,
1342}; 525};
1343 526
@@ -1350,16 +533,12 @@ static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
1350 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, 533 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
1351}; 534};
1352 535
1353static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
1354 &am35xx_l4_core__uart4,
1355};
1356
1357static struct omap_hwmod am35xx_uart4_hwmod = { 536static struct omap_hwmod am35xx_uart4_hwmod = {
1358 .name = "uart4", 537 .name = "uart4",
1359 .mpu_irqs = am35xx_uart4_mpu_irqs, 538 .mpu_irqs = am35xx_uart4_mpu_irqs,
1360 .sdma_reqs = am35xx_uart4_sdma_reqs, 539 .sdma_reqs = am35xx_uart4_sdma_reqs,
1361 .main_clk = "uart4_fck", 540 .main_clk = "uart4_fck",
1362 .prcm = { 541 .prcm = {
1363 .omap2 = { 542 .omap2 = {
1364 .module_offs = CORE_MOD, 543 .module_offs = CORE_MOD,
1365 .prcm_reg_id = 1, 544 .prcm_reg_id = 1,
@@ -1368,12 +547,9 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
1368 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, 547 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
1369 }, 548 },
1370 }, 549 },
1371 .slaves = am35xx_uart4_slaves, 550 .class = &omap2_uart_class,
1372 .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves),
1373 .class = &omap2_uart_class,
1374}; 551};
1375 552
1376
1377static struct omap_hwmod_class i2c_class = { 553static struct omap_hwmod_class i2c_class = {
1378 .name = "i2c", 554 .name = "i2c",
1379 .sysc = &i2c_sysc, 555 .sysc = &i2c_sysc,
@@ -1388,51 +564,6 @@ static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1388}; 564};
1389 565
1390/* dss */ 566/* dss */
1391/* dss master ports */
1392static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1393 &omap3xxx_dss__l3,
1394};
1395
1396/* l4_core -> dss */
1397static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1398 .master = &omap3xxx_l4_core_hwmod,
1399 .slave = &omap3430es1_dss_core_hwmod,
1400 .clk = "dss_ick",
1401 .addr = omap2_dss_addrs,
1402 .fw = {
1403 .omap2 = {
1404 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1405 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1406 .flags = OMAP_FIREWALL_L4,
1407 }
1408 },
1409 .user = OCP_USER_MPU | OCP_USER_SDMA,
1410};
1411
1412static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1413 .master = &omap3xxx_l4_core_hwmod,
1414 .slave = &omap3xxx_dss_core_hwmod,
1415 .clk = "dss_ick",
1416 .addr = omap2_dss_addrs,
1417 .fw = {
1418 .omap2 = {
1419 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1420 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1421 .flags = OMAP_FIREWALL_L4,
1422 }
1423 },
1424 .user = OCP_USER_MPU | OCP_USER_SDMA,
1425};
1426
1427/* dss slave ports */
1428static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1429 &omap3430es1_l4_core__dss,
1430};
1431
1432static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1433 &omap3xxx_l4_core__dss,
1434};
1435
1436static struct omap_hwmod_opt_clk dss_opt_clks[] = { 567static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1437 /* 568 /*
1438 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 569 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
@@ -1460,10 +591,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1460 }, 591 },
1461 .opt_clks = dss_opt_clks, 592 .opt_clks = dss_opt_clks,
1462 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 593 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1463 .slaves = omap3430es1_dss_slaves,
1464 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1465 .masters = omap3xxx_dss_masters,
1466 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1467 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 594 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1468}; 595};
1469 596
@@ -1485,10 +612,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1485 }, 612 },
1486 .opt_clks = dss_opt_clks, 613 .opt_clks = dss_opt_clks,
1487 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 614 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1488 .slaves = omap3xxx_dss_slaves,
1489 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1490 .masters = omap3xxx_dss_masters,
1491 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1492}; 615};
1493 616
1494/* 617/*
@@ -1513,27 +636,6 @@ static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1513 .sysc = &omap3_dispc_sysc, 636 .sysc = &omap3_dispc_sysc,
1514}; 637};
1515 638
1516/* l4_core -> dss_dispc */
1517static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1518 .master = &omap3xxx_l4_core_hwmod,
1519 .slave = &omap3xxx_dss_dispc_hwmod,
1520 .clk = "dss_ick",
1521 .addr = omap2_dss_dispc_addrs,
1522 .fw = {
1523 .omap2 = {
1524 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1525 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1526 .flags = OMAP_FIREWALL_L4,
1527 }
1528 },
1529 .user = OCP_USER_MPU | OCP_USER_SDMA,
1530};
1531
1532/* dss_dispc slave ports */
1533static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1534 &omap3xxx_l4_core__dss_dispc,
1535};
1536
1537static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 639static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1538 .name = "dss_dispc", 640 .name = "dss_dispc",
1539 .class = &omap3_dispc_hwmod_class, 641 .class = &omap3_dispc_hwmod_class,
@@ -1546,8 +648,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1546 .module_offs = OMAP3430_DSS_MOD, 648 .module_offs = OMAP3430_DSS_MOD,
1547 }, 649 },
1548 }, 650 },
1549 .slaves = omap3xxx_dss_dispc_slaves,
1550 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1551 .flags = HWMOD_NO_IDLEST, 651 .flags = HWMOD_NO_IDLEST,
1552 .dev_attr = &omap2_3_dss_dispc_dev_attr 652 .dev_attr = &omap2_3_dss_dispc_dev_attr
1553}; 653};
@@ -1567,36 +667,6 @@ static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1567}; 667};
1568 668
1569/* dss_dsi1 */ 669/* dss_dsi1 */
1570static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1571 {
1572 .pa_start = 0x4804FC00,
1573 .pa_end = 0x4804FFFF,
1574 .flags = ADDR_TYPE_RT
1575 },
1576 { }
1577};
1578
1579/* l4_core -> dss_dsi1 */
1580static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1581 .master = &omap3xxx_l4_core_hwmod,
1582 .slave = &omap3xxx_dss_dsi1_hwmod,
1583 .clk = "dss_ick",
1584 .addr = omap3xxx_dss_dsi1_addrs,
1585 .fw = {
1586 .omap2 = {
1587 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1588 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1589 .flags = OMAP_FIREWALL_L4,
1590 }
1591 },
1592 .user = OCP_USER_MPU | OCP_USER_SDMA,
1593};
1594
1595/* dss_dsi1 slave ports */
1596static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1597 &omap3xxx_l4_core__dss_dsi1,
1598};
1599
1600static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 670static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1601 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 671 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1602}; 672};
@@ -1615,32 +685,9 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1615 }, 685 },
1616 .opt_clks = dss_dsi1_opt_clks, 686 .opt_clks = dss_dsi1_opt_clks,
1617 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 687 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1618 .slaves = omap3xxx_dss_dsi1_slaves,
1619 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1620 .flags = HWMOD_NO_IDLEST, 688 .flags = HWMOD_NO_IDLEST,
1621}; 689};
1622 690
1623/* l4_core -> dss_rfbi */
1624static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1625 .master = &omap3xxx_l4_core_hwmod,
1626 .slave = &omap3xxx_dss_rfbi_hwmod,
1627 .clk = "dss_ick",
1628 .addr = omap2_dss_rfbi_addrs,
1629 .fw = {
1630 .omap2 = {
1631 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1632 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1633 .flags = OMAP_FIREWALL_L4,
1634 }
1635 },
1636 .user = OCP_USER_MPU | OCP_USER_SDMA,
1637};
1638
1639/* dss_rfbi slave ports */
1640static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1641 &omap3xxx_l4_core__dss_rfbi,
1642};
1643
1644static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 691static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1645 { .role = "ick", .clk = "dss_ick" }, 692 { .role = "ick", .clk = "dss_ick" },
1646}; 693};
@@ -1658,32 +705,9 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1658 }, 705 },
1659 .opt_clks = dss_rfbi_opt_clks, 706 .opt_clks = dss_rfbi_opt_clks,
1660 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 707 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1661 .slaves = omap3xxx_dss_rfbi_slaves,
1662 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1663 .flags = HWMOD_NO_IDLEST, 708 .flags = HWMOD_NO_IDLEST,
1664}; 709};
1665 710
1666/* l4_core -> dss_venc */
1667static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1668 .master = &omap3xxx_l4_core_hwmod,
1669 .slave = &omap3xxx_dss_venc_hwmod,
1670 .clk = "dss_ick",
1671 .addr = omap2_dss_venc_addrs,
1672 .fw = {
1673 .omap2 = {
1674 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1675 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1676 .flags = OMAP_FIREWALL_L4,
1677 }
1678 },
1679 .user = OCP_USER_MPU | OCP_USER_SDMA,
1680};
1681
1682/* dss_venc slave ports */
1683static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1684 &omap3xxx_l4_core__dss_venc,
1685};
1686
1687static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { 711static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1688 /* required only on OMAP3430 */ 712 /* required only on OMAP3430 */
1689 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 713 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
@@ -1702,13 +726,10 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1702 }, 726 },
1703 .opt_clks = dss_venc_opt_clks, 727 .opt_clks = dss_venc_opt_clks,
1704 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), 728 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
1705 .slaves = omap3xxx_dss_venc_slaves,
1706 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1707 .flags = HWMOD_NO_IDLEST, 729 .flags = HWMOD_NO_IDLEST,
1708}; 730};
1709 731
1710/* I2C1 */ 732/* I2C1 */
1711
1712static struct omap_i2c_dev_attr i2c1_dev_attr = { 733static struct omap_i2c_dev_attr i2c1_dev_attr = {
1713 .fifo_depth = 8, /* bytes */ 734 .fifo_depth = 8, /* bytes */
1714 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 735 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1716,10 +737,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
1716 OMAP_I2C_FLAG_BUS_SHIFT_2, 737 OMAP_I2C_FLAG_BUS_SHIFT_2,
1717}; 738};
1718 739
1719static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1720 &omap3_l4_core__i2c1,
1721};
1722
1723static struct omap_hwmod omap3xxx_i2c1_hwmod = { 740static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1724 .name = "i2c1", 741 .name = "i2c1",
1725 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 742 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1735,14 +752,11 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1735 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, 752 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1736 }, 753 },
1737 }, 754 },
1738 .slaves = omap3xxx_i2c1_slaves,
1739 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1740 .class = &i2c_class, 755 .class = &i2c_class,
1741 .dev_attr = &i2c1_dev_attr, 756 .dev_attr = &i2c1_dev_attr,
1742}; 757};
1743 758
1744/* I2C2 */ 759/* I2C2 */
1745
1746static struct omap_i2c_dev_attr i2c2_dev_attr = { 760static struct omap_i2c_dev_attr i2c2_dev_attr = {
1747 .fifo_depth = 8, /* bytes */ 761 .fifo_depth = 8, /* bytes */
1748 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 762 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1750,10 +764,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
1750 OMAP_I2C_FLAG_BUS_SHIFT_2, 764 OMAP_I2C_FLAG_BUS_SHIFT_2,
1751}; 765};
1752 766
1753static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1754 &omap3_l4_core__i2c2,
1755};
1756
1757static struct omap_hwmod omap3xxx_i2c2_hwmod = { 767static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1758 .name = "i2c2", 768 .name = "i2c2",
1759 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 769 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1769,14 +779,11 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1769 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, 779 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1770 }, 780 },
1771 }, 781 },
1772 .slaves = omap3xxx_i2c2_slaves,
1773 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1774 .class = &i2c_class, 782 .class = &i2c_class,
1775 .dev_attr = &i2c2_dev_attr, 783 .dev_attr = &i2c2_dev_attr,
1776}; 784};
1777 785
1778/* I2C3 */ 786/* I2C3 */
1779
1780static struct omap_i2c_dev_attr i2c3_dev_attr = { 787static struct omap_i2c_dev_attr i2c3_dev_attr = {
1781 .fifo_depth = 64, /* bytes */ 788 .fifo_depth = 64, /* bytes */
1782 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 789 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1795,10 +802,6 @@ static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1795 { .dma_req = -1 } 802 { .dma_req = -1 }
1796}; 803};
1797 804
1798static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1799 &omap3_l4_core__i2c3,
1800};
1801
1802static struct omap_hwmod omap3xxx_i2c3_hwmod = { 805static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1803 .name = "i2c3", 806 .name = "i2c3",
1804 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 807 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1814,114 +817,10 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1814 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, 817 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1815 }, 818 },
1816 }, 819 },
1817 .slaves = omap3xxx_i2c3_slaves,
1818 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1819 .class = &i2c_class, 820 .class = &i2c_class,
1820 .dev_attr = &i2c3_dev_attr, 821 .dev_attr = &i2c3_dev_attr,
1821}; 822};
1822 823
1823/* l4_wkup -> gpio1 */
1824static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1825 {
1826 .pa_start = 0x48310000,
1827 .pa_end = 0x483101ff,
1828 .flags = ADDR_TYPE_RT
1829 },
1830 { }
1831};
1832
1833static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1834 .master = &omap3xxx_l4_wkup_hwmod,
1835 .slave = &omap3xxx_gpio1_hwmod,
1836 .addr = omap3xxx_gpio1_addrs,
1837 .user = OCP_USER_MPU | OCP_USER_SDMA,
1838};
1839
1840/* l4_per -> gpio2 */
1841static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1842 {
1843 .pa_start = 0x49050000,
1844 .pa_end = 0x490501ff,
1845 .flags = ADDR_TYPE_RT
1846 },
1847 { }
1848};
1849
1850static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1851 .master = &omap3xxx_l4_per_hwmod,
1852 .slave = &omap3xxx_gpio2_hwmod,
1853 .addr = omap3xxx_gpio2_addrs,
1854 .user = OCP_USER_MPU | OCP_USER_SDMA,
1855};
1856
1857/* l4_per -> gpio3 */
1858static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1859 {
1860 .pa_start = 0x49052000,
1861 .pa_end = 0x490521ff,
1862 .flags = ADDR_TYPE_RT
1863 },
1864 { }
1865};
1866
1867static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1868 .master = &omap3xxx_l4_per_hwmod,
1869 .slave = &omap3xxx_gpio3_hwmod,
1870 .addr = omap3xxx_gpio3_addrs,
1871 .user = OCP_USER_MPU | OCP_USER_SDMA,
1872};
1873
1874/* l4_per -> gpio4 */
1875static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1876 {
1877 .pa_start = 0x49054000,
1878 .pa_end = 0x490541ff,
1879 .flags = ADDR_TYPE_RT
1880 },
1881 { }
1882};
1883
1884static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1885 .master = &omap3xxx_l4_per_hwmod,
1886 .slave = &omap3xxx_gpio4_hwmod,
1887 .addr = omap3xxx_gpio4_addrs,
1888 .user = OCP_USER_MPU | OCP_USER_SDMA,
1889};
1890
1891/* l4_per -> gpio5 */
1892static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1893 {
1894 .pa_start = 0x49056000,
1895 .pa_end = 0x490561ff,
1896 .flags = ADDR_TYPE_RT
1897 },
1898 { }
1899};
1900
1901static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1902 .master = &omap3xxx_l4_per_hwmod,
1903 .slave = &omap3xxx_gpio5_hwmod,
1904 .addr = omap3xxx_gpio5_addrs,
1905 .user = OCP_USER_MPU | OCP_USER_SDMA,
1906};
1907
1908/* l4_per -> gpio6 */
1909static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1910 {
1911 .pa_start = 0x49058000,
1912 .pa_end = 0x490581ff,
1913 .flags = ADDR_TYPE_RT
1914 },
1915 { }
1916};
1917
1918static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1919 .master = &omap3xxx_l4_per_hwmod,
1920 .slave = &omap3xxx_gpio6_hwmod,
1921 .addr = omap3xxx_gpio6_addrs,
1922 .user = OCP_USER_MPU | OCP_USER_SDMA,
1923};
1924
1925/* 824/*
1926 * 'gpio' class 825 * 'gpio' class
1927 * general purpose io module 826 * general purpose io module
@@ -1944,7 +843,7 @@ static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1944 .rev = 1, 843 .rev = 1,
1945}; 844};
1946 845
1947/* gpio_dev_attr*/ 846/* gpio_dev_attr */
1948static struct omap_gpio_dev_attr gpio_dev_attr = { 847static struct omap_gpio_dev_attr gpio_dev_attr = {
1949 .bank_width = 32, 848 .bank_width = 32,
1950 .dbck_flag = true, 849 .dbck_flag = true,
@@ -1955,10 +854,6 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1955 { .role = "dbclk", .clk = "gpio1_dbck", }, 854 { .role = "dbclk", .clk = "gpio1_dbck", },
1956}; 855};
1957 856
1958static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1959 &omap3xxx_l4_wkup__gpio1,
1960};
1961
1962static struct omap_hwmod omap3xxx_gpio1_hwmod = { 857static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1963 .name = "gpio1", 858 .name = "gpio1",
1964 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 859 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1975,8 +870,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1975 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, 870 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1976 }, 871 },
1977 }, 872 },
1978 .slaves = omap3xxx_gpio1_slaves,
1979 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1980 .class = &omap3xxx_gpio_hwmod_class, 873 .class = &omap3xxx_gpio_hwmod_class,
1981 .dev_attr = &gpio_dev_attr, 874 .dev_attr = &gpio_dev_attr,
1982}; 875};
@@ -1986,10 +879,6 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1986 { .role = "dbclk", .clk = "gpio2_dbck", }, 879 { .role = "dbclk", .clk = "gpio2_dbck", },
1987}; 880};
1988 881
1989static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1990 &omap3xxx_l4_per__gpio2,
1991};
1992
1993static struct omap_hwmod omap3xxx_gpio2_hwmod = { 882static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1994 .name = "gpio2", 883 .name = "gpio2",
1995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 884 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2006,8 +895,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2006 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, 895 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2007 }, 896 },
2008 }, 897 },
2009 .slaves = omap3xxx_gpio2_slaves,
2010 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2011 .class = &omap3xxx_gpio_hwmod_class, 898 .class = &omap3xxx_gpio_hwmod_class,
2012 .dev_attr = &gpio_dev_attr, 899 .dev_attr = &gpio_dev_attr,
2013}; 900};
@@ -2017,10 +904,6 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2017 { .role = "dbclk", .clk = "gpio3_dbck", }, 904 { .role = "dbclk", .clk = "gpio3_dbck", },
2018}; 905};
2019 906
2020static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2021 &omap3xxx_l4_per__gpio3,
2022};
2023
2024static struct omap_hwmod omap3xxx_gpio3_hwmod = { 907static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2025 .name = "gpio3", 908 .name = "gpio3",
2026 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 909 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2037,8 +920,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2037 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, 920 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2038 }, 921 },
2039 }, 922 },
2040 .slaves = omap3xxx_gpio3_slaves,
2041 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2042 .class = &omap3xxx_gpio_hwmod_class, 923 .class = &omap3xxx_gpio_hwmod_class,
2043 .dev_attr = &gpio_dev_attr, 924 .dev_attr = &gpio_dev_attr,
2044}; 925};
@@ -2048,10 +929,6 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2048 { .role = "dbclk", .clk = "gpio4_dbck", }, 929 { .role = "dbclk", .clk = "gpio4_dbck", },
2049}; 930};
2050 931
2051static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2052 &omap3xxx_l4_per__gpio4,
2053};
2054
2055static struct omap_hwmod omap3xxx_gpio4_hwmod = { 932static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2056 .name = "gpio4", 933 .name = "gpio4",
2057 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 934 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2068,8 +945,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2068 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, 945 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2069 }, 946 },
2070 }, 947 },
2071 .slaves = omap3xxx_gpio4_slaves,
2072 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2073 .class = &omap3xxx_gpio_hwmod_class, 948 .class = &omap3xxx_gpio_hwmod_class,
2074 .dev_attr = &gpio_dev_attr, 949 .dev_attr = &gpio_dev_attr,
2075}; 950};
@@ -2084,10 +959,6 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2084 { .role = "dbclk", .clk = "gpio5_dbck", }, 959 { .role = "dbclk", .clk = "gpio5_dbck", },
2085}; 960};
2086 961
2087static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2088 &omap3xxx_l4_per__gpio5,
2089};
2090
2091static struct omap_hwmod omap3xxx_gpio5_hwmod = { 962static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2092 .name = "gpio5", 963 .name = "gpio5",
2093 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 964 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2104,8 +975,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2104 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, 975 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2105 }, 976 },
2106 }, 977 },
2107 .slaves = omap3xxx_gpio5_slaves,
2108 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2109 .class = &omap3xxx_gpio_hwmod_class, 978 .class = &omap3xxx_gpio_hwmod_class,
2110 .dev_attr = &gpio_dev_attr, 979 .dev_attr = &gpio_dev_attr,
2111}; 980};
@@ -2120,10 +989,6 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2120 { .role = "dbclk", .clk = "gpio6_dbck", }, 989 { .role = "dbclk", .clk = "gpio6_dbck", },
2121}; 990};
2122 991
2123static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2124 &omap3xxx_l4_per__gpio6,
2125};
2126
2127static struct omap_hwmod omap3xxx_gpio6_hwmod = { 992static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2128 .name = "gpio6", 993 .name = "gpio6",
2129 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 994 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2140,20 +1005,10 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2140 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, 1005 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2141 }, 1006 },
2142 }, 1007 },
2143 .slaves = omap3xxx_gpio6_slaves,
2144 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2145 .class = &omap3xxx_gpio_hwmod_class, 1008 .class = &omap3xxx_gpio_hwmod_class,
2146 .dev_attr = &gpio_dev_attr, 1009 .dev_attr = &gpio_dev_attr,
2147}; 1010};
2148 1011
2149/* dma_system -> L3 */
2150static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2151 .master = &omap3xxx_dma_system_hwmod,
2152 .slave = &omap3xxx_l3_main_hwmod,
2153 .clk = "core_l3_ick",
2154 .user = OCP_USER_MPU | OCP_USER_SDMA,
2155};
2156
2157/* dma attributes */ 1012/* dma attributes */
2158static struct omap_dma_dev_attr dma_dev_attr = { 1013static struct omap_dma_dev_attr dma_dev_attr = {
2159 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1014 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -2180,34 +1035,6 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2180}; 1035};
2181 1036
2182/* dma_system */ 1037/* dma_system */
2183static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2184 {
2185 .pa_start = 0x48056000,
2186 .pa_end = 0x48056fff,
2187 .flags = ADDR_TYPE_RT
2188 },
2189 { }
2190};
2191
2192/* dma_system master ports */
2193static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2194 &omap3xxx_dma_system__l3,
2195};
2196
2197/* l4_cfg -> dma_system */
2198static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2199 .master = &omap3xxx_l4_core_hwmod,
2200 .slave = &omap3xxx_dma_system_hwmod,
2201 .clk = "core_l4_ick",
2202 .addr = omap3xxx_dma_system_addrs,
2203 .user = OCP_USER_MPU | OCP_USER_SDMA,
2204};
2205
2206/* dma_system slave ports */
2207static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2208 &omap3xxx_l4_core__dma_system,
2209};
2210
2211static struct omap_hwmod omap3xxx_dma_system_hwmod = { 1038static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2212 .name = "dma", 1039 .name = "dma",
2213 .class = &omap3xxx_dma_hwmod_class, 1040 .class = &omap3xxx_dma_hwmod_class,
@@ -2222,10 +1049,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2222 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, 1049 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2223 }, 1050 },
2224 }, 1051 },
2225 .slaves = omap3xxx_dma_system_slaves,
2226 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2227 .masters = omap3xxx_dma_system_masters,
2228 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2229 .dev_attr = &dma_dev_attr, 1052 .dev_attr = &dma_dev_attr,
2230 .flags = HWMOD_NO_IDLEST, 1053 .flags = HWMOD_NO_IDLEST,
2231}; 1054};
@@ -2258,30 +1081,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2258 { .irq = -1 } 1081 { .irq = -1 }
2259}; 1082};
2260 1083
2261static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2262 {
2263 .name = "mpu",
2264 .pa_start = 0x48074000,
2265 .pa_end = 0x480740ff,
2266 .flags = ADDR_TYPE_RT
2267 },
2268 { }
2269};
2270
2271/* l4_core -> mcbsp1 */
2272static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2273 .master = &omap3xxx_l4_core_hwmod,
2274 .slave = &omap3xxx_mcbsp1_hwmod,
2275 .clk = "mcbsp1_ick",
2276 .addr = omap3xxx_mcbsp1_addrs,
2277 .user = OCP_USER_MPU | OCP_USER_SDMA,
2278};
2279
2280/* mcbsp1 slave ports */
2281static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2282 &omap3xxx_l4_core__mcbsp1,
2283};
2284
2285static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 1084static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2286 .name = "mcbsp1", 1085 .name = "mcbsp1",
2287 .class = &omap3xxx_mcbsp_hwmod_class, 1086 .class = &omap3xxx_mcbsp_hwmod_class,
@@ -2297,8 +1096,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2297 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, 1096 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2298 }, 1097 },
2299 }, 1098 },
2300 .slaves = omap3xxx_mcbsp1_slaves,
2301 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2302}; 1099};
2303 1100
2304/* mcbsp2 */ 1101/* mcbsp2 */
@@ -2309,30 +1106,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2309 { .irq = -1 } 1106 { .irq = -1 }
2310}; 1107};
2311 1108
2312static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2313 {
2314 .name = "mpu",
2315 .pa_start = 0x49022000,
2316 .pa_end = 0x490220ff,
2317 .flags = ADDR_TYPE_RT
2318 },
2319 { }
2320};
2321
2322/* l4_per -> mcbsp2 */
2323static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2324 .master = &omap3xxx_l4_per_hwmod,
2325 .slave = &omap3xxx_mcbsp2_hwmod,
2326 .clk = "mcbsp2_ick",
2327 .addr = omap3xxx_mcbsp2_addrs,
2328 .user = OCP_USER_MPU | OCP_USER_SDMA,
2329};
2330
2331/* mcbsp2 slave ports */
2332static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2333 &omap3xxx_l4_per__mcbsp2,
2334};
2335
2336static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { 1109static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2337 .sidetone = "mcbsp2_sidetone", 1110 .sidetone = "mcbsp2_sidetone",
2338}; 1111};
@@ -2352,8 +1125,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2352 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1125 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2353 }, 1126 },
2354 }, 1127 },
2355 .slaves = omap3xxx_mcbsp2_slaves,
2356 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2357 .dev_attr = &omap34xx_mcbsp2_dev_attr, 1128 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2358}; 1129};
2359 1130
@@ -2365,32 +1136,8 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2365 { .irq = -1 } 1136 { .irq = -1 }
2366}; 1137};
2367 1138
2368static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2369 {
2370 .name = "mpu",
2371 .pa_start = 0x49024000,
2372 .pa_end = 0x490240ff,
2373 .flags = ADDR_TYPE_RT
2374 },
2375 { }
2376};
2377
2378/* l4_per -> mcbsp3 */
2379static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2380 .master = &omap3xxx_l4_per_hwmod,
2381 .slave = &omap3xxx_mcbsp3_hwmod,
2382 .clk = "mcbsp3_ick",
2383 .addr = omap3xxx_mcbsp3_addrs,
2384 .user = OCP_USER_MPU | OCP_USER_SDMA,
2385};
2386
2387/* mcbsp3 slave ports */
2388static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2389 &omap3xxx_l4_per__mcbsp3,
2390};
2391
2392static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { 1139static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2393 .sidetone = "mcbsp3_sidetone", 1140 .sidetone = "mcbsp3_sidetone",
2394}; 1141};
2395 1142
2396static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { 1143static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
@@ -2408,8 +1155,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2408 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1155 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2409 }, 1156 },
2410 }, 1157 },
2411 .slaves = omap3xxx_mcbsp3_slaves,
2412 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2413 .dev_attr = &omap34xx_mcbsp3_dev_attr, 1158 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2414}; 1159};
2415 1160
@@ -2427,30 +1172,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2427 { .dma_req = -1 } 1172 { .dma_req = -1 }
2428}; 1173};
2429 1174
2430static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2431 {
2432 .name = "mpu",
2433 .pa_start = 0x49026000,
2434 .pa_end = 0x490260ff,
2435 .flags = ADDR_TYPE_RT
2436 },
2437 { }
2438};
2439
2440/* l4_per -> mcbsp4 */
2441static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2442 .master = &omap3xxx_l4_per_hwmod,
2443 .slave = &omap3xxx_mcbsp4_hwmod,
2444 .clk = "mcbsp4_ick",
2445 .addr = omap3xxx_mcbsp4_addrs,
2446 .user = OCP_USER_MPU | OCP_USER_SDMA,
2447};
2448
2449/* mcbsp4 slave ports */
2450static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2451 &omap3xxx_l4_per__mcbsp4,
2452};
2453
2454static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 1175static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2455 .name = "mcbsp4", 1176 .name = "mcbsp4",
2456 .class = &omap3xxx_mcbsp_hwmod_class, 1177 .class = &omap3xxx_mcbsp_hwmod_class,
@@ -2466,8 +1187,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2466 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, 1187 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2467 }, 1188 },
2468 }, 1189 },
2469 .slaves = omap3xxx_mcbsp4_slaves,
2470 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2471}; 1190};
2472 1191
2473/* mcbsp5 */ 1192/* mcbsp5 */
@@ -2484,30 +1203,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2484 { .dma_req = -1 } 1203 { .dma_req = -1 }
2485}; 1204};
2486 1205
2487static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2488 {
2489 .name = "mpu",
2490 .pa_start = 0x48096000,
2491 .pa_end = 0x480960ff,
2492 .flags = ADDR_TYPE_RT
2493 },
2494 { }
2495};
2496
2497/* l4_core -> mcbsp5 */
2498static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2499 .master = &omap3xxx_l4_core_hwmod,
2500 .slave = &omap3xxx_mcbsp5_hwmod,
2501 .clk = "mcbsp5_ick",
2502 .addr = omap3xxx_mcbsp5_addrs,
2503 .user = OCP_USER_MPU | OCP_USER_SDMA,
2504};
2505
2506/* mcbsp5 slave ports */
2507static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2508 &omap3xxx_l4_core__mcbsp5,
2509};
2510
2511static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 1206static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2512 .name = "mcbsp5", 1207 .name = "mcbsp5",
2513 .class = &omap3xxx_mcbsp_hwmod_class, 1208 .class = &omap3xxx_mcbsp_hwmod_class,
@@ -2523,11 +1218,9 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2523 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, 1218 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2524 }, 1219 },
2525 }, 1220 },
2526 .slaves = omap3xxx_mcbsp5_slaves,
2527 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2528}; 1221};
2529/* 'mcbsp sidetone' class */
2530 1222
1223/* 'mcbsp sidetone' class */
2531static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { 1224static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2532 .sysc_offs = 0x0010, 1225 .sysc_offs = 0x0010,
2533 .sysc_flags = SYSC_HAS_AUTOIDLE, 1226 .sysc_flags = SYSC_HAS_AUTOIDLE,
@@ -2545,30 +1238,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2545 { .irq = -1 } 1238 { .irq = -1 }
2546}; 1239};
2547 1240
2548static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2549 {
2550 .name = "sidetone",
2551 .pa_start = 0x49028000,
2552 .pa_end = 0x490280ff,
2553 .flags = ADDR_TYPE_RT
2554 },
2555 { }
2556};
2557
2558/* l4_per -> mcbsp2_sidetone */
2559static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2560 .master = &omap3xxx_l4_per_hwmod,
2561 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2562 .clk = "mcbsp2_ick",
2563 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2564 .user = OCP_USER_MPU,
2565};
2566
2567/* mcbsp2_sidetone slave ports */
2568static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2569 &omap3xxx_l4_per__mcbsp2_sidetone,
2570};
2571
2572static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 1241static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2573 .name = "mcbsp2_sidetone", 1242 .name = "mcbsp2_sidetone",
2574 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1243 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -2583,8 +1252,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2583 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1252 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2584 }, 1253 },
2585 }, 1254 },
2586 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2587 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2588}; 1255};
2589 1256
2590/* mcbsp3_sidetone */ 1257/* mcbsp3_sidetone */
@@ -2593,30 +1260,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2593 { .irq = -1 } 1260 { .irq = -1 }
2594}; 1261};
2595 1262
2596static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2597 {
2598 .name = "sidetone",
2599 .pa_start = 0x4902A000,
2600 .pa_end = 0x4902A0ff,
2601 .flags = ADDR_TYPE_RT
2602 },
2603 { }
2604};
2605
2606/* l4_per -> mcbsp3_sidetone */
2607static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2608 .master = &omap3xxx_l4_per_hwmod,
2609 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2610 .clk = "mcbsp3_ick",
2611 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2612 .user = OCP_USER_MPU,
2613};
2614
2615/* mcbsp3_sidetone slave ports */
2616static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2617 &omap3xxx_l4_per__mcbsp3_sidetone,
2618};
2619
2620static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 1263static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2621 .name = "mcbsp3_sidetone", 1264 .name = "mcbsp3_sidetone",
2622 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1265 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -2631,11 +1274,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2631 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1274 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2632 }, 1275 },
2633 }, 1276 },
2634 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2635 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2636}; 1277};
2637 1278
2638
2639/* SR common */ 1279/* SR common */
2640static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { 1280static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2641 .clkact_shift = 20, 1281 .clkact_shift = 20,
@@ -2656,7 +1296,7 @@ static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2656 1296
2657static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { 1297static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2658 .sidle_shift = 24, 1298 .sidle_shift = 24,
2659 .enwkup_shift = 26 1299 .enwkup_shift = 26,
2660}; 1300};
2661 1301
2662static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { 1302static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
@@ -2678,12 +1318,13 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2678 .sensor_voltdm_name = "mpu_iva", 1318 .sensor_voltdm_name = "mpu_iva",
2679}; 1319};
2680 1320
2681static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { 1321static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
2682 &omap3_l4_core__sr1, 1322 { .irq = 18 },
1323 { .irq = -1 }
2683}; 1324};
2684 1325
2685static struct omap_hwmod omap34xx_sr1_hwmod = { 1326static struct omap_hwmod omap34xx_sr1_hwmod = {
2686 .name = "sr1_hwmod", 1327 .name = "sr1",
2687 .class = &omap34xx_smartreflex_hwmod_class, 1328 .class = &omap34xx_smartreflex_hwmod_class,
2688 .main_clk = "sr1_fck", 1329 .main_clk = "sr1_fck",
2689 .prcm = { 1330 .prcm = {
@@ -2695,15 +1336,13 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
2695 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1336 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2696 }, 1337 },
2697 }, 1338 },
2698 .slaves = omap3_sr1_slaves,
2699 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2700 .dev_attr = &sr1_dev_attr, 1339 .dev_attr = &sr1_dev_attr,
2701 .mpu_irqs = omap3_smartreflex_mpu_irqs, 1340 .mpu_irqs = omap3_smartreflex_mpu_irqs,
2702 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1341 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2703}; 1342};
2704 1343
2705static struct omap_hwmod omap36xx_sr1_hwmod = { 1344static struct omap_hwmod omap36xx_sr1_hwmod = {
2706 .name = "sr1_hwmod", 1345 .name = "sr1",
2707 .class = &omap36xx_smartreflex_hwmod_class, 1346 .class = &omap36xx_smartreflex_hwmod_class,
2708 .main_clk = "sr1_fck", 1347 .main_clk = "sr1_fck",
2709 .prcm = { 1348 .prcm = {
@@ -2715,8 +1354,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
2715 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1354 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2716 }, 1355 },
2717 }, 1356 },
2718 .slaves = omap3_sr1_slaves,
2719 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2720 .dev_attr = &sr1_dev_attr, 1357 .dev_attr = &sr1_dev_attr,
2721 .mpu_irqs = omap3_smartreflex_mpu_irqs, 1358 .mpu_irqs = omap3_smartreflex_mpu_irqs,
2722}; 1359};
@@ -2726,12 +1363,13 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2726 .sensor_voltdm_name = "core", 1363 .sensor_voltdm_name = "core",
2727}; 1364};
2728 1365
2729static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { 1366static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
2730 &omap3_l4_core__sr2, 1367 { .irq = 19 },
1368 { .irq = -1 }
2731}; 1369};
2732 1370
2733static struct omap_hwmod omap34xx_sr2_hwmod = { 1371static struct omap_hwmod omap34xx_sr2_hwmod = {
2734 .name = "sr2_hwmod", 1372 .name = "sr2",
2735 .class = &omap34xx_smartreflex_hwmod_class, 1373 .class = &omap34xx_smartreflex_hwmod_class,
2736 .main_clk = "sr2_fck", 1374 .main_clk = "sr2_fck",
2737 .prcm = { 1375 .prcm = {
@@ -2743,15 +1381,13 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
2743 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1381 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2744 }, 1382 },
2745 }, 1383 },
2746 .slaves = omap3_sr2_slaves,
2747 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2748 .dev_attr = &sr2_dev_attr, 1384 .dev_attr = &sr2_dev_attr,
2749 .mpu_irqs = omap3_smartreflex_core_irqs, 1385 .mpu_irqs = omap3_smartreflex_core_irqs,
2750 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1386 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2751}; 1387};
2752 1388
2753static struct omap_hwmod omap36xx_sr2_hwmod = { 1389static struct omap_hwmod omap36xx_sr2_hwmod = {
2754 .name = "sr2_hwmod", 1390 .name = "sr2",
2755 .class = &omap36xx_smartreflex_hwmod_class, 1391 .class = &omap36xx_smartreflex_hwmod_class,
2756 .main_clk = "sr2_fck", 1392 .main_clk = "sr2_fck",
2757 .prcm = { 1393 .prcm = {
@@ -2763,8 +1399,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
2763 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1399 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2764 }, 1400 },
2765 }, 1401 },
2766 .slaves = omap3_sr2_slaves,
2767 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2768 .dev_attr = &sr2_dev_attr, 1402 .dev_attr = &sr2_dev_attr,
2769 .mpu_irqs = omap3_smartreflex_core_irqs, 1403 .mpu_irqs = omap3_smartreflex_core_irqs,
2770}; 1404};
@@ -2790,34 +1424,11 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2790 .sysc = &omap3xxx_mailbox_sysc, 1424 .sysc = &omap3xxx_mailbox_sysc,
2791}; 1425};
2792 1426
2793static struct omap_hwmod omap3xxx_mailbox_hwmod;
2794static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 1427static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2795 { .irq = 26 }, 1428 { .irq = 26 },
2796 { .irq = -1 } 1429 { .irq = -1 }
2797}; 1430};
2798 1431
2799static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2800 {
2801 .pa_start = 0x48094000,
2802 .pa_end = 0x480941ff,
2803 .flags = ADDR_TYPE_RT,
2804 },
2805 { }
2806};
2807
2808/* l4_core -> mailbox */
2809static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2810 .master = &omap3xxx_l4_core_hwmod,
2811 .slave = &omap3xxx_mailbox_hwmod,
2812 .addr = omap3xxx_mailbox_addrs,
2813 .user = OCP_USER_MPU | OCP_USER_SDMA,
2814};
2815
2816/* mailbox slave ports */
2817static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2818 &omap3xxx_l4_core__mailbox,
2819};
2820
2821static struct omap_hwmod omap3xxx_mailbox_hwmod = { 1432static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2822 .name = "mailbox", 1433 .name = "mailbox",
2823 .class = &omap3xxx_mailbox_hwmod_class, 1434 .class = &omap3xxx_mailbox_hwmod_class,
@@ -2832,53 +1443,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2832 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 1443 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2833 }, 1444 },
2834 }, 1445 },
2835 .slaves = omap3xxx_mailbox_slaves,
2836 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2837};
2838
2839/* l4 core -> mcspi1 interface */
2840static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2841 .master = &omap3xxx_l4_core_hwmod,
2842 .slave = &omap34xx_mcspi1,
2843 .clk = "mcspi1_ick",
2844 .addr = omap2_mcspi1_addr_space,
2845 .user = OCP_USER_MPU | OCP_USER_SDMA,
2846};
2847
2848/* l4 core -> mcspi2 interface */
2849static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2850 .master = &omap3xxx_l4_core_hwmod,
2851 .slave = &omap34xx_mcspi2,
2852 .clk = "mcspi2_ick",
2853 .addr = omap2_mcspi2_addr_space,
2854 .user = OCP_USER_MPU | OCP_USER_SDMA,
2855};
2856
2857/* l4 core -> mcspi3 interface */
2858static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2859 .master = &omap3xxx_l4_core_hwmod,
2860 .slave = &omap34xx_mcspi3,
2861 .clk = "mcspi3_ick",
2862 .addr = omap2430_mcspi3_addr_space,
2863 .user = OCP_USER_MPU | OCP_USER_SDMA,
2864};
2865
2866/* l4 core -> mcspi4 interface */
2867static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2868 {
2869 .pa_start = 0x480ba000,
2870 .pa_end = 0x480ba0ff,
2871 .flags = ADDR_TYPE_RT,
2872 },
2873 { }
2874};
2875
2876static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2877 .master = &omap3xxx_l4_core_hwmod,
2878 .slave = &omap34xx_mcspi4,
2879 .clk = "mcspi4_ick",
2880 .addr = omap34xx_mcspi4_addr_space,
2881 .user = OCP_USER_MPU | OCP_USER_SDMA,
2882}; 1446};
2883 1447
2884/* 1448/*
@@ -2905,10 +1469,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
2905}; 1469};
2906 1470
2907/* mcspi1 */ 1471/* mcspi1 */
2908static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2909 &omap34xx_l4_core__mcspi1,
2910};
2911
2912static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 1472static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2913 .num_chipselect = 4, 1473 .num_chipselect = 4,
2914}; 1474};
@@ -2927,17 +1487,11 @@ static struct omap_hwmod omap34xx_mcspi1 = {
2927 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, 1487 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2928 }, 1488 },
2929 }, 1489 },
2930 .slaves = omap34xx_mcspi1_slaves,
2931 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2932 .class = &omap34xx_mcspi_class, 1490 .class = &omap34xx_mcspi_class,
2933 .dev_attr = &omap_mcspi1_dev_attr, 1491 .dev_attr = &omap_mcspi1_dev_attr,
2934}; 1492};
2935 1493
2936/* mcspi2 */ 1494/* mcspi2 */
2937static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2938 &omap34xx_l4_core__mcspi2,
2939};
2940
2941static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 1495static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2942 .num_chipselect = 2, 1496 .num_chipselect = 2,
2943}; 1497};
@@ -2956,8 +1510,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
2956 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, 1510 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2957 }, 1511 },
2958 }, 1512 },
2959 .slaves = omap34xx_mcspi2_slaves,
2960 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2961 .class = &omap34xx_mcspi_class, 1513 .class = &omap34xx_mcspi_class,
2962 .dev_attr = &omap_mcspi2_dev_attr, 1514 .dev_attr = &omap_mcspi2_dev_attr,
2963}; 1515};
@@ -2976,10 +1528,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2976 { .dma_req = -1 } 1528 { .dma_req = -1 }
2977}; 1529};
2978 1530
2979static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2980 &omap34xx_l4_core__mcspi3,
2981};
2982
2983static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 1531static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2984 .num_chipselect = 2, 1532 .num_chipselect = 2,
2985}; 1533};
@@ -2998,13 +1546,11 @@ static struct omap_hwmod omap34xx_mcspi3 = {
2998 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, 1546 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2999 }, 1547 },
3000 }, 1548 },
3001 .slaves = omap34xx_mcspi3_slaves,
3002 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3003 .class = &omap34xx_mcspi_class, 1549 .class = &omap34xx_mcspi_class,
3004 .dev_attr = &omap_mcspi3_dev_attr, 1550 .dev_attr = &omap_mcspi3_dev_attr,
3005}; 1551};
3006 1552
3007/* SPI4 */ 1553/* mcspi4 */
3008static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { 1554static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3009 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ 1555 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3010 { .irq = -1 } 1556 { .irq = -1 }
@@ -3016,10 +1562,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3016 { .dma_req = -1 } 1562 { .dma_req = -1 }
3017}; 1563};
3018 1564
3019static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3020 &omap34xx_l4_core__mcspi4,
3021};
3022
3023static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { 1565static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3024 .num_chipselect = 1, 1566 .num_chipselect = 1,
3025}; 1567};
@@ -3038,15 +1580,11 @@ static struct omap_hwmod omap34xx_mcspi4 = {
3038 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, 1580 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3039 }, 1581 },
3040 }, 1582 },
3041 .slaves = omap34xx_mcspi4_slaves,
3042 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3043 .class = &omap34xx_mcspi_class, 1583 .class = &omap34xx_mcspi_class,
3044 .dev_attr = &omap_mcspi4_dev_attr, 1584 .dev_attr = &omap_mcspi4_dev_attr,
3045}; 1585};
3046 1586
3047/* 1587/* usbhsotg */
3048 * usbhsotg
3049 */
3050static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { 1588static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3051 .rev_offs = 0x0400, 1589 .rev_offs = 0x0400,
3052 .sysc_offs = 0x0404, 1590 .sysc_offs = 0x0404,
@@ -3063,6 +1601,7 @@ static struct omap_hwmod_class usbotg_class = {
3063 .name = "usbotg", 1601 .name = "usbotg",
3064 .sysc = &omap3xxx_usbhsotg_sysc, 1602 .sysc = &omap3xxx_usbhsotg_sysc,
3065}; 1603};
1604
3066/* usb_otg_hs */ 1605/* usb_otg_hs */
3067static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { 1606static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3068 1607
@@ -3085,10 +1624,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3085 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 1624 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3086 }, 1625 },
3087 }, 1626 },
3088 .masters = omap3xxx_usbhsotg_masters,
3089 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3090 .slaves = omap3xxx_usbhsotg_slaves,
3091 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3092 .class = &usbotg_class, 1627 .class = &usbotg_class,
3093 1628
3094 /* 1629 /*
@@ -3120,15 +1655,10 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3120 .omap2 = { 1655 .omap2 = {
3121 }, 1656 },
3122 }, 1657 },
3123 .masters = am35xx_usbhsotg_masters,
3124 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3125 .slaves = am35xx_usbhsotg_slaves,
3126 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3127 .class = &am35xx_usbotg_class, 1658 .class = &am35xx_usbotg_class,
3128}; 1659};
3129 1660
3130/* MMC/SD/SDIO common */ 1661/* MMC/SD/SDIO common */
3131
3132static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { 1662static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3133 .rev_offs = 0x1fc, 1663 .rev_offs = 0x1fc,
3134 .sysc_offs = 0x10, 1664 .sysc_offs = 0x10,
@@ -3162,10 +1692,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3162 { .role = "dbck", .clk = "omap_32k_fck", }, 1692 { .role = "dbck", .clk = "omap_32k_fck", },
3163}; 1693};
3164 1694
3165static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3166 &omap3xxx_l4_core__mmc1,
3167};
3168
3169static struct omap_mmc_dev_attr mmc1_dev_attr = { 1695static struct omap_mmc_dev_attr mmc1_dev_attr = {
3170 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1696 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3171}; 1697};
@@ -3193,8 +1719,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3193 }, 1719 },
3194 }, 1720 },
3195 .dev_attr = &mmc1_pre_es3_dev_attr, 1721 .dev_attr = &mmc1_pre_es3_dev_attr,
3196 .slaves = omap3xxx_mmc1_slaves,
3197 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3198 .class = &omap34xx_mmc_class, 1722 .class = &omap34xx_mmc_class,
3199}; 1723};
3200 1724
@@ -3215,8 +1739,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3215 }, 1739 },
3216 }, 1740 },
3217 .dev_attr = &mmc1_dev_attr, 1741 .dev_attr = &mmc1_dev_attr,
3218 .slaves = omap3xxx_mmc1_slaves,
3219 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3220 .class = &omap34xx_mmc_class, 1742 .class = &omap34xx_mmc_class,
3221}; 1743};
3222 1744
@@ -3237,10 +1759,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3237 { .role = "dbck", .clk = "omap_32k_fck", }, 1759 { .role = "dbck", .clk = "omap_32k_fck", },
3238}; 1760};
3239 1761
3240static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3241 &omap3xxx_l4_core__mmc2,
3242};
3243
3244/* See 35xx errata 2.1.1.128 in SPRZ278F */ 1762/* See 35xx errata 2.1.1.128 in SPRZ278F */
3245static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { 1763static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3246 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1764 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
@@ -3263,8 +1781,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3263 }, 1781 },
3264 }, 1782 },
3265 .dev_attr = &mmc2_pre_es3_dev_attr, 1783 .dev_attr = &mmc2_pre_es3_dev_attr,
3266 .slaves = omap3xxx_mmc2_slaves,
3267 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3268 .class = &omap34xx_mmc_class, 1784 .class = &omap34xx_mmc_class,
3269}; 1785};
3270 1786
@@ -3284,8 +1800,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3284 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1800 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3285 }, 1801 },
3286 }, 1802 },
3287 .slaves = omap3xxx_mmc2_slaves,
3288 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3289 .class = &omap34xx_mmc_class, 1803 .class = &omap34xx_mmc_class,
3290}; 1804};
3291 1805
@@ -3306,10 +1820,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3306 { .role = "dbck", .clk = "omap_32k_fck", }, 1820 { .role = "dbck", .clk = "omap_32k_fck", },
3307}; 1821};
3308 1822
3309static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3310 &omap3xxx_l4_core__mmc3,
3311};
3312
3313static struct omap_hwmod omap3xxx_mmc3_hwmod = { 1823static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3314 .name = "mmc3", 1824 .name = "mmc3",
3315 .mpu_irqs = omap34xx_mmc3_mpu_irqs, 1825 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
@@ -3325,8 +1835,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3325 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, 1835 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3326 }, 1836 },
3327 }, 1837 },
3328 .slaves = omap3xxx_mmc3_slaves,
3329 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3330 .class = &omap34xx_mmc_class, 1838 .class = &omap34xx_mmc_class,
3331}; 1839};
3332 1840
@@ -3334,12 +1842,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3334 * 'usb_host_hs' class 1842 * 'usb_host_hs' class
3335 * high-speed multi-port usb host controller 1843 * high-speed multi-port usb host controller
3336 */ 1844 */
3337static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3338 .master = &omap3xxx_usb_host_hs_hwmod,
3339 .slave = &omap3xxx_l3_main_hwmod,
3340 .clk = "core_l3_ick",
3341 .user = OCP_USER_MPU,
3342};
3343 1845
3344static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { 1846static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
3345 .rev_offs = 0x0000, 1847 .rev_offs = 0x0000,
@@ -3358,42 +1860,6 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
3358 .sysc = &omap3xxx_usb_host_hs_sysc, 1860 .sysc = &omap3xxx_usb_host_hs_sysc,
3359}; 1861};
3360 1862
3361static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
3362 &omap3xxx_usb_host_hs__l3_main_2,
3363};
3364
3365static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3366 {
3367 .name = "uhh",
3368 .pa_start = 0x48064000,
3369 .pa_end = 0x480643ff,
3370 .flags = ADDR_TYPE_RT
3371 },
3372 {
3373 .name = "ohci",
3374 .pa_start = 0x48064400,
3375 .pa_end = 0x480647ff,
3376 },
3377 {
3378 .name = "ehci",
3379 .pa_start = 0x48064800,
3380 .pa_end = 0x48064cff,
3381 },
3382 {}
3383};
3384
3385static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3386 .master = &omap3xxx_l4_core_hwmod,
3387 .slave = &omap3xxx_usb_host_hs_hwmod,
3388 .clk = "usbhost_ick",
3389 .addr = omap3xxx_usb_host_hs_addrs,
3390 .user = OCP_USER_MPU | OCP_USER_SDMA,
3391};
3392
3393static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
3394 &omap3xxx_l4_core__usb_host_hs,
3395};
3396
3397static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { 1863static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
3398 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, 1864 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
3399}; 1865};
@@ -3422,10 +1888,6 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
3422 }, 1888 },
3423 .opt_clks = omap3xxx_usb_host_hs_opt_clks, 1889 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
3424 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), 1890 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
3425 .slaves = omap3xxx_usb_host_hs_slaves,
3426 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
3427 .masters = omap3xxx_usb_host_hs_masters,
3428 .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
3429 1891
3430 /* 1892 /*
3431 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 1893 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
@@ -3501,6 +1963,1084 @@ static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
3501 { .irq = -1 } 1963 { .irq = -1 }
3502}; 1964};
3503 1965
1966static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1967 .name = "usb_tll_hs",
1968 .class = &omap3xxx_usb_tll_hs_hwmod_class,
1969 .clkdm_name = "l3_init_clkdm",
1970 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
1971 .main_clk = "usbtll_fck",
1972 .prcm = {
1973 .omap2 = {
1974 .module_offs = CORE_MOD,
1975 .prcm_reg_id = 3,
1976 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1977 .idlest_reg_id = 3,
1978 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1979 },
1980 },
1981};
1982
1983/*
1984 * interfaces
1985 */
1986
1987/* L3 -> L4_CORE interface */
1988static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1989 .master = &omap3xxx_l3_main_hwmod,
1990 .slave = &omap3xxx_l4_core_hwmod,
1991 .user = OCP_USER_MPU | OCP_USER_SDMA,
1992};
1993
1994/* L3 -> L4_PER interface */
1995static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1996 .master = &omap3xxx_l3_main_hwmod,
1997 .slave = &omap3xxx_l4_per_hwmod,
1998 .user = OCP_USER_MPU | OCP_USER_SDMA,
1999};
2000
2001static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2002 {
2003 .pa_start = 0x68000000,
2004 .pa_end = 0x6800ffff,
2005 .flags = ADDR_TYPE_RT,
2006 },
2007 { }
2008};
2009
2010/* MPU -> L3 interface */
2011static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2012 .master = &omap3xxx_mpu_hwmod,
2013 .slave = &omap3xxx_l3_main_hwmod,
2014 .addr = omap3xxx_l3_main_addrs,
2015 .user = OCP_USER_MPU,
2016};
2017
2018/* DSS -> l3 */
2019static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2020 .master = &omap3430es1_dss_core_hwmod,
2021 .slave = &omap3xxx_l3_main_hwmod,
2022 .user = OCP_USER_MPU | OCP_USER_SDMA,
2023};
2024
2025static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2026 .master = &omap3xxx_dss_core_hwmod,
2027 .slave = &omap3xxx_l3_main_hwmod,
2028 .fw = {
2029 .omap2 = {
2030 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2031 .flags = OMAP_FIREWALL_L3,
2032 }
2033 },
2034 .user = OCP_USER_MPU | OCP_USER_SDMA,
2035};
2036
2037/* l3_core -> usbhsotg interface */
2038static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2039 .master = &omap3xxx_usbhsotg_hwmod,
2040 .slave = &omap3xxx_l3_main_hwmod,
2041 .clk = "core_l3_ick",
2042 .user = OCP_USER_MPU,
2043};
2044
2045/* l3_core -> am35xx_usbhsotg interface */
2046static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2047 .master = &am35xx_usbhsotg_hwmod,
2048 .slave = &omap3xxx_l3_main_hwmod,
2049 .clk = "core_l3_ick",
2050 .user = OCP_USER_MPU,
2051};
2052/* L4_CORE -> L4_WKUP interface */
2053static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2054 .master = &omap3xxx_l4_core_hwmod,
2055 .slave = &omap3xxx_l4_wkup_hwmod,
2056 .user = OCP_USER_MPU | OCP_USER_SDMA,
2057};
2058
2059/* L4 CORE -> MMC1 interface */
2060static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2061 .master = &omap3xxx_l4_core_hwmod,
2062 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2063 .clk = "mmchs1_ick",
2064 .addr = omap2430_mmc1_addr_space,
2065 .user = OCP_USER_MPU | OCP_USER_SDMA,
2066 .flags = OMAP_FIREWALL_L4
2067};
2068
2069static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2070 .master = &omap3xxx_l4_core_hwmod,
2071 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2072 .clk = "mmchs1_ick",
2073 .addr = omap2430_mmc1_addr_space,
2074 .user = OCP_USER_MPU | OCP_USER_SDMA,
2075 .flags = OMAP_FIREWALL_L4
2076};
2077
2078/* L4 CORE -> MMC2 interface */
2079static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2080 .master = &omap3xxx_l4_core_hwmod,
2081 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2082 .clk = "mmchs2_ick",
2083 .addr = omap2430_mmc2_addr_space,
2084 .user = OCP_USER_MPU | OCP_USER_SDMA,
2085 .flags = OMAP_FIREWALL_L4
2086};
2087
2088static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2089 .master = &omap3xxx_l4_core_hwmod,
2090 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2091 .clk = "mmchs2_ick",
2092 .addr = omap2430_mmc2_addr_space,
2093 .user = OCP_USER_MPU | OCP_USER_SDMA,
2094 .flags = OMAP_FIREWALL_L4
2095};
2096
2097/* L4 CORE -> MMC3 interface */
2098static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2099 {
2100 .pa_start = 0x480ad000,
2101 .pa_end = 0x480ad1ff,
2102 .flags = ADDR_TYPE_RT,
2103 },
2104 { }
2105};
2106
2107static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2108 .master = &omap3xxx_l4_core_hwmod,
2109 .slave = &omap3xxx_mmc3_hwmod,
2110 .clk = "mmchs3_ick",
2111 .addr = omap3xxx_mmc3_addr_space,
2112 .user = OCP_USER_MPU | OCP_USER_SDMA,
2113 .flags = OMAP_FIREWALL_L4
2114};
2115
2116/* L4 CORE -> UART1 interface */
2117static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2118 {
2119 .pa_start = OMAP3_UART1_BASE,
2120 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2121 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2122 },
2123 { }
2124};
2125
2126static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2127 .master = &omap3xxx_l4_core_hwmod,
2128 .slave = &omap3xxx_uart1_hwmod,
2129 .clk = "uart1_ick",
2130 .addr = omap3xxx_uart1_addr_space,
2131 .user = OCP_USER_MPU | OCP_USER_SDMA,
2132};
2133
2134/* L4 CORE -> UART2 interface */
2135static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2136 {
2137 .pa_start = OMAP3_UART2_BASE,
2138 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2139 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2140 },
2141 { }
2142};
2143
2144static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2145 .master = &omap3xxx_l4_core_hwmod,
2146 .slave = &omap3xxx_uart2_hwmod,
2147 .clk = "uart2_ick",
2148 .addr = omap3xxx_uart2_addr_space,
2149 .user = OCP_USER_MPU | OCP_USER_SDMA,
2150};
2151
2152/* L4 PER -> UART3 interface */
2153static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2154 {
2155 .pa_start = OMAP3_UART3_BASE,
2156 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2157 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2158 },
2159 { }
2160};
2161
2162static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2163 .master = &omap3xxx_l4_per_hwmod,
2164 .slave = &omap3xxx_uart3_hwmod,
2165 .clk = "uart3_ick",
2166 .addr = omap3xxx_uart3_addr_space,
2167 .user = OCP_USER_MPU | OCP_USER_SDMA,
2168};
2169
2170/* L4 PER -> UART4 interface */
2171static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2172 {
2173 .pa_start = OMAP3_UART4_BASE,
2174 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2175 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2176 },
2177 { }
2178};
2179
2180static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2181 .master = &omap3xxx_l4_per_hwmod,
2182 .slave = &omap36xx_uart4_hwmod,
2183 .clk = "uart4_ick",
2184 .addr = omap36xx_uart4_addr_space,
2185 .user = OCP_USER_MPU | OCP_USER_SDMA,
2186};
2187
2188/* AM35xx: L4 CORE -> UART4 interface */
2189static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2190 {
2191 .pa_start = OMAP3_UART4_AM35XX_BASE,
2192 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2193 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2194 },
2195};
2196
2197static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2198 .master = &omap3xxx_l4_core_hwmod,
2199 .slave = &am35xx_uart4_hwmod,
2200 .clk = "uart4_ick",
2201 .addr = am35xx_uart4_addr_space,
2202 .user = OCP_USER_MPU | OCP_USER_SDMA,
2203};
2204
2205/* L4 CORE -> I2C1 interface */
2206static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2207 .master = &omap3xxx_l4_core_hwmod,
2208 .slave = &omap3xxx_i2c1_hwmod,
2209 .clk = "i2c1_ick",
2210 .addr = omap2_i2c1_addr_space,
2211 .fw = {
2212 .omap2 = {
2213 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2214 .l4_prot_group = 7,
2215 .flags = OMAP_FIREWALL_L4,
2216 }
2217 },
2218 .user = OCP_USER_MPU | OCP_USER_SDMA,
2219};
2220
2221/* L4 CORE -> I2C2 interface */
2222static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2223 .master = &omap3xxx_l4_core_hwmod,
2224 .slave = &omap3xxx_i2c2_hwmod,
2225 .clk = "i2c2_ick",
2226 .addr = omap2_i2c2_addr_space,
2227 .fw = {
2228 .omap2 = {
2229 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2230 .l4_prot_group = 7,
2231 .flags = OMAP_FIREWALL_L4,
2232 }
2233 },
2234 .user = OCP_USER_MPU | OCP_USER_SDMA,
2235};
2236
2237/* L4 CORE -> I2C3 interface */
2238static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2239 {
2240 .pa_start = 0x48060000,
2241 .pa_end = 0x48060000 + SZ_128 - 1,
2242 .flags = ADDR_TYPE_RT,
2243 },
2244 { }
2245};
2246
2247static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2248 .master = &omap3xxx_l4_core_hwmod,
2249 .slave = &omap3xxx_i2c3_hwmod,
2250 .clk = "i2c3_ick",
2251 .addr = omap3xxx_i2c3_addr_space,
2252 .fw = {
2253 .omap2 = {
2254 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2255 .l4_prot_group = 7,
2256 .flags = OMAP_FIREWALL_L4,
2257 }
2258 },
2259 .user = OCP_USER_MPU | OCP_USER_SDMA,
2260};
2261
2262/* L4 CORE -> SR1 interface */
2263static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2264 {
2265 .pa_start = OMAP34XX_SR1_BASE,
2266 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2267 .flags = ADDR_TYPE_RT,
2268 },
2269 { }
2270};
2271
2272static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2273 .master = &omap3xxx_l4_core_hwmod,
2274 .slave = &omap34xx_sr1_hwmod,
2275 .clk = "sr_l4_ick",
2276 .addr = omap3_sr1_addr_space,
2277 .user = OCP_USER_MPU,
2278};
2279
2280static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2281 .master = &omap3xxx_l4_core_hwmod,
2282 .slave = &omap36xx_sr1_hwmod,
2283 .clk = "sr_l4_ick",
2284 .addr = omap3_sr1_addr_space,
2285 .user = OCP_USER_MPU,
2286};
2287
2288/* L4 CORE -> SR1 interface */
2289static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2290 {
2291 .pa_start = OMAP34XX_SR2_BASE,
2292 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2293 .flags = ADDR_TYPE_RT,
2294 },
2295 { }
2296};
2297
2298static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2299 .master = &omap3xxx_l4_core_hwmod,
2300 .slave = &omap34xx_sr2_hwmod,
2301 .clk = "sr_l4_ick",
2302 .addr = omap3_sr2_addr_space,
2303 .user = OCP_USER_MPU,
2304};
2305
2306static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2307 .master = &omap3xxx_l4_core_hwmod,
2308 .slave = &omap36xx_sr2_hwmod,
2309 .clk = "sr_l4_ick",
2310 .addr = omap3_sr2_addr_space,
2311 .user = OCP_USER_MPU,
2312};
2313
2314static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2315 {
2316 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2317 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2318 .flags = ADDR_TYPE_RT
2319 },
2320 { }
2321};
2322
2323/* l4_core -> usbhsotg */
2324static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2325 .master = &omap3xxx_l4_core_hwmod,
2326 .slave = &omap3xxx_usbhsotg_hwmod,
2327 .clk = "l4_ick",
2328 .addr = omap3xxx_usbhsotg_addrs,
2329 .user = OCP_USER_MPU,
2330};
2331
2332static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2333 {
2334 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2335 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2336 .flags = ADDR_TYPE_RT
2337 },
2338 { }
2339};
2340
2341/* l4_core -> usbhsotg */
2342static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2343 .master = &omap3xxx_l4_core_hwmod,
2344 .slave = &am35xx_usbhsotg_hwmod,
2345 .clk = "l4_ick",
2346 .addr = am35xx_usbhsotg_addrs,
2347 .user = OCP_USER_MPU,
2348};
2349
2350/* L4_WKUP -> L4_SEC interface */
2351static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2352 .master = &omap3xxx_l4_wkup_hwmod,
2353 .slave = &omap3xxx_l4_sec_hwmod,
2354 .user = OCP_USER_MPU | OCP_USER_SDMA,
2355};
2356
2357/* IVA2 <- L3 interface */
2358static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2359 .master = &omap3xxx_l3_main_hwmod,
2360 .slave = &omap3xxx_iva_hwmod,
2361 .clk = "core_l3_ick",
2362 .user = OCP_USER_MPU | OCP_USER_SDMA,
2363};
2364
2365static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2366 {
2367 .pa_start = 0x48318000,
2368 .pa_end = 0x48318000 + SZ_1K - 1,
2369 .flags = ADDR_TYPE_RT
2370 },
2371 { }
2372};
2373
2374/* l4_wkup -> timer1 */
2375static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2376 .master = &omap3xxx_l4_wkup_hwmod,
2377 .slave = &omap3xxx_timer1_hwmod,
2378 .clk = "gpt1_ick",
2379 .addr = omap3xxx_timer1_addrs,
2380 .user = OCP_USER_MPU | OCP_USER_SDMA,
2381};
2382
2383static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2384 {
2385 .pa_start = 0x49032000,
2386 .pa_end = 0x49032000 + SZ_1K - 1,
2387 .flags = ADDR_TYPE_RT
2388 },
2389 { }
2390};
2391
2392/* l4_per -> timer2 */
2393static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2394 .master = &omap3xxx_l4_per_hwmod,
2395 .slave = &omap3xxx_timer2_hwmod,
2396 .clk = "gpt2_ick",
2397 .addr = omap3xxx_timer2_addrs,
2398 .user = OCP_USER_MPU | OCP_USER_SDMA,
2399};
2400
2401static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2402 {
2403 .pa_start = 0x49034000,
2404 .pa_end = 0x49034000 + SZ_1K - 1,
2405 .flags = ADDR_TYPE_RT
2406 },
2407 { }
2408};
2409
2410/* l4_per -> timer3 */
2411static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2412 .master = &omap3xxx_l4_per_hwmod,
2413 .slave = &omap3xxx_timer3_hwmod,
2414 .clk = "gpt3_ick",
2415 .addr = omap3xxx_timer3_addrs,
2416 .user = OCP_USER_MPU | OCP_USER_SDMA,
2417};
2418
2419static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2420 {
2421 .pa_start = 0x49036000,
2422 .pa_end = 0x49036000 + SZ_1K - 1,
2423 .flags = ADDR_TYPE_RT
2424 },
2425 { }
2426};
2427
2428/* l4_per -> timer4 */
2429static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2430 .master = &omap3xxx_l4_per_hwmod,
2431 .slave = &omap3xxx_timer4_hwmod,
2432 .clk = "gpt4_ick",
2433 .addr = omap3xxx_timer4_addrs,
2434 .user = OCP_USER_MPU | OCP_USER_SDMA,
2435};
2436
2437static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2438 {
2439 .pa_start = 0x49038000,
2440 .pa_end = 0x49038000 + SZ_1K - 1,
2441 .flags = ADDR_TYPE_RT
2442 },
2443 { }
2444};
2445
2446/* l4_per -> timer5 */
2447static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2448 .master = &omap3xxx_l4_per_hwmod,
2449 .slave = &omap3xxx_timer5_hwmod,
2450 .clk = "gpt5_ick",
2451 .addr = omap3xxx_timer5_addrs,
2452 .user = OCP_USER_MPU | OCP_USER_SDMA,
2453};
2454
2455static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2456 {
2457 .pa_start = 0x4903A000,
2458 .pa_end = 0x4903A000 + SZ_1K - 1,
2459 .flags = ADDR_TYPE_RT
2460 },
2461 { }
2462};
2463
2464/* l4_per -> timer6 */
2465static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2466 .master = &omap3xxx_l4_per_hwmod,
2467 .slave = &omap3xxx_timer6_hwmod,
2468 .clk = "gpt6_ick",
2469 .addr = omap3xxx_timer6_addrs,
2470 .user = OCP_USER_MPU | OCP_USER_SDMA,
2471};
2472
2473static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2474 {
2475 .pa_start = 0x4903C000,
2476 .pa_end = 0x4903C000 + SZ_1K - 1,
2477 .flags = ADDR_TYPE_RT
2478 },
2479 { }
2480};
2481
2482/* l4_per -> timer7 */
2483static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2484 .master = &omap3xxx_l4_per_hwmod,
2485 .slave = &omap3xxx_timer7_hwmod,
2486 .clk = "gpt7_ick",
2487 .addr = omap3xxx_timer7_addrs,
2488 .user = OCP_USER_MPU | OCP_USER_SDMA,
2489};
2490
2491static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2492 {
2493 .pa_start = 0x4903E000,
2494 .pa_end = 0x4903E000 + SZ_1K - 1,
2495 .flags = ADDR_TYPE_RT
2496 },
2497 { }
2498};
2499
2500/* l4_per -> timer8 */
2501static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2502 .master = &omap3xxx_l4_per_hwmod,
2503 .slave = &omap3xxx_timer8_hwmod,
2504 .clk = "gpt8_ick",
2505 .addr = omap3xxx_timer8_addrs,
2506 .user = OCP_USER_MPU | OCP_USER_SDMA,
2507};
2508
2509static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2510 {
2511 .pa_start = 0x49040000,
2512 .pa_end = 0x49040000 + SZ_1K - 1,
2513 .flags = ADDR_TYPE_RT
2514 },
2515 { }
2516};
2517
2518/* l4_per -> timer9 */
2519static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2520 .master = &omap3xxx_l4_per_hwmod,
2521 .slave = &omap3xxx_timer9_hwmod,
2522 .clk = "gpt9_ick",
2523 .addr = omap3xxx_timer9_addrs,
2524 .user = OCP_USER_MPU | OCP_USER_SDMA,
2525};
2526
2527/* l4_core -> timer10 */
2528static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2529 .master = &omap3xxx_l4_core_hwmod,
2530 .slave = &omap3xxx_timer10_hwmod,
2531 .clk = "gpt10_ick",
2532 .addr = omap2_timer10_addrs,
2533 .user = OCP_USER_MPU | OCP_USER_SDMA,
2534};
2535
2536/* l4_core -> timer11 */
2537static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2538 .master = &omap3xxx_l4_core_hwmod,
2539 .slave = &omap3xxx_timer11_hwmod,
2540 .clk = "gpt11_ick",
2541 .addr = omap2_timer11_addrs,
2542 .user = OCP_USER_MPU | OCP_USER_SDMA,
2543};
2544
2545static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2546 {
2547 .pa_start = 0x48304000,
2548 .pa_end = 0x48304000 + SZ_1K - 1,
2549 .flags = ADDR_TYPE_RT
2550 },
2551 { }
2552};
2553
2554/* l4_core -> timer12 */
2555static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2556 .master = &omap3xxx_l4_sec_hwmod,
2557 .slave = &omap3xxx_timer12_hwmod,
2558 .clk = "gpt12_ick",
2559 .addr = omap3xxx_timer12_addrs,
2560 .user = OCP_USER_MPU | OCP_USER_SDMA,
2561};
2562
2563/* l4_wkup -> wd_timer2 */
2564static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2565 {
2566 .pa_start = 0x48314000,
2567 .pa_end = 0x4831407f,
2568 .flags = ADDR_TYPE_RT
2569 },
2570 { }
2571};
2572
2573static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2574 .master = &omap3xxx_l4_wkup_hwmod,
2575 .slave = &omap3xxx_wd_timer2_hwmod,
2576 .clk = "wdt2_ick",
2577 .addr = omap3xxx_wd_timer2_addrs,
2578 .user = OCP_USER_MPU | OCP_USER_SDMA,
2579};
2580
2581/* l4_core -> dss */
2582static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2583 .master = &omap3xxx_l4_core_hwmod,
2584 .slave = &omap3430es1_dss_core_hwmod,
2585 .clk = "dss_ick",
2586 .addr = omap2_dss_addrs,
2587 .fw = {
2588 .omap2 = {
2589 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2590 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2591 .flags = OMAP_FIREWALL_L4,
2592 }
2593 },
2594 .user = OCP_USER_MPU | OCP_USER_SDMA,
2595};
2596
2597static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2598 .master = &omap3xxx_l4_core_hwmod,
2599 .slave = &omap3xxx_dss_core_hwmod,
2600 .clk = "dss_ick",
2601 .addr = omap2_dss_addrs,
2602 .fw = {
2603 .omap2 = {
2604 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2605 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2606 .flags = OMAP_FIREWALL_L4,
2607 }
2608 },
2609 .user = OCP_USER_MPU | OCP_USER_SDMA,
2610};
2611
2612/* l4_core -> dss_dispc */
2613static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2614 .master = &omap3xxx_l4_core_hwmod,
2615 .slave = &omap3xxx_dss_dispc_hwmod,
2616 .clk = "dss_ick",
2617 .addr = omap2_dss_dispc_addrs,
2618 .fw = {
2619 .omap2 = {
2620 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2621 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2622 .flags = OMAP_FIREWALL_L4,
2623 }
2624 },
2625 .user = OCP_USER_MPU | OCP_USER_SDMA,
2626};
2627
2628static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2629 {
2630 .pa_start = 0x4804FC00,
2631 .pa_end = 0x4804FFFF,
2632 .flags = ADDR_TYPE_RT
2633 },
2634 { }
2635};
2636
2637/* l4_core -> dss_dsi1 */
2638static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2639 .master = &omap3xxx_l4_core_hwmod,
2640 .slave = &omap3xxx_dss_dsi1_hwmod,
2641 .clk = "dss_ick",
2642 .addr = omap3xxx_dss_dsi1_addrs,
2643 .fw = {
2644 .omap2 = {
2645 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2646 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2647 .flags = OMAP_FIREWALL_L4,
2648 }
2649 },
2650 .user = OCP_USER_MPU | OCP_USER_SDMA,
2651};
2652
2653/* l4_core -> dss_rfbi */
2654static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2655 .master = &omap3xxx_l4_core_hwmod,
2656 .slave = &omap3xxx_dss_rfbi_hwmod,
2657 .clk = "dss_ick",
2658 .addr = omap2_dss_rfbi_addrs,
2659 .fw = {
2660 .omap2 = {
2661 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2662 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2663 .flags = OMAP_FIREWALL_L4,
2664 }
2665 },
2666 .user = OCP_USER_MPU | OCP_USER_SDMA,
2667};
2668
2669/* l4_core -> dss_venc */
2670static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2671 .master = &omap3xxx_l4_core_hwmod,
2672 .slave = &omap3xxx_dss_venc_hwmod,
2673 .clk = "dss_ick",
2674 .addr = omap2_dss_venc_addrs,
2675 .fw = {
2676 .omap2 = {
2677 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2678 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2679 .flags = OMAP_FIREWALL_L4,
2680 }
2681 },
2682 .flags = OCPIF_SWSUP_IDLE,
2683 .user = OCP_USER_MPU | OCP_USER_SDMA,
2684};
2685
2686/* l4_wkup -> gpio1 */
2687static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2688 {
2689 .pa_start = 0x48310000,
2690 .pa_end = 0x483101ff,
2691 .flags = ADDR_TYPE_RT
2692 },
2693 { }
2694};
2695
2696static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2697 .master = &omap3xxx_l4_wkup_hwmod,
2698 .slave = &omap3xxx_gpio1_hwmod,
2699 .addr = omap3xxx_gpio1_addrs,
2700 .user = OCP_USER_MPU | OCP_USER_SDMA,
2701};
2702
2703/* l4_per -> gpio2 */
2704static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2705 {
2706 .pa_start = 0x49050000,
2707 .pa_end = 0x490501ff,
2708 .flags = ADDR_TYPE_RT
2709 },
2710 { }
2711};
2712
2713static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2714 .master = &omap3xxx_l4_per_hwmod,
2715 .slave = &omap3xxx_gpio2_hwmod,
2716 .addr = omap3xxx_gpio2_addrs,
2717 .user = OCP_USER_MPU | OCP_USER_SDMA,
2718};
2719
2720/* l4_per -> gpio3 */
2721static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2722 {
2723 .pa_start = 0x49052000,
2724 .pa_end = 0x490521ff,
2725 .flags = ADDR_TYPE_RT
2726 },
2727 { }
2728};
2729
2730static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2731 .master = &omap3xxx_l4_per_hwmod,
2732 .slave = &omap3xxx_gpio3_hwmod,
2733 .addr = omap3xxx_gpio3_addrs,
2734 .user = OCP_USER_MPU | OCP_USER_SDMA,
2735};
2736
2737/* l4_per -> gpio4 */
2738static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2739 {
2740 .pa_start = 0x49054000,
2741 .pa_end = 0x490541ff,
2742 .flags = ADDR_TYPE_RT
2743 },
2744 { }
2745};
2746
2747static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2748 .master = &omap3xxx_l4_per_hwmod,
2749 .slave = &omap3xxx_gpio4_hwmod,
2750 .addr = omap3xxx_gpio4_addrs,
2751 .user = OCP_USER_MPU | OCP_USER_SDMA,
2752};
2753
2754/* l4_per -> gpio5 */
2755static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2756 {
2757 .pa_start = 0x49056000,
2758 .pa_end = 0x490561ff,
2759 .flags = ADDR_TYPE_RT
2760 },
2761 { }
2762};
2763
2764static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2765 .master = &omap3xxx_l4_per_hwmod,
2766 .slave = &omap3xxx_gpio5_hwmod,
2767 .addr = omap3xxx_gpio5_addrs,
2768 .user = OCP_USER_MPU | OCP_USER_SDMA,
2769};
2770
2771/* l4_per -> gpio6 */
2772static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2773 {
2774 .pa_start = 0x49058000,
2775 .pa_end = 0x490581ff,
2776 .flags = ADDR_TYPE_RT
2777 },
2778 { }
2779};
2780
2781static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2782 .master = &omap3xxx_l4_per_hwmod,
2783 .slave = &omap3xxx_gpio6_hwmod,
2784 .addr = omap3xxx_gpio6_addrs,
2785 .user = OCP_USER_MPU | OCP_USER_SDMA,
2786};
2787
2788/* dma_system -> L3 */
2789static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2790 .master = &omap3xxx_dma_system_hwmod,
2791 .slave = &omap3xxx_l3_main_hwmod,
2792 .clk = "core_l3_ick",
2793 .user = OCP_USER_MPU | OCP_USER_SDMA,
2794};
2795
2796static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2797 {
2798 .pa_start = 0x48056000,
2799 .pa_end = 0x48056fff,
2800 .flags = ADDR_TYPE_RT
2801 },
2802 { }
2803};
2804
2805/* l4_cfg -> dma_system */
2806static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2807 .master = &omap3xxx_l4_core_hwmod,
2808 .slave = &omap3xxx_dma_system_hwmod,
2809 .clk = "core_l4_ick",
2810 .addr = omap3xxx_dma_system_addrs,
2811 .user = OCP_USER_MPU | OCP_USER_SDMA,
2812};
2813
2814static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2815 {
2816 .name = "mpu",
2817 .pa_start = 0x48074000,
2818 .pa_end = 0x480740ff,
2819 .flags = ADDR_TYPE_RT
2820 },
2821 { }
2822};
2823
2824/* l4_core -> mcbsp1 */
2825static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2826 .master = &omap3xxx_l4_core_hwmod,
2827 .slave = &omap3xxx_mcbsp1_hwmod,
2828 .clk = "mcbsp1_ick",
2829 .addr = omap3xxx_mcbsp1_addrs,
2830 .user = OCP_USER_MPU | OCP_USER_SDMA,
2831};
2832
2833static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2834 {
2835 .name = "mpu",
2836 .pa_start = 0x49022000,
2837 .pa_end = 0x490220ff,
2838 .flags = ADDR_TYPE_RT
2839 },
2840 { }
2841};
2842
2843/* l4_per -> mcbsp2 */
2844static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2845 .master = &omap3xxx_l4_per_hwmod,
2846 .slave = &omap3xxx_mcbsp2_hwmod,
2847 .clk = "mcbsp2_ick",
2848 .addr = omap3xxx_mcbsp2_addrs,
2849 .user = OCP_USER_MPU | OCP_USER_SDMA,
2850};
2851
2852static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2853 {
2854 .name = "mpu",
2855 .pa_start = 0x49024000,
2856 .pa_end = 0x490240ff,
2857 .flags = ADDR_TYPE_RT
2858 },
2859 { }
2860};
2861
2862/* l4_per -> mcbsp3 */
2863static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2864 .master = &omap3xxx_l4_per_hwmod,
2865 .slave = &omap3xxx_mcbsp3_hwmod,
2866 .clk = "mcbsp3_ick",
2867 .addr = omap3xxx_mcbsp3_addrs,
2868 .user = OCP_USER_MPU | OCP_USER_SDMA,
2869};
2870
2871static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2872 {
2873 .name = "mpu",
2874 .pa_start = 0x49026000,
2875 .pa_end = 0x490260ff,
2876 .flags = ADDR_TYPE_RT
2877 },
2878 { }
2879};
2880
2881/* l4_per -> mcbsp4 */
2882static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2883 .master = &omap3xxx_l4_per_hwmod,
2884 .slave = &omap3xxx_mcbsp4_hwmod,
2885 .clk = "mcbsp4_ick",
2886 .addr = omap3xxx_mcbsp4_addrs,
2887 .user = OCP_USER_MPU | OCP_USER_SDMA,
2888};
2889
2890static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2891 {
2892 .name = "mpu",
2893 .pa_start = 0x48096000,
2894 .pa_end = 0x480960ff,
2895 .flags = ADDR_TYPE_RT
2896 },
2897 { }
2898};
2899
2900/* l4_core -> mcbsp5 */
2901static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2902 .master = &omap3xxx_l4_core_hwmod,
2903 .slave = &omap3xxx_mcbsp5_hwmod,
2904 .clk = "mcbsp5_ick",
2905 .addr = omap3xxx_mcbsp5_addrs,
2906 .user = OCP_USER_MPU | OCP_USER_SDMA,
2907};
2908
2909static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2910 {
2911 .name = "sidetone",
2912 .pa_start = 0x49028000,
2913 .pa_end = 0x490280ff,
2914 .flags = ADDR_TYPE_RT
2915 },
2916 { }
2917};
2918
2919/* l4_per -> mcbsp2_sidetone */
2920static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2921 .master = &omap3xxx_l4_per_hwmod,
2922 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2923 .clk = "mcbsp2_ick",
2924 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2925 .user = OCP_USER_MPU,
2926};
2927
2928static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2929 {
2930 .name = "sidetone",
2931 .pa_start = 0x4902A000,
2932 .pa_end = 0x4902A0ff,
2933 .flags = ADDR_TYPE_RT
2934 },
2935 { }
2936};
2937
2938/* l4_per -> mcbsp3_sidetone */
2939static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2940 .master = &omap3xxx_l4_per_hwmod,
2941 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2942 .clk = "mcbsp3_ick",
2943 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2944 .user = OCP_USER_MPU,
2945};
2946
2947static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2948 {
2949 .pa_start = 0x48094000,
2950 .pa_end = 0x480941ff,
2951 .flags = ADDR_TYPE_RT,
2952 },
2953 { }
2954};
2955
2956/* l4_core -> mailbox */
2957static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2958 .master = &omap3xxx_l4_core_hwmod,
2959 .slave = &omap3xxx_mailbox_hwmod,
2960 .addr = omap3xxx_mailbox_addrs,
2961 .user = OCP_USER_MPU | OCP_USER_SDMA,
2962};
2963
2964/* l4 core -> mcspi1 interface */
2965static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2966 .master = &omap3xxx_l4_core_hwmod,
2967 .slave = &omap34xx_mcspi1,
2968 .clk = "mcspi1_ick",
2969 .addr = omap2_mcspi1_addr_space,
2970 .user = OCP_USER_MPU | OCP_USER_SDMA,
2971};
2972
2973/* l4 core -> mcspi2 interface */
2974static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2975 .master = &omap3xxx_l4_core_hwmod,
2976 .slave = &omap34xx_mcspi2,
2977 .clk = "mcspi2_ick",
2978 .addr = omap2_mcspi2_addr_space,
2979 .user = OCP_USER_MPU | OCP_USER_SDMA,
2980};
2981
2982/* l4 core -> mcspi3 interface */
2983static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2984 .master = &omap3xxx_l4_core_hwmod,
2985 .slave = &omap34xx_mcspi3,
2986 .clk = "mcspi3_ick",
2987 .addr = omap2430_mcspi3_addr_space,
2988 .user = OCP_USER_MPU | OCP_USER_SDMA,
2989};
2990
2991/* l4 core -> mcspi4 interface */
2992static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2993 {
2994 .pa_start = 0x480ba000,
2995 .pa_end = 0x480ba0ff,
2996 .flags = ADDR_TYPE_RT,
2997 },
2998 { }
2999};
3000
3001static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3002 .master = &omap3xxx_l4_core_hwmod,
3003 .slave = &omap34xx_mcspi4,
3004 .clk = "mcspi4_ick",
3005 .addr = omap34xx_mcspi4_addr_space,
3006 .user = OCP_USER_MPU | OCP_USER_SDMA,
3007};
3008
3009static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3010 .master = &omap3xxx_usb_host_hs_hwmod,
3011 .slave = &omap3xxx_l3_main_hwmod,
3012 .clk = "core_l3_ick",
3013 .user = OCP_USER_MPU,
3014};
3015
3016static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3017 {
3018 .name = "uhh",
3019 .pa_start = 0x48064000,
3020 .pa_end = 0x480643ff,
3021 .flags = ADDR_TYPE_RT
3022 },
3023 {
3024 .name = "ohci",
3025 .pa_start = 0x48064400,
3026 .pa_end = 0x480647ff,
3027 },
3028 {
3029 .name = "ehci",
3030 .pa_start = 0x48064800,
3031 .pa_end = 0x48064cff,
3032 },
3033 {}
3034};
3035
3036static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3037 .master = &omap3xxx_l4_core_hwmod,
3038 .slave = &omap3xxx_usb_host_hs_hwmod,
3039 .clk = "usbhost_ick",
3040 .addr = omap3xxx_usb_host_hs_addrs,
3041 .user = OCP_USER_MPU | OCP_USER_SDMA,
3042};
3043
3504static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { 3044static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3505 { 3045 {
3506 .name = "tll", 3046 .name = "tll",
@@ -3519,183 +3059,156 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3519 .user = OCP_USER_MPU | OCP_USER_SDMA, 3059 .user = OCP_USER_MPU | OCP_USER_SDMA,
3520}; 3060};
3521 3061
3522static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = { 3062static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3523 &omap3xxx_l4_core__usb_tll_hs, 3063 &omap3xxx_l3_main__l4_core,
3524}; 3064 &omap3xxx_l3_main__l4_per,
3525 3065 &omap3xxx_mpu__l3_main,
3526static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { 3066 &omap3xxx_l4_core__l4_wkup,
3527 .name = "usb_tll_hs", 3067 &omap3xxx_l4_core__mmc3,
3528 .class = &omap3xxx_usb_tll_hs_hwmod_class, 3068 &omap3_l4_core__uart1,
3529 .clkdm_name = "l3_init_clkdm", 3069 &omap3_l4_core__uart2,
3530 .mpu_irqs = omap3xxx_usb_tll_hs_irqs, 3070 &omap3_l4_per__uart3,
3531 .main_clk = "usbtll_fck", 3071 &omap3_l4_core__i2c1,
3532 .prcm = { 3072 &omap3_l4_core__i2c2,
3533 .omap2 = { 3073 &omap3_l4_core__i2c3,
3534 .module_offs = CORE_MOD, 3074 &omap3xxx_l4_wkup__l4_sec,
3535 .prcm_reg_id = 3, 3075 &omap3xxx_l4_wkup__timer1,
3536 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 3076 &omap3xxx_l4_per__timer2,
3537 .idlest_reg_id = 3, 3077 &omap3xxx_l4_per__timer3,
3538 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, 3078 &omap3xxx_l4_per__timer4,
3539 }, 3079 &omap3xxx_l4_per__timer5,
3540 }, 3080 &omap3xxx_l4_per__timer6,
3541 .slaves = omap3xxx_usb_tll_hs_slaves, 3081 &omap3xxx_l4_per__timer7,
3542 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves), 3082 &omap3xxx_l4_per__timer8,
3543}; 3083 &omap3xxx_l4_per__timer9,
3544 3084 &omap3xxx_l4_core__timer10,
3545static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 3085 &omap3xxx_l4_core__timer11,
3546 &omap3xxx_l3_main_hwmod, 3086 &omap3xxx_l4_wkup__wd_timer2,
3547 &omap3xxx_l4_core_hwmod, 3087 &omap3xxx_l4_wkup__gpio1,
3548 &omap3xxx_l4_per_hwmod, 3088 &omap3xxx_l4_per__gpio2,
3549 &omap3xxx_l4_wkup_hwmod, 3089 &omap3xxx_l4_per__gpio3,
3550 &omap3xxx_mmc3_hwmod, 3090 &omap3xxx_l4_per__gpio4,
3551 &omap3xxx_mpu_hwmod, 3091 &omap3xxx_l4_per__gpio5,
3552 3092 &omap3xxx_l4_per__gpio6,
3553 &omap3xxx_timer1_hwmod, 3093 &omap3xxx_dma_system__l3,
3554 &omap3xxx_timer2_hwmod, 3094 &omap3xxx_l4_core__dma_system,
3555 &omap3xxx_timer3_hwmod, 3095 &omap3xxx_l4_core__mcbsp1,
3556 &omap3xxx_timer4_hwmod, 3096 &omap3xxx_l4_per__mcbsp2,
3557 &omap3xxx_timer5_hwmod, 3097 &omap3xxx_l4_per__mcbsp3,
3558 &omap3xxx_timer6_hwmod, 3098 &omap3xxx_l4_per__mcbsp4,
3559 &omap3xxx_timer7_hwmod, 3099 &omap3xxx_l4_core__mcbsp5,
3560 &omap3xxx_timer8_hwmod, 3100 &omap3xxx_l4_per__mcbsp2_sidetone,
3561 &omap3xxx_timer9_hwmod, 3101 &omap3xxx_l4_per__mcbsp3_sidetone,
3562 &omap3xxx_timer10_hwmod, 3102 &omap34xx_l4_core__mcspi1,
3563 &omap3xxx_timer11_hwmod, 3103 &omap34xx_l4_core__mcspi2,
3564 3104 &omap34xx_l4_core__mcspi3,
3565 &omap3xxx_wd_timer2_hwmod, 3105 &omap34xx_l4_core__mcspi4,
3566 &omap3xxx_uart1_hwmod,
3567 &omap3xxx_uart2_hwmod,
3568 &omap3xxx_uart3_hwmod,
3569
3570 /* i2c class */
3571 &omap3xxx_i2c1_hwmod,
3572 &omap3xxx_i2c2_hwmod,
3573 &omap3xxx_i2c3_hwmod,
3574
3575 /* gpio class */
3576 &omap3xxx_gpio1_hwmod,
3577 &omap3xxx_gpio2_hwmod,
3578 &omap3xxx_gpio3_hwmod,
3579 &omap3xxx_gpio4_hwmod,
3580 &omap3xxx_gpio5_hwmod,
3581 &omap3xxx_gpio6_hwmod,
3582
3583 /* dma_system class*/
3584 &omap3xxx_dma_system_hwmod,
3585
3586 /* mcbsp class */
3587 &omap3xxx_mcbsp1_hwmod,
3588 &omap3xxx_mcbsp2_hwmod,
3589 &omap3xxx_mcbsp3_hwmod,
3590 &omap3xxx_mcbsp4_hwmod,
3591 &omap3xxx_mcbsp5_hwmod,
3592 &omap3xxx_mcbsp2_sidetone_hwmod,
3593 &omap3xxx_mcbsp3_sidetone_hwmod,
3594
3595
3596 /* mcspi class */
3597 &omap34xx_mcspi1,
3598 &omap34xx_mcspi2,
3599 &omap34xx_mcspi3,
3600 &omap34xx_mcspi4,
3601
3602 NULL, 3106 NULL,
3603}; 3107};
3604 3108
3605/* GP-only hwmods */ 3109/* GP-only hwmod links */
3606static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = { 3110static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3607 &omap3xxx_timer12_hwmod, 3111 &omap3xxx_l4_sec__timer12,
3608 NULL 3112 NULL
3609}; 3113};
3610 3114
3611/* 3430ES1-only hwmods */ 3115/* 3430ES1-only hwmod links */
3612static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { 3116static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3613 &omap3430es1_dss_core_hwmod, 3117 &omap3430es1_dss__l3,
3118 &omap3430es1_l4_core__dss,
3614 NULL 3119 NULL
3615}; 3120};
3616 3121
3617/* 3430ES2+-only hwmods */ 3122/* 3430ES2+-only hwmod links */
3618static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { 3123static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3619 &omap3xxx_dss_core_hwmod, 3124 &omap3xxx_dss__l3,
3620 &omap3xxx_usbhsotg_hwmod, 3125 &omap3xxx_l4_core__dss,
3621 &omap3xxx_usb_host_hs_hwmod, 3126 &omap3xxx_usbhsotg__l3,
3622 &omap3xxx_usb_tll_hs_hwmod, 3127 &omap3xxx_l4_core__usbhsotg,
3128 &omap3xxx_usb_host_hs__l3_main_2,
3129 &omap3xxx_l4_core__usb_host_hs,
3130 &omap3xxx_l4_core__usb_tll_hs,
3623 NULL 3131 NULL
3624}; 3132};
3625 3133
3626/* <= 3430ES3-only hwmods */ 3134/* <= 3430ES3-only hwmod links */
3627static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = { 3135static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3628 &omap3xxx_pre_es3_mmc1_hwmod, 3136 &omap3xxx_l4_core__pre_es3_mmc1,
3629 &omap3xxx_pre_es3_mmc2_hwmod, 3137 &omap3xxx_l4_core__pre_es3_mmc2,
3630 NULL 3138 NULL
3631}; 3139};
3632 3140
3633/* 3430ES3+-only hwmods */ 3141/* 3430ES3+-only hwmod links */
3634static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = { 3142static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3635 &omap3xxx_es3plus_mmc1_hwmod, 3143 &omap3xxx_l4_core__es3plus_mmc1,
3636 &omap3xxx_es3plus_mmc2_hwmod, 3144 &omap3xxx_l4_core__es3plus_mmc2,
3637 NULL 3145 NULL
3638}; 3146};
3639 3147
3640/* 34xx-only hwmods (all ES revisions) */ 3148/* 34xx-only hwmod links (all ES revisions) */
3641static __initdata struct omap_hwmod *omap34xx_hwmods[] = { 3149static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3642 &omap3xxx_iva_hwmod, 3150 &omap3xxx_l3__iva,
3643 &omap34xx_sr1_hwmod, 3151 &omap34xx_l4_core__sr1,
3644 &omap34xx_sr2_hwmod, 3152 &omap34xx_l4_core__sr2,
3645 &omap3xxx_mailbox_hwmod, 3153 &omap3xxx_l4_core__mailbox,
3646 NULL 3154 NULL
3647}; 3155};
3648 3156
3649/* 36xx-only hwmods (all ES revisions) */ 3157/* 36xx-only hwmod links (all ES revisions) */
3650static __initdata struct omap_hwmod *omap36xx_hwmods[] = { 3158static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3651 &omap3xxx_iva_hwmod, 3159 &omap3xxx_l3__iva,
3652 &omap3xxx_uart4_hwmod, 3160 &omap36xx_l4_per__uart4,
3653 &omap3xxx_dss_core_hwmod, 3161 &omap3xxx_dss__l3,
3654 &omap36xx_sr1_hwmod, 3162 &omap3xxx_l4_core__dss,
3655 &omap36xx_sr2_hwmod, 3163 &omap36xx_l4_core__sr1,
3656 &omap3xxx_usbhsotg_hwmod, 3164 &omap36xx_l4_core__sr2,
3657 &omap3xxx_mailbox_hwmod, 3165 &omap3xxx_usbhsotg__l3,
3658 &omap3xxx_usb_host_hs_hwmod, 3166 &omap3xxx_l4_core__usbhsotg,
3659 &omap3xxx_usb_tll_hs_hwmod, 3167 &omap3xxx_l4_core__mailbox,
3660 &omap3xxx_es3plus_mmc1_hwmod, 3168 &omap3xxx_usb_host_hs__l3_main_2,
3661 &omap3xxx_es3plus_mmc2_hwmod, 3169 &omap3xxx_l4_core__usb_host_hs,
3170 &omap3xxx_l4_core__usb_tll_hs,
3171 &omap3xxx_l4_core__es3plus_mmc1,
3172 &omap3xxx_l4_core__es3plus_mmc2,
3662 NULL 3173 NULL
3663}; 3174};
3664 3175
3665static __initdata struct omap_hwmod *am35xx_hwmods[] = { 3176static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3666 &omap3xxx_dss_core_hwmod, /* XXX ??? */ 3177 &omap3xxx_dss__l3,
3667 &am35xx_usbhsotg_hwmod, 3178 &omap3xxx_l4_core__dss,
3668 &am35xx_uart4_hwmod, 3179 &am35xx_usbhsotg__l3,
3669 &omap3xxx_usb_host_hs_hwmod, 3180 &am35xx_l4_core__usbhsotg,
3670 &omap3xxx_usb_tll_hs_hwmod, 3181 &am35xx_l4_core__uart4,
3671 &omap3xxx_es3plus_mmc1_hwmod, 3182 &omap3xxx_usb_host_hs__l3_main_2,
3672 &omap3xxx_es3plus_mmc2_hwmod, 3183 &omap3xxx_l4_core__usb_host_hs,
3184 &omap3xxx_l4_core__usb_tll_hs,
3185 &omap3xxx_l4_core__es3plus_mmc1,
3186 &omap3xxx_l4_core__es3plus_mmc2,
3673 NULL 3187 NULL
3674}; 3188};
3675 3189
3676static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = { 3190static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3677 /* dss class */ 3191 &omap3xxx_l4_core__dss_dispc,
3678 &omap3xxx_dss_dispc_hwmod, 3192 &omap3xxx_l4_core__dss_dsi1,
3679 &omap3xxx_dss_dsi1_hwmod, 3193 &omap3xxx_l4_core__dss_rfbi,
3680 &omap3xxx_dss_rfbi_hwmod, 3194 &omap3xxx_l4_core__dss_venc,
3681 &omap3xxx_dss_venc_hwmod,
3682 NULL 3195 NULL
3683}; 3196};
3684 3197
3685int __init omap3xxx_hwmod_init(void) 3198int __init omap3xxx_hwmod_init(void)
3686{ 3199{
3687 int r; 3200 int r;
3688 struct omap_hwmod **h = NULL; 3201 struct omap_hwmod_ocp_if **h = NULL;
3689 unsigned int rev; 3202 unsigned int rev;
3690 3203
3691 /* Register hwmods common to all OMAP3 */ 3204 /* Register hwmod links common to all OMAP3 */
3692 r = omap_hwmod_register(omap3xxx_hwmods); 3205 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3693 if (r < 0) 3206 if (r < 0)
3694 return r; 3207 return r;
3695 3208
3696 /* Register GP-only hwmods. */ 3209 /* Register GP-only hwmod links. */
3697 if (omap_type() == OMAP2_DEVICE_TYPE_GP) { 3210 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3698 r = omap_hwmod_register(omap3xxx_gp_hwmods); 3211 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3699 if (r < 0) 3212 if (r < 0)
3700 return r; 3213 return r;
3701 } 3214 }
@@ -3703,43 +3216,43 @@ int __init omap3xxx_hwmod_init(void)
3703 rev = omap_rev(); 3216 rev = omap_rev();
3704 3217
3705 /* 3218 /*
3706 * Register hwmods common to individual OMAP3 families, all 3219 * Register hwmod links common to individual OMAP3 families, all
3707 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) 3220 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3708 * All possible revisions should be included in this conditional. 3221 * All possible revisions should be included in this conditional.
3709 */ 3222 */
3710 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3223 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3711 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || 3224 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3712 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { 3225 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3713 h = omap34xx_hwmods; 3226 h = omap34xx_hwmod_ocp_ifs;
3714 } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) { 3227 } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3715 h = am35xx_hwmods; 3228 h = am35xx_hwmod_ocp_ifs;
3716 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || 3229 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3717 rev == OMAP3630_REV_ES1_2) { 3230 rev == OMAP3630_REV_ES1_2) {
3718 h = omap36xx_hwmods; 3231 h = omap36xx_hwmod_ocp_ifs;
3719 } else { 3232 } else {
3720 WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); 3233 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3721 return -EINVAL; 3234 return -EINVAL;
3722 }; 3235 };
3723 3236
3724 r = omap_hwmod_register(h); 3237 r = omap_hwmod_register_links(h);
3725 if (r < 0) 3238 if (r < 0)
3726 return r; 3239 return r;
3727 3240
3728 /* 3241 /*
3729 * Register hwmods specific to certain ES levels of a 3242 * Register hwmod links specific to certain ES levels of a
3730 * particular family of silicon (e.g., 34xx ES1.0) 3243 * particular family of silicon (e.g., 34xx ES1.0)
3731 */ 3244 */
3732 h = NULL; 3245 h = NULL;
3733 if (rev == OMAP3430_REV_ES1_0) { 3246 if (rev == OMAP3430_REV_ES1_0) {
3734 h = omap3430es1_hwmods; 3247 h = omap3430es1_hwmod_ocp_ifs;
3735 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 3248 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3736 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3249 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3737 rev == OMAP3430_REV_ES3_1_2) { 3250 rev == OMAP3430_REV_ES3_1_2) {
3738 h = omap3430es2plus_hwmods; 3251 h = omap3430es2plus_hwmod_ocp_ifs;
3739 }; 3252 };
3740 3253
3741 if (h) { 3254 if (h) {
3742 r = omap_hwmod_register(h); 3255 r = omap_hwmod_register_links(h);
3743 if (r < 0) 3256 if (r < 0)
3744 return r; 3257 return r;
3745 } 3258 }
@@ -3747,29 +3260,29 @@ int __init omap3xxx_hwmod_init(void)
3747 h = NULL; 3260 h = NULL;
3748 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3261 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3749 rev == OMAP3430_REV_ES2_1) { 3262 rev == OMAP3430_REV_ES2_1) {
3750 h = omap3430_pre_es3_hwmods; 3263 h = omap3430_pre_es3_hwmod_ocp_ifs;
3751 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3264 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3752 rev == OMAP3430_REV_ES3_1_2) { 3265 rev == OMAP3430_REV_ES3_1_2) {
3753 h = omap3430_es3plus_hwmods; 3266 h = omap3430_es3plus_hwmod_ocp_ifs;
3754 }; 3267 };
3755 3268
3756 if (h) 3269 if (h)
3757 r = omap_hwmod_register(h); 3270 r = omap_hwmod_register_links(h);
3758 if (r < 0) 3271 if (r < 0)
3759 return r; 3272 return r;
3760 3273
3761 /* 3274 /*
3762 * DSS code presumes that dss_core hwmod is handled first, 3275 * DSS code presumes that dss_core hwmod is handled first,
3763 * _before_ any other DSS related hwmods so register common 3276 * _before_ any other DSS related hwmods so register common
3764 * DSS hwmods last to ensure that dss_core is already registered. 3277 * DSS hwmod links last to ensure that dss_core is already
3765 * Otherwise some change things may happen, for ex. if dispc 3278 * registered. Otherwise some change things may happen, for
3766 * is handled before dss_core and DSS is enabled in bootloader 3279 * ex. if dispc is handled before dss_core and DSS is enabled
3767 * DIPSC will be reset with outputs enabled which sometimes leads 3280 * in bootloader DISPC will be reset with outputs enabled
3768 * to unrecoverable L3 error. 3281 * which sometimes leads to unrecoverable L3 error. XXX The
3769 * XXX The long-term fix to this is to ensure modules are set up 3282 * long-term fix to this is to ensure hwmods are set up in
3770 * in dependency order in the hwmod core code. 3283 * dependency order in the hwmod core code.
3771 */ 3284 */
3772 r = omap_hwmod_register(omap3xxx_dss_hwmods); 3285 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3773 3286
3774 return r; 3287 return r;
3775} 3288}
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 6abc75753e4..0d91dec5b4b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Hardware modules present on the OMAP44xx chips 2 * Hardware modules present on the OMAP44xx chips
3 * 3 *
4 * Copyright (C) 2009-2011 Texas Instruments, Inc. 4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley 7 * Paul Walmsley
@@ -44,38 +44,10 @@
44#define OMAP44XX_IRQ_GIC_START 32 44#define OMAP44XX_IRQ_GIC_START 32
45 45
46/* Base offset for all OMAP4 dma requests */ 46/* Base offset for all OMAP4 dma requests */
47#define OMAP44XX_DMA_REQ_START 1 47#define OMAP44XX_DMA_REQ_START 1
48
49/* Backward references (IPs with Bus Master capability) */
50static struct omap_hwmod omap44xx_aess_hwmod;
51static struct omap_hwmod omap44xx_dma_system_hwmod;
52static struct omap_hwmod omap44xx_dmm_hwmod;
53static struct omap_hwmod omap44xx_dsp_hwmod;
54static struct omap_hwmod omap44xx_dss_hwmod;
55static struct omap_hwmod omap44xx_emif_fw_hwmod;
56static struct omap_hwmod omap44xx_hsi_hwmod;
57static struct omap_hwmod omap44xx_ipu_hwmod;
58static struct omap_hwmod omap44xx_iss_hwmod;
59static struct omap_hwmod omap44xx_iva_hwmod;
60static struct omap_hwmod omap44xx_l3_instr_hwmod;
61static struct omap_hwmod omap44xx_l3_main_1_hwmod;
62static struct omap_hwmod omap44xx_l3_main_2_hwmod;
63static struct omap_hwmod omap44xx_l3_main_3_hwmod;
64static struct omap_hwmod omap44xx_l4_abe_hwmod;
65static struct omap_hwmod omap44xx_l4_cfg_hwmod;
66static struct omap_hwmod omap44xx_l4_per_hwmod;
67static struct omap_hwmod omap44xx_l4_wkup_hwmod;
68static struct omap_hwmod omap44xx_mmc1_hwmod;
69static struct omap_hwmod omap44xx_mmc2_hwmod;
70static struct omap_hwmod omap44xx_mpu_hwmod;
71static struct omap_hwmod omap44xx_mpu_private_hwmod;
72static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
73static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
74static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
75 48
76/* 49/*
77 * Interconnects omap_hwmod structures 50 * IP blocks
78 * hwmods that compose the global OMAP interconnect
79 */ 51 */
80 52
81/* 53/*
@@ -92,51 +64,17 @@ static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
92 { .irq = -1 } 64 { .irq = -1 }
93}; 65};
94 66
95/* l3_main_1 -> dmm */
96static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
97 .master = &omap44xx_l3_main_1_hwmod,
98 .slave = &omap44xx_dmm_hwmod,
99 .clk = "l3_div_ck",
100 .user = OCP_USER_SDMA,
101};
102
103static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
104 {
105 .pa_start = 0x4e000000,
106 .pa_end = 0x4e0007ff,
107 .flags = ADDR_TYPE_RT
108 },
109 { }
110};
111
112/* mpu -> dmm */
113static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
114 .master = &omap44xx_mpu_hwmod,
115 .slave = &omap44xx_dmm_hwmod,
116 .clk = "l3_div_ck",
117 .addr = omap44xx_dmm_addrs,
118 .user = OCP_USER_MPU,
119};
120
121/* dmm slave ports */
122static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
123 &omap44xx_l3_main_1__dmm,
124 &omap44xx_mpu__dmm,
125};
126
127static struct omap_hwmod omap44xx_dmm_hwmod = { 67static struct omap_hwmod omap44xx_dmm_hwmod = {
128 .name = "dmm", 68 .name = "dmm",
129 .class = &omap44xx_dmm_hwmod_class, 69 .class = &omap44xx_dmm_hwmod_class,
130 .clkdm_name = "l3_emif_clkdm", 70 .clkdm_name = "l3_emif_clkdm",
71 .mpu_irqs = omap44xx_dmm_irqs,
131 .prcm = { 72 .prcm = {
132 .omap4 = { 73 .omap4 = {
133 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, 74 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
134 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, 75 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
135 }, 76 },
136 }, 77 },
137 .slaves = omap44xx_dmm_slaves,
138 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
139 .mpu_irqs = omap44xx_dmm_irqs,
140}; 78};
141 79
142/* 80/*
@@ -148,38 +86,6 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
148}; 86};
149 87
150/* emif_fw */ 88/* emif_fw */
151/* dmm -> emif_fw */
152static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
153 .master = &omap44xx_dmm_hwmod,
154 .slave = &omap44xx_emif_fw_hwmod,
155 .clk = "l3_div_ck",
156 .user = OCP_USER_MPU | OCP_USER_SDMA,
157};
158
159static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
160 {
161 .pa_start = 0x4a20c000,
162 .pa_end = 0x4a20c0ff,
163 .flags = ADDR_TYPE_RT
164 },
165 { }
166};
167
168/* l4_cfg -> emif_fw */
169static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
170 .master = &omap44xx_l4_cfg_hwmod,
171 .slave = &omap44xx_emif_fw_hwmod,
172 .clk = "l4_div_ck",
173 .addr = omap44xx_emif_fw_addrs,
174 .user = OCP_USER_MPU,
175};
176
177/* emif_fw slave ports */
178static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
179 &omap44xx_dmm__emif_fw,
180 &omap44xx_l4_cfg__emif_fw,
181};
182
183static struct omap_hwmod omap44xx_emif_fw_hwmod = { 89static struct omap_hwmod omap44xx_emif_fw_hwmod = {
184 .name = "emif_fw", 90 .name = "emif_fw",
185 .class = &omap44xx_emif_fw_hwmod_class, 91 .class = &omap44xx_emif_fw_hwmod_class,
@@ -190,8 +96,6 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
190 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, 96 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
191 }, 97 },
192 }, 98 },
193 .slaves = omap44xx_emif_fw_slaves,
194 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
195}; 99};
196 100
197/* 101/*
@@ -203,28 +107,6 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
203}; 107};
204 108
205/* l3_instr */ 109/* l3_instr */
206/* iva -> l3_instr */
207static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
208 .master = &omap44xx_iva_hwmod,
209 .slave = &omap44xx_l3_instr_hwmod,
210 .clk = "l3_div_ck",
211 .user = OCP_USER_MPU | OCP_USER_SDMA,
212};
213
214/* l3_main_3 -> l3_instr */
215static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
216 .master = &omap44xx_l3_main_3_hwmod,
217 .slave = &omap44xx_l3_instr_hwmod,
218 .clk = "l3_div_ck",
219 .user = OCP_USER_MPU | OCP_USER_SDMA,
220};
221
222/* l3_instr slave ports */
223static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
224 &omap44xx_iva__l3_instr,
225 &omap44xx_l3_main_3__l3_instr,
226};
227
228static struct omap_hwmod omap44xx_l3_instr_hwmod = { 110static struct omap_hwmod omap44xx_l3_instr_hwmod = {
229 .name = "l3_instr", 111 .name = "l3_instr",
230 .class = &omap44xx_l3_hwmod_class, 112 .class = &omap44xx_l3_hwmod_class,
@@ -236,8 +118,6 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
236 .modulemode = MODULEMODE_HWCTRL, 118 .modulemode = MODULEMODE_HWCTRL,
237 }, 119 },
238 }, 120 },
239 .slaves = omap44xx_l3_instr_slaves,
240 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
241}; 121};
242 122
243/* l3_main_1 */ 123/* l3_main_1 */
@@ -247,83 +127,6 @@ static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
247 { .irq = -1 } 127 { .irq = -1 }
248}; 128};
249 129
250/* dsp -> l3_main_1 */
251static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
252 .master = &omap44xx_dsp_hwmod,
253 .slave = &omap44xx_l3_main_1_hwmod,
254 .clk = "l3_div_ck",
255 .user = OCP_USER_MPU | OCP_USER_SDMA,
256};
257
258/* dss -> l3_main_1 */
259static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
260 .master = &omap44xx_dss_hwmod,
261 .slave = &omap44xx_l3_main_1_hwmod,
262 .clk = "l3_div_ck",
263 .user = OCP_USER_MPU | OCP_USER_SDMA,
264};
265
266/* l3_main_2 -> l3_main_1 */
267static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
268 .master = &omap44xx_l3_main_2_hwmod,
269 .slave = &omap44xx_l3_main_1_hwmod,
270 .clk = "l3_div_ck",
271 .user = OCP_USER_MPU | OCP_USER_SDMA,
272};
273
274/* l4_cfg -> l3_main_1 */
275static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
276 .master = &omap44xx_l4_cfg_hwmod,
277 .slave = &omap44xx_l3_main_1_hwmod,
278 .clk = "l4_div_ck",
279 .user = OCP_USER_MPU | OCP_USER_SDMA,
280};
281
282/* mmc1 -> l3_main_1 */
283static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
284 .master = &omap44xx_mmc1_hwmod,
285 .slave = &omap44xx_l3_main_1_hwmod,
286 .clk = "l3_div_ck",
287 .user = OCP_USER_MPU | OCP_USER_SDMA,
288};
289
290/* mmc2 -> l3_main_1 */
291static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
292 .master = &omap44xx_mmc2_hwmod,
293 .slave = &omap44xx_l3_main_1_hwmod,
294 .clk = "l3_div_ck",
295 .user = OCP_USER_MPU | OCP_USER_SDMA,
296};
297
298static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
299 {
300 .pa_start = 0x44000000,
301 .pa_end = 0x44000fff,
302 .flags = ADDR_TYPE_RT
303 },
304 { }
305};
306
307/* mpu -> l3_main_1 */
308static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
309 .master = &omap44xx_mpu_hwmod,
310 .slave = &omap44xx_l3_main_1_hwmod,
311 .clk = "l3_div_ck",
312 .addr = omap44xx_l3_main_1_addrs,
313 .user = OCP_USER_MPU,
314};
315
316/* l3_main_1 slave ports */
317static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
318 &omap44xx_dsp__l3_main_1,
319 &omap44xx_dss__l3_main_1,
320 &omap44xx_l3_main_2__l3_main_1,
321 &omap44xx_l4_cfg__l3_main_1,
322 &omap44xx_mmc1__l3_main_1,
323 &omap44xx_mmc2__l3_main_1,
324 &omap44xx_mpu__l3_main_1,
325};
326
327static struct omap_hwmod omap44xx_l3_main_1_hwmod = { 130static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
328 .name = "l3_main_1", 131 .name = "l3_main_1",
329 .class = &omap44xx_l3_hwmod_class, 132 .class = &omap44xx_l3_hwmod_class,
@@ -335,97 +138,9 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
335 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, 138 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
336 }, 139 },
337 }, 140 },
338 .slaves = omap44xx_l3_main_1_slaves,
339 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
340}; 141};
341 142
342/* l3_main_2 */ 143/* l3_main_2 */
343/* dma_system -> l3_main_2 */
344static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
345 .master = &omap44xx_dma_system_hwmod,
346 .slave = &omap44xx_l3_main_2_hwmod,
347 .clk = "l3_div_ck",
348 .user = OCP_USER_MPU | OCP_USER_SDMA,
349};
350
351/* hsi -> l3_main_2 */
352static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
353 .master = &omap44xx_hsi_hwmod,
354 .slave = &omap44xx_l3_main_2_hwmod,
355 .clk = "l3_div_ck",
356 .user = OCP_USER_MPU | OCP_USER_SDMA,
357};
358
359/* ipu -> l3_main_2 */
360static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
361 .master = &omap44xx_ipu_hwmod,
362 .slave = &omap44xx_l3_main_2_hwmod,
363 .clk = "l3_div_ck",
364 .user = OCP_USER_MPU | OCP_USER_SDMA,
365};
366
367/* iss -> l3_main_2 */
368static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
369 .master = &omap44xx_iss_hwmod,
370 .slave = &omap44xx_l3_main_2_hwmod,
371 .clk = "l3_div_ck",
372 .user = OCP_USER_MPU | OCP_USER_SDMA,
373};
374
375/* iva -> l3_main_2 */
376static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
377 .master = &omap44xx_iva_hwmod,
378 .slave = &omap44xx_l3_main_2_hwmod,
379 .clk = "l3_div_ck",
380 .user = OCP_USER_MPU | OCP_USER_SDMA,
381};
382
383static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
384 {
385 .pa_start = 0x44800000,
386 .pa_end = 0x44801fff,
387 .flags = ADDR_TYPE_RT
388 },
389 { }
390};
391
392/* l3_main_1 -> l3_main_2 */
393static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
394 .master = &omap44xx_l3_main_1_hwmod,
395 .slave = &omap44xx_l3_main_2_hwmod,
396 .clk = "l3_div_ck",
397 .addr = omap44xx_l3_main_2_addrs,
398 .user = OCP_USER_MPU,
399};
400
401/* l4_cfg -> l3_main_2 */
402static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
403 .master = &omap44xx_l4_cfg_hwmod,
404 .slave = &omap44xx_l3_main_2_hwmod,
405 .clk = "l4_div_ck",
406 .user = OCP_USER_MPU | OCP_USER_SDMA,
407};
408
409/* usb_otg_hs -> l3_main_2 */
410static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
411 .master = &omap44xx_usb_otg_hs_hwmod,
412 .slave = &omap44xx_l3_main_2_hwmod,
413 .clk = "l3_div_ck",
414 .user = OCP_USER_MPU | OCP_USER_SDMA,
415};
416
417/* l3_main_2 slave ports */
418static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
419 &omap44xx_dma_system__l3_main_2,
420 &omap44xx_hsi__l3_main_2,
421 &omap44xx_ipu__l3_main_2,
422 &omap44xx_iss__l3_main_2,
423 &omap44xx_iva__l3_main_2,
424 &omap44xx_l3_main_1__l3_main_2,
425 &omap44xx_l4_cfg__l3_main_2,
426 &omap44xx_usb_otg_hs__l3_main_2,
427};
428
429static struct omap_hwmod omap44xx_l3_main_2_hwmod = { 144static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
430 .name = "l3_main_2", 145 .name = "l3_main_2",
431 .class = &omap44xx_l3_hwmod_class, 146 .class = &omap44xx_l3_hwmod_class,
@@ -436,52 +151,9 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
436 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, 151 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
437 }, 152 },
438 }, 153 },
439 .slaves = omap44xx_l3_main_2_slaves,
440 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
441}; 154};
442 155
443/* l3_main_3 */ 156/* l3_main_3 */
444static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
445 {
446 .pa_start = 0x45000000,
447 .pa_end = 0x45000fff,
448 .flags = ADDR_TYPE_RT
449 },
450 { }
451};
452
453/* l3_main_1 -> l3_main_3 */
454static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
455 .master = &omap44xx_l3_main_1_hwmod,
456 .slave = &omap44xx_l3_main_3_hwmod,
457 .clk = "l3_div_ck",
458 .addr = omap44xx_l3_main_3_addrs,
459 .user = OCP_USER_MPU,
460};
461
462/* l3_main_2 -> l3_main_3 */
463static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
464 .master = &omap44xx_l3_main_2_hwmod,
465 .slave = &omap44xx_l3_main_3_hwmod,
466 .clk = "l3_div_ck",
467 .user = OCP_USER_MPU | OCP_USER_SDMA,
468};
469
470/* l4_cfg -> l3_main_3 */
471static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
472 .master = &omap44xx_l4_cfg_hwmod,
473 .slave = &omap44xx_l3_main_3_hwmod,
474 .clk = "l4_div_ck",
475 .user = OCP_USER_MPU | OCP_USER_SDMA,
476};
477
478/* l3_main_3 slave ports */
479static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
480 &omap44xx_l3_main_1__l3_main_3,
481 &omap44xx_l3_main_2__l3_main_3,
482 &omap44xx_l4_cfg__l3_main_3,
483};
484
485static struct omap_hwmod omap44xx_l3_main_3_hwmod = { 157static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
486 .name = "l3_main_3", 158 .name = "l3_main_3",
487 .class = &omap44xx_l3_hwmod_class, 159 .class = &omap44xx_l3_hwmod_class,
@@ -493,8 +165,6 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
493 .modulemode = MODULEMODE_HWCTRL, 165 .modulemode = MODULEMODE_HWCTRL,
494 }, 166 },
495 }, 167 },
496 .slaves = omap44xx_l3_main_3_slaves,
497 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
498}; 168};
499 169
500/* 170/*
@@ -506,46 +176,6 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
506}; 176};
507 177
508/* l4_abe */ 178/* l4_abe */
509/* aess -> l4_abe */
510static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
511 .master = &omap44xx_aess_hwmod,
512 .slave = &omap44xx_l4_abe_hwmod,
513 .clk = "ocp_abe_iclk",
514 .user = OCP_USER_MPU | OCP_USER_SDMA,
515};
516
517/* dsp -> l4_abe */
518static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
519 .master = &omap44xx_dsp_hwmod,
520 .slave = &omap44xx_l4_abe_hwmod,
521 .clk = "ocp_abe_iclk",
522 .user = OCP_USER_MPU | OCP_USER_SDMA,
523};
524
525/* l3_main_1 -> l4_abe */
526static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
527 .master = &omap44xx_l3_main_1_hwmod,
528 .slave = &omap44xx_l4_abe_hwmod,
529 .clk = "l3_div_ck",
530 .user = OCP_USER_MPU | OCP_USER_SDMA,
531};
532
533/* mpu -> l4_abe */
534static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
535 .master = &omap44xx_mpu_hwmod,
536 .slave = &omap44xx_l4_abe_hwmod,
537 .clk = "ocp_abe_iclk",
538 .user = OCP_USER_MPU | OCP_USER_SDMA,
539};
540
541/* l4_abe slave ports */
542static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
543 &omap44xx_aess__l4_abe,
544 &omap44xx_dsp__l4_abe,
545 &omap44xx_l3_main_1__l4_abe,
546 &omap44xx_mpu__l4_abe,
547};
548
549static struct omap_hwmod omap44xx_l4_abe_hwmod = { 179static struct omap_hwmod omap44xx_l4_abe_hwmod = {
550 .name = "l4_abe", 180 .name = "l4_abe",
551 .class = &omap44xx_l4_hwmod_class, 181 .class = &omap44xx_l4_hwmod_class,
@@ -555,24 +185,9 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
555 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, 185 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
556 }, 186 },
557 }, 187 },
558 .slaves = omap44xx_l4_abe_slaves,
559 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
560}; 188};
561 189
562/* l4_cfg */ 190/* l4_cfg */
563/* l3_main_1 -> l4_cfg */
564static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
565 .master = &omap44xx_l3_main_1_hwmod,
566 .slave = &omap44xx_l4_cfg_hwmod,
567 .clk = "l3_div_ck",
568 .user = OCP_USER_MPU | OCP_USER_SDMA,
569};
570
571/* l4_cfg slave ports */
572static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
573 &omap44xx_l3_main_1__l4_cfg,
574};
575
576static struct omap_hwmod omap44xx_l4_cfg_hwmod = { 191static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
577 .name = "l4_cfg", 192 .name = "l4_cfg",
578 .class = &omap44xx_l4_hwmod_class, 193 .class = &omap44xx_l4_hwmod_class,
@@ -583,24 +198,9 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
583 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, 198 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
584 }, 199 },
585 }, 200 },
586 .slaves = omap44xx_l4_cfg_slaves,
587 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
588}; 201};
589 202
590/* l4_per */ 203/* l4_per */
591/* l3_main_2 -> l4_per */
592static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
593 .master = &omap44xx_l3_main_2_hwmod,
594 .slave = &omap44xx_l4_per_hwmod,
595 .clk = "l3_div_ck",
596 .user = OCP_USER_MPU | OCP_USER_SDMA,
597};
598
599/* l4_per slave ports */
600static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
601 &omap44xx_l3_main_2__l4_per,
602};
603
604static struct omap_hwmod omap44xx_l4_per_hwmod = { 204static struct omap_hwmod omap44xx_l4_per_hwmod = {
605 .name = "l4_per", 205 .name = "l4_per",
606 .class = &omap44xx_l4_hwmod_class, 206 .class = &omap44xx_l4_hwmod_class,
@@ -611,24 +211,9 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
611 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, 211 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
612 }, 212 },
613 }, 213 },
614 .slaves = omap44xx_l4_per_slaves,
615 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
616}; 214};
617 215
618/* l4_wkup */ 216/* l4_wkup */
619/* l4_cfg -> l4_wkup */
620static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
621 .master = &omap44xx_l4_cfg_hwmod,
622 .slave = &omap44xx_l4_wkup_hwmod,
623 .clk = "l4_div_ck",
624 .user = OCP_USER_MPU | OCP_USER_SDMA,
625};
626
627/* l4_wkup slave ports */
628static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
629 &omap44xx_l4_cfg__l4_wkup,
630};
631
632static struct omap_hwmod omap44xx_l4_wkup_hwmod = { 217static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
633 .name = "l4_wkup", 218 .name = "l4_wkup",
634 .class = &omap44xx_l4_hwmod_class, 219 .class = &omap44xx_l4_hwmod_class,
@@ -639,8 +224,6 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
639 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, 224 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
640 }, 225 },
641 }, 226 },
642 .slaves = omap44xx_l4_wkup_slaves,
643 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
644}; 227};
645 228
646/* 229/*
@@ -652,25 +235,10 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
652}; 235};
653 236
654/* mpu_private */ 237/* mpu_private */
655/* mpu -> mpu_private */
656static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
657 .master = &omap44xx_mpu_hwmod,
658 .slave = &omap44xx_mpu_private_hwmod,
659 .clk = "l3_div_ck",
660 .user = OCP_USER_MPU | OCP_USER_SDMA,
661};
662
663/* mpu_private slave ports */
664static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
665 &omap44xx_mpu__mpu_private,
666};
667
668static struct omap_hwmod omap44xx_mpu_private_hwmod = { 238static struct omap_hwmod omap44xx_mpu_private_hwmod = {
669 .name = "mpu_private", 239 .name = "mpu_private",
670 .class = &omap44xx_mpu_bus_hwmod_class, 240 .class = &omap44xx_mpu_bus_hwmod_class,
671 .clkdm_name = "mpuss_clkdm", 241 .clkdm_name = "mpuss_clkdm",
672 .slaves = omap44xx_mpu_private_slaves,
673 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
674}; 242};
675 243
676/* 244/*
@@ -756,53 +324,6 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
756 { .dma_req = -1 } 324 { .dma_req = -1 }
757}; 325};
758 326
759/* aess master ports */
760static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
761 &omap44xx_aess__l4_abe,
762};
763
764static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
765 {
766 .pa_start = 0x401f1000,
767 .pa_end = 0x401f13ff,
768 .flags = ADDR_TYPE_RT
769 },
770 { }
771};
772
773/* l4_abe -> aess */
774static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
775 .master = &omap44xx_l4_abe_hwmod,
776 .slave = &omap44xx_aess_hwmod,
777 .clk = "ocp_abe_iclk",
778 .addr = omap44xx_aess_addrs,
779 .user = OCP_USER_MPU,
780};
781
782static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
783 {
784 .pa_start = 0x490f1000,
785 .pa_end = 0x490f13ff,
786 .flags = ADDR_TYPE_RT
787 },
788 { }
789};
790
791/* l4_abe -> aess (dma) */
792static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
793 .master = &omap44xx_l4_abe_hwmod,
794 .slave = &omap44xx_aess_hwmod,
795 .clk = "ocp_abe_iclk",
796 .addr = omap44xx_aess_dma_addrs,
797 .user = OCP_USER_SDMA,
798};
799
800/* aess slave ports */
801static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
802 &omap44xx_l4_abe__aess,
803 &omap44xx_l4_abe__aess_dma,
804};
805
806static struct omap_hwmod omap44xx_aess_hwmod = { 327static struct omap_hwmod omap44xx_aess_hwmod = {
807 .name = "aess", 328 .name = "aess",
808 .class = &omap44xx_aess_hwmod_class, 329 .class = &omap44xx_aess_hwmod_class,
@@ -817,37 +338,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
817 .modulemode = MODULEMODE_SWCTRL, 338 .modulemode = MODULEMODE_SWCTRL,
818 }, 339 },
819 }, 340 },
820 .slaves = omap44xx_aess_slaves,
821 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
822 .masters = omap44xx_aess_masters,
823 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
824};
825
826/*
827 * 'bandgap' class
828 * bangap reference for ldo regulators
829 */
830
831static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
832 .name = "bandgap",
833};
834
835/* bandgap */
836static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
837 { .role = "fclk", .clk = "bandgap_fclk" },
838};
839
840static struct omap_hwmod omap44xx_bandgap_hwmod = {
841 .name = "bandgap",
842 .class = &omap44xx_bandgap_hwmod_class,
843 .clkdm_name = "l4_wkup_clkdm",
844 .prcm = {
845 .omap4 = {
846 .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
847 },
848 },
849 .opt_clks = bandgap_opt_clks,
850 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
851}; 341};
852 342
853/* 343/*
@@ -870,30 +360,6 @@ static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
870}; 360};
871 361
872/* counter_32k */ 362/* counter_32k */
873static struct omap_hwmod omap44xx_counter_32k_hwmod;
874static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
875 {
876 .pa_start = 0x4a304000,
877 .pa_end = 0x4a30401f,
878 .flags = ADDR_TYPE_RT
879 },
880 { }
881};
882
883/* l4_wkup -> counter_32k */
884static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
885 .master = &omap44xx_l4_wkup_hwmod,
886 .slave = &omap44xx_counter_32k_hwmod,
887 .clk = "l4_wkup_clk_mux_ck",
888 .addr = omap44xx_counter_32k_addrs,
889 .user = OCP_USER_MPU | OCP_USER_SDMA,
890};
891
892/* counter_32k slave ports */
893static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
894 &omap44xx_l4_wkup__counter_32k,
895};
896
897static struct omap_hwmod omap44xx_counter_32k_hwmod = { 363static struct omap_hwmod omap44xx_counter_32k_hwmod = {
898 .name = "counter_32k", 364 .name = "counter_32k",
899 .class = &omap44xx_counter_hwmod_class, 365 .class = &omap44xx_counter_hwmod_class,
@@ -906,8 +372,6 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
906 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, 372 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
907 }, 373 },
908 }, 374 },
909 .slaves = omap44xx_counter_32k_slaves,
910 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
911}; 375};
912 376
913/* 377/*
@@ -950,34 +414,6 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
950 { .irq = -1 } 414 { .irq = -1 }
951}; 415};
952 416
953/* dma_system master ports */
954static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
955 &omap44xx_dma_system__l3_main_2,
956};
957
958static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
959 {
960 .pa_start = 0x4a056000,
961 .pa_end = 0x4a056fff,
962 .flags = ADDR_TYPE_RT
963 },
964 { }
965};
966
967/* l4_cfg -> dma_system */
968static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
969 .master = &omap44xx_l4_cfg_hwmod,
970 .slave = &omap44xx_dma_system_hwmod,
971 .clk = "l4_div_ck",
972 .addr = omap44xx_dma_system_addrs,
973 .user = OCP_USER_MPU | OCP_USER_SDMA,
974};
975
976/* dma_system slave ports */
977static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
978 &omap44xx_l4_cfg__dma_system,
979};
980
981static struct omap_hwmod omap44xx_dma_system_hwmod = { 417static struct omap_hwmod omap44xx_dma_system_hwmod = {
982 .name = "dma_system", 418 .name = "dma_system",
983 .class = &omap44xx_dma_hwmod_class, 419 .class = &omap44xx_dma_hwmod_class,
@@ -991,10 +427,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
991 }, 427 },
992 }, 428 },
993 .dev_attr = &dma_dev_attr, 429 .dev_attr = &dma_dev_attr,
994 .slaves = omap44xx_dma_system_slaves,
995 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
996 .masters = omap44xx_dma_system_masters,
997 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
998}; 430};
999 431
1000/* 432/*
@@ -1018,7 +450,6 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1018}; 450};
1019 451
1020/* dmic */ 452/* dmic */
1021static struct omap_hwmod omap44xx_dmic_hwmod;
1022static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { 453static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1023 { .irq = 114 + OMAP44XX_IRQ_GIC_START }, 454 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1024 { .irq = -1 } 455 { .irq = -1 }
@@ -1029,50 +460,6 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1029 { .dma_req = -1 } 460 { .dma_req = -1 }
1030}; 461};
1031 462
1032static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1033 {
1034 .name = "mpu",
1035 .pa_start = 0x4012e000,
1036 .pa_end = 0x4012e07f,
1037 .flags = ADDR_TYPE_RT
1038 },
1039 { }
1040};
1041
1042/* l4_abe -> dmic */
1043static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1044 .master = &omap44xx_l4_abe_hwmod,
1045 .slave = &omap44xx_dmic_hwmod,
1046 .clk = "ocp_abe_iclk",
1047 .addr = omap44xx_dmic_addrs,
1048 .user = OCP_USER_MPU,
1049};
1050
1051static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1052 {
1053 .name = "dma",
1054 .pa_start = 0x4902e000,
1055 .pa_end = 0x4902e07f,
1056 .flags = ADDR_TYPE_RT
1057 },
1058 { }
1059};
1060
1061/* l4_abe -> dmic (dma) */
1062static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1063 .master = &omap44xx_l4_abe_hwmod,
1064 .slave = &omap44xx_dmic_hwmod,
1065 .clk = "ocp_abe_iclk",
1066 .addr = omap44xx_dmic_dma_addrs,
1067 .user = OCP_USER_SDMA,
1068};
1069
1070/* dmic slave ports */
1071static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1072 &omap44xx_l4_abe__dmic,
1073 &omap44xx_l4_abe__dmic_dma,
1074};
1075
1076static struct omap_hwmod omap44xx_dmic_hwmod = { 463static struct omap_hwmod omap44xx_dmic_hwmod = {
1077 .name = "dmic", 464 .name = "dmic",
1078 .class = &omap44xx_dmic_hwmod_class, 465 .class = &omap44xx_dmic_hwmod_class,
@@ -1087,8 +474,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
1087 .modulemode = MODULEMODE_SWCTRL, 474 .modulemode = MODULEMODE_SWCTRL,
1088 }, 475 },
1089 }, 476 },
1090 .slaves = omap44xx_dmic_slaves,
1091 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1092}; 477};
1093 478
1094/* 479/*
@@ -1107,53 +492,8 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1107}; 492};
1108 493
1109static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { 494static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1110 { .name = "mmu_cache", .rst_shift = 1 },
1111};
1112
1113static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1114 { .name = "dsp", .rst_shift = 0 }, 495 { .name = "dsp", .rst_shift = 0 },
1115}; 496 { .name = "mmu_cache", .rst_shift = 1 },
1116
1117/* dsp -> iva */
1118static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1119 .master = &omap44xx_dsp_hwmod,
1120 .slave = &omap44xx_iva_hwmod,
1121 .clk = "dpll_iva_m5x2_ck",
1122};
1123
1124/* dsp master ports */
1125static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1126 &omap44xx_dsp__l3_main_1,
1127 &omap44xx_dsp__l4_abe,
1128 &omap44xx_dsp__iva,
1129};
1130
1131/* l4_cfg -> dsp */
1132static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1133 .master = &omap44xx_l4_cfg_hwmod,
1134 .slave = &omap44xx_dsp_hwmod,
1135 .clk = "l4_div_ck",
1136 .user = OCP_USER_MPU | OCP_USER_SDMA,
1137};
1138
1139/* dsp slave ports */
1140static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1141 &omap44xx_l4_cfg__dsp,
1142};
1143
1144/* Pseudo hwmod for reset control purpose only */
1145static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1146 .name = "dsp_c0",
1147 .class = &omap44xx_dsp_hwmod_class,
1148 .clkdm_name = "tesla_clkdm",
1149 .flags = HWMOD_INIT_NO_RESET,
1150 .rst_lines = omap44xx_dsp_c0_resets,
1151 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1152 .prcm = {
1153 .omap4 = {
1154 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1155 },
1156 },
1157}; 497};
1158 498
1159static struct omap_hwmod omap44xx_dsp_hwmod = { 499static struct omap_hwmod omap44xx_dsp_hwmod = {
@@ -1172,10 +512,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
1172 .modulemode = MODULEMODE_HWCTRL, 512 .modulemode = MODULEMODE_HWCTRL,
1173 }, 513 },
1174 }, 514 },
1175 .slaves = omap44xx_dsp_slaves,
1176 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1177 .masters = omap44xx_dsp_masters,
1178 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1179}; 515};
1180 516
1181/* 517/*
@@ -1196,53 +532,6 @@ static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1196}; 532};
1197 533
1198/* dss */ 534/* dss */
1199/* dss master ports */
1200static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1201 &omap44xx_dss__l3_main_1,
1202};
1203
1204static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1205 {
1206 .pa_start = 0x58000000,
1207 .pa_end = 0x5800007f,
1208 .flags = ADDR_TYPE_RT
1209 },
1210 { }
1211};
1212
1213/* l3_main_2 -> dss */
1214static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1215 .master = &omap44xx_l3_main_2_hwmod,
1216 .slave = &omap44xx_dss_hwmod,
1217 .clk = "dss_fck",
1218 .addr = omap44xx_dss_dma_addrs,
1219 .user = OCP_USER_SDMA,
1220};
1221
1222static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1223 {
1224 .pa_start = 0x48040000,
1225 .pa_end = 0x4804007f,
1226 .flags = ADDR_TYPE_RT
1227 },
1228 { }
1229};
1230
1231/* l4_per -> dss */
1232static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1233 .master = &omap44xx_l4_per_hwmod,
1234 .slave = &omap44xx_dss_hwmod,
1235 .clk = "l4_div_ck",
1236 .addr = omap44xx_dss_addrs,
1237 .user = OCP_USER_MPU,
1238};
1239
1240/* dss slave ports */
1241static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1242 &omap44xx_l3_main_2__dss,
1243 &omap44xx_l4_per__dss,
1244};
1245
1246static struct omap_hwmod_opt_clk dss_opt_clks[] = { 535static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1247 { .role = "sys_clk", .clk = "dss_sys_clk" }, 536 { .role = "sys_clk", .clk = "dss_sys_clk" },
1248 { .role = "tv_clk", .clk = "dss_tv_clk" }, 537 { .role = "tv_clk", .clk = "dss_tv_clk" },
@@ -1263,10 +552,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
1263 }, 552 },
1264 .opt_clks = dss_opt_clks, 553 .opt_clks = dss_opt_clks,
1265 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 554 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1266 .slaves = omap44xx_dss_slaves,
1267 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1268 .masters = omap44xx_dss_masters,
1269 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1270}; 555};
1271 556
1272/* 557/*
@@ -1293,7 +578,6 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1293}; 578};
1294 579
1295/* dss_dispc */ 580/* dss_dispc */
1296static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1297static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { 581static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1298 { .irq = 25 + OMAP44XX_IRQ_GIC_START }, 582 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1299 { .irq = -1 } 583 { .irq = -1 }
@@ -1304,53 +588,11 @@ static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1304 { .dma_req = -1 } 588 { .dma_req = -1 }
1305}; 589};
1306 590
1307static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1308 {
1309 .pa_start = 0x58001000,
1310 .pa_end = 0x58001fff,
1311 .flags = ADDR_TYPE_RT
1312 },
1313 { }
1314};
1315
1316/* l3_main_2 -> dss_dispc */
1317static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1318 .master = &omap44xx_l3_main_2_hwmod,
1319 .slave = &omap44xx_dss_dispc_hwmod,
1320 .clk = "dss_fck",
1321 .addr = omap44xx_dss_dispc_dma_addrs,
1322 .user = OCP_USER_SDMA,
1323};
1324
1325static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1326 {
1327 .pa_start = 0x48041000,
1328 .pa_end = 0x48041fff,
1329 .flags = ADDR_TYPE_RT
1330 },
1331 { }
1332};
1333
1334static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { 591static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1335 .manager_count = 3, 592 .manager_count = 3,
1336 .has_framedonetv_irq = 1 593 .has_framedonetv_irq = 1
1337}; 594};
1338 595
1339/* l4_per -> dss_dispc */
1340static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1341 .master = &omap44xx_l4_per_hwmod,
1342 .slave = &omap44xx_dss_dispc_hwmod,
1343 .clk = "l4_div_ck",
1344 .addr = omap44xx_dss_dispc_addrs,
1345 .user = OCP_USER_MPU,
1346};
1347
1348/* dss_dispc slave ports */
1349static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1350 &omap44xx_l3_main_2__dss_dispc,
1351 &omap44xx_l4_per__dss_dispc,
1352};
1353
1354static struct omap_hwmod omap44xx_dss_dispc_hwmod = { 596static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1355 .name = "dss_dispc", 597 .name = "dss_dispc",
1356 .class = &omap44xx_dispc_hwmod_class, 598 .class = &omap44xx_dispc_hwmod_class,
@@ -1364,8 +606,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1364 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 606 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1365 }, 607 },
1366 }, 608 },
1367 .slaves = omap44xx_dss_dispc_slaves,
1368 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1369 .dev_attr = &omap44xx_dss_dispc_dev_attr 609 .dev_attr = &omap44xx_dss_dispc_dev_attr
1370}; 610};
1371 611
@@ -1391,7 +631,6 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1391}; 631};
1392 632
1393/* dss_dsi1 */ 633/* dss_dsi1 */
1394static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1395static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { 634static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1396 { .irq = 53 + OMAP44XX_IRQ_GIC_START }, 635 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1397 { .irq = -1 } 636 { .irq = -1 }
@@ -1402,48 +641,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1402 { .dma_req = -1 } 641 { .dma_req = -1 }
1403}; 642};
1404 643
1405static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1406 {
1407 .pa_start = 0x58004000,
1408 .pa_end = 0x580041ff,
1409 .flags = ADDR_TYPE_RT
1410 },
1411 { }
1412};
1413
1414/* l3_main_2 -> dss_dsi1 */
1415static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1416 .master = &omap44xx_l3_main_2_hwmod,
1417 .slave = &omap44xx_dss_dsi1_hwmod,
1418 .clk = "dss_fck",
1419 .addr = omap44xx_dss_dsi1_dma_addrs,
1420 .user = OCP_USER_SDMA,
1421};
1422
1423static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1424 {
1425 .pa_start = 0x48044000,
1426 .pa_end = 0x480441ff,
1427 .flags = ADDR_TYPE_RT
1428 },
1429 { }
1430};
1431
1432/* l4_per -> dss_dsi1 */
1433static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1434 .master = &omap44xx_l4_per_hwmod,
1435 .slave = &omap44xx_dss_dsi1_hwmod,
1436 .clk = "l4_div_ck",
1437 .addr = omap44xx_dss_dsi1_addrs,
1438 .user = OCP_USER_MPU,
1439};
1440
1441/* dss_dsi1 slave ports */
1442static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1443 &omap44xx_l3_main_2__dss_dsi1,
1444 &omap44xx_l4_per__dss_dsi1,
1445};
1446
1447static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 644static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1448 { .role = "sys_clk", .clk = "dss_sys_clk" }, 645 { .role = "sys_clk", .clk = "dss_sys_clk" },
1449}; 646};
@@ -1463,12 +660,9 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1463 }, 660 },
1464 .opt_clks = dss_dsi1_opt_clks, 661 .opt_clks = dss_dsi1_opt_clks,
1465 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 662 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1466 .slaves = omap44xx_dss_dsi1_slaves,
1467 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1468}; 663};
1469 664
1470/* dss_dsi2 */ 665/* dss_dsi2 */
1471static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1472static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { 666static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1473 { .irq = 84 + OMAP44XX_IRQ_GIC_START }, 667 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1474 { .irq = -1 } 668 { .irq = -1 }
@@ -1479,48 +673,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1479 { .dma_req = -1 } 673 { .dma_req = -1 }
1480}; 674};
1481 675
1482static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1483 {
1484 .pa_start = 0x58005000,
1485 .pa_end = 0x580051ff,
1486 .flags = ADDR_TYPE_RT
1487 },
1488 { }
1489};
1490
1491/* l3_main_2 -> dss_dsi2 */
1492static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1493 .master = &omap44xx_l3_main_2_hwmod,
1494 .slave = &omap44xx_dss_dsi2_hwmod,
1495 .clk = "dss_fck",
1496 .addr = omap44xx_dss_dsi2_dma_addrs,
1497 .user = OCP_USER_SDMA,
1498};
1499
1500static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1501 {
1502 .pa_start = 0x48045000,
1503 .pa_end = 0x480451ff,
1504 .flags = ADDR_TYPE_RT
1505 },
1506 { }
1507};
1508
1509/* l4_per -> dss_dsi2 */
1510static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1511 .master = &omap44xx_l4_per_hwmod,
1512 .slave = &omap44xx_dss_dsi2_hwmod,
1513 .clk = "l4_div_ck",
1514 .addr = omap44xx_dss_dsi2_addrs,
1515 .user = OCP_USER_MPU,
1516};
1517
1518/* dss_dsi2 slave ports */
1519static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1520 &omap44xx_l3_main_2__dss_dsi2,
1521 &omap44xx_l4_per__dss_dsi2,
1522};
1523
1524static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { 676static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1525 { .role = "sys_clk", .clk = "dss_sys_clk" }, 677 { .role = "sys_clk", .clk = "dss_sys_clk" },
1526}; 678};
@@ -1540,8 +692,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1540 }, 692 },
1541 .opt_clks = dss_dsi2_opt_clks, 693 .opt_clks = dss_dsi2_opt_clks,
1542 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), 694 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
1543 .slaves = omap44xx_dss_dsi2_slaves,
1544 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1545}; 695};
1546 696
1547/* 697/*
@@ -1565,7 +715,6 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1565}; 715};
1566 716
1567/* dss_hdmi */ 717/* dss_hdmi */
1568static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1569static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { 718static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1570 { .irq = 101 + OMAP44XX_IRQ_GIC_START }, 719 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1571 { .irq = -1 } 720 { .irq = -1 }
@@ -1576,48 +725,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1576 { .dma_req = -1 } 725 { .dma_req = -1 }
1577}; 726};
1578 727
1579static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1580 {
1581 .pa_start = 0x58006000,
1582 .pa_end = 0x58006fff,
1583 .flags = ADDR_TYPE_RT
1584 },
1585 { }
1586};
1587
1588/* l3_main_2 -> dss_hdmi */
1589static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1590 .master = &omap44xx_l3_main_2_hwmod,
1591 .slave = &omap44xx_dss_hdmi_hwmod,
1592 .clk = "dss_fck",
1593 .addr = omap44xx_dss_hdmi_dma_addrs,
1594 .user = OCP_USER_SDMA,
1595};
1596
1597static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1598 {
1599 .pa_start = 0x48046000,
1600 .pa_end = 0x48046fff,
1601 .flags = ADDR_TYPE_RT
1602 },
1603 { }
1604};
1605
1606/* l4_per -> dss_hdmi */
1607static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1608 .master = &omap44xx_l4_per_hwmod,
1609 .slave = &omap44xx_dss_hdmi_hwmod,
1610 .clk = "l4_div_ck",
1611 .addr = omap44xx_dss_hdmi_addrs,
1612 .user = OCP_USER_MPU,
1613};
1614
1615/* dss_hdmi slave ports */
1616static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1617 &omap44xx_l3_main_2__dss_hdmi,
1618 &omap44xx_l4_per__dss_hdmi,
1619};
1620
1621static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { 728static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1622 { .role = "sys_clk", .clk = "dss_sys_clk" }, 729 { .role = "sys_clk", .clk = "dss_sys_clk" },
1623}; 730};
@@ -1637,8 +744,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1637 }, 744 },
1638 .opt_clks = dss_hdmi_opt_clks, 745 .opt_clks = dss_hdmi_opt_clks,
1639 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), 746 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
1640 .slaves = omap44xx_dss_hdmi_slaves,
1641 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1642}; 747};
1643 748
1644/* 749/*
@@ -1662,54 +767,11 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1662}; 767};
1663 768
1664/* dss_rfbi */ 769/* dss_rfbi */
1665static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1666static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { 770static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1667 { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, 771 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1668 { .dma_req = -1 } 772 { .dma_req = -1 }
1669}; 773};
1670 774
1671static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1672 {
1673 .pa_start = 0x58002000,
1674 .pa_end = 0x580020ff,
1675 .flags = ADDR_TYPE_RT
1676 },
1677 { }
1678};
1679
1680/* l3_main_2 -> dss_rfbi */
1681static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1682 .master = &omap44xx_l3_main_2_hwmod,
1683 .slave = &omap44xx_dss_rfbi_hwmod,
1684 .clk = "dss_fck",
1685 .addr = omap44xx_dss_rfbi_dma_addrs,
1686 .user = OCP_USER_SDMA,
1687};
1688
1689static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1690 {
1691 .pa_start = 0x48042000,
1692 .pa_end = 0x480420ff,
1693 .flags = ADDR_TYPE_RT
1694 },
1695 { }
1696};
1697
1698/* l4_per -> dss_rfbi */
1699static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1700 .master = &omap44xx_l4_per_hwmod,
1701 .slave = &omap44xx_dss_rfbi_hwmod,
1702 .clk = "l4_div_ck",
1703 .addr = omap44xx_dss_rfbi_addrs,
1704 .user = OCP_USER_MPU,
1705};
1706
1707/* dss_rfbi slave ports */
1708static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1709 &omap44xx_l3_main_2__dss_rfbi,
1710 &omap44xx_l4_per__dss_rfbi,
1711};
1712
1713static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 775static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1714 { .role = "ick", .clk = "dss_fck" }, 776 { .role = "ick", .clk = "dss_fck" },
1715}; 777};
@@ -1728,8 +790,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1728 }, 790 },
1729 .opt_clks = dss_rfbi_opt_clks, 791 .opt_clks = dss_rfbi_opt_clks,
1730 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 792 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1731 .slaves = omap44xx_dss_rfbi_slaves,
1732 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1733}; 793};
1734 794
1735/* 795/*
@@ -1742,49 +802,6 @@ static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1742}; 802};
1743 803
1744/* dss_venc */ 804/* dss_venc */
1745static struct omap_hwmod omap44xx_dss_venc_hwmod;
1746static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1747 {
1748 .pa_start = 0x58003000,
1749 .pa_end = 0x580030ff,
1750 .flags = ADDR_TYPE_RT
1751 },
1752 { }
1753};
1754
1755/* l3_main_2 -> dss_venc */
1756static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1757 .master = &omap44xx_l3_main_2_hwmod,
1758 .slave = &omap44xx_dss_venc_hwmod,
1759 .clk = "dss_fck",
1760 .addr = omap44xx_dss_venc_dma_addrs,
1761 .user = OCP_USER_SDMA,
1762};
1763
1764static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1765 {
1766 .pa_start = 0x48043000,
1767 .pa_end = 0x480430ff,
1768 .flags = ADDR_TYPE_RT
1769 },
1770 { }
1771};
1772
1773/* l4_per -> dss_venc */
1774static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1775 .master = &omap44xx_l4_per_hwmod,
1776 .slave = &omap44xx_dss_venc_hwmod,
1777 .clk = "l4_div_ck",
1778 .addr = omap44xx_dss_venc_addrs,
1779 .user = OCP_USER_MPU,
1780};
1781
1782/* dss_venc slave ports */
1783static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1784 &omap44xx_l3_main_2__dss_venc,
1785 &omap44xx_l4_per__dss_venc,
1786};
1787
1788static struct omap_hwmod omap44xx_dss_venc_hwmod = { 805static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1789 .name = "dss_venc", 806 .name = "dss_venc",
1790 .class = &omap44xx_venc_hwmod_class, 807 .class = &omap44xx_venc_hwmod_class,
@@ -1796,8 +813,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1796 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 813 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1797 }, 814 },
1798 }, 815 },
1799 .slaves = omap44xx_dss_venc_slaves,
1800 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1801}; 816};
1802 817
1803/* 818/*
@@ -1830,35 +845,11 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
1830}; 845};
1831 846
1832/* gpio1 */ 847/* gpio1 */
1833static struct omap_hwmod omap44xx_gpio1_hwmod;
1834static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { 848static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1835 { .irq = 29 + OMAP44XX_IRQ_GIC_START }, 849 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1836 { .irq = -1 } 850 { .irq = -1 }
1837}; 851};
1838 852
1839static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1840 {
1841 .pa_start = 0x4a310000,
1842 .pa_end = 0x4a3101ff,
1843 .flags = ADDR_TYPE_RT
1844 },
1845 { }
1846};
1847
1848/* l4_wkup -> gpio1 */
1849static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1850 .master = &omap44xx_l4_wkup_hwmod,
1851 .slave = &omap44xx_gpio1_hwmod,
1852 .clk = "l4_wkup_clk_mux_ck",
1853 .addr = omap44xx_gpio1_addrs,
1854 .user = OCP_USER_MPU | OCP_USER_SDMA,
1855};
1856
1857/* gpio1 slave ports */
1858static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1859 &omap44xx_l4_wkup__gpio1,
1860};
1861
1862static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 853static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1863 { .role = "dbclk", .clk = "gpio1_dbclk" }, 854 { .role = "dbclk", .clk = "gpio1_dbclk" },
1864}; 855};
@@ -1879,40 +870,14 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
1879 .opt_clks = gpio1_opt_clks, 870 .opt_clks = gpio1_opt_clks,
1880 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 871 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1881 .dev_attr = &gpio_dev_attr, 872 .dev_attr = &gpio_dev_attr,
1882 .slaves = omap44xx_gpio1_slaves,
1883 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
1884}; 873};
1885 874
1886/* gpio2 */ 875/* gpio2 */
1887static struct omap_hwmod omap44xx_gpio2_hwmod;
1888static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { 876static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1889 { .irq = 30 + OMAP44XX_IRQ_GIC_START }, 877 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1890 { .irq = -1 } 878 { .irq = -1 }
1891}; 879};
1892 880
1893static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1894 {
1895 .pa_start = 0x48055000,
1896 .pa_end = 0x480551ff,
1897 .flags = ADDR_TYPE_RT
1898 },
1899 { }
1900};
1901
1902/* l4_per -> gpio2 */
1903static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1904 .master = &omap44xx_l4_per_hwmod,
1905 .slave = &omap44xx_gpio2_hwmod,
1906 .clk = "l4_div_ck",
1907 .addr = omap44xx_gpio2_addrs,
1908 .user = OCP_USER_MPU | OCP_USER_SDMA,
1909};
1910
1911/* gpio2 slave ports */
1912static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1913 &omap44xx_l4_per__gpio2,
1914};
1915
1916static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 881static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1917 { .role = "dbclk", .clk = "gpio2_dbclk" }, 882 { .role = "dbclk", .clk = "gpio2_dbclk" },
1918}; 883};
@@ -1934,40 +899,14 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
1934 .opt_clks = gpio2_opt_clks, 899 .opt_clks = gpio2_opt_clks,
1935 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 900 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1936 .dev_attr = &gpio_dev_attr, 901 .dev_attr = &gpio_dev_attr,
1937 .slaves = omap44xx_gpio2_slaves,
1938 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
1939}; 902};
1940 903
1941/* gpio3 */ 904/* gpio3 */
1942static struct omap_hwmod omap44xx_gpio3_hwmod;
1943static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { 905static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1944 { .irq = 31 + OMAP44XX_IRQ_GIC_START }, 906 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1945 { .irq = -1 } 907 { .irq = -1 }
1946}; 908};
1947 909
1948static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1949 {
1950 .pa_start = 0x48057000,
1951 .pa_end = 0x480571ff,
1952 .flags = ADDR_TYPE_RT
1953 },
1954 { }
1955};
1956
1957/* l4_per -> gpio3 */
1958static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1959 .master = &omap44xx_l4_per_hwmod,
1960 .slave = &omap44xx_gpio3_hwmod,
1961 .clk = "l4_div_ck",
1962 .addr = omap44xx_gpio3_addrs,
1963 .user = OCP_USER_MPU | OCP_USER_SDMA,
1964};
1965
1966/* gpio3 slave ports */
1967static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1968 &omap44xx_l4_per__gpio3,
1969};
1970
1971static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 910static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1972 { .role = "dbclk", .clk = "gpio3_dbclk" }, 911 { .role = "dbclk", .clk = "gpio3_dbclk" },
1973}; 912};
@@ -1989,40 +928,14 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
1989 .opt_clks = gpio3_opt_clks, 928 .opt_clks = gpio3_opt_clks,
1990 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 929 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1991 .dev_attr = &gpio_dev_attr, 930 .dev_attr = &gpio_dev_attr,
1992 .slaves = omap44xx_gpio3_slaves,
1993 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
1994}; 931};
1995 932
1996/* gpio4 */ 933/* gpio4 */
1997static struct omap_hwmod omap44xx_gpio4_hwmod;
1998static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { 934static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1999 { .irq = 32 + OMAP44XX_IRQ_GIC_START }, 935 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
2000 { .irq = -1 } 936 { .irq = -1 }
2001}; 937};
2002 938
2003static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2004 {
2005 .pa_start = 0x48059000,
2006 .pa_end = 0x480591ff,
2007 .flags = ADDR_TYPE_RT
2008 },
2009 { }
2010};
2011
2012/* l4_per -> gpio4 */
2013static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2014 .master = &omap44xx_l4_per_hwmod,
2015 .slave = &omap44xx_gpio4_hwmod,
2016 .clk = "l4_div_ck",
2017 .addr = omap44xx_gpio4_addrs,
2018 .user = OCP_USER_MPU | OCP_USER_SDMA,
2019};
2020
2021/* gpio4 slave ports */
2022static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2023 &omap44xx_l4_per__gpio4,
2024};
2025
2026static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 939static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2027 { .role = "dbclk", .clk = "gpio4_dbclk" }, 940 { .role = "dbclk", .clk = "gpio4_dbclk" },
2028}; 941};
@@ -2044,40 +957,14 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
2044 .opt_clks = gpio4_opt_clks, 957 .opt_clks = gpio4_opt_clks,
2045 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 958 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2046 .dev_attr = &gpio_dev_attr, 959 .dev_attr = &gpio_dev_attr,
2047 .slaves = omap44xx_gpio4_slaves,
2048 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
2049}; 960};
2050 961
2051/* gpio5 */ 962/* gpio5 */
2052static struct omap_hwmod omap44xx_gpio5_hwmod;
2053static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { 963static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2054 { .irq = 33 + OMAP44XX_IRQ_GIC_START }, 964 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2055 { .irq = -1 } 965 { .irq = -1 }
2056}; 966};
2057 967
2058static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2059 {
2060 .pa_start = 0x4805b000,
2061 .pa_end = 0x4805b1ff,
2062 .flags = ADDR_TYPE_RT
2063 },
2064 { }
2065};
2066
2067/* l4_per -> gpio5 */
2068static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2069 .master = &omap44xx_l4_per_hwmod,
2070 .slave = &omap44xx_gpio5_hwmod,
2071 .clk = "l4_div_ck",
2072 .addr = omap44xx_gpio5_addrs,
2073 .user = OCP_USER_MPU | OCP_USER_SDMA,
2074};
2075
2076/* gpio5 slave ports */
2077static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2078 &omap44xx_l4_per__gpio5,
2079};
2080
2081static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 968static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2082 { .role = "dbclk", .clk = "gpio5_dbclk" }, 969 { .role = "dbclk", .clk = "gpio5_dbclk" },
2083}; 970};
@@ -2099,40 +986,14 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
2099 .opt_clks = gpio5_opt_clks, 986 .opt_clks = gpio5_opt_clks,
2100 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 987 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2101 .dev_attr = &gpio_dev_attr, 988 .dev_attr = &gpio_dev_attr,
2102 .slaves = omap44xx_gpio5_slaves,
2103 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
2104}; 989};
2105 990
2106/* gpio6 */ 991/* gpio6 */
2107static struct omap_hwmod omap44xx_gpio6_hwmod;
2108static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { 992static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2109 { .irq = 34 + OMAP44XX_IRQ_GIC_START }, 993 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2110 { .irq = -1 } 994 { .irq = -1 }
2111}; 995};
2112 996
2113static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2114 {
2115 .pa_start = 0x4805d000,
2116 .pa_end = 0x4805d1ff,
2117 .flags = ADDR_TYPE_RT
2118 },
2119 { }
2120};
2121
2122/* l4_per -> gpio6 */
2123static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2124 .master = &omap44xx_l4_per_hwmod,
2125 .slave = &omap44xx_gpio6_hwmod,
2126 .clk = "l4_div_ck",
2127 .addr = omap44xx_gpio6_addrs,
2128 .user = OCP_USER_MPU | OCP_USER_SDMA,
2129};
2130
2131/* gpio6 slave ports */
2132static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2133 &omap44xx_l4_per__gpio6,
2134};
2135
2136static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 997static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2137 { .role = "dbclk", .clk = "gpio6_dbclk" }, 998 { .role = "dbclk", .clk = "gpio6_dbclk" },
2138}; 999};
@@ -2154,8 +1015,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
2154 .opt_clks = gpio6_opt_clks, 1015 .opt_clks = gpio6_opt_clks,
2155 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 1016 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2156 .dev_attr = &gpio_dev_attr, 1017 .dev_attr = &gpio_dev_attr,
2157 .slaves = omap44xx_gpio6_slaves,
2158 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
2159}; 1018};
2160 1019
2161/* 1020/*
@@ -2190,34 +1049,6 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2190 { .irq = -1 } 1049 { .irq = -1 }
2191}; 1050};
2192 1051
2193/* hsi master ports */
2194static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2195 &omap44xx_hsi__l3_main_2,
2196};
2197
2198static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2199 {
2200 .pa_start = 0x4a058000,
2201 .pa_end = 0x4a05bfff,
2202 .flags = ADDR_TYPE_RT
2203 },
2204 { }
2205};
2206
2207/* l4_cfg -> hsi */
2208static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2209 .master = &omap44xx_l4_cfg_hwmod,
2210 .slave = &omap44xx_hsi_hwmod,
2211 .clk = "l4_div_ck",
2212 .addr = omap44xx_hsi_addrs,
2213 .user = OCP_USER_MPU | OCP_USER_SDMA,
2214};
2215
2216/* hsi slave ports */
2217static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2218 &omap44xx_l4_cfg__hsi,
2219};
2220
2221static struct omap_hwmod omap44xx_hsi_hwmod = { 1052static struct omap_hwmod omap44xx_hsi_hwmod = {
2222 .name = "hsi", 1053 .name = "hsi",
2223 .class = &omap44xx_hsi_hwmod_class, 1054 .class = &omap44xx_hsi_hwmod_class,
@@ -2231,10 +1062,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
2231 .modulemode = MODULEMODE_HWCTRL, 1062 .modulemode = MODULEMODE_HWCTRL,
2232 }, 1063 },
2233 }, 1064 },
2234 .slaves = omap44xx_hsi_slaves,
2235 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2236 .masters = omap44xx_hsi_masters,
2237 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2238}; 1065};
2239 1066
2240/* 1067/*
@@ -2266,7 +1093,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
2266}; 1093};
2267 1094
2268/* i2c1 */ 1095/* i2c1 */
2269static struct omap_hwmod omap44xx_i2c1_hwmod;
2270static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { 1096static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2271 { .irq = 56 + OMAP44XX_IRQ_GIC_START }, 1097 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2272 { .irq = -1 } 1098 { .irq = -1 }
@@ -2278,29 +1104,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2278 { .dma_req = -1 } 1104 { .dma_req = -1 }
2279}; 1105};
2280 1106
2281static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2282 {
2283 .pa_start = 0x48070000,
2284 .pa_end = 0x480700ff,
2285 .flags = ADDR_TYPE_RT
2286 },
2287 { }
2288};
2289
2290/* l4_per -> i2c1 */
2291static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2292 .master = &omap44xx_l4_per_hwmod,
2293 .slave = &omap44xx_i2c1_hwmod,
2294 .clk = "l4_div_ck",
2295 .addr = omap44xx_i2c1_addrs,
2296 .user = OCP_USER_MPU | OCP_USER_SDMA,
2297};
2298
2299/* i2c1 slave ports */
2300static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2301 &omap44xx_l4_per__i2c1,
2302};
2303
2304static struct omap_hwmod omap44xx_i2c1_hwmod = { 1107static struct omap_hwmod omap44xx_i2c1_hwmod = {
2305 .name = "i2c1", 1108 .name = "i2c1",
2306 .class = &omap44xx_i2c_hwmod_class, 1109 .class = &omap44xx_i2c_hwmod_class,
@@ -2316,13 +1119,10 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
2316 .modulemode = MODULEMODE_SWCTRL, 1119 .modulemode = MODULEMODE_SWCTRL,
2317 }, 1120 },
2318 }, 1121 },
2319 .slaves = omap44xx_i2c1_slaves,
2320 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
2321 .dev_attr = &i2c_dev_attr, 1122 .dev_attr = &i2c_dev_attr,
2322}; 1123};
2323 1124
2324/* i2c2 */ 1125/* i2c2 */
2325static struct omap_hwmod omap44xx_i2c2_hwmod;
2326static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { 1126static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2327 { .irq = 57 + OMAP44XX_IRQ_GIC_START }, 1127 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2328 { .irq = -1 } 1128 { .irq = -1 }
@@ -2334,29 +1134,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2334 { .dma_req = -1 } 1134 { .dma_req = -1 }
2335}; 1135};
2336 1136
2337static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2338 {
2339 .pa_start = 0x48072000,
2340 .pa_end = 0x480720ff,
2341 .flags = ADDR_TYPE_RT
2342 },
2343 { }
2344};
2345
2346/* l4_per -> i2c2 */
2347static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2348 .master = &omap44xx_l4_per_hwmod,
2349 .slave = &omap44xx_i2c2_hwmod,
2350 .clk = "l4_div_ck",
2351 .addr = omap44xx_i2c2_addrs,
2352 .user = OCP_USER_MPU | OCP_USER_SDMA,
2353};
2354
2355/* i2c2 slave ports */
2356static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2357 &omap44xx_l4_per__i2c2,
2358};
2359
2360static struct omap_hwmod omap44xx_i2c2_hwmod = { 1137static struct omap_hwmod omap44xx_i2c2_hwmod = {
2361 .name = "i2c2", 1138 .name = "i2c2",
2362 .class = &omap44xx_i2c_hwmod_class, 1139 .class = &omap44xx_i2c_hwmod_class,
@@ -2372,13 +1149,10 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
2372 .modulemode = MODULEMODE_SWCTRL, 1149 .modulemode = MODULEMODE_SWCTRL,
2373 }, 1150 },
2374 }, 1151 },
2375 .slaves = omap44xx_i2c2_slaves,
2376 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
2377 .dev_attr = &i2c_dev_attr, 1152 .dev_attr = &i2c_dev_attr,
2378}; 1153};
2379 1154
2380/* i2c3 */ 1155/* i2c3 */
2381static struct omap_hwmod omap44xx_i2c3_hwmod;
2382static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { 1156static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2383 { .irq = 61 + OMAP44XX_IRQ_GIC_START }, 1157 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2384 { .irq = -1 } 1158 { .irq = -1 }
@@ -2390,29 +1164,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2390 { .dma_req = -1 } 1164 { .dma_req = -1 }
2391}; 1165};
2392 1166
2393static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2394 {
2395 .pa_start = 0x48060000,
2396 .pa_end = 0x480600ff,
2397 .flags = ADDR_TYPE_RT
2398 },
2399 { }
2400};
2401
2402/* l4_per -> i2c3 */
2403static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2404 .master = &omap44xx_l4_per_hwmod,
2405 .slave = &omap44xx_i2c3_hwmod,
2406 .clk = "l4_div_ck",
2407 .addr = omap44xx_i2c3_addrs,
2408 .user = OCP_USER_MPU | OCP_USER_SDMA,
2409};
2410
2411/* i2c3 slave ports */
2412static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2413 &omap44xx_l4_per__i2c3,
2414};
2415
2416static struct omap_hwmod omap44xx_i2c3_hwmod = { 1167static struct omap_hwmod omap44xx_i2c3_hwmod = {
2417 .name = "i2c3", 1168 .name = "i2c3",
2418 .class = &omap44xx_i2c_hwmod_class, 1169 .class = &omap44xx_i2c_hwmod_class,
@@ -2428,13 +1179,10 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
2428 .modulemode = MODULEMODE_SWCTRL, 1179 .modulemode = MODULEMODE_SWCTRL,
2429 }, 1180 },
2430 }, 1181 },
2431 .slaves = omap44xx_i2c3_slaves,
2432 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
2433 .dev_attr = &i2c_dev_attr, 1182 .dev_attr = &i2c_dev_attr,
2434}; 1183};
2435 1184
2436/* i2c4 */ 1185/* i2c4 */
2437static struct omap_hwmod omap44xx_i2c4_hwmod;
2438static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { 1186static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2439 { .irq = 62 + OMAP44XX_IRQ_GIC_START }, 1187 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2440 { .irq = -1 } 1188 { .irq = -1 }
@@ -2446,29 +1194,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2446 { .dma_req = -1 } 1194 { .dma_req = -1 }
2447}; 1195};
2448 1196
2449static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2450 {
2451 .pa_start = 0x48350000,
2452 .pa_end = 0x483500ff,
2453 .flags = ADDR_TYPE_RT
2454 },
2455 { }
2456};
2457
2458/* l4_per -> i2c4 */
2459static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2460 .master = &omap44xx_l4_per_hwmod,
2461 .slave = &omap44xx_i2c4_hwmod,
2462 .clk = "l4_div_ck",
2463 .addr = omap44xx_i2c4_addrs,
2464 .user = OCP_USER_MPU | OCP_USER_SDMA,
2465};
2466
2467/* i2c4 slave ports */
2468static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2469 &omap44xx_l4_per__i2c4,
2470};
2471
2472static struct omap_hwmod omap44xx_i2c4_hwmod = { 1197static struct omap_hwmod omap44xx_i2c4_hwmod = {
2473 .name = "i2c4", 1198 .name = "i2c4",
2474 .class = &omap44xx_i2c_hwmod_class, 1199 .class = &omap44xx_i2c_hwmod_class,
@@ -2484,8 +1209,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
2484 .modulemode = MODULEMODE_SWCTRL, 1209 .modulemode = MODULEMODE_SWCTRL,
2485 }, 1210 },
2486 }, 1211 },
2487 .slaves = omap44xx_i2c4_slaves,
2488 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
2489 .dev_attr = &i2c_dev_attr, 1212 .dev_attr = &i2c_dev_attr,
2490}; 1213};
2491 1214
@@ -2504,66 +1227,12 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2504 { .irq = -1 } 1227 { .irq = -1 }
2505}; 1228};
2506 1229
2507static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { 1230static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2508 { .name = "cpu0", .rst_shift = 0 }, 1231 { .name = "cpu0", .rst_shift = 0 },
2509};
2510
2511static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2512 { .name = "cpu1", .rst_shift = 1 }, 1232 { .name = "cpu1", .rst_shift = 1 },
2513};
2514
2515static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2516 { .name = "mmu_cache", .rst_shift = 2 }, 1233 { .name = "mmu_cache", .rst_shift = 2 },
2517}; 1234};
2518 1235
2519/* ipu master ports */
2520static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2521 &omap44xx_ipu__l3_main_2,
2522};
2523
2524/* l3_main_2 -> ipu */
2525static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2526 .master = &omap44xx_l3_main_2_hwmod,
2527 .slave = &omap44xx_ipu_hwmod,
2528 .clk = "l3_div_ck",
2529 .user = OCP_USER_MPU | OCP_USER_SDMA,
2530};
2531
2532/* ipu slave ports */
2533static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2534 &omap44xx_l3_main_2__ipu,
2535};
2536
2537/* Pseudo hwmod for reset control purpose only */
2538static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2539 .name = "ipu_c0",
2540 .class = &omap44xx_ipu_hwmod_class,
2541 .clkdm_name = "ducati_clkdm",
2542 .flags = HWMOD_INIT_NO_RESET,
2543 .rst_lines = omap44xx_ipu_c0_resets,
2544 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2545 .prcm = {
2546 .omap4 = {
2547 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2548 },
2549 },
2550};
2551
2552/* Pseudo hwmod for reset control purpose only */
2553static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2554 .name = "ipu_c1",
2555 .class = &omap44xx_ipu_hwmod_class,
2556 .clkdm_name = "ducati_clkdm",
2557 .flags = HWMOD_INIT_NO_RESET,
2558 .rst_lines = omap44xx_ipu_c1_resets,
2559 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2560 .prcm = {
2561 .omap4 = {
2562 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2563 },
2564 },
2565};
2566
2567static struct omap_hwmod omap44xx_ipu_hwmod = { 1236static struct omap_hwmod omap44xx_ipu_hwmod = {
2568 .name = "ipu", 1237 .name = "ipu",
2569 .class = &omap44xx_ipu_hwmod_class, 1238 .class = &omap44xx_ipu_hwmod_class,
@@ -2580,10 +1249,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
2580 .modulemode = MODULEMODE_HWCTRL, 1249 .modulemode = MODULEMODE_HWCTRL,
2581 }, 1250 },
2582 }, 1251 },
2583 .slaves = omap44xx_ipu_slaves,
2584 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2585 .masters = omap44xx_ipu_masters,
2586 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2587}; 1252};
2588 1253
2589/* 1254/*
@@ -2630,34 +1295,6 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2630 { .dma_req = -1 } 1295 { .dma_req = -1 }
2631}; 1296};
2632 1297
2633/* iss master ports */
2634static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2635 &omap44xx_iss__l3_main_2,
2636};
2637
2638static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2639 {
2640 .pa_start = 0x52000000,
2641 .pa_end = 0x520000ff,
2642 .flags = ADDR_TYPE_RT
2643 },
2644 { }
2645};
2646
2647/* l3_main_2 -> iss */
2648static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2649 .master = &omap44xx_l3_main_2_hwmod,
2650 .slave = &omap44xx_iss_hwmod,
2651 .clk = "l3_div_ck",
2652 .addr = omap44xx_iss_addrs,
2653 .user = OCP_USER_MPU | OCP_USER_SDMA,
2654};
2655
2656/* iss slave ports */
2657static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2658 &omap44xx_l3_main_2__iss,
2659};
2660
2661static struct omap_hwmod_opt_clk iss_opt_clks[] = { 1298static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2662 { .role = "ctrlclk", .clk = "iss_ctrlclk" }, 1299 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2663}; 1300};
@@ -2678,10 +1315,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
2678 }, 1315 },
2679 .opt_clks = iss_opt_clks, 1316 .opt_clks = iss_opt_clks,
2680 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), 1317 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2681 .slaves = omap44xx_iss_slaves,
2682 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2683 .masters = omap44xx_iss_masters,
2684 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2685}; 1318};
2686 1319
2687/* 1320/*
@@ -2702,75 +1335,9 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2702}; 1335};
2703 1336
2704static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { 1337static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2705 { .name = "logic", .rst_shift = 2 },
2706};
2707
2708static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2709 { .name = "seq0", .rst_shift = 0 }, 1338 { .name = "seq0", .rst_shift = 0 },
2710};
2711
2712static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2713 { .name = "seq1", .rst_shift = 1 }, 1339 { .name = "seq1", .rst_shift = 1 },
2714}; 1340 { .name = "logic", .rst_shift = 2 },
2715
2716/* iva master ports */
2717static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2718 &omap44xx_iva__l3_main_2,
2719 &omap44xx_iva__l3_instr,
2720};
2721
2722static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2723 {
2724 .pa_start = 0x5a000000,
2725 .pa_end = 0x5a07ffff,
2726 .flags = ADDR_TYPE_RT
2727 },
2728 { }
2729};
2730
2731/* l3_main_2 -> iva */
2732static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2733 .master = &omap44xx_l3_main_2_hwmod,
2734 .slave = &omap44xx_iva_hwmod,
2735 .clk = "l3_div_ck",
2736 .addr = omap44xx_iva_addrs,
2737 .user = OCP_USER_MPU,
2738};
2739
2740/* iva slave ports */
2741static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2742 &omap44xx_dsp__iva,
2743 &omap44xx_l3_main_2__iva,
2744};
2745
2746/* Pseudo hwmod for reset control purpose only */
2747static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2748 .name = "iva_seq0",
2749 .class = &omap44xx_iva_hwmod_class,
2750 .clkdm_name = "ivahd_clkdm",
2751 .flags = HWMOD_INIT_NO_RESET,
2752 .rst_lines = omap44xx_iva_seq0_resets,
2753 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2754 .prcm = {
2755 .omap4 = {
2756 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2757 },
2758 },
2759};
2760
2761/* Pseudo hwmod for reset control purpose only */
2762static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2763 .name = "iva_seq1",
2764 .class = &omap44xx_iva_hwmod_class,
2765 .clkdm_name = "ivahd_clkdm",
2766 .flags = HWMOD_INIT_NO_RESET,
2767 .rst_lines = omap44xx_iva_seq1_resets,
2768 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2769 .prcm = {
2770 .omap4 = {
2771 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2772 },
2773 },
2774}; 1341};
2775 1342
2776static struct omap_hwmod omap44xx_iva_hwmod = { 1343static struct omap_hwmod omap44xx_iva_hwmod = {
@@ -2789,10 +1356,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
2789 .modulemode = MODULEMODE_HWCTRL, 1356 .modulemode = MODULEMODE_HWCTRL,
2790 }, 1357 },
2791 }, 1358 },
2792 .slaves = omap44xx_iva_slaves,
2793 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2794 .masters = omap44xx_iva_masters,
2795 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2796}; 1359};
2797 1360
2798/* 1361/*
@@ -2818,35 +1381,11 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2818}; 1381};
2819 1382
2820/* kbd */ 1383/* kbd */
2821static struct omap_hwmod omap44xx_kbd_hwmod;
2822static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { 1384static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2823 { .irq = 120 + OMAP44XX_IRQ_GIC_START }, 1385 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2824 { .irq = -1 } 1386 { .irq = -1 }
2825}; 1387};
2826 1388
2827static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2828 {
2829 .pa_start = 0x4a31c000,
2830 .pa_end = 0x4a31c07f,
2831 .flags = ADDR_TYPE_RT
2832 },
2833 { }
2834};
2835
2836/* l4_wkup -> kbd */
2837static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2838 .master = &omap44xx_l4_wkup_hwmod,
2839 .slave = &omap44xx_kbd_hwmod,
2840 .clk = "l4_wkup_clk_mux_ck",
2841 .addr = omap44xx_kbd_addrs,
2842 .user = OCP_USER_MPU | OCP_USER_SDMA,
2843};
2844
2845/* kbd slave ports */
2846static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2847 &omap44xx_l4_wkup__kbd,
2848};
2849
2850static struct omap_hwmod omap44xx_kbd_hwmod = { 1389static struct omap_hwmod omap44xx_kbd_hwmod = {
2851 .name = "kbd", 1390 .name = "kbd",
2852 .class = &omap44xx_kbd_hwmod_class, 1391 .class = &omap44xx_kbd_hwmod_class,
@@ -2860,8 +1399,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
2860 .modulemode = MODULEMODE_SWCTRL, 1399 .modulemode = MODULEMODE_SWCTRL,
2861 }, 1400 },
2862 }, 1401 },
2863 .slaves = omap44xx_kbd_slaves,
2864 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2865}; 1402};
2866 1403
2867/* 1404/*
@@ -2885,35 +1422,11 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2885}; 1422};
2886 1423
2887/* mailbox */ 1424/* mailbox */
2888static struct omap_hwmod omap44xx_mailbox_hwmod;
2889static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { 1425static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2890 { .irq = 26 + OMAP44XX_IRQ_GIC_START }, 1426 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2891 { .irq = -1 } 1427 { .irq = -1 }
2892}; 1428};
2893 1429
2894static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2895 {
2896 .pa_start = 0x4a0f4000,
2897 .pa_end = 0x4a0f41ff,
2898 .flags = ADDR_TYPE_RT
2899 },
2900 { }
2901};
2902
2903/* l4_cfg -> mailbox */
2904static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2905 .master = &omap44xx_l4_cfg_hwmod,
2906 .slave = &omap44xx_mailbox_hwmod,
2907 .clk = "l4_div_ck",
2908 .addr = omap44xx_mailbox_addrs,
2909 .user = OCP_USER_MPU | OCP_USER_SDMA,
2910};
2911
2912/* mailbox slave ports */
2913static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2914 &omap44xx_l4_cfg__mailbox,
2915};
2916
2917static struct omap_hwmod omap44xx_mailbox_hwmod = { 1430static struct omap_hwmod omap44xx_mailbox_hwmod = {
2918 .name = "mailbox", 1431 .name = "mailbox",
2919 .class = &omap44xx_mailbox_hwmod_class, 1432 .class = &omap44xx_mailbox_hwmod_class,
@@ -2925,8 +1438,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
2925 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, 1438 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2926 }, 1439 },
2927 }, 1440 },
2928 .slaves = omap44xx_mailbox_slaves,
2929 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2930}; 1441};
2931 1442
2932/* 1443/*
@@ -2949,7 +1460,6 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2949}; 1460};
2950 1461
2951/* mcbsp1 */ 1462/* mcbsp1 */
2952static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2953static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { 1463static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2954 { .irq = 17 + OMAP44XX_IRQ_GIC_START }, 1464 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2955 { .irq = -1 } 1465 { .irq = -1 }
@@ -2961,50 +1471,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2961 { .dma_req = -1 } 1471 { .dma_req = -1 }
2962}; 1472};
2963 1473
2964static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2965 {
2966 .name = "mpu",
2967 .pa_start = 0x40122000,
2968 .pa_end = 0x401220ff,
2969 .flags = ADDR_TYPE_RT
2970 },
2971 { }
2972};
2973
2974/* l4_abe -> mcbsp1 */
2975static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2976 .master = &omap44xx_l4_abe_hwmod,
2977 .slave = &omap44xx_mcbsp1_hwmod,
2978 .clk = "ocp_abe_iclk",
2979 .addr = omap44xx_mcbsp1_addrs,
2980 .user = OCP_USER_MPU,
2981};
2982
2983static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2984 {
2985 .name = "dma",
2986 .pa_start = 0x49022000,
2987 .pa_end = 0x490220ff,
2988 .flags = ADDR_TYPE_RT
2989 },
2990 { }
2991};
2992
2993/* l4_abe -> mcbsp1 (dma) */
2994static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2995 .master = &omap44xx_l4_abe_hwmod,
2996 .slave = &omap44xx_mcbsp1_hwmod,
2997 .clk = "ocp_abe_iclk",
2998 .addr = omap44xx_mcbsp1_dma_addrs,
2999 .user = OCP_USER_SDMA,
3000};
3001
3002/* mcbsp1 slave ports */
3003static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
3004 &omap44xx_l4_abe__mcbsp1,
3005 &omap44xx_l4_abe__mcbsp1_dma,
3006};
3007
3008static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { 1474static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
3009 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1475 { .role = "pad_fck", .clk = "pad_clks_ck" },
3010 { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" }, 1476 { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
@@ -3024,14 +1490,11 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
3024 .modulemode = MODULEMODE_SWCTRL, 1490 .modulemode = MODULEMODE_SWCTRL,
3025 }, 1491 },
3026 }, 1492 },
3027 .slaves = omap44xx_mcbsp1_slaves,
3028 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3029 .opt_clks = mcbsp1_opt_clks, 1493 .opt_clks = mcbsp1_opt_clks,
3030 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), 1494 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
3031}; 1495};
3032 1496
3033/* mcbsp2 */ 1497/* mcbsp2 */
3034static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3035static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { 1498static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3036 { .irq = 22 + OMAP44XX_IRQ_GIC_START }, 1499 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3037 { .irq = -1 } 1500 { .irq = -1 }
@@ -3043,50 +1506,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3043 { .dma_req = -1 } 1506 { .dma_req = -1 }
3044}; 1507};
3045 1508
3046static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3047 {
3048 .name = "mpu",
3049 .pa_start = 0x40124000,
3050 .pa_end = 0x401240ff,
3051 .flags = ADDR_TYPE_RT
3052 },
3053 { }
3054};
3055
3056/* l4_abe -> mcbsp2 */
3057static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3058 .master = &omap44xx_l4_abe_hwmod,
3059 .slave = &omap44xx_mcbsp2_hwmod,
3060 .clk = "ocp_abe_iclk",
3061 .addr = omap44xx_mcbsp2_addrs,
3062 .user = OCP_USER_MPU,
3063};
3064
3065static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3066 {
3067 .name = "dma",
3068 .pa_start = 0x49024000,
3069 .pa_end = 0x490240ff,
3070 .flags = ADDR_TYPE_RT
3071 },
3072 { }
3073};
3074
3075/* l4_abe -> mcbsp2 (dma) */
3076static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3077 .master = &omap44xx_l4_abe_hwmod,
3078 .slave = &omap44xx_mcbsp2_hwmod,
3079 .clk = "ocp_abe_iclk",
3080 .addr = omap44xx_mcbsp2_dma_addrs,
3081 .user = OCP_USER_SDMA,
3082};
3083
3084/* mcbsp2 slave ports */
3085static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3086 &omap44xx_l4_abe__mcbsp2,
3087 &omap44xx_l4_abe__mcbsp2_dma,
3088};
3089
3090static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { 1509static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
3091 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1510 { .role = "pad_fck", .clk = "pad_clks_ck" },
3092 { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, 1511 { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
@@ -3106,14 +1525,11 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3106 .modulemode = MODULEMODE_SWCTRL, 1525 .modulemode = MODULEMODE_SWCTRL,
3107 }, 1526 },
3108 }, 1527 },
3109 .slaves = omap44xx_mcbsp2_slaves,
3110 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3111 .opt_clks = mcbsp2_opt_clks, 1528 .opt_clks = mcbsp2_opt_clks,
3112 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), 1529 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
3113}; 1530};
3114 1531
3115/* mcbsp3 */ 1532/* mcbsp3 */
3116static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3117static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { 1533static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3118 { .irq = 23 + OMAP44XX_IRQ_GIC_START }, 1534 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3119 { .irq = -1 } 1535 { .irq = -1 }
@@ -3125,50 +1541,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3125 { .dma_req = -1 } 1541 { .dma_req = -1 }
3126}; 1542};
3127 1543
3128static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3129 {
3130 .name = "mpu",
3131 .pa_start = 0x40126000,
3132 .pa_end = 0x401260ff,
3133 .flags = ADDR_TYPE_RT
3134 },
3135 { }
3136};
3137
3138/* l4_abe -> mcbsp3 */
3139static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3140 .master = &omap44xx_l4_abe_hwmod,
3141 .slave = &omap44xx_mcbsp3_hwmod,
3142 .clk = "ocp_abe_iclk",
3143 .addr = omap44xx_mcbsp3_addrs,
3144 .user = OCP_USER_MPU,
3145};
3146
3147static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3148 {
3149 .name = "dma",
3150 .pa_start = 0x49026000,
3151 .pa_end = 0x490260ff,
3152 .flags = ADDR_TYPE_RT
3153 },
3154 { }
3155};
3156
3157/* l4_abe -> mcbsp3 (dma) */
3158static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3159 .master = &omap44xx_l4_abe_hwmod,
3160 .slave = &omap44xx_mcbsp3_hwmod,
3161 .clk = "ocp_abe_iclk",
3162 .addr = omap44xx_mcbsp3_dma_addrs,
3163 .user = OCP_USER_SDMA,
3164};
3165
3166/* mcbsp3 slave ports */
3167static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3168 &omap44xx_l4_abe__mcbsp3,
3169 &omap44xx_l4_abe__mcbsp3_dma,
3170};
3171
3172static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { 1544static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
3173 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1545 { .role = "pad_fck", .clk = "pad_clks_ck" },
3174 { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, 1546 { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
@@ -3188,14 +1560,11 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3188 .modulemode = MODULEMODE_SWCTRL, 1560 .modulemode = MODULEMODE_SWCTRL,
3189 }, 1561 },
3190 }, 1562 },
3191 .slaves = omap44xx_mcbsp3_slaves,
3192 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3193 .opt_clks = mcbsp3_opt_clks, 1563 .opt_clks = mcbsp3_opt_clks,
3194 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), 1564 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
3195}; 1565};
3196 1566
3197/* mcbsp4 */ 1567/* mcbsp4 */
3198static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3199static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { 1568static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3200 { .irq = 16 + OMAP44XX_IRQ_GIC_START }, 1569 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3201 { .irq = -1 } 1570 { .irq = -1 }
@@ -3207,29 +1576,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3207 { .dma_req = -1 } 1576 { .dma_req = -1 }
3208}; 1577};
3209 1578
3210static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3211 {
3212 .pa_start = 0x48096000,
3213 .pa_end = 0x480960ff,
3214 .flags = ADDR_TYPE_RT
3215 },
3216 { }
3217};
3218
3219/* l4_per -> mcbsp4 */
3220static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3221 .master = &omap44xx_l4_per_hwmod,
3222 .slave = &omap44xx_mcbsp4_hwmod,
3223 .clk = "l4_div_ck",
3224 .addr = omap44xx_mcbsp4_addrs,
3225 .user = OCP_USER_MPU | OCP_USER_SDMA,
3226};
3227
3228/* mcbsp4 slave ports */
3229static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3230 &omap44xx_l4_per__mcbsp4,
3231};
3232
3233static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { 1579static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
3234 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1580 { .role = "pad_fck", .clk = "pad_clks_ck" },
3235 { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, 1581 { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
@@ -3249,8 +1595,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3249 .modulemode = MODULEMODE_SWCTRL, 1595 .modulemode = MODULEMODE_SWCTRL,
3250 }, 1596 },
3251 }, 1597 },
3252 .slaves = omap44xx_mcbsp4_slaves,
3253 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3254 .opt_clks = mcbsp4_opt_clks, 1598 .opt_clks = mcbsp4_opt_clks,
3255 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), 1599 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
3256}; 1600};
@@ -3277,7 +1621,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3277}; 1621};
3278 1622
3279/* mcpdm */ 1623/* mcpdm */
3280static struct omap_hwmod omap44xx_mcpdm_hwmod;
3281static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { 1624static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3282 { .irq = 112 + OMAP44XX_IRQ_GIC_START }, 1625 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3283 { .irq = -1 } 1626 { .irq = -1 }
@@ -3289,48 +1632,6 @@ static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3289 { .dma_req = -1 } 1632 { .dma_req = -1 }
3290}; 1633};
3291 1634
3292static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3293 {
3294 .pa_start = 0x40132000,
3295 .pa_end = 0x4013207f,
3296 .flags = ADDR_TYPE_RT
3297 },
3298 { }
3299};
3300
3301/* l4_abe -> mcpdm */
3302static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3303 .master = &omap44xx_l4_abe_hwmod,
3304 .slave = &omap44xx_mcpdm_hwmod,
3305 .clk = "ocp_abe_iclk",
3306 .addr = omap44xx_mcpdm_addrs,
3307 .user = OCP_USER_MPU,
3308};
3309
3310static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3311 {
3312 .pa_start = 0x49032000,
3313 .pa_end = 0x4903207f,
3314 .flags = ADDR_TYPE_RT
3315 },
3316 { }
3317};
3318
3319/* l4_abe -> mcpdm (dma) */
3320static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3321 .master = &omap44xx_l4_abe_hwmod,
3322 .slave = &omap44xx_mcpdm_hwmod,
3323 .clk = "ocp_abe_iclk",
3324 .addr = omap44xx_mcpdm_dma_addrs,
3325 .user = OCP_USER_SDMA,
3326};
3327
3328/* mcpdm slave ports */
3329static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3330 &omap44xx_l4_abe__mcpdm,
3331 &omap44xx_l4_abe__mcpdm_dma,
3332};
3333
3334static struct omap_hwmod omap44xx_mcpdm_hwmod = { 1635static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3335 .name = "mcpdm", 1636 .name = "mcpdm",
3336 .class = &omap44xx_mcpdm_hwmod_class, 1637 .class = &omap44xx_mcpdm_hwmod_class,
@@ -3345,8 +1646,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3345 .modulemode = MODULEMODE_SWCTRL, 1646 .modulemode = MODULEMODE_SWCTRL,
3346 }, 1647 },
3347 }, 1648 },
3348 .slaves = omap44xx_mcpdm_slaves,
3349 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3350}; 1649};
3351 1650
3352/* 1651/*
@@ -3372,7 +1671,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3372}; 1671};
3373 1672
3374/* mcspi1 */ 1673/* mcspi1 */
3375static struct omap_hwmod omap44xx_mcspi1_hwmod;
3376static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { 1674static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3377 { .irq = 65 + OMAP44XX_IRQ_GIC_START }, 1675 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3378 { .irq = -1 } 1676 { .irq = -1 }
@@ -3390,29 +1688,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3390 { .dma_req = -1 } 1688 { .dma_req = -1 }
3391}; 1689};
3392 1690
3393static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3394 {
3395 .pa_start = 0x48098000,
3396 .pa_end = 0x480981ff,
3397 .flags = ADDR_TYPE_RT
3398 },
3399 { }
3400};
3401
3402/* l4_per -> mcspi1 */
3403static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3404 .master = &omap44xx_l4_per_hwmod,
3405 .slave = &omap44xx_mcspi1_hwmod,
3406 .clk = "l4_div_ck",
3407 .addr = omap44xx_mcspi1_addrs,
3408 .user = OCP_USER_MPU | OCP_USER_SDMA,
3409};
3410
3411/* mcspi1 slave ports */
3412static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3413 &omap44xx_l4_per__mcspi1,
3414};
3415
3416/* mcspi1 dev_attr */ 1691/* mcspi1 dev_attr */
3417static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { 1692static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3418 .num_chipselect = 4, 1693 .num_chipselect = 4,
@@ -3433,12 +1708,9 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3433 }, 1708 },
3434 }, 1709 },
3435 .dev_attr = &mcspi1_dev_attr, 1710 .dev_attr = &mcspi1_dev_attr,
3436 .slaves = omap44xx_mcspi1_slaves,
3437 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3438}; 1711};
3439 1712
3440/* mcspi2 */ 1713/* mcspi2 */
3441static struct omap_hwmod omap44xx_mcspi2_hwmod;
3442static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { 1714static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3443 { .irq = 66 + OMAP44XX_IRQ_GIC_START }, 1715 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3444 { .irq = -1 } 1716 { .irq = -1 }
@@ -3452,29 +1724,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3452 { .dma_req = -1 } 1724 { .dma_req = -1 }
3453}; 1725};
3454 1726
3455static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3456 {
3457 .pa_start = 0x4809a000,
3458 .pa_end = 0x4809a1ff,
3459 .flags = ADDR_TYPE_RT
3460 },
3461 { }
3462};
3463
3464/* l4_per -> mcspi2 */
3465static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3466 .master = &omap44xx_l4_per_hwmod,
3467 .slave = &omap44xx_mcspi2_hwmod,
3468 .clk = "l4_div_ck",
3469 .addr = omap44xx_mcspi2_addrs,
3470 .user = OCP_USER_MPU | OCP_USER_SDMA,
3471};
3472
3473/* mcspi2 slave ports */
3474static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3475 &omap44xx_l4_per__mcspi2,
3476};
3477
3478/* mcspi2 dev_attr */ 1727/* mcspi2 dev_attr */
3479static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { 1728static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3480 .num_chipselect = 2, 1729 .num_chipselect = 2,
@@ -3495,12 +1744,9 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3495 }, 1744 },
3496 }, 1745 },
3497 .dev_attr = &mcspi2_dev_attr, 1746 .dev_attr = &mcspi2_dev_attr,
3498 .slaves = omap44xx_mcspi2_slaves,
3499 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3500}; 1747};
3501 1748
3502/* mcspi3 */ 1749/* mcspi3 */
3503static struct omap_hwmod omap44xx_mcspi3_hwmod;
3504static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { 1750static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3505 { .irq = 91 + OMAP44XX_IRQ_GIC_START }, 1751 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3506 { .irq = -1 } 1752 { .irq = -1 }
@@ -3514,29 +1760,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3514 { .dma_req = -1 } 1760 { .dma_req = -1 }
3515}; 1761};
3516 1762
3517static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3518 {
3519 .pa_start = 0x480b8000,
3520 .pa_end = 0x480b81ff,
3521 .flags = ADDR_TYPE_RT
3522 },
3523 { }
3524};
3525
3526/* l4_per -> mcspi3 */
3527static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3528 .master = &omap44xx_l4_per_hwmod,
3529 .slave = &omap44xx_mcspi3_hwmod,
3530 .clk = "l4_div_ck",
3531 .addr = omap44xx_mcspi3_addrs,
3532 .user = OCP_USER_MPU | OCP_USER_SDMA,
3533};
3534
3535/* mcspi3 slave ports */
3536static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3537 &omap44xx_l4_per__mcspi3,
3538};
3539
3540/* mcspi3 dev_attr */ 1763/* mcspi3 dev_attr */
3541static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { 1764static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3542 .num_chipselect = 2, 1765 .num_chipselect = 2,
@@ -3557,12 +1780,9 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3557 }, 1780 },
3558 }, 1781 },
3559 .dev_attr = &mcspi3_dev_attr, 1782 .dev_attr = &mcspi3_dev_attr,
3560 .slaves = omap44xx_mcspi3_slaves,
3561 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3562}; 1783};
3563 1784
3564/* mcspi4 */ 1785/* mcspi4 */
3565static struct omap_hwmod omap44xx_mcspi4_hwmod;
3566static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { 1786static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3567 { .irq = 48 + OMAP44XX_IRQ_GIC_START }, 1787 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3568 { .irq = -1 } 1788 { .irq = -1 }
@@ -3574,29 +1794,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3574 { .dma_req = -1 } 1794 { .dma_req = -1 }
3575}; 1795};
3576 1796
3577static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3578 {
3579 .pa_start = 0x480ba000,
3580 .pa_end = 0x480ba1ff,
3581 .flags = ADDR_TYPE_RT
3582 },
3583 { }
3584};
3585
3586/* l4_per -> mcspi4 */
3587static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3588 .master = &omap44xx_l4_per_hwmod,
3589 .slave = &omap44xx_mcspi4_hwmod,
3590 .clk = "l4_div_ck",
3591 .addr = omap44xx_mcspi4_addrs,
3592 .user = OCP_USER_MPU | OCP_USER_SDMA,
3593};
3594
3595/* mcspi4 slave ports */
3596static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3597 &omap44xx_l4_per__mcspi4,
3598};
3599
3600/* mcspi4 dev_attr */ 1797/* mcspi4 dev_attr */
3601static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { 1798static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3602 .num_chipselect = 1, 1799 .num_chipselect = 1,
@@ -3617,8 +1814,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3617 }, 1814 },
3618 }, 1815 },
3619 .dev_attr = &mcspi4_dev_attr, 1816 .dev_attr = &mcspi4_dev_attr,
3620 .slaves = omap44xx_mcspi4_slaves,
3621 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3622}; 1817};
3623 1818
3624/* 1819/*
@@ -3655,34 +1850,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3655 { .dma_req = -1 } 1850 { .dma_req = -1 }
3656}; 1851};
3657 1852
3658/* mmc1 master ports */
3659static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3660 &omap44xx_mmc1__l3_main_1,
3661};
3662
3663static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3664 {
3665 .pa_start = 0x4809c000,
3666 .pa_end = 0x4809c3ff,
3667 .flags = ADDR_TYPE_RT
3668 },
3669 { }
3670};
3671
3672/* l4_per -> mmc1 */
3673static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3674 .master = &omap44xx_l4_per_hwmod,
3675 .slave = &omap44xx_mmc1_hwmod,
3676 .clk = "l4_div_ck",
3677 .addr = omap44xx_mmc1_addrs,
3678 .user = OCP_USER_MPU | OCP_USER_SDMA,
3679};
3680
3681/* mmc1 slave ports */
3682static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3683 &omap44xx_l4_per__mmc1,
3684};
3685
3686/* mmc1 dev_attr */ 1853/* mmc1 dev_attr */
3687static struct omap_mmc_dev_attr mmc1_dev_attr = { 1854static struct omap_mmc_dev_attr mmc1_dev_attr = {
3688 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1855 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
@@ -3703,10 +1870,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
3703 }, 1870 },
3704 }, 1871 },
3705 .dev_attr = &mmc1_dev_attr, 1872 .dev_attr = &mmc1_dev_attr,
3706 .slaves = omap44xx_mmc1_slaves,
3707 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3708 .masters = omap44xx_mmc1_masters,
3709 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3710}; 1873};
3711 1874
3712/* mmc2 */ 1875/* mmc2 */
@@ -3721,34 +1884,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3721 { .dma_req = -1 } 1884 { .dma_req = -1 }
3722}; 1885};
3723 1886
3724/* mmc2 master ports */
3725static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3726 &omap44xx_mmc2__l3_main_1,
3727};
3728
3729static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3730 {
3731 .pa_start = 0x480b4000,
3732 .pa_end = 0x480b43ff,
3733 .flags = ADDR_TYPE_RT
3734 },
3735 { }
3736};
3737
3738/* l4_per -> mmc2 */
3739static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3740 .master = &omap44xx_l4_per_hwmod,
3741 .slave = &omap44xx_mmc2_hwmod,
3742 .clk = "l4_div_ck",
3743 .addr = omap44xx_mmc2_addrs,
3744 .user = OCP_USER_MPU | OCP_USER_SDMA,
3745};
3746
3747/* mmc2 slave ports */
3748static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3749 &omap44xx_l4_per__mmc2,
3750};
3751
3752static struct omap_hwmod omap44xx_mmc2_hwmod = { 1887static struct omap_hwmod omap44xx_mmc2_hwmod = {
3753 .name = "mmc2", 1888 .name = "mmc2",
3754 .class = &omap44xx_mmc_hwmod_class, 1889 .class = &omap44xx_mmc_hwmod_class,
@@ -3763,14 +1898,9 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
3763 .modulemode = MODULEMODE_SWCTRL, 1898 .modulemode = MODULEMODE_SWCTRL,
3764 }, 1899 },
3765 }, 1900 },
3766 .slaves = omap44xx_mmc2_slaves,
3767 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3768 .masters = omap44xx_mmc2_masters,
3769 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3770}; 1901};
3771 1902
3772/* mmc3 */ 1903/* mmc3 */
3773static struct omap_hwmod omap44xx_mmc3_hwmod;
3774static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { 1904static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3775 { .irq = 94 + OMAP44XX_IRQ_GIC_START }, 1905 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3776 { .irq = -1 } 1906 { .irq = -1 }
@@ -3782,29 +1912,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3782 { .dma_req = -1 } 1912 { .dma_req = -1 }
3783}; 1913};
3784 1914
3785static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3786 {
3787 .pa_start = 0x480ad000,
3788 .pa_end = 0x480ad3ff,
3789 .flags = ADDR_TYPE_RT
3790 },
3791 { }
3792};
3793
3794/* l4_per -> mmc3 */
3795static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3796 .master = &omap44xx_l4_per_hwmod,
3797 .slave = &omap44xx_mmc3_hwmod,
3798 .clk = "l4_div_ck",
3799 .addr = omap44xx_mmc3_addrs,
3800 .user = OCP_USER_MPU | OCP_USER_SDMA,
3801};
3802
3803/* mmc3 slave ports */
3804static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3805 &omap44xx_l4_per__mmc3,
3806};
3807
3808static struct omap_hwmod omap44xx_mmc3_hwmod = { 1915static struct omap_hwmod omap44xx_mmc3_hwmod = {
3809 .name = "mmc3", 1916 .name = "mmc3",
3810 .class = &omap44xx_mmc_hwmod_class, 1917 .class = &omap44xx_mmc_hwmod_class,
@@ -3819,12 +1926,9 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
3819 .modulemode = MODULEMODE_SWCTRL, 1926 .modulemode = MODULEMODE_SWCTRL,
3820 }, 1927 },
3821 }, 1928 },
3822 .slaves = omap44xx_mmc3_slaves,
3823 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3824}; 1929};
3825 1930
3826/* mmc4 */ 1931/* mmc4 */
3827static struct omap_hwmod omap44xx_mmc4_hwmod;
3828static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { 1932static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3829 { .irq = 96 + OMAP44XX_IRQ_GIC_START }, 1933 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3830 { .irq = -1 } 1934 { .irq = -1 }
@@ -3836,35 +1940,11 @@ static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3836 { .dma_req = -1 } 1940 { .dma_req = -1 }
3837}; 1941};
3838 1942
3839static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3840 {
3841 .pa_start = 0x480d1000,
3842 .pa_end = 0x480d13ff,
3843 .flags = ADDR_TYPE_RT
3844 },
3845 { }
3846};
3847
3848/* l4_per -> mmc4 */
3849static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3850 .master = &omap44xx_l4_per_hwmod,
3851 .slave = &omap44xx_mmc4_hwmod,
3852 .clk = "l4_div_ck",
3853 .addr = omap44xx_mmc4_addrs,
3854 .user = OCP_USER_MPU | OCP_USER_SDMA,
3855};
3856
3857/* mmc4 slave ports */
3858static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3859 &omap44xx_l4_per__mmc4,
3860};
3861
3862static struct omap_hwmod omap44xx_mmc4_hwmod = { 1943static struct omap_hwmod omap44xx_mmc4_hwmod = {
3863 .name = "mmc4", 1944 .name = "mmc4",
3864 .class = &omap44xx_mmc_hwmod_class, 1945 .class = &omap44xx_mmc_hwmod_class,
3865 .clkdm_name = "l4_per_clkdm", 1946 .clkdm_name = "l4_per_clkdm",
3866 .mpu_irqs = omap44xx_mmc4_irqs, 1947 .mpu_irqs = omap44xx_mmc4_irqs,
3867
3868 .sdma_reqs = omap44xx_mmc4_sdma_reqs, 1948 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3869 .main_clk = "mmc4_fck", 1949 .main_clk = "mmc4_fck",
3870 .prcm = { 1950 .prcm = {
@@ -3874,12 +1954,9 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
3874 .modulemode = MODULEMODE_SWCTRL, 1954 .modulemode = MODULEMODE_SWCTRL,
3875 }, 1955 },
3876 }, 1956 },
3877 .slaves = omap44xx_mmc4_slaves,
3878 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3879}; 1957};
3880 1958
3881/* mmc5 */ 1959/* mmc5 */
3882static struct omap_hwmod omap44xx_mmc5_hwmod;
3883static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { 1960static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3884 { .irq = 59 + OMAP44XX_IRQ_GIC_START }, 1961 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3885 { .irq = -1 } 1962 { .irq = -1 }
@@ -3891,29 +1968,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3891 { .dma_req = -1 } 1968 { .dma_req = -1 }
3892}; 1969};
3893 1970
3894static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3895 {
3896 .pa_start = 0x480d5000,
3897 .pa_end = 0x480d53ff,
3898 .flags = ADDR_TYPE_RT
3899 },
3900 { }
3901};
3902
3903/* l4_per -> mmc5 */
3904static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3905 .master = &omap44xx_l4_per_hwmod,
3906 .slave = &omap44xx_mmc5_hwmod,
3907 .clk = "l4_div_ck",
3908 .addr = omap44xx_mmc5_addrs,
3909 .user = OCP_USER_MPU | OCP_USER_SDMA,
3910};
3911
3912/* mmc5 slave ports */
3913static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3914 &omap44xx_l4_per__mmc5,
3915};
3916
3917static struct omap_hwmod omap44xx_mmc5_hwmod = { 1971static struct omap_hwmod omap44xx_mmc5_hwmod = {
3918 .name = "mmc5", 1972 .name = "mmc5",
3919 .class = &omap44xx_mmc_hwmod_class, 1973 .class = &omap44xx_mmc_hwmod_class,
@@ -3928,8 +1982,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
3928 .modulemode = MODULEMODE_SWCTRL, 1982 .modulemode = MODULEMODE_SWCTRL,
3929 }, 1983 },
3930 }, 1984 },
3931 .slaves = omap44xx_mmc5_slaves,
3932 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3933}; 1985};
3934 1986
3935/* 1987/*
@@ -3949,13 +2001,6 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3949 { .irq = -1 } 2001 { .irq = -1 }
3950}; 2002};
3951 2003
3952/* mpu master ports */
3953static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3954 &omap44xx_mpu__l3_main_1,
3955 &omap44xx_mpu__l4_abe,
3956 &omap44xx_mpu__dmm,
3957};
3958
3959static struct omap_hwmod omap44xx_mpu_hwmod = { 2004static struct omap_hwmod omap44xx_mpu_hwmod = {
3960 .name = "mpu", 2005 .name = "mpu",
3961 .class = &omap44xx_mpu_hwmod_class, 2006 .class = &omap44xx_mpu_hwmod_class,
@@ -3969,8 +2014,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
3969 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, 2014 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3970 }, 2015 },
3971 }, 2016 },
3972 .masters = omap44xx_mpu_masters,
3973 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
3974}; 2017};
3975 2018
3976/* 2019/*
@@ -4004,35 +2047,11 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
4004 .sensor_voltdm_name = "core", 2047 .sensor_voltdm_name = "core",
4005}; 2048};
4006 2049
4007static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
4008static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { 2050static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
4009 { .irq = 19 + OMAP44XX_IRQ_GIC_START }, 2051 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
4010 { .irq = -1 } 2052 { .irq = -1 }
4011}; 2053};
4012 2054
4013static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4014 {
4015 .pa_start = 0x4a0dd000,
4016 .pa_end = 0x4a0dd03f,
4017 .flags = ADDR_TYPE_RT
4018 },
4019 { }
4020};
4021
4022/* l4_cfg -> smartreflex_core */
4023static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4024 .master = &omap44xx_l4_cfg_hwmod,
4025 .slave = &omap44xx_smartreflex_core_hwmod,
4026 .clk = "l4_div_ck",
4027 .addr = omap44xx_smartreflex_core_addrs,
4028 .user = OCP_USER_MPU | OCP_USER_SDMA,
4029};
4030
4031/* smartreflex_core slave ports */
4032static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
4033 &omap44xx_l4_cfg__smartreflex_core,
4034};
4035
4036static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { 2055static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
4037 .name = "smartreflex_core", 2056 .name = "smartreflex_core",
4038 .class = &omap44xx_smartreflex_hwmod_class, 2057 .class = &omap44xx_smartreflex_hwmod_class,
@@ -4047,8 +2066,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
4047 .modulemode = MODULEMODE_SWCTRL, 2066 .modulemode = MODULEMODE_SWCTRL,
4048 }, 2067 },
4049 }, 2068 },
4050 .slaves = omap44xx_smartreflex_core_slaves,
4051 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4052 .dev_attr = &smartreflex_core_dev_attr, 2069 .dev_attr = &smartreflex_core_dev_attr,
4053}; 2070};
4054 2071
@@ -4057,35 +2074,11 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
4057 .sensor_voltdm_name = "iva", 2074 .sensor_voltdm_name = "iva",
4058}; 2075};
4059 2076
4060static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4061static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { 2077static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4062 { .irq = 102 + OMAP44XX_IRQ_GIC_START }, 2078 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4063 { .irq = -1 } 2079 { .irq = -1 }
4064}; 2080};
4065 2081
4066static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4067 {
4068 .pa_start = 0x4a0db000,
4069 .pa_end = 0x4a0db03f,
4070 .flags = ADDR_TYPE_RT
4071 },
4072 { }
4073};
4074
4075/* l4_cfg -> smartreflex_iva */
4076static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4077 .master = &omap44xx_l4_cfg_hwmod,
4078 .slave = &omap44xx_smartreflex_iva_hwmod,
4079 .clk = "l4_div_ck",
4080 .addr = omap44xx_smartreflex_iva_addrs,
4081 .user = OCP_USER_MPU | OCP_USER_SDMA,
4082};
4083
4084/* smartreflex_iva slave ports */
4085static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4086 &omap44xx_l4_cfg__smartreflex_iva,
4087};
4088
4089static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { 2082static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4090 .name = "smartreflex_iva", 2083 .name = "smartreflex_iva",
4091 .class = &omap44xx_smartreflex_hwmod_class, 2084 .class = &omap44xx_smartreflex_hwmod_class,
@@ -4099,8 +2092,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4099 .modulemode = MODULEMODE_SWCTRL, 2092 .modulemode = MODULEMODE_SWCTRL,
4100 }, 2093 },
4101 }, 2094 },
4102 .slaves = omap44xx_smartreflex_iva_slaves,
4103 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4104 .dev_attr = &smartreflex_iva_dev_attr, 2095 .dev_attr = &smartreflex_iva_dev_attr,
4105}; 2096};
4106 2097
@@ -4109,35 +2100,11 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
4109 .sensor_voltdm_name = "mpu", 2100 .sensor_voltdm_name = "mpu",
4110}; 2101};
4111 2102
4112static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4113static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { 2103static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4114 { .irq = 18 + OMAP44XX_IRQ_GIC_START }, 2104 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4115 { .irq = -1 } 2105 { .irq = -1 }
4116}; 2106};
4117 2107
4118static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4119 {
4120 .pa_start = 0x4a0d9000,
4121 .pa_end = 0x4a0d903f,
4122 .flags = ADDR_TYPE_RT
4123 },
4124 { }
4125};
4126
4127/* l4_cfg -> smartreflex_mpu */
4128static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4129 .master = &omap44xx_l4_cfg_hwmod,
4130 .slave = &omap44xx_smartreflex_mpu_hwmod,
4131 .clk = "l4_div_ck",
4132 .addr = omap44xx_smartreflex_mpu_addrs,
4133 .user = OCP_USER_MPU | OCP_USER_SDMA,
4134};
4135
4136/* smartreflex_mpu slave ports */
4137static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4138 &omap44xx_l4_cfg__smartreflex_mpu,
4139};
4140
4141static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { 2108static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4142 .name = "smartreflex_mpu", 2109 .name = "smartreflex_mpu",
4143 .class = &omap44xx_smartreflex_hwmod_class, 2110 .class = &omap44xx_smartreflex_hwmod_class,
@@ -4151,8 +2118,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4151 .modulemode = MODULEMODE_SWCTRL, 2118 .modulemode = MODULEMODE_SWCTRL,
4152 }, 2119 },
4153 }, 2120 },
4154 .slaves = omap44xx_smartreflex_mpu_slaves,
4155 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4156 .dev_attr = &smartreflex_mpu_dev_attr, 2121 .dev_attr = &smartreflex_mpu_dev_attr,
4157}; 2122};
4158 2123
@@ -4180,30 +2145,6 @@ static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4180}; 2145};
4181 2146
4182/* spinlock */ 2147/* spinlock */
4183static struct omap_hwmod omap44xx_spinlock_hwmod;
4184static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4185 {
4186 .pa_start = 0x4a0f6000,
4187 .pa_end = 0x4a0f6fff,
4188 .flags = ADDR_TYPE_RT
4189 },
4190 { }
4191};
4192
4193/* l4_cfg -> spinlock */
4194static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4195 .master = &omap44xx_l4_cfg_hwmod,
4196 .slave = &omap44xx_spinlock_hwmod,
4197 .clk = "l4_div_ck",
4198 .addr = omap44xx_spinlock_addrs,
4199 .user = OCP_USER_MPU | OCP_USER_SDMA,
4200};
4201
4202/* spinlock slave ports */
4203static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4204 &omap44xx_l4_cfg__spinlock,
4205};
4206
4207static struct omap_hwmod omap44xx_spinlock_hwmod = { 2148static struct omap_hwmod omap44xx_spinlock_hwmod = {
4208 .name = "spinlock", 2149 .name = "spinlock",
4209 .class = &omap44xx_spinlock_hwmod_class, 2150 .class = &omap44xx_spinlock_hwmod_class,
@@ -4214,8 +2155,6 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
4214 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, 2155 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4215 }, 2156 },
4216 }, 2157 },
4217 .slaves = omap44xx_spinlock_slaves,
4218 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
4219}; 2158};
4220 2159
4221/* 2160/*
@@ -4267,35 +2206,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4267}; 2206};
4268 2207
4269/* timer1 */ 2208/* timer1 */
4270static struct omap_hwmod omap44xx_timer1_hwmod;
4271static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { 2209static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4272 { .irq = 37 + OMAP44XX_IRQ_GIC_START }, 2210 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4273 { .irq = -1 } 2211 { .irq = -1 }
4274}; 2212};
4275 2213
4276static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4277 {
4278 .pa_start = 0x4a318000,
4279 .pa_end = 0x4a31807f,
4280 .flags = ADDR_TYPE_RT
4281 },
4282 { }
4283};
4284
4285/* l4_wkup -> timer1 */
4286static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4287 .master = &omap44xx_l4_wkup_hwmod,
4288 .slave = &omap44xx_timer1_hwmod,
4289 .clk = "l4_wkup_clk_mux_ck",
4290 .addr = omap44xx_timer1_addrs,
4291 .user = OCP_USER_MPU | OCP_USER_SDMA,
4292};
4293
4294/* timer1 slave ports */
4295static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4296 &omap44xx_l4_wkup__timer1,
4297};
4298
4299static struct omap_hwmod omap44xx_timer1_hwmod = { 2214static struct omap_hwmod omap44xx_timer1_hwmod = {
4300 .name = "timer1", 2215 .name = "timer1",
4301 .class = &omap44xx_timer_1ms_hwmod_class, 2216 .class = &omap44xx_timer_1ms_hwmod_class,
@@ -4310,40 +2225,14 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
4310 }, 2225 },
4311 }, 2226 },
4312 .dev_attr = &capability_alwon_dev_attr, 2227 .dev_attr = &capability_alwon_dev_attr,
4313 .slaves = omap44xx_timer1_slaves,
4314 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4315}; 2228};
4316 2229
4317/* timer2 */ 2230/* timer2 */
4318static struct omap_hwmod omap44xx_timer2_hwmod;
4319static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { 2231static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4320 { .irq = 38 + OMAP44XX_IRQ_GIC_START }, 2232 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4321 { .irq = -1 } 2233 { .irq = -1 }
4322}; 2234};
4323 2235
4324static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4325 {
4326 .pa_start = 0x48032000,
4327 .pa_end = 0x4803207f,
4328 .flags = ADDR_TYPE_RT
4329 },
4330 { }
4331};
4332
4333/* l4_per -> timer2 */
4334static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4335 .master = &omap44xx_l4_per_hwmod,
4336 .slave = &omap44xx_timer2_hwmod,
4337 .clk = "l4_div_ck",
4338 .addr = omap44xx_timer2_addrs,
4339 .user = OCP_USER_MPU | OCP_USER_SDMA,
4340};
4341
4342/* timer2 slave ports */
4343static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4344 &omap44xx_l4_per__timer2,
4345};
4346
4347static struct omap_hwmod omap44xx_timer2_hwmod = { 2236static struct omap_hwmod omap44xx_timer2_hwmod = {
4348 .name = "timer2", 2237 .name = "timer2",
4349 .class = &omap44xx_timer_1ms_hwmod_class, 2238 .class = &omap44xx_timer_1ms_hwmod_class,
@@ -4358,40 +2247,14 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
4358 }, 2247 },
4359 }, 2248 },
4360 .dev_attr = &capability_alwon_dev_attr, 2249 .dev_attr = &capability_alwon_dev_attr,
4361 .slaves = omap44xx_timer2_slaves,
4362 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4363}; 2250};
4364 2251
4365/* timer3 */ 2252/* timer3 */
4366static struct omap_hwmod omap44xx_timer3_hwmod;
4367static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { 2253static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4368 { .irq = 39 + OMAP44XX_IRQ_GIC_START }, 2254 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4369 { .irq = -1 } 2255 { .irq = -1 }
4370}; 2256};
4371 2257
4372static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4373 {
4374 .pa_start = 0x48034000,
4375 .pa_end = 0x4803407f,
4376 .flags = ADDR_TYPE_RT
4377 },
4378 { }
4379};
4380
4381/* l4_per -> timer3 */
4382static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4383 .master = &omap44xx_l4_per_hwmod,
4384 .slave = &omap44xx_timer3_hwmod,
4385 .clk = "l4_div_ck",
4386 .addr = omap44xx_timer3_addrs,
4387 .user = OCP_USER_MPU | OCP_USER_SDMA,
4388};
4389
4390/* timer3 slave ports */
4391static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4392 &omap44xx_l4_per__timer3,
4393};
4394
4395static struct omap_hwmod omap44xx_timer3_hwmod = { 2258static struct omap_hwmod omap44xx_timer3_hwmod = {
4396 .name = "timer3", 2259 .name = "timer3",
4397 .class = &omap44xx_timer_hwmod_class, 2260 .class = &omap44xx_timer_hwmod_class,
@@ -4406,40 +2269,14 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
4406 }, 2269 },
4407 }, 2270 },
4408 .dev_attr = &capability_alwon_dev_attr, 2271 .dev_attr = &capability_alwon_dev_attr,
4409 .slaves = omap44xx_timer3_slaves,
4410 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4411}; 2272};
4412 2273
4413/* timer4 */ 2274/* timer4 */
4414static struct omap_hwmod omap44xx_timer4_hwmod;
4415static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { 2275static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4416 { .irq = 40 + OMAP44XX_IRQ_GIC_START }, 2276 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4417 { .irq = -1 } 2277 { .irq = -1 }
4418}; 2278};
4419 2279
4420static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4421 {
4422 .pa_start = 0x48036000,
4423 .pa_end = 0x4803607f,
4424 .flags = ADDR_TYPE_RT
4425 },
4426 { }
4427};
4428
4429/* l4_per -> timer4 */
4430static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4431 .master = &omap44xx_l4_per_hwmod,
4432 .slave = &omap44xx_timer4_hwmod,
4433 .clk = "l4_div_ck",
4434 .addr = omap44xx_timer4_addrs,
4435 .user = OCP_USER_MPU | OCP_USER_SDMA,
4436};
4437
4438/* timer4 slave ports */
4439static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4440 &omap44xx_l4_per__timer4,
4441};
4442
4443static struct omap_hwmod omap44xx_timer4_hwmod = { 2280static struct omap_hwmod omap44xx_timer4_hwmod = {
4444 .name = "timer4", 2281 .name = "timer4",
4445 .class = &omap44xx_timer_hwmod_class, 2282 .class = &omap44xx_timer_hwmod_class,
@@ -4454,59 +2291,14 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
4454 }, 2291 },
4455 }, 2292 },
4456 .dev_attr = &capability_alwon_dev_attr, 2293 .dev_attr = &capability_alwon_dev_attr,
4457 .slaves = omap44xx_timer4_slaves,
4458 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4459}; 2294};
4460 2295
4461/* timer5 */ 2296/* timer5 */
4462static struct omap_hwmod omap44xx_timer5_hwmod;
4463static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { 2297static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4464 { .irq = 41 + OMAP44XX_IRQ_GIC_START }, 2298 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4465 { .irq = -1 } 2299 { .irq = -1 }
4466}; 2300};
4467 2301
4468static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4469 {
4470 .pa_start = 0x40138000,
4471 .pa_end = 0x4013807f,
4472 .flags = ADDR_TYPE_RT
4473 },
4474 { }
4475};
4476
4477/* l4_abe -> timer5 */
4478static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4479 .master = &omap44xx_l4_abe_hwmod,
4480 .slave = &omap44xx_timer5_hwmod,
4481 .clk = "ocp_abe_iclk",
4482 .addr = omap44xx_timer5_addrs,
4483 .user = OCP_USER_MPU,
4484};
4485
4486static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4487 {
4488 .pa_start = 0x49038000,
4489 .pa_end = 0x4903807f,
4490 .flags = ADDR_TYPE_RT
4491 },
4492 { }
4493};
4494
4495/* l4_abe -> timer5 (dma) */
4496static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4497 .master = &omap44xx_l4_abe_hwmod,
4498 .slave = &omap44xx_timer5_hwmod,
4499 .clk = "ocp_abe_iclk",
4500 .addr = omap44xx_timer5_dma_addrs,
4501 .user = OCP_USER_SDMA,
4502};
4503
4504/* timer5 slave ports */
4505static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4506 &omap44xx_l4_abe__timer5,
4507 &omap44xx_l4_abe__timer5_dma,
4508};
4509
4510static struct omap_hwmod omap44xx_timer5_hwmod = { 2302static struct omap_hwmod omap44xx_timer5_hwmod = {
4511 .name = "timer5", 2303 .name = "timer5",
4512 .class = &omap44xx_timer_hwmod_class, 2304 .class = &omap44xx_timer_hwmod_class,
@@ -4521,59 +2313,14 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
4521 }, 2313 },
4522 }, 2314 },
4523 .dev_attr = &capability_alwon_dev_attr, 2315 .dev_attr = &capability_alwon_dev_attr,
4524 .slaves = omap44xx_timer5_slaves,
4525 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4526}; 2316};
4527 2317
4528/* timer6 */ 2318/* timer6 */
4529static struct omap_hwmod omap44xx_timer6_hwmod;
4530static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { 2319static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4531 { .irq = 42 + OMAP44XX_IRQ_GIC_START }, 2320 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4532 { .irq = -1 } 2321 { .irq = -1 }
4533}; 2322};
4534 2323
4535static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4536 {
4537 .pa_start = 0x4013a000,
4538 .pa_end = 0x4013a07f,
4539 .flags = ADDR_TYPE_RT
4540 },
4541 { }
4542};
4543
4544/* l4_abe -> timer6 */
4545static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4546 .master = &omap44xx_l4_abe_hwmod,
4547 .slave = &omap44xx_timer6_hwmod,
4548 .clk = "ocp_abe_iclk",
4549 .addr = omap44xx_timer6_addrs,
4550 .user = OCP_USER_MPU,
4551};
4552
4553static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4554 {
4555 .pa_start = 0x4903a000,
4556 .pa_end = 0x4903a07f,
4557 .flags = ADDR_TYPE_RT
4558 },
4559 { }
4560};
4561
4562/* l4_abe -> timer6 (dma) */
4563static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4564 .master = &omap44xx_l4_abe_hwmod,
4565 .slave = &omap44xx_timer6_hwmod,
4566 .clk = "ocp_abe_iclk",
4567 .addr = omap44xx_timer6_dma_addrs,
4568 .user = OCP_USER_SDMA,
4569};
4570
4571/* timer6 slave ports */
4572static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4573 &omap44xx_l4_abe__timer6,
4574 &omap44xx_l4_abe__timer6_dma,
4575};
4576
4577static struct omap_hwmod omap44xx_timer6_hwmod = { 2324static struct omap_hwmod omap44xx_timer6_hwmod = {
4578 .name = "timer6", 2325 .name = "timer6",
4579 .class = &omap44xx_timer_hwmod_class, 2326 .class = &omap44xx_timer_hwmod_class,
@@ -4589,59 +2336,14 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
4589 }, 2336 },
4590 }, 2337 },
4591 .dev_attr = &capability_alwon_dev_attr, 2338 .dev_attr = &capability_alwon_dev_attr,
4592 .slaves = omap44xx_timer6_slaves,
4593 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4594}; 2339};
4595 2340
4596/* timer7 */ 2341/* timer7 */
4597static struct omap_hwmod omap44xx_timer7_hwmod;
4598static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { 2342static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4599 { .irq = 43 + OMAP44XX_IRQ_GIC_START }, 2343 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4600 { .irq = -1 } 2344 { .irq = -1 }
4601}; 2345};
4602 2346
4603static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4604 {
4605 .pa_start = 0x4013c000,
4606 .pa_end = 0x4013c07f,
4607 .flags = ADDR_TYPE_RT
4608 },
4609 { }
4610};
4611
4612/* l4_abe -> timer7 */
4613static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4614 .master = &omap44xx_l4_abe_hwmod,
4615 .slave = &omap44xx_timer7_hwmod,
4616 .clk = "ocp_abe_iclk",
4617 .addr = omap44xx_timer7_addrs,
4618 .user = OCP_USER_MPU,
4619};
4620
4621static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4622 {
4623 .pa_start = 0x4903c000,
4624 .pa_end = 0x4903c07f,
4625 .flags = ADDR_TYPE_RT
4626 },
4627 { }
4628};
4629
4630/* l4_abe -> timer7 (dma) */
4631static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4632 .master = &omap44xx_l4_abe_hwmod,
4633 .slave = &omap44xx_timer7_hwmod,
4634 .clk = "ocp_abe_iclk",
4635 .addr = omap44xx_timer7_dma_addrs,
4636 .user = OCP_USER_SDMA,
4637};
4638
4639/* timer7 slave ports */
4640static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4641 &omap44xx_l4_abe__timer7,
4642 &omap44xx_l4_abe__timer7_dma,
4643};
4644
4645static struct omap_hwmod omap44xx_timer7_hwmod = { 2347static struct omap_hwmod omap44xx_timer7_hwmod = {
4646 .name = "timer7", 2348 .name = "timer7",
4647 .class = &omap44xx_timer_hwmod_class, 2349 .class = &omap44xx_timer_hwmod_class,
@@ -4656,59 +2358,14 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
4656 }, 2358 },
4657 }, 2359 },
4658 .dev_attr = &capability_alwon_dev_attr, 2360 .dev_attr = &capability_alwon_dev_attr,
4659 .slaves = omap44xx_timer7_slaves,
4660 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4661}; 2361};
4662 2362
4663/* timer8 */ 2363/* timer8 */
4664static struct omap_hwmod omap44xx_timer8_hwmod;
4665static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { 2364static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4666 { .irq = 44 + OMAP44XX_IRQ_GIC_START }, 2365 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4667 { .irq = -1 } 2366 { .irq = -1 }
4668}; 2367};
4669 2368
4670static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4671 {
4672 .pa_start = 0x4013e000,
4673 .pa_end = 0x4013e07f,
4674 .flags = ADDR_TYPE_RT
4675 },
4676 { }
4677};
4678
4679/* l4_abe -> timer8 */
4680static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4681 .master = &omap44xx_l4_abe_hwmod,
4682 .slave = &omap44xx_timer8_hwmod,
4683 .clk = "ocp_abe_iclk",
4684 .addr = omap44xx_timer8_addrs,
4685 .user = OCP_USER_MPU,
4686};
4687
4688static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4689 {
4690 .pa_start = 0x4903e000,
4691 .pa_end = 0x4903e07f,
4692 .flags = ADDR_TYPE_RT
4693 },
4694 { }
4695};
4696
4697/* l4_abe -> timer8 (dma) */
4698static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4699 .master = &omap44xx_l4_abe_hwmod,
4700 .slave = &omap44xx_timer8_hwmod,
4701 .clk = "ocp_abe_iclk",
4702 .addr = omap44xx_timer8_dma_addrs,
4703 .user = OCP_USER_SDMA,
4704};
4705
4706/* timer8 slave ports */
4707static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4708 &omap44xx_l4_abe__timer8,
4709 &omap44xx_l4_abe__timer8_dma,
4710};
4711
4712static struct omap_hwmod omap44xx_timer8_hwmod = { 2369static struct omap_hwmod omap44xx_timer8_hwmod = {
4713 .name = "timer8", 2370 .name = "timer8",
4714 .class = &omap44xx_timer_hwmod_class, 2371 .class = &omap44xx_timer_hwmod_class,
@@ -4723,40 +2380,14 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
4723 }, 2380 },
4724 }, 2381 },
4725 .dev_attr = &capability_pwm_dev_attr, 2382 .dev_attr = &capability_pwm_dev_attr,
4726 .slaves = omap44xx_timer8_slaves,
4727 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4728}; 2383};
4729 2384
4730/* timer9 */ 2385/* timer9 */
4731static struct omap_hwmod omap44xx_timer9_hwmod;
4732static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { 2386static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4733 { .irq = 45 + OMAP44XX_IRQ_GIC_START }, 2387 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4734 { .irq = -1 } 2388 { .irq = -1 }
4735}; 2389};
4736 2390
4737static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4738 {
4739 .pa_start = 0x4803e000,
4740 .pa_end = 0x4803e07f,
4741 .flags = ADDR_TYPE_RT
4742 },
4743 { }
4744};
4745
4746/* l4_per -> timer9 */
4747static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4748 .master = &omap44xx_l4_per_hwmod,
4749 .slave = &omap44xx_timer9_hwmod,
4750 .clk = "l4_div_ck",
4751 .addr = omap44xx_timer9_addrs,
4752 .user = OCP_USER_MPU | OCP_USER_SDMA,
4753};
4754
4755/* timer9 slave ports */
4756static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4757 &omap44xx_l4_per__timer9,
4758};
4759
4760static struct omap_hwmod omap44xx_timer9_hwmod = { 2391static struct omap_hwmod omap44xx_timer9_hwmod = {
4761 .name = "timer9", 2392 .name = "timer9",
4762 .class = &omap44xx_timer_hwmod_class, 2393 .class = &omap44xx_timer_hwmod_class,
@@ -4771,40 +2402,14 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
4771 }, 2402 },
4772 }, 2403 },
4773 .dev_attr = &capability_pwm_dev_attr, 2404 .dev_attr = &capability_pwm_dev_attr,
4774 .slaves = omap44xx_timer9_slaves,
4775 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4776}; 2405};
4777 2406
4778/* timer10 */ 2407/* timer10 */
4779static struct omap_hwmod omap44xx_timer10_hwmod;
4780static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { 2408static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4781 { .irq = 46 + OMAP44XX_IRQ_GIC_START }, 2409 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4782 { .irq = -1 } 2410 { .irq = -1 }
4783}; 2411};
4784 2412
4785static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4786 {
4787 .pa_start = 0x48086000,
4788 .pa_end = 0x4808607f,
4789 .flags = ADDR_TYPE_RT
4790 },
4791 { }
4792};
4793
4794/* l4_per -> timer10 */
4795static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4796 .master = &omap44xx_l4_per_hwmod,
4797 .slave = &omap44xx_timer10_hwmod,
4798 .clk = "l4_div_ck",
4799 .addr = omap44xx_timer10_addrs,
4800 .user = OCP_USER_MPU | OCP_USER_SDMA,
4801};
4802
4803/* timer10 slave ports */
4804static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4805 &omap44xx_l4_per__timer10,
4806};
4807
4808static struct omap_hwmod omap44xx_timer10_hwmod = { 2413static struct omap_hwmod omap44xx_timer10_hwmod = {
4809 .name = "timer10", 2414 .name = "timer10",
4810 .class = &omap44xx_timer_1ms_hwmod_class, 2415 .class = &omap44xx_timer_1ms_hwmod_class,
@@ -4819,40 +2424,14 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
4819 }, 2424 },
4820 }, 2425 },
4821 .dev_attr = &capability_pwm_dev_attr, 2426 .dev_attr = &capability_pwm_dev_attr,
4822 .slaves = omap44xx_timer10_slaves,
4823 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4824}; 2427};
4825 2428
4826/* timer11 */ 2429/* timer11 */
4827static struct omap_hwmod omap44xx_timer11_hwmod;
4828static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { 2430static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4829 { .irq = 47 + OMAP44XX_IRQ_GIC_START }, 2431 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4830 { .irq = -1 } 2432 { .irq = -1 }
4831}; 2433};
4832 2434
4833static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4834 {
4835 .pa_start = 0x48088000,
4836 .pa_end = 0x4808807f,
4837 .flags = ADDR_TYPE_RT
4838 },
4839 { }
4840};
4841
4842/* l4_per -> timer11 */
4843static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4844 .master = &omap44xx_l4_per_hwmod,
4845 .slave = &omap44xx_timer11_hwmod,
4846 .clk = "l4_div_ck",
4847 .addr = omap44xx_timer11_addrs,
4848 .user = OCP_USER_MPU | OCP_USER_SDMA,
4849};
4850
4851/* timer11 slave ports */
4852static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4853 &omap44xx_l4_per__timer11,
4854};
4855
4856static struct omap_hwmod omap44xx_timer11_hwmod = { 2435static struct omap_hwmod omap44xx_timer11_hwmod = {
4857 .name = "timer11", 2436 .name = "timer11",
4858 .class = &omap44xx_timer_hwmod_class, 2437 .class = &omap44xx_timer_hwmod_class,
@@ -4867,8 +2446,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
4867 }, 2446 },
4868 }, 2447 },
4869 .dev_attr = &capability_pwm_dev_attr, 2448 .dev_attr = &capability_pwm_dev_attr,
4870 .slaves = omap44xx_timer11_slaves,
4871 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4872}; 2449};
4873 2450
4874/* 2451/*
@@ -4894,7 +2471,6 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4894}; 2471};
4895 2472
4896/* uart1 */ 2473/* uart1 */
4897static struct omap_hwmod omap44xx_uart1_hwmod;
4898static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { 2474static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4899 { .irq = 72 + OMAP44XX_IRQ_GIC_START }, 2475 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4900 { .irq = -1 } 2476 { .irq = -1 }
@@ -4906,29 +2482,6 @@ static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4906 { .dma_req = -1 } 2482 { .dma_req = -1 }
4907}; 2483};
4908 2484
4909static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4910 {
4911 .pa_start = 0x4806a000,
4912 .pa_end = 0x4806a0ff,
4913 .flags = ADDR_TYPE_RT
4914 },
4915 { }
4916};
4917
4918/* l4_per -> uart1 */
4919static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4920 .master = &omap44xx_l4_per_hwmod,
4921 .slave = &omap44xx_uart1_hwmod,
4922 .clk = "l4_div_ck",
4923 .addr = omap44xx_uart1_addrs,
4924 .user = OCP_USER_MPU | OCP_USER_SDMA,
4925};
4926
4927/* uart1 slave ports */
4928static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4929 &omap44xx_l4_per__uart1,
4930};
4931
4932static struct omap_hwmod omap44xx_uart1_hwmod = { 2485static struct omap_hwmod omap44xx_uart1_hwmod = {
4933 .name = "uart1", 2486 .name = "uart1",
4934 .class = &omap44xx_uart_hwmod_class, 2487 .class = &omap44xx_uart_hwmod_class,
@@ -4943,12 +2496,9 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
4943 .modulemode = MODULEMODE_SWCTRL, 2496 .modulemode = MODULEMODE_SWCTRL,
4944 }, 2497 },
4945 }, 2498 },
4946 .slaves = omap44xx_uart1_slaves,
4947 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
4948}; 2499};
4949 2500
4950/* uart2 */ 2501/* uart2 */
4951static struct omap_hwmod omap44xx_uart2_hwmod;
4952static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { 2502static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4953 { .irq = 73 + OMAP44XX_IRQ_GIC_START }, 2503 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4954 { .irq = -1 } 2504 { .irq = -1 }
@@ -4960,29 +2510,6 @@ static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4960 { .dma_req = -1 } 2510 { .dma_req = -1 }
4961}; 2511};
4962 2512
4963static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4964 {
4965 .pa_start = 0x4806c000,
4966 .pa_end = 0x4806c0ff,
4967 .flags = ADDR_TYPE_RT
4968 },
4969 { }
4970};
4971
4972/* l4_per -> uart2 */
4973static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4974 .master = &omap44xx_l4_per_hwmod,
4975 .slave = &omap44xx_uart2_hwmod,
4976 .clk = "l4_div_ck",
4977 .addr = omap44xx_uart2_addrs,
4978 .user = OCP_USER_MPU | OCP_USER_SDMA,
4979};
4980
4981/* uart2 slave ports */
4982static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4983 &omap44xx_l4_per__uart2,
4984};
4985
4986static struct omap_hwmod omap44xx_uart2_hwmod = { 2513static struct omap_hwmod omap44xx_uart2_hwmod = {
4987 .name = "uart2", 2514 .name = "uart2",
4988 .class = &omap44xx_uart_hwmod_class, 2515 .class = &omap44xx_uart_hwmod_class,
@@ -4997,12 +2524,9 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
4997 .modulemode = MODULEMODE_SWCTRL, 2524 .modulemode = MODULEMODE_SWCTRL,
4998 }, 2525 },
4999 }, 2526 },
5000 .slaves = omap44xx_uart2_slaves,
5001 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
5002}; 2527};
5003 2528
5004/* uart3 */ 2529/* uart3 */
5005static struct omap_hwmod omap44xx_uart3_hwmod;
5006static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { 2530static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
5007 { .irq = 74 + OMAP44XX_IRQ_GIC_START }, 2531 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
5008 { .irq = -1 } 2532 { .irq = -1 }
@@ -5014,29 +2538,6 @@ static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
5014 { .dma_req = -1 } 2538 { .dma_req = -1 }
5015}; 2539};
5016 2540
5017static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5018 {
5019 .pa_start = 0x48020000,
5020 .pa_end = 0x480200ff,
5021 .flags = ADDR_TYPE_RT
5022 },
5023 { }
5024};
5025
5026/* l4_per -> uart3 */
5027static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5028 .master = &omap44xx_l4_per_hwmod,
5029 .slave = &omap44xx_uart3_hwmod,
5030 .clk = "l4_div_ck",
5031 .addr = omap44xx_uart3_addrs,
5032 .user = OCP_USER_MPU | OCP_USER_SDMA,
5033};
5034
5035/* uart3 slave ports */
5036static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
5037 &omap44xx_l4_per__uart3,
5038};
5039
5040static struct omap_hwmod omap44xx_uart3_hwmod = { 2541static struct omap_hwmod omap44xx_uart3_hwmod = {
5041 .name = "uart3", 2542 .name = "uart3",
5042 .class = &omap44xx_uart_hwmod_class, 2543 .class = &omap44xx_uart_hwmod_class,
@@ -5052,12 +2553,9 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
5052 .modulemode = MODULEMODE_SWCTRL, 2553 .modulemode = MODULEMODE_SWCTRL,
5053 }, 2554 },
5054 }, 2555 },
5055 .slaves = omap44xx_uart3_slaves,
5056 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
5057}; 2556};
5058 2557
5059/* uart4 */ 2558/* uart4 */
5060static struct omap_hwmod omap44xx_uart4_hwmod;
5061static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { 2559static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5062 { .irq = 70 + OMAP44XX_IRQ_GIC_START }, 2560 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5063 { .irq = -1 } 2561 { .irq = -1 }
@@ -5069,29 +2567,6 @@ static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5069 { .dma_req = -1 } 2567 { .dma_req = -1 }
5070}; 2568};
5071 2569
5072static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5073 {
5074 .pa_start = 0x4806e000,
5075 .pa_end = 0x4806e0ff,
5076 .flags = ADDR_TYPE_RT
5077 },
5078 { }
5079};
5080
5081/* l4_per -> uart4 */
5082static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5083 .master = &omap44xx_l4_per_hwmod,
5084 .slave = &omap44xx_uart4_hwmod,
5085 .clk = "l4_div_ck",
5086 .addr = omap44xx_uart4_addrs,
5087 .user = OCP_USER_MPU | OCP_USER_SDMA,
5088};
5089
5090/* uart4 slave ports */
5091static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5092 &omap44xx_l4_per__uart4,
5093};
5094
5095static struct omap_hwmod omap44xx_uart4_hwmod = { 2570static struct omap_hwmod omap44xx_uart4_hwmod = {
5096 .name = "uart4", 2571 .name = "uart4",
5097 .class = &omap44xx_uart_hwmod_class, 2572 .class = &omap44xx_uart_hwmod_class,
@@ -5106,8 +2581,98 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
5106 .modulemode = MODULEMODE_SWCTRL, 2581 .modulemode = MODULEMODE_SWCTRL,
5107 }, 2582 },
5108 }, 2583 },
5109 .slaves = omap44xx_uart4_slaves, 2584};
5110 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), 2585
2586/*
2587 * 'usb_host_hs' class
2588 * high-speed multi-port usb host controller
2589 */
2590
2591static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2592 .rev_offs = 0x0000,
2593 .sysc_offs = 0x0010,
2594 .syss_offs = 0x0014,
2595 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2596 SYSC_HAS_SOFTRESET),
2597 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2598 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2599 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2600 .sysc_fields = &omap_hwmod_sysc_type2,
2601};
2602
2603static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2604 .name = "usb_host_hs",
2605 .sysc = &omap44xx_usb_host_hs_sysc,
2606};
2607
2608/* usb_host_hs */
2609static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
2610 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
2611 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
2612 { .irq = -1 }
2613};
2614
2615static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2616 .name = "usb_host_hs",
2617 .class = &omap44xx_usb_host_hs_hwmod_class,
2618 .clkdm_name = "l3_init_clkdm",
2619 .main_clk = "usb_host_hs_fck",
2620 .prcm = {
2621 .omap4 = {
2622 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2623 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2624 .modulemode = MODULEMODE_SWCTRL,
2625 },
2626 },
2627 .mpu_irqs = omap44xx_usb_host_hs_irqs,
2628
2629 /*
2630 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2631 * id: i660
2632 *
2633 * Description:
2634 * In the following configuration :
2635 * - USBHOST module is set to smart-idle mode
2636 * - PRCM asserts idle_req to the USBHOST module ( This typically
2637 * happens when the system is going to a low power mode : all ports
2638 * have been suspended, the master part of the USBHOST module has
2639 * entered the standby state, and SW has cut the functional clocks)
2640 * - an USBHOST interrupt occurs before the module is able to answer
2641 * idle_ack, typically a remote wakeup IRQ.
2642 * Then the USB HOST module will enter a deadlock situation where it
2643 * is no more accessible nor functional.
2644 *
2645 * Workaround:
2646 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2647 */
2648
2649 /*
2650 * Errata: USB host EHCI may stall when entering smart-standby mode
2651 * Id: i571
2652 *
2653 * Description:
2654 * When the USBHOST module is set to smart-standby mode, and when it is
2655 * ready to enter the standby state (i.e. all ports are suspended and
2656 * all attached devices are in suspend mode), then it can wrongly assert
2657 * the Mstandby signal too early while there are still some residual OCP
2658 * transactions ongoing. If this condition occurs, the internal state
2659 * machine may go to an undefined state and the USB link may be stuck
2660 * upon the next resume.
2661 *
2662 * Workaround:
2663 * Don't use smart standby; use only force standby,
2664 * hence HWMOD_SWSUP_MSTANDBY
2665 */
2666
2667 /*
2668 * During system boot; If the hwmod framework resets the module
2669 * the module will have smart idle settings; which can lead to deadlock
2670 * (above Errata Id:i660); so, dont reset the module during boot;
2671 * Use HWMOD_INIT_NO_RESET.
2672 */
2673
2674 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
2675 HWMOD_INIT_NO_RESET,
5111}; 2676};
5112 2677
5113/* 2678/*
@@ -5140,34 +2705,6 @@ static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5140 { .irq = -1 } 2705 { .irq = -1 }
5141}; 2706};
5142 2707
5143/* usb_otg_hs master ports */
5144static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5145 &omap44xx_usb_otg_hs__l3_main_2,
5146};
5147
5148static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5149 {
5150 .pa_start = 0x4a0ab000,
5151 .pa_end = 0x4a0ab003,
5152 .flags = ADDR_TYPE_RT
5153 },
5154 { }
5155};
5156
5157/* l4_cfg -> usb_otg_hs */
5158static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5159 .master = &omap44xx_l4_cfg_hwmod,
5160 .slave = &omap44xx_usb_otg_hs_hwmod,
5161 .clk = "l4_div_ck",
5162 .addr = omap44xx_usb_otg_hs_addrs,
5163 .user = OCP_USER_MPU | OCP_USER_SDMA,
5164};
5165
5166/* usb_otg_hs slave ports */
5167static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5168 &omap44xx_l4_cfg__usb_otg_hs,
5169};
5170
5171static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { 2708static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5172 { .role = "xclk", .clk = "usb_otg_hs_xclk" }, 2709 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5173}; 2710};
@@ -5188,10 +2725,47 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5188 }, 2725 },
5189 .opt_clks = usb_otg_hs_opt_clks, 2726 .opt_clks = usb_otg_hs_opt_clks,
5190 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), 2727 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
5191 .slaves = omap44xx_usb_otg_hs_slaves, 2728};
5192 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), 2729
5193 .masters = omap44xx_usb_otg_hs_masters, 2730/*
5194 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), 2731 * 'usb_tll_hs' class
2732 * usb_tll_hs module is the adapter on the usb_host_hs ports
2733 */
2734
2735static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
2736 .rev_offs = 0x0000,
2737 .sysc_offs = 0x0010,
2738 .syss_offs = 0x0014,
2739 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2740 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2741 SYSC_HAS_AUTOIDLE),
2742 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2743 .sysc_fields = &omap_hwmod_sysc_type1,
2744};
2745
2746static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
2747 .name = "usb_tll_hs",
2748 .sysc = &omap44xx_usb_tll_hs_sysc,
2749};
2750
2751static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
2752 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
2753 { .irq = -1 }
2754};
2755
2756static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
2757 .name = "usb_tll_hs",
2758 .class = &omap44xx_usb_tll_hs_hwmod_class,
2759 .clkdm_name = "l3_init_clkdm",
2760 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
2761 .main_clk = "usb_tll_hs_ick",
2762 .prcm = {
2763 .omap4 = {
2764 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
2765 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
2766 .modulemode = MODULEMODE_HWCTRL,
2767 },
2768 },
5195}; 2769};
5196 2770
5197/* 2771/*
@@ -5218,35 +2792,11 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5218}; 2792};
5219 2793
5220/* wd_timer2 */ 2794/* wd_timer2 */
5221static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5222static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { 2795static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5223 { .irq = 80 + OMAP44XX_IRQ_GIC_START }, 2796 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5224 { .irq = -1 } 2797 { .irq = -1 }
5225}; 2798};
5226 2799
5227static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5228 {
5229 .pa_start = 0x4a314000,
5230 .pa_end = 0x4a31407f,
5231 .flags = ADDR_TYPE_RT
5232 },
5233 { }
5234};
5235
5236/* l4_wkup -> wd_timer2 */
5237static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5238 .master = &omap44xx_l4_wkup_hwmod,
5239 .slave = &omap44xx_wd_timer2_hwmod,
5240 .clk = "l4_wkup_clk_mux_ck",
5241 .addr = omap44xx_wd_timer2_addrs,
5242 .user = OCP_USER_MPU | OCP_USER_SDMA,
5243};
5244
5245/* wd_timer2 slave ports */
5246static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5247 &omap44xx_l4_wkup__wd_timer2,
5248};
5249
5250static struct omap_hwmod omap44xx_wd_timer2_hwmod = { 2800static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5251 .name = "wd_timer2", 2801 .name = "wd_timer2",
5252 .class = &omap44xx_wd_timer_hwmod_class, 2802 .class = &omap44xx_wd_timer_hwmod_class,
@@ -5260,106 +2810,1746 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5260 .modulemode = MODULEMODE_SWCTRL, 2810 .modulemode = MODULEMODE_SWCTRL,
5261 }, 2811 },
5262 }, 2812 },
5263 .slaves = omap44xx_wd_timer2_slaves,
5264 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5265}; 2813};
5266 2814
5267/* wd_timer3 */ 2815/* wd_timer3 */
5268static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5269static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { 2816static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5270 { .irq = 36 + OMAP44XX_IRQ_GIC_START }, 2817 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5271 { .irq = -1 } 2818 { .irq = -1 }
5272}; 2819};
5273 2820
5274static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { 2821static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
2822 .name = "wd_timer3",
2823 .class = &omap44xx_wd_timer_hwmod_class,
2824 .clkdm_name = "abe_clkdm",
2825 .mpu_irqs = omap44xx_wd_timer3_irqs,
2826 .main_clk = "wd_timer3_fck",
2827 .prcm = {
2828 .omap4 = {
2829 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
2830 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
2831 .modulemode = MODULEMODE_SWCTRL,
2832 },
2833 },
2834};
2835
2836
2837/*
2838 * interfaces
2839 */
2840
2841/* l3_main_1 -> dmm */
2842static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
2843 .master = &omap44xx_l3_main_1_hwmod,
2844 .slave = &omap44xx_dmm_hwmod,
2845 .clk = "l3_div_ck",
2846 .user = OCP_USER_SDMA,
2847};
2848
2849static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
5275 { 2850 {
5276 .pa_start = 0x40130000, 2851 .pa_start = 0x4e000000,
5277 .pa_end = 0x4013007f, 2852 .pa_end = 0x4e0007ff,
5278 .flags = ADDR_TYPE_RT 2853 .flags = ADDR_TYPE_RT
5279 }, 2854 },
5280 { } 2855 { }
5281}; 2856};
5282 2857
5283/* l4_abe -> wd_timer3 */ 2858/* mpu -> dmm */
5284static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { 2859static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
2860 .master = &omap44xx_mpu_hwmod,
2861 .slave = &omap44xx_dmm_hwmod,
2862 .clk = "l3_div_ck",
2863 .addr = omap44xx_dmm_addrs,
2864 .user = OCP_USER_MPU,
2865};
2866
2867/* dmm -> emif_fw */
2868static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
2869 .master = &omap44xx_dmm_hwmod,
2870 .slave = &omap44xx_emif_fw_hwmod,
2871 .clk = "l3_div_ck",
2872 .user = OCP_USER_MPU | OCP_USER_SDMA,
2873};
2874
2875static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
2876 {
2877 .pa_start = 0x4a20c000,
2878 .pa_end = 0x4a20c0ff,
2879 .flags = ADDR_TYPE_RT
2880 },
2881 { }
2882};
2883
2884/* l4_cfg -> emif_fw */
2885static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
2886 .master = &omap44xx_l4_cfg_hwmod,
2887 .slave = &omap44xx_emif_fw_hwmod,
2888 .clk = "l4_div_ck",
2889 .addr = omap44xx_emif_fw_addrs,
2890 .user = OCP_USER_MPU,
2891};
2892
2893/* iva -> l3_instr */
2894static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
2895 .master = &omap44xx_iva_hwmod,
2896 .slave = &omap44xx_l3_instr_hwmod,
2897 .clk = "l3_div_ck",
2898 .user = OCP_USER_MPU | OCP_USER_SDMA,
2899};
2900
2901/* l3_main_3 -> l3_instr */
2902static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
2903 .master = &omap44xx_l3_main_3_hwmod,
2904 .slave = &omap44xx_l3_instr_hwmod,
2905 .clk = "l3_div_ck",
2906 .user = OCP_USER_MPU | OCP_USER_SDMA,
2907};
2908
2909/* dsp -> l3_main_1 */
2910static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
2911 .master = &omap44xx_dsp_hwmod,
2912 .slave = &omap44xx_l3_main_1_hwmod,
2913 .clk = "l3_div_ck",
2914 .user = OCP_USER_MPU | OCP_USER_SDMA,
2915};
2916
2917/* dss -> l3_main_1 */
2918static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
2919 .master = &omap44xx_dss_hwmod,
2920 .slave = &omap44xx_l3_main_1_hwmod,
2921 .clk = "l3_div_ck",
2922 .user = OCP_USER_MPU | OCP_USER_SDMA,
2923};
2924
2925/* l3_main_2 -> l3_main_1 */
2926static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
2927 .master = &omap44xx_l3_main_2_hwmod,
2928 .slave = &omap44xx_l3_main_1_hwmod,
2929 .clk = "l3_div_ck",
2930 .user = OCP_USER_MPU | OCP_USER_SDMA,
2931};
2932
2933/* l4_cfg -> l3_main_1 */
2934static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
2935 .master = &omap44xx_l4_cfg_hwmod,
2936 .slave = &omap44xx_l3_main_1_hwmod,
2937 .clk = "l4_div_ck",
2938 .user = OCP_USER_MPU | OCP_USER_SDMA,
2939};
2940
2941/* mmc1 -> l3_main_1 */
2942static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
2943 .master = &omap44xx_mmc1_hwmod,
2944 .slave = &omap44xx_l3_main_1_hwmod,
2945 .clk = "l3_div_ck",
2946 .user = OCP_USER_MPU | OCP_USER_SDMA,
2947};
2948
2949/* mmc2 -> l3_main_1 */
2950static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
2951 .master = &omap44xx_mmc2_hwmod,
2952 .slave = &omap44xx_l3_main_1_hwmod,
2953 .clk = "l3_div_ck",
2954 .user = OCP_USER_MPU | OCP_USER_SDMA,
2955};
2956
2957static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
2958 {
2959 .pa_start = 0x44000000,
2960 .pa_end = 0x44000fff,
2961 .flags = ADDR_TYPE_RT
2962 },
2963 { }
2964};
2965
2966/* mpu -> l3_main_1 */
2967static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
2968 .master = &omap44xx_mpu_hwmod,
2969 .slave = &omap44xx_l3_main_1_hwmod,
2970 .clk = "l3_div_ck",
2971 .addr = omap44xx_l3_main_1_addrs,
2972 .user = OCP_USER_MPU,
2973};
2974
2975/* dma_system -> l3_main_2 */
2976static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
2977 .master = &omap44xx_dma_system_hwmod,
2978 .slave = &omap44xx_l3_main_2_hwmod,
2979 .clk = "l3_div_ck",
2980 .user = OCP_USER_MPU | OCP_USER_SDMA,
2981};
2982
2983/* hsi -> l3_main_2 */
2984static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
2985 .master = &omap44xx_hsi_hwmod,
2986 .slave = &omap44xx_l3_main_2_hwmod,
2987 .clk = "l3_div_ck",
2988 .user = OCP_USER_MPU | OCP_USER_SDMA,
2989};
2990
2991/* ipu -> l3_main_2 */
2992static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
2993 .master = &omap44xx_ipu_hwmod,
2994 .slave = &omap44xx_l3_main_2_hwmod,
2995 .clk = "l3_div_ck",
2996 .user = OCP_USER_MPU | OCP_USER_SDMA,
2997};
2998
2999/* iss -> l3_main_2 */
3000static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3001 .master = &omap44xx_iss_hwmod,
3002 .slave = &omap44xx_l3_main_2_hwmod,
3003 .clk = "l3_div_ck",
3004 .user = OCP_USER_MPU | OCP_USER_SDMA,
3005};
3006
3007/* iva -> l3_main_2 */
3008static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3009 .master = &omap44xx_iva_hwmod,
3010 .slave = &omap44xx_l3_main_2_hwmod,
3011 .clk = "l3_div_ck",
3012 .user = OCP_USER_MPU | OCP_USER_SDMA,
3013};
3014
3015static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3016 {
3017 .pa_start = 0x44800000,
3018 .pa_end = 0x44801fff,
3019 .flags = ADDR_TYPE_RT
3020 },
3021 { }
3022};
3023
3024/* l3_main_1 -> l3_main_2 */
3025static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3026 .master = &omap44xx_l3_main_1_hwmod,
3027 .slave = &omap44xx_l3_main_2_hwmod,
3028 .clk = "l3_div_ck",
3029 .addr = omap44xx_l3_main_2_addrs,
3030 .user = OCP_USER_MPU,
3031};
3032
3033/* l4_cfg -> l3_main_2 */
3034static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3035 .master = &omap44xx_l4_cfg_hwmod,
3036 .slave = &omap44xx_l3_main_2_hwmod,
3037 .clk = "l4_div_ck",
3038 .user = OCP_USER_MPU | OCP_USER_SDMA,
3039};
3040
3041/* usb_host_hs -> l3_main_2 */
3042static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3043 .master = &omap44xx_usb_host_hs_hwmod,
3044 .slave = &omap44xx_l3_main_2_hwmod,
3045 .clk = "l3_div_ck",
3046 .user = OCP_USER_MPU | OCP_USER_SDMA,
3047};
3048
3049/* usb_otg_hs -> l3_main_2 */
3050static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3051 .master = &omap44xx_usb_otg_hs_hwmod,
3052 .slave = &omap44xx_l3_main_2_hwmod,
3053 .clk = "l3_div_ck",
3054 .user = OCP_USER_MPU | OCP_USER_SDMA,
3055};
3056
3057static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3058 {
3059 .pa_start = 0x45000000,
3060 .pa_end = 0x45000fff,
3061 .flags = ADDR_TYPE_RT
3062 },
3063 { }
3064};
3065
3066/* l3_main_1 -> l3_main_3 */
3067static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3068 .master = &omap44xx_l3_main_1_hwmod,
3069 .slave = &omap44xx_l3_main_3_hwmod,
3070 .clk = "l3_div_ck",
3071 .addr = omap44xx_l3_main_3_addrs,
3072 .user = OCP_USER_MPU,
3073};
3074
3075/* l3_main_2 -> l3_main_3 */
3076static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3077 .master = &omap44xx_l3_main_2_hwmod,
3078 .slave = &omap44xx_l3_main_3_hwmod,
3079 .clk = "l3_div_ck",
3080 .user = OCP_USER_MPU | OCP_USER_SDMA,
3081};
3082
3083/* l4_cfg -> l3_main_3 */
3084static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3085 .master = &omap44xx_l4_cfg_hwmod,
3086 .slave = &omap44xx_l3_main_3_hwmod,
3087 .clk = "l4_div_ck",
3088 .user = OCP_USER_MPU | OCP_USER_SDMA,
3089};
3090
3091/* aess -> l4_abe */
3092static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
3093 .master = &omap44xx_aess_hwmod,
3094 .slave = &omap44xx_l4_abe_hwmod,
3095 .clk = "ocp_abe_iclk",
3096 .user = OCP_USER_MPU | OCP_USER_SDMA,
3097};
3098
3099/* dsp -> l4_abe */
3100static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3101 .master = &omap44xx_dsp_hwmod,
3102 .slave = &omap44xx_l4_abe_hwmod,
3103 .clk = "ocp_abe_iclk",
3104 .user = OCP_USER_MPU | OCP_USER_SDMA,
3105};
3106
3107/* l3_main_1 -> l4_abe */
3108static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3109 .master = &omap44xx_l3_main_1_hwmod,
3110 .slave = &omap44xx_l4_abe_hwmod,
3111 .clk = "l3_div_ck",
3112 .user = OCP_USER_MPU | OCP_USER_SDMA,
3113};
3114
3115/* mpu -> l4_abe */
3116static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3117 .master = &omap44xx_mpu_hwmod,
3118 .slave = &omap44xx_l4_abe_hwmod,
3119 .clk = "ocp_abe_iclk",
3120 .user = OCP_USER_MPU | OCP_USER_SDMA,
3121};
3122
3123/* l3_main_1 -> l4_cfg */
3124static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3125 .master = &omap44xx_l3_main_1_hwmod,
3126 .slave = &omap44xx_l4_cfg_hwmod,
3127 .clk = "l3_div_ck",
3128 .user = OCP_USER_MPU | OCP_USER_SDMA,
3129};
3130
3131/* l3_main_2 -> l4_per */
3132static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3133 .master = &omap44xx_l3_main_2_hwmod,
3134 .slave = &omap44xx_l4_per_hwmod,
3135 .clk = "l3_div_ck",
3136 .user = OCP_USER_MPU | OCP_USER_SDMA,
3137};
3138
3139/* l4_cfg -> l4_wkup */
3140static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3141 .master = &omap44xx_l4_cfg_hwmod,
3142 .slave = &omap44xx_l4_wkup_hwmod,
3143 .clk = "l4_div_ck",
3144 .user = OCP_USER_MPU | OCP_USER_SDMA,
3145};
3146
3147/* mpu -> mpu_private */
3148static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3149 .master = &omap44xx_mpu_hwmod,
3150 .slave = &omap44xx_mpu_private_hwmod,
3151 .clk = "l3_div_ck",
3152 .user = OCP_USER_MPU | OCP_USER_SDMA,
3153};
3154
3155static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3156 {
3157 .pa_start = 0x401f1000,
3158 .pa_end = 0x401f13ff,
3159 .flags = ADDR_TYPE_RT
3160 },
3161 { }
3162};
3163
3164/* l4_abe -> aess */
3165static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
5285 .master = &omap44xx_l4_abe_hwmod, 3166 .master = &omap44xx_l4_abe_hwmod,
5286 .slave = &omap44xx_wd_timer3_hwmod, 3167 .slave = &omap44xx_aess_hwmod,
5287 .clk = "ocp_abe_iclk", 3168 .clk = "ocp_abe_iclk",
5288 .addr = omap44xx_wd_timer3_addrs, 3169 .addr = omap44xx_aess_addrs,
5289 .user = OCP_USER_MPU, 3170 .user = OCP_USER_MPU,
5290}; 3171};
5291 3172
5292static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { 3173static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
5293 { 3174 {
5294 .pa_start = 0x49030000, 3175 .pa_start = 0x490f1000,
5295 .pa_end = 0x4903007f, 3176 .pa_end = 0x490f13ff,
5296 .flags = ADDR_TYPE_RT 3177 .flags = ADDR_TYPE_RT
5297 }, 3178 },
5298 { } 3179 { }
5299}; 3180};
5300 3181
5301/* l4_abe -> wd_timer3 (dma) */ 3182/* l4_abe -> aess (dma) */
5302static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { 3183static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
5303 .master = &omap44xx_l4_abe_hwmod, 3184 .master = &omap44xx_l4_abe_hwmod,
5304 .slave = &omap44xx_wd_timer3_hwmod, 3185 .slave = &omap44xx_aess_hwmod,
5305 .clk = "ocp_abe_iclk", 3186 .clk = "ocp_abe_iclk",
5306 .addr = omap44xx_wd_timer3_dma_addrs, 3187 .addr = omap44xx_aess_dma_addrs,
5307 .user = OCP_USER_SDMA, 3188 .user = OCP_USER_SDMA,
5308}; 3189};
5309 3190
5310/* wd_timer3 slave ports */ 3191static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
5311static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { 3192 {
5312 &omap44xx_l4_abe__wd_timer3, 3193 .pa_start = 0x4a304000,
5313 &omap44xx_l4_abe__wd_timer3_dma, 3194 .pa_end = 0x4a30401f,
3195 .flags = ADDR_TYPE_RT
3196 },
3197 { }
5314}; 3198};
5315 3199
5316static struct omap_hwmod omap44xx_wd_timer3_hwmod = { 3200/* l4_wkup -> counter_32k */
5317 .name = "wd_timer3", 3201static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
5318 .class = &omap44xx_wd_timer_hwmod_class, 3202 .master = &omap44xx_l4_wkup_hwmod,
5319 .clkdm_name = "abe_clkdm", 3203 .slave = &omap44xx_counter_32k_hwmod,
5320 .mpu_irqs = omap44xx_wd_timer3_irqs, 3204 .clk = "l4_wkup_clk_mux_ck",
5321 .main_clk = "wd_timer3_fck", 3205 .addr = omap44xx_counter_32k_addrs,
5322 .prcm = { 3206 .user = OCP_USER_MPU | OCP_USER_SDMA,
5323 .omap4 = { 3207};
5324 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, 3208
5325 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, 3209static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
5326 .modulemode = MODULEMODE_SWCTRL, 3210 {
5327 }, 3211 .pa_start = 0x4a056000,
3212 .pa_end = 0x4a056fff,
3213 .flags = ADDR_TYPE_RT
5328 }, 3214 },
5329 .slaves = omap44xx_wd_timer3_slaves, 3215 { }
5330 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5331}; 3216};
5332 3217
5333/* 3218/* l4_cfg -> dma_system */
5334 * 'usb_host_hs' class 3219static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
5335 * high-speed multi-port usb host controller 3220 .master = &omap44xx_l4_cfg_hwmod,
5336 */ 3221 .slave = &omap44xx_dma_system_hwmod,
5337static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { 3222 .clk = "l4_div_ck",
5338 .master = &omap44xx_usb_host_hs_hwmod, 3223 .addr = omap44xx_dma_system_addrs,
5339 .slave = &omap44xx_l3_main_2_hwmod, 3224 .user = OCP_USER_MPU | OCP_USER_SDMA,
3225};
3226
3227static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
3228 {
3229 .name = "mpu",
3230 .pa_start = 0x4012e000,
3231 .pa_end = 0x4012e07f,
3232 .flags = ADDR_TYPE_RT
3233 },
3234 { }
3235};
3236
3237/* l4_abe -> dmic */
3238static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3239 .master = &omap44xx_l4_abe_hwmod,
3240 .slave = &omap44xx_dmic_hwmod,
3241 .clk = "ocp_abe_iclk",
3242 .addr = omap44xx_dmic_addrs,
3243 .user = OCP_USER_MPU,
3244};
3245
3246static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
3247 {
3248 .name = "dma",
3249 .pa_start = 0x4902e000,
3250 .pa_end = 0x4902e07f,
3251 .flags = ADDR_TYPE_RT
3252 },
3253 { }
3254};
3255
3256/* l4_abe -> dmic (dma) */
3257static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
3258 .master = &omap44xx_l4_abe_hwmod,
3259 .slave = &omap44xx_dmic_hwmod,
3260 .clk = "ocp_abe_iclk",
3261 .addr = omap44xx_dmic_dma_addrs,
3262 .user = OCP_USER_SDMA,
3263};
3264
3265/* dsp -> iva */
3266static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3267 .master = &omap44xx_dsp_hwmod,
3268 .slave = &omap44xx_iva_hwmod,
3269 .clk = "dpll_iva_m5x2_ck",
3270 .user = OCP_USER_DSP,
3271};
3272
3273/* l4_cfg -> dsp */
3274static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3275 .master = &omap44xx_l4_cfg_hwmod,
3276 .slave = &omap44xx_dsp_hwmod,
3277 .clk = "l4_div_ck",
3278 .user = OCP_USER_MPU | OCP_USER_SDMA,
3279};
3280
3281static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3282 {
3283 .pa_start = 0x58000000,
3284 .pa_end = 0x5800007f,
3285 .flags = ADDR_TYPE_RT
3286 },
3287 { }
3288};
3289
3290/* l3_main_2 -> dss */
3291static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3292 .master = &omap44xx_l3_main_2_hwmod,
3293 .slave = &omap44xx_dss_hwmod,
3294 .clk = "dss_fck",
3295 .addr = omap44xx_dss_dma_addrs,
3296 .user = OCP_USER_SDMA,
3297};
3298
3299static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3300 {
3301 .pa_start = 0x48040000,
3302 .pa_end = 0x4804007f,
3303 .flags = ADDR_TYPE_RT
3304 },
3305 { }
3306};
3307
3308/* l4_per -> dss */
3309static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3310 .master = &omap44xx_l4_per_hwmod,
3311 .slave = &omap44xx_dss_hwmod,
3312 .clk = "l4_div_ck",
3313 .addr = omap44xx_dss_addrs,
3314 .user = OCP_USER_MPU,
3315};
3316
3317static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3318 {
3319 .pa_start = 0x58001000,
3320 .pa_end = 0x58001fff,
3321 .flags = ADDR_TYPE_RT
3322 },
3323 { }
3324};
3325
3326/* l3_main_2 -> dss_dispc */
3327static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3328 .master = &omap44xx_l3_main_2_hwmod,
3329 .slave = &omap44xx_dss_dispc_hwmod,
3330 .clk = "dss_fck",
3331 .addr = omap44xx_dss_dispc_dma_addrs,
3332 .user = OCP_USER_SDMA,
3333};
3334
3335static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3336 {
3337 .pa_start = 0x48041000,
3338 .pa_end = 0x48041fff,
3339 .flags = ADDR_TYPE_RT
3340 },
3341 { }
3342};
3343
3344/* l4_per -> dss_dispc */
3345static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3346 .master = &omap44xx_l4_per_hwmod,
3347 .slave = &omap44xx_dss_dispc_hwmod,
3348 .clk = "l4_div_ck",
3349 .addr = omap44xx_dss_dispc_addrs,
3350 .user = OCP_USER_MPU,
3351};
3352
3353static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3354 {
3355 .pa_start = 0x58004000,
3356 .pa_end = 0x580041ff,
3357 .flags = ADDR_TYPE_RT
3358 },
3359 { }
3360};
3361
3362/* l3_main_2 -> dss_dsi1 */
3363static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3364 .master = &omap44xx_l3_main_2_hwmod,
3365 .slave = &omap44xx_dss_dsi1_hwmod,
3366 .clk = "dss_fck",
3367 .addr = omap44xx_dss_dsi1_dma_addrs,
3368 .user = OCP_USER_SDMA,
3369};
3370
3371static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3372 {
3373 .pa_start = 0x48044000,
3374 .pa_end = 0x480441ff,
3375 .flags = ADDR_TYPE_RT
3376 },
3377 { }
3378};
3379
3380/* l4_per -> dss_dsi1 */
3381static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3382 .master = &omap44xx_l4_per_hwmod,
3383 .slave = &omap44xx_dss_dsi1_hwmod,
3384 .clk = "l4_div_ck",
3385 .addr = omap44xx_dss_dsi1_addrs,
3386 .user = OCP_USER_MPU,
3387};
3388
3389static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3390 {
3391 .pa_start = 0x58005000,
3392 .pa_end = 0x580051ff,
3393 .flags = ADDR_TYPE_RT
3394 },
3395 { }
3396};
3397
3398/* l3_main_2 -> dss_dsi2 */
3399static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3400 .master = &omap44xx_l3_main_2_hwmod,
3401 .slave = &omap44xx_dss_dsi2_hwmod,
3402 .clk = "dss_fck",
3403 .addr = omap44xx_dss_dsi2_dma_addrs,
3404 .user = OCP_USER_SDMA,
3405};
3406
3407static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3408 {
3409 .pa_start = 0x48045000,
3410 .pa_end = 0x480451ff,
3411 .flags = ADDR_TYPE_RT
3412 },
3413 { }
3414};
3415
3416/* l4_per -> dss_dsi2 */
3417static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3418 .master = &omap44xx_l4_per_hwmod,
3419 .slave = &omap44xx_dss_dsi2_hwmod,
3420 .clk = "l4_div_ck",
3421 .addr = omap44xx_dss_dsi2_addrs,
3422 .user = OCP_USER_MPU,
3423};
3424
3425static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3426 {
3427 .pa_start = 0x58006000,
3428 .pa_end = 0x58006fff,
3429 .flags = ADDR_TYPE_RT
3430 },
3431 { }
3432};
3433
3434/* l3_main_2 -> dss_hdmi */
3435static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3436 .master = &omap44xx_l3_main_2_hwmod,
3437 .slave = &omap44xx_dss_hdmi_hwmod,
3438 .clk = "dss_fck",
3439 .addr = omap44xx_dss_hdmi_dma_addrs,
3440 .user = OCP_USER_SDMA,
3441};
3442
3443static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3444 {
3445 .pa_start = 0x48046000,
3446 .pa_end = 0x48046fff,
3447 .flags = ADDR_TYPE_RT
3448 },
3449 { }
3450};
3451
3452/* l4_per -> dss_hdmi */
3453static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3454 .master = &omap44xx_l4_per_hwmod,
3455 .slave = &omap44xx_dss_hdmi_hwmod,
3456 .clk = "l4_div_ck",
3457 .addr = omap44xx_dss_hdmi_addrs,
3458 .user = OCP_USER_MPU,
3459};
3460
3461static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3462 {
3463 .pa_start = 0x58002000,
3464 .pa_end = 0x580020ff,
3465 .flags = ADDR_TYPE_RT
3466 },
3467 { }
3468};
3469
3470/* l3_main_2 -> dss_rfbi */
3471static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3472 .master = &omap44xx_l3_main_2_hwmod,
3473 .slave = &omap44xx_dss_rfbi_hwmod,
3474 .clk = "dss_fck",
3475 .addr = omap44xx_dss_rfbi_dma_addrs,
3476 .user = OCP_USER_SDMA,
3477};
3478
3479static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3480 {
3481 .pa_start = 0x48042000,
3482 .pa_end = 0x480420ff,
3483 .flags = ADDR_TYPE_RT
3484 },
3485 { }
3486};
3487
3488/* l4_per -> dss_rfbi */
3489static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3490 .master = &omap44xx_l4_per_hwmod,
3491 .slave = &omap44xx_dss_rfbi_hwmod,
3492 .clk = "l4_div_ck",
3493 .addr = omap44xx_dss_rfbi_addrs,
3494 .user = OCP_USER_MPU,
3495};
3496
3497static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3498 {
3499 .pa_start = 0x58003000,
3500 .pa_end = 0x580030ff,
3501 .flags = ADDR_TYPE_RT
3502 },
3503 { }
3504};
3505
3506/* l3_main_2 -> dss_venc */
3507static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3508 .master = &omap44xx_l3_main_2_hwmod,
3509 .slave = &omap44xx_dss_venc_hwmod,
3510 .clk = "dss_fck",
3511 .addr = omap44xx_dss_venc_dma_addrs,
3512 .user = OCP_USER_SDMA,
3513};
3514
3515static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
3516 {
3517 .pa_start = 0x48043000,
3518 .pa_end = 0x480430ff,
3519 .flags = ADDR_TYPE_RT
3520 },
3521 { }
3522};
3523
3524/* l4_per -> dss_venc */
3525static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3526 .master = &omap44xx_l4_per_hwmod,
3527 .slave = &omap44xx_dss_venc_hwmod,
3528 .clk = "l4_div_ck",
3529 .addr = omap44xx_dss_venc_addrs,
3530 .user = OCP_USER_MPU,
3531};
3532
3533static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
3534 {
3535 .pa_start = 0x4a310000,
3536 .pa_end = 0x4a3101ff,
3537 .flags = ADDR_TYPE_RT
3538 },
3539 { }
3540};
3541
3542/* l4_wkup -> gpio1 */
3543static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3544 .master = &omap44xx_l4_wkup_hwmod,
3545 .slave = &omap44xx_gpio1_hwmod,
3546 .clk = "l4_wkup_clk_mux_ck",
3547 .addr = omap44xx_gpio1_addrs,
3548 .user = OCP_USER_MPU | OCP_USER_SDMA,
3549};
3550
3551static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
3552 {
3553 .pa_start = 0x48055000,
3554 .pa_end = 0x480551ff,
3555 .flags = ADDR_TYPE_RT
3556 },
3557 { }
3558};
3559
3560/* l4_per -> gpio2 */
3561static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3562 .master = &omap44xx_l4_per_hwmod,
3563 .slave = &omap44xx_gpio2_hwmod,
3564 .clk = "l4_div_ck",
3565 .addr = omap44xx_gpio2_addrs,
3566 .user = OCP_USER_MPU | OCP_USER_SDMA,
3567};
3568
3569static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
3570 {
3571 .pa_start = 0x48057000,
3572 .pa_end = 0x480571ff,
3573 .flags = ADDR_TYPE_RT
3574 },
3575 { }
3576};
3577
3578/* l4_per -> gpio3 */
3579static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3580 .master = &omap44xx_l4_per_hwmod,
3581 .slave = &omap44xx_gpio3_hwmod,
3582 .clk = "l4_div_ck",
3583 .addr = omap44xx_gpio3_addrs,
3584 .user = OCP_USER_MPU | OCP_USER_SDMA,
3585};
3586
3587static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
3588 {
3589 .pa_start = 0x48059000,
3590 .pa_end = 0x480591ff,
3591 .flags = ADDR_TYPE_RT
3592 },
3593 { }
3594};
3595
3596/* l4_per -> gpio4 */
3597static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3598 .master = &omap44xx_l4_per_hwmod,
3599 .slave = &omap44xx_gpio4_hwmod,
3600 .clk = "l4_div_ck",
3601 .addr = omap44xx_gpio4_addrs,
3602 .user = OCP_USER_MPU | OCP_USER_SDMA,
3603};
3604
3605static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
3606 {
3607 .pa_start = 0x4805b000,
3608 .pa_end = 0x4805b1ff,
3609 .flags = ADDR_TYPE_RT
3610 },
3611 { }
3612};
3613
3614/* l4_per -> gpio5 */
3615static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3616 .master = &omap44xx_l4_per_hwmod,
3617 .slave = &omap44xx_gpio5_hwmod,
3618 .clk = "l4_div_ck",
3619 .addr = omap44xx_gpio5_addrs,
3620 .user = OCP_USER_MPU | OCP_USER_SDMA,
3621};
3622
3623static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
3624 {
3625 .pa_start = 0x4805d000,
3626 .pa_end = 0x4805d1ff,
3627 .flags = ADDR_TYPE_RT
3628 },
3629 { }
3630};
3631
3632/* l4_per -> gpio6 */
3633static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3634 .master = &omap44xx_l4_per_hwmod,
3635 .slave = &omap44xx_gpio6_hwmod,
3636 .clk = "l4_div_ck",
3637 .addr = omap44xx_gpio6_addrs,
3638 .user = OCP_USER_MPU | OCP_USER_SDMA,
3639};
3640
3641static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
3642 {
3643 .pa_start = 0x4a058000,
3644 .pa_end = 0x4a05bfff,
3645 .flags = ADDR_TYPE_RT
3646 },
3647 { }
3648};
3649
3650/* l4_cfg -> hsi */
3651static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
3652 .master = &omap44xx_l4_cfg_hwmod,
3653 .slave = &omap44xx_hsi_hwmod,
3654 .clk = "l4_div_ck",
3655 .addr = omap44xx_hsi_addrs,
3656 .user = OCP_USER_MPU | OCP_USER_SDMA,
3657};
3658
3659static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
3660 {
3661 .pa_start = 0x48070000,
3662 .pa_end = 0x480700ff,
3663 .flags = ADDR_TYPE_RT
3664 },
3665 { }
3666};
3667
3668/* l4_per -> i2c1 */
3669static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
3670 .master = &omap44xx_l4_per_hwmod,
3671 .slave = &omap44xx_i2c1_hwmod,
3672 .clk = "l4_div_ck",
3673 .addr = omap44xx_i2c1_addrs,
3674 .user = OCP_USER_MPU | OCP_USER_SDMA,
3675};
3676
3677static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
3678 {
3679 .pa_start = 0x48072000,
3680 .pa_end = 0x480720ff,
3681 .flags = ADDR_TYPE_RT
3682 },
3683 { }
3684};
3685
3686/* l4_per -> i2c2 */
3687static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
3688 .master = &omap44xx_l4_per_hwmod,
3689 .slave = &omap44xx_i2c2_hwmod,
3690 .clk = "l4_div_ck",
3691 .addr = omap44xx_i2c2_addrs,
3692 .user = OCP_USER_MPU | OCP_USER_SDMA,
3693};
3694
3695static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
3696 {
3697 .pa_start = 0x48060000,
3698 .pa_end = 0x480600ff,
3699 .flags = ADDR_TYPE_RT
3700 },
3701 { }
3702};
3703
3704/* l4_per -> i2c3 */
3705static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
3706 .master = &omap44xx_l4_per_hwmod,
3707 .slave = &omap44xx_i2c3_hwmod,
3708 .clk = "l4_div_ck",
3709 .addr = omap44xx_i2c3_addrs,
3710 .user = OCP_USER_MPU | OCP_USER_SDMA,
3711};
3712
3713static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
3714 {
3715 .pa_start = 0x48350000,
3716 .pa_end = 0x483500ff,
3717 .flags = ADDR_TYPE_RT
3718 },
3719 { }
3720};
3721
3722/* l4_per -> i2c4 */
3723static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
3724 .master = &omap44xx_l4_per_hwmod,
3725 .slave = &omap44xx_i2c4_hwmod,
3726 .clk = "l4_div_ck",
3727 .addr = omap44xx_i2c4_addrs,
3728 .user = OCP_USER_MPU | OCP_USER_SDMA,
3729};
3730
3731/* l3_main_2 -> ipu */
3732static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
3733 .master = &omap44xx_l3_main_2_hwmod,
3734 .slave = &omap44xx_ipu_hwmod,
5340 .clk = "l3_div_ck", 3735 .clk = "l3_div_ck",
5341 .user = OCP_USER_MPU | OCP_USER_SDMA, 3736 .user = OCP_USER_MPU | OCP_USER_SDMA,
5342}; 3737};
5343 3738
5344static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { 3739static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5345 .rev_offs = 0x0000, 3740 {
5346 .sysc_offs = 0x0010, 3741 .pa_start = 0x52000000,
5347 .syss_offs = 0x0014, 3742 .pa_end = 0x520000ff,
5348 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | 3743 .flags = ADDR_TYPE_RT
5349 SYSC_HAS_SOFTRESET), 3744 },
5350 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 3745 { }
5351 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5352 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
5353 .sysc_fields = &omap_hwmod_sysc_type2,
5354}; 3746};
5355 3747
5356static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { 3748/* l3_main_2 -> iss */
5357 .name = "usb_host_hs", 3749static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5358 .sysc = &omap44xx_usb_host_hs_sysc, 3750 .master = &omap44xx_l3_main_2_hwmod,
3751 .slave = &omap44xx_iss_hwmod,
3752 .clk = "l3_div_ck",
3753 .addr = omap44xx_iss_addrs,
3754 .user = OCP_USER_MPU | OCP_USER_SDMA,
5359}; 3755};
5360 3756
5361static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = { 3757static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5362 &omap44xx_usb_host_hs__l3_main_2, 3758 {
3759 .pa_start = 0x5a000000,
3760 .pa_end = 0x5a07ffff,
3761 .flags = ADDR_TYPE_RT
3762 },
3763 { }
3764};
3765
3766/* l3_main_2 -> iva */
3767static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
3768 .master = &omap44xx_l3_main_2_hwmod,
3769 .slave = &omap44xx_iva_hwmod,
3770 .clk = "l3_div_ck",
3771 .addr = omap44xx_iva_addrs,
3772 .user = OCP_USER_MPU,
3773};
3774
3775static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
3776 {
3777 .pa_start = 0x4a31c000,
3778 .pa_end = 0x4a31c07f,
3779 .flags = ADDR_TYPE_RT
3780 },
3781 { }
3782};
3783
3784/* l4_wkup -> kbd */
3785static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
3786 .master = &omap44xx_l4_wkup_hwmod,
3787 .slave = &omap44xx_kbd_hwmod,
3788 .clk = "l4_wkup_clk_mux_ck",
3789 .addr = omap44xx_kbd_addrs,
3790 .user = OCP_USER_MPU | OCP_USER_SDMA,
3791};
3792
3793static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
3794 {
3795 .pa_start = 0x4a0f4000,
3796 .pa_end = 0x4a0f41ff,
3797 .flags = ADDR_TYPE_RT
3798 },
3799 { }
3800};
3801
3802/* l4_cfg -> mailbox */
3803static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
3804 .master = &omap44xx_l4_cfg_hwmod,
3805 .slave = &omap44xx_mailbox_hwmod,
3806 .clk = "l4_div_ck",
3807 .addr = omap44xx_mailbox_addrs,
3808 .user = OCP_USER_MPU | OCP_USER_SDMA,
3809};
3810
3811static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
3812 {
3813 .name = "mpu",
3814 .pa_start = 0x40122000,
3815 .pa_end = 0x401220ff,
3816 .flags = ADDR_TYPE_RT
3817 },
3818 { }
3819};
3820
3821/* l4_abe -> mcbsp1 */
3822static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
3823 .master = &omap44xx_l4_abe_hwmod,
3824 .slave = &omap44xx_mcbsp1_hwmod,
3825 .clk = "ocp_abe_iclk",
3826 .addr = omap44xx_mcbsp1_addrs,
3827 .user = OCP_USER_MPU,
3828};
3829
3830static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
3831 {
3832 .name = "dma",
3833 .pa_start = 0x49022000,
3834 .pa_end = 0x490220ff,
3835 .flags = ADDR_TYPE_RT
3836 },
3837 { }
3838};
3839
3840/* l4_abe -> mcbsp1 (dma) */
3841static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
3842 .master = &omap44xx_l4_abe_hwmod,
3843 .slave = &omap44xx_mcbsp1_hwmod,
3844 .clk = "ocp_abe_iclk",
3845 .addr = omap44xx_mcbsp1_dma_addrs,
3846 .user = OCP_USER_SDMA,
3847};
3848
3849static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3850 {
3851 .name = "mpu",
3852 .pa_start = 0x40124000,
3853 .pa_end = 0x401240ff,
3854 .flags = ADDR_TYPE_RT
3855 },
3856 { }
3857};
3858
3859/* l4_abe -> mcbsp2 */
3860static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3861 .master = &omap44xx_l4_abe_hwmod,
3862 .slave = &omap44xx_mcbsp2_hwmod,
3863 .clk = "ocp_abe_iclk",
3864 .addr = omap44xx_mcbsp2_addrs,
3865 .user = OCP_USER_MPU,
3866};
3867
3868static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3869 {
3870 .name = "dma",
3871 .pa_start = 0x49024000,
3872 .pa_end = 0x490240ff,
3873 .flags = ADDR_TYPE_RT
3874 },
3875 { }
3876};
3877
3878/* l4_abe -> mcbsp2 (dma) */
3879static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3880 .master = &omap44xx_l4_abe_hwmod,
3881 .slave = &omap44xx_mcbsp2_hwmod,
3882 .clk = "ocp_abe_iclk",
3883 .addr = omap44xx_mcbsp2_dma_addrs,
3884 .user = OCP_USER_SDMA,
3885};
3886
3887static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3888 {
3889 .name = "mpu",
3890 .pa_start = 0x40126000,
3891 .pa_end = 0x401260ff,
3892 .flags = ADDR_TYPE_RT
3893 },
3894 { }
3895};
3896
3897/* l4_abe -> mcbsp3 */
3898static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3899 .master = &omap44xx_l4_abe_hwmod,
3900 .slave = &omap44xx_mcbsp3_hwmod,
3901 .clk = "ocp_abe_iclk",
3902 .addr = omap44xx_mcbsp3_addrs,
3903 .user = OCP_USER_MPU,
3904};
3905
3906static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3907 {
3908 .name = "dma",
3909 .pa_start = 0x49026000,
3910 .pa_end = 0x490260ff,
3911 .flags = ADDR_TYPE_RT
3912 },
3913 { }
3914};
3915
3916/* l4_abe -> mcbsp3 (dma) */
3917static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3918 .master = &omap44xx_l4_abe_hwmod,
3919 .slave = &omap44xx_mcbsp3_hwmod,
3920 .clk = "ocp_abe_iclk",
3921 .addr = omap44xx_mcbsp3_dma_addrs,
3922 .user = OCP_USER_SDMA,
3923};
3924
3925static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3926 {
3927 .pa_start = 0x48096000,
3928 .pa_end = 0x480960ff,
3929 .flags = ADDR_TYPE_RT
3930 },
3931 { }
3932};
3933
3934/* l4_per -> mcbsp4 */
3935static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3936 .master = &omap44xx_l4_per_hwmod,
3937 .slave = &omap44xx_mcbsp4_hwmod,
3938 .clk = "l4_div_ck",
3939 .addr = omap44xx_mcbsp4_addrs,
3940 .user = OCP_USER_MPU | OCP_USER_SDMA,
3941};
3942
3943static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3944 {
3945 .pa_start = 0x40132000,
3946 .pa_end = 0x4013207f,
3947 .flags = ADDR_TYPE_RT
3948 },
3949 { }
3950};
3951
3952/* l4_abe -> mcpdm */
3953static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3954 .master = &omap44xx_l4_abe_hwmod,
3955 .slave = &omap44xx_mcpdm_hwmod,
3956 .clk = "ocp_abe_iclk",
3957 .addr = omap44xx_mcpdm_addrs,
3958 .user = OCP_USER_MPU,
3959};
3960
3961static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3962 {
3963 .pa_start = 0x49032000,
3964 .pa_end = 0x4903207f,
3965 .flags = ADDR_TYPE_RT
3966 },
3967 { }
3968};
3969
3970/* l4_abe -> mcpdm (dma) */
3971static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3972 .master = &omap44xx_l4_abe_hwmod,
3973 .slave = &omap44xx_mcpdm_hwmod,
3974 .clk = "ocp_abe_iclk",
3975 .addr = omap44xx_mcpdm_dma_addrs,
3976 .user = OCP_USER_SDMA,
3977};
3978
3979static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3980 {
3981 .pa_start = 0x48098000,
3982 .pa_end = 0x480981ff,
3983 .flags = ADDR_TYPE_RT
3984 },
3985 { }
3986};
3987
3988/* l4_per -> mcspi1 */
3989static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3990 .master = &omap44xx_l4_per_hwmod,
3991 .slave = &omap44xx_mcspi1_hwmod,
3992 .clk = "l4_div_ck",
3993 .addr = omap44xx_mcspi1_addrs,
3994 .user = OCP_USER_MPU | OCP_USER_SDMA,
3995};
3996
3997static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3998 {
3999 .pa_start = 0x4809a000,
4000 .pa_end = 0x4809a1ff,
4001 .flags = ADDR_TYPE_RT
4002 },
4003 { }
4004};
4005
4006/* l4_per -> mcspi2 */
4007static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4008 .master = &omap44xx_l4_per_hwmod,
4009 .slave = &omap44xx_mcspi2_hwmod,
4010 .clk = "l4_div_ck",
4011 .addr = omap44xx_mcspi2_addrs,
4012 .user = OCP_USER_MPU | OCP_USER_SDMA,
4013};
4014
4015static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
4016 {
4017 .pa_start = 0x480b8000,
4018 .pa_end = 0x480b81ff,
4019 .flags = ADDR_TYPE_RT
4020 },
4021 { }
4022};
4023
4024/* l4_per -> mcspi3 */
4025static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4026 .master = &omap44xx_l4_per_hwmod,
4027 .slave = &omap44xx_mcspi3_hwmod,
4028 .clk = "l4_div_ck",
4029 .addr = omap44xx_mcspi3_addrs,
4030 .user = OCP_USER_MPU | OCP_USER_SDMA,
4031};
4032
4033static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
4034 {
4035 .pa_start = 0x480ba000,
4036 .pa_end = 0x480ba1ff,
4037 .flags = ADDR_TYPE_RT
4038 },
4039 { }
4040};
4041
4042/* l4_per -> mcspi4 */
4043static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4044 .master = &omap44xx_l4_per_hwmod,
4045 .slave = &omap44xx_mcspi4_hwmod,
4046 .clk = "l4_div_ck",
4047 .addr = omap44xx_mcspi4_addrs,
4048 .user = OCP_USER_MPU | OCP_USER_SDMA,
4049};
4050
4051static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
4052 {
4053 .pa_start = 0x4809c000,
4054 .pa_end = 0x4809c3ff,
4055 .flags = ADDR_TYPE_RT
4056 },
4057 { }
4058};
4059
4060/* l4_per -> mmc1 */
4061static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4062 .master = &omap44xx_l4_per_hwmod,
4063 .slave = &omap44xx_mmc1_hwmod,
4064 .clk = "l4_div_ck",
4065 .addr = omap44xx_mmc1_addrs,
4066 .user = OCP_USER_MPU | OCP_USER_SDMA,
4067};
4068
4069static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
4070 {
4071 .pa_start = 0x480b4000,
4072 .pa_end = 0x480b43ff,
4073 .flags = ADDR_TYPE_RT
4074 },
4075 { }
4076};
4077
4078/* l4_per -> mmc2 */
4079static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4080 .master = &omap44xx_l4_per_hwmod,
4081 .slave = &omap44xx_mmc2_hwmod,
4082 .clk = "l4_div_ck",
4083 .addr = omap44xx_mmc2_addrs,
4084 .user = OCP_USER_MPU | OCP_USER_SDMA,
4085};
4086
4087static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
4088 {
4089 .pa_start = 0x480ad000,
4090 .pa_end = 0x480ad3ff,
4091 .flags = ADDR_TYPE_RT
4092 },
4093 { }
4094};
4095
4096/* l4_per -> mmc3 */
4097static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4098 .master = &omap44xx_l4_per_hwmod,
4099 .slave = &omap44xx_mmc3_hwmod,
4100 .clk = "l4_div_ck",
4101 .addr = omap44xx_mmc3_addrs,
4102 .user = OCP_USER_MPU | OCP_USER_SDMA,
4103};
4104
4105static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
4106 {
4107 .pa_start = 0x480d1000,
4108 .pa_end = 0x480d13ff,
4109 .flags = ADDR_TYPE_RT
4110 },
4111 { }
4112};
4113
4114/* l4_per -> mmc4 */
4115static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4116 .master = &omap44xx_l4_per_hwmod,
4117 .slave = &omap44xx_mmc4_hwmod,
4118 .clk = "l4_div_ck",
4119 .addr = omap44xx_mmc4_addrs,
4120 .user = OCP_USER_MPU | OCP_USER_SDMA,
4121};
4122
4123static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
4124 {
4125 .pa_start = 0x480d5000,
4126 .pa_end = 0x480d53ff,
4127 .flags = ADDR_TYPE_RT
4128 },
4129 { }
4130};
4131
4132/* l4_per -> mmc5 */
4133static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4134 .master = &omap44xx_l4_per_hwmod,
4135 .slave = &omap44xx_mmc5_hwmod,
4136 .clk = "l4_div_ck",
4137 .addr = omap44xx_mmc5_addrs,
4138 .user = OCP_USER_MPU | OCP_USER_SDMA,
4139};
4140
4141static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4142 {
4143 .pa_start = 0x4a0dd000,
4144 .pa_end = 0x4a0dd03f,
4145 .flags = ADDR_TYPE_RT
4146 },
4147 { }
4148};
4149
4150/* l4_cfg -> smartreflex_core */
4151static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4152 .master = &omap44xx_l4_cfg_hwmod,
4153 .slave = &omap44xx_smartreflex_core_hwmod,
4154 .clk = "l4_div_ck",
4155 .addr = omap44xx_smartreflex_core_addrs,
4156 .user = OCP_USER_MPU | OCP_USER_SDMA,
4157};
4158
4159static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4160 {
4161 .pa_start = 0x4a0db000,
4162 .pa_end = 0x4a0db03f,
4163 .flags = ADDR_TYPE_RT
4164 },
4165 { }
4166};
4167
4168/* l4_cfg -> smartreflex_iva */
4169static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4170 .master = &omap44xx_l4_cfg_hwmod,
4171 .slave = &omap44xx_smartreflex_iva_hwmod,
4172 .clk = "l4_div_ck",
4173 .addr = omap44xx_smartreflex_iva_addrs,
4174 .user = OCP_USER_MPU | OCP_USER_SDMA,
4175};
4176
4177static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4178 {
4179 .pa_start = 0x4a0d9000,
4180 .pa_end = 0x4a0d903f,
4181 .flags = ADDR_TYPE_RT
4182 },
4183 { }
4184};
4185
4186/* l4_cfg -> smartreflex_mpu */
4187static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4188 .master = &omap44xx_l4_cfg_hwmod,
4189 .slave = &omap44xx_smartreflex_mpu_hwmod,
4190 .clk = "l4_div_ck",
4191 .addr = omap44xx_smartreflex_mpu_addrs,
4192 .user = OCP_USER_MPU | OCP_USER_SDMA,
4193};
4194
4195static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4196 {
4197 .pa_start = 0x4a0f6000,
4198 .pa_end = 0x4a0f6fff,
4199 .flags = ADDR_TYPE_RT
4200 },
4201 { }
4202};
4203
4204/* l4_cfg -> spinlock */
4205static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4206 .master = &omap44xx_l4_cfg_hwmod,
4207 .slave = &omap44xx_spinlock_hwmod,
4208 .clk = "l4_div_ck",
4209 .addr = omap44xx_spinlock_addrs,
4210 .user = OCP_USER_MPU | OCP_USER_SDMA,
4211};
4212
4213static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4214 {
4215 .pa_start = 0x4a318000,
4216 .pa_end = 0x4a31807f,
4217 .flags = ADDR_TYPE_RT
4218 },
4219 { }
4220};
4221
4222/* l4_wkup -> timer1 */
4223static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4224 .master = &omap44xx_l4_wkup_hwmod,
4225 .slave = &omap44xx_timer1_hwmod,
4226 .clk = "l4_wkup_clk_mux_ck",
4227 .addr = omap44xx_timer1_addrs,
4228 .user = OCP_USER_MPU | OCP_USER_SDMA,
4229};
4230
4231static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4232 {
4233 .pa_start = 0x48032000,
4234 .pa_end = 0x4803207f,
4235 .flags = ADDR_TYPE_RT
4236 },
4237 { }
4238};
4239
4240/* l4_per -> timer2 */
4241static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4242 .master = &omap44xx_l4_per_hwmod,
4243 .slave = &omap44xx_timer2_hwmod,
4244 .clk = "l4_div_ck",
4245 .addr = omap44xx_timer2_addrs,
4246 .user = OCP_USER_MPU | OCP_USER_SDMA,
4247};
4248
4249static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4250 {
4251 .pa_start = 0x48034000,
4252 .pa_end = 0x4803407f,
4253 .flags = ADDR_TYPE_RT
4254 },
4255 { }
4256};
4257
4258/* l4_per -> timer3 */
4259static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4260 .master = &omap44xx_l4_per_hwmod,
4261 .slave = &omap44xx_timer3_hwmod,
4262 .clk = "l4_div_ck",
4263 .addr = omap44xx_timer3_addrs,
4264 .user = OCP_USER_MPU | OCP_USER_SDMA,
4265};
4266
4267static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4268 {
4269 .pa_start = 0x48036000,
4270 .pa_end = 0x4803607f,
4271 .flags = ADDR_TYPE_RT
4272 },
4273 { }
4274};
4275
4276/* l4_per -> timer4 */
4277static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4278 .master = &omap44xx_l4_per_hwmod,
4279 .slave = &omap44xx_timer4_hwmod,
4280 .clk = "l4_div_ck",
4281 .addr = omap44xx_timer4_addrs,
4282 .user = OCP_USER_MPU | OCP_USER_SDMA,
4283};
4284
4285static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4286 {
4287 .pa_start = 0x40138000,
4288 .pa_end = 0x4013807f,
4289 .flags = ADDR_TYPE_RT
4290 },
4291 { }
4292};
4293
4294/* l4_abe -> timer5 */
4295static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4296 .master = &omap44xx_l4_abe_hwmod,
4297 .slave = &omap44xx_timer5_hwmod,
4298 .clk = "ocp_abe_iclk",
4299 .addr = omap44xx_timer5_addrs,
4300 .user = OCP_USER_MPU,
4301};
4302
4303static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4304 {
4305 .pa_start = 0x49038000,
4306 .pa_end = 0x4903807f,
4307 .flags = ADDR_TYPE_RT
4308 },
4309 { }
4310};
4311
4312/* l4_abe -> timer5 (dma) */
4313static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4314 .master = &omap44xx_l4_abe_hwmod,
4315 .slave = &omap44xx_timer5_hwmod,
4316 .clk = "ocp_abe_iclk",
4317 .addr = omap44xx_timer5_dma_addrs,
4318 .user = OCP_USER_SDMA,
4319};
4320
4321static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4322 {
4323 .pa_start = 0x4013a000,
4324 .pa_end = 0x4013a07f,
4325 .flags = ADDR_TYPE_RT
4326 },
4327 { }
4328};
4329
4330/* l4_abe -> timer6 */
4331static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4332 .master = &omap44xx_l4_abe_hwmod,
4333 .slave = &omap44xx_timer6_hwmod,
4334 .clk = "ocp_abe_iclk",
4335 .addr = omap44xx_timer6_addrs,
4336 .user = OCP_USER_MPU,
4337};
4338
4339static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4340 {
4341 .pa_start = 0x4903a000,
4342 .pa_end = 0x4903a07f,
4343 .flags = ADDR_TYPE_RT
4344 },
4345 { }
4346};
4347
4348/* l4_abe -> timer6 (dma) */
4349static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4350 .master = &omap44xx_l4_abe_hwmod,
4351 .slave = &omap44xx_timer6_hwmod,
4352 .clk = "ocp_abe_iclk",
4353 .addr = omap44xx_timer6_dma_addrs,
4354 .user = OCP_USER_SDMA,
4355};
4356
4357static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4358 {
4359 .pa_start = 0x4013c000,
4360 .pa_end = 0x4013c07f,
4361 .flags = ADDR_TYPE_RT
4362 },
4363 { }
4364};
4365
4366/* l4_abe -> timer7 */
4367static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4368 .master = &omap44xx_l4_abe_hwmod,
4369 .slave = &omap44xx_timer7_hwmod,
4370 .clk = "ocp_abe_iclk",
4371 .addr = omap44xx_timer7_addrs,
4372 .user = OCP_USER_MPU,
4373};
4374
4375static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4376 {
4377 .pa_start = 0x4903c000,
4378 .pa_end = 0x4903c07f,
4379 .flags = ADDR_TYPE_RT
4380 },
4381 { }
4382};
4383
4384/* l4_abe -> timer7 (dma) */
4385static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4386 .master = &omap44xx_l4_abe_hwmod,
4387 .slave = &omap44xx_timer7_hwmod,
4388 .clk = "ocp_abe_iclk",
4389 .addr = omap44xx_timer7_dma_addrs,
4390 .user = OCP_USER_SDMA,
4391};
4392
4393static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4394 {
4395 .pa_start = 0x4013e000,
4396 .pa_end = 0x4013e07f,
4397 .flags = ADDR_TYPE_RT
4398 },
4399 { }
4400};
4401
4402/* l4_abe -> timer8 */
4403static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4404 .master = &omap44xx_l4_abe_hwmod,
4405 .slave = &omap44xx_timer8_hwmod,
4406 .clk = "ocp_abe_iclk",
4407 .addr = omap44xx_timer8_addrs,
4408 .user = OCP_USER_MPU,
4409};
4410
4411static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4412 {
4413 .pa_start = 0x4903e000,
4414 .pa_end = 0x4903e07f,
4415 .flags = ADDR_TYPE_RT
4416 },
4417 { }
4418};
4419
4420/* l4_abe -> timer8 (dma) */
4421static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4422 .master = &omap44xx_l4_abe_hwmod,
4423 .slave = &omap44xx_timer8_hwmod,
4424 .clk = "ocp_abe_iclk",
4425 .addr = omap44xx_timer8_dma_addrs,
4426 .user = OCP_USER_SDMA,
4427};
4428
4429static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4430 {
4431 .pa_start = 0x4803e000,
4432 .pa_end = 0x4803e07f,
4433 .flags = ADDR_TYPE_RT
4434 },
4435 { }
4436};
4437
4438/* l4_per -> timer9 */
4439static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4440 .master = &omap44xx_l4_per_hwmod,
4441 .slave = &omap44xx_timer9_hwmod,
4442 .clk = "l4_div_ck",
4443 .addr = omap44xx_timer9_addrs,
4444 .user = OCP_USER_MPU | OCP_USER_SDMA,
4445};
4446
4447static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4448 {
4449 .pa_start = 0x48086000,
4450 .pa_end = 0x4808607f,
4451 .flags = ADDR_TYPE_RT
4452 },
4453 { }
4454};
4455
4456/* l4_per -> timer10 */
4457static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4458 .master = &omap44xx_l4_per_hwmod,
4459 .slave = &omap44xx_timer10_hwmod,
4460 .clk = "l4_div_ck",
4461 .addr = omap44xx_timer10_addrs,
4462 .user = OCP_USER_MPU | OCP_USER_SDMA,
4463};
4464
4465static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4466 {
4467 .pa_start = 0x48088000,
4468 .pa_end = 0x4808807f,
4469 .flags = ADDR_TYPE_RT
4470 },
4471 { }
4472};
4473
4474/* l4_per -> timer11 */
4475static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4476 .master = &omap44xx_l4_per_hwmod,
4477 .slave = &omap44xx_timer11_hwmod,
4478 .clk = "l4_div_ck",
4479 .addr = omap44xx_timer11_addrs,
4480 .user = OCP_USER_MPU | OCP_USER_SDMA,
4481};
4482
4483static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4484 {
4485 .pa_start = 0x4806a000,
4486 .pa_end = 0x4806a0ff,
4487 .flags = ADDR_TYPE_RT
4488 },
4489 { }
4490};
4491
4492/* l4_per -> uart1 */
4493static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4494 .master = &omap44xx_l4_per_hwmod,
4495 .slave = &omap44xx_uart1_hwmod,
4496 .clk = "l4_div_ck",
4497 .addr = omap44xx_uart1_addrs,
4498 .user = OCP_USER_MPU | OCP_USER_SDMA,
4499};
4500
4501static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4502 {
4503 .pa_start = 0x4806c000,
4504 .pa_end = 0x4806c0ff,
4505 .flags = ADDR_TYPE_RT
4506 },
4507 { }
4508};
4509
4510/* l4_per -> uart2 */
4511static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4512 .master = &omap44xx_l4_per_hwmod,
4513 .slave = &omap44xx_uart2_hwmod,
4514 .clk = "l4_div_ck",
4515 .addr = omap44xx_uart2_addrs,
4516 .user = OCP_USER_MPU | OCP_USER_SDMA,
4517};
4518
4519static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4520 {
4521 .pa_start = 0x48020000,
4522 .pa_end = 0x480200ff,
4523 .flags = ADDR_TYPE_RT
4524 },
4525 { }
4526};
4527
4528/* l4_per -> uart3 */
4529static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4530 .master = &omap44xx_l4_per_hwmod,
4531 .slave = &omap44xx_uart3_hwmod,
4532 .clk = "l4_div_ck",
4533 .addr = omap44xx_uart3_addrs,
4534 .user = OCP_USER_MPU | OCP_USER_SDMA,
4535};
4536
4537static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4538 {
4539 .pa_start = 0x4806e000,
4540 .pa_end = 0x4806e0ff,
4541 .flags = ADDR_TYPE_RT
4542 },
4543 { }
4544};
4545
4546/* l4_per -> uart4 */
4547static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4548 .master = &omap44xx_l4_per_hwmod,
4549 .slave = &omap44xx_uart4_hwmod,
4550 .clk = "l4_div_ck",
4551 .addr = omap44xx_uart4_addrs,
4552 .user = OCP_USER_MPU | OCP_USER_SDMA,
5363}; 4553};
5364 4554
5365static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { 4555static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
@@ -5382,12 +4572,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5382 {} 4572 {}
5383}; 4573};
5384 4574
5385static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { 4575/* l4_cfg -> usb_host_hs */
5386 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
5387 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
5388 { .irq = -1 }
5389};
5390
5391static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { 4576static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5392 .master = &omap44xx_l4_cfg_hwmod, 4577 .master = &omap44xx_l4_cfg_hwmod,
5393 .slave = &omap44xx_usb_host_hs_hwmod, 4578 .slave = &omap44xx_usb_host_hs_hwmod,
@@ -5396,100 +4581,22 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5396 .user = OCP_USER_MPU | OCP_USER_SDMA, 4581 .user = OCP_USER_MPU | OCP_USER_SDMA,
5397}; 4582};
5398 4583
5399static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = { 4584static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5400 &omap44xx_l4_cfg__usb_host_hs, 4585 {
5401}; 4586 .pa_start = 0x4a0ab000,
5402 4587 .pa_end = 0x4a0ab003,
5403static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { 4588 .flags = ADDR_TYPE_RT
5404 .name = "usb_host_hs",
5405 .class = &omap44xx_usb_host_hs_hwmod_class,
5406 .clkdm_name = "l3_init_clkdm",
5407 .main_clk = "usb_host_hs_fck",
5408 .prcm = {
5409 .omap4 = {
5410 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
5411 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
5412 .modulemode = MODULEMODE_SWCTRL,
5413 },
5414 }, 4589 },
5415 .mpu_irqs = omap44xx_usb_host_hs_irqs, 4590 { }
5416 .slaves = omap44xx_usb_host_hs_slaves,
5417 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
5418 .masters = omap44xx_usb_host_hs_masters,
5419 .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
5420
5421 /*
5422 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
5423 * id: i660
5424 *
5425 * Description:
5426 * In the following configuration :
5427 * - USBHOST module is set to smart-idle mode
5428 * - PRCM asserts idle_req to the USBHOST module ( This typically
5429 * happens when the system is going to a low power mode : all ports
5430 * have been suspended, the master part of the USBHOST module has
5431 * entered the standby state, and SW has cut the functional clocks)
5432 * - an USBHOST interrupt occurs before the module is able to answer
5433 * idle_ack, typically a remote wakeup IRQ.
5434 * Then the USB HOST module will enter a deadlock situation where it
5435 * is no more accessible nor functional.
5436 *
5437 * Workaround:
5438 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
5439 */
5440
5441 /*
5442 * Errata: USB host EHCI may stall when entering smart-standby mode
5443 * Id: i571
5444 *
5445 * Description:
5446 * When the USBHOST module is set to smart-standby mode, and when it is
5447 * ready to enter the standby state (i.e. all ports are suspended and
5448 * all attached devices are in suspend mode), then it can wrongly assert
5449 * the Mstandby signal too early while there are still some residual OCP
5450 * transactions ongoing. If this condition occurs, the internal state
5451 * machine may go to an undefined state and the USB link may be stuck
5452 * upon the next resume.
5453 *
5454 * Workaround:
5455 * Don't use smart standby; use only force standby,
5456 * hence HWMOD_SWSUP_MSTANDBY
5457 */
5458
5459 /*
5460 * During system boot; If the hwmod framework resets the module
5461 * the module will have smart idle settings; which can lead to deadlock
5462 * (above Errata Id:i660); so, dont reset the module during boot;
5463 * Use HWMOD_INIT_NO_RESET.
5464 */
5465
5466 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
5467 HWMOD_INIT_NO_RESET,
5468};
5469
5470/*
5471 * 'usb_tll_hs' class
5472 * usb_tll_hs module is the adapter on the usb_host_hs ports
5473 */
5474static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
5475 .rev_offs = 0x0000,
5476 .sysc_offs = 0x0010,
5477 .syss_offs = 0x0014,
5478 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
5479 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
5480 SYSC_HAS_AUTOIDLE),
5481 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
5482 .sysc_fields = &omap_hwmod_sysc_type1,
5483};
5484
5485static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
5486 .name = "usb_tll_hs",
5487 .sysc = &omap44xx_usb_tll_hs_sysc,
5488}; 4591};
5489 4592
5490static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { 4593/* l4_cfg -> usb_otg_hs */
5491 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, 4594static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5492 { .irq = -1 } 4595 .master = &omap44xx_l4_cfg_hwmod,
4596 .slave = &omap44xx_usb_otg_hs_hwmod,
4597 .clk = "l4_div_ck",
4598 .addr = omap44xx_usb_otg_hs_addrs,
4599 .user = OCP_USER_MPU | OCP_USER_SDMA,
5493}; 4600};
5494 4601
5495static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { 4602static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
@@ -5502,6 +4609,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5502 {} 4609 {}
5503}; 4610};
5504 4611
4612/* l4_cfg -> usb_tll_hs */
5505static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { 4613static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5506 .master = &omap44xx_l4_cfg_hwmod, 4614 .master = &omap44xx_l4_cfg_hwmod,
5507 .slave = &omap44xx_usb_tll_hs_hwmod, 4615 .slave = &omap44xx_usb_tll_hs_hwmod,
@@ -5510,181 +4618,184 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5510 .user = OCP_USER_MPU | OCP_USER_SDMA, 4618 .user = OCP_USER_MPU | OCP_USER_SDMA,
5511}; 4619};
5512 4620
5513static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = { 4621static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5514 &omap44xx_l4_cfg__usb_tll_hs, 4622 {
4623 .pa_start = 0x4a314000,
4624 .pa_end = 0x4a31407f,
4625 .flags = ADDR_TYPE_RT
4626 },
4627 { }
5515}; 4628};
5516 4629
5517static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { 4630/* l4_wkup -> wd_timer2 */
5518 .name = "usb_tll_hs", 4631static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5519 .class = &omap44xx_usb_tll_hs_hwmod_class, 4632 .master = &omap44xx_l4_wkup_hwmod,
5520 .clkdm_name = "l3_init_clkdm", 4633 .slave = &omap44xx_wd_timer2_hwmod,
5521 .main_clk = "usb_tll_hs_ick", 4634 .clk = "l4_wkup_clk_mux_ck",
5522 .prcm = { 4635 .addr = omap44xx_wd_timer2_addrs,
5523 .omap4 = { 4636 .user = OCP_USER_MPU | OCP_USER_SDMA,
5524 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, 4637};
5525 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, 4638
5526 .modulemode = MODULEMODE_HWCTRL, 4639static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5527 }, 4640 {
4641 .pa_start = 0x40130000,
4642 .pa_end = 0x4013007f,
4643 .flags = ADDR_TYPE_RT
5528 }, 4644 },
5529 .mpu_irqs = omap44xx_usb_tll_hs_irqs, 4645 { }
5530 .slaves = omap44xx_usb_tll_hs_slaves, 4646};
5531 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves), 4647
4648/* l4_abe -> wd_timer3 */
4649static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4650 .master = &omap44xx_l4_abe_hwmod,
4651 .slave = &omap44xx_wd_timer3_hwmod,
4652 .clk = "ocp_abe_iclk",
4653 .addr = omap44xx_wd_timer3_addrs,
4654 .user = OCP_USER_MPU,
5532}; 4655};
5533 4656
5534static __initdata struct omap_hwmod *omap44xx_hwmods[] = { 4657static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5535 4658 {
5536 /* dmm class */ 4659 .pa_start = 0x49030000,
5537 &omap44xx_dmm_hwmod, 4660 .pa_end = 0x4903007f,
5538 4661 .flags = ADDR_TYPE_RT
5539 /* emif_fw class */ 4662 },
5540 &omap44xx_emif_fw_hwmod, 4663 { }
5541 4664};
5542 /* l3 class */ 4665
5543 &omap44xx_l3_instr_hwmod, 4666/* l4_abe -> wd_timer3 (dma) */
5544 &omap44xx_l3_main_1_hwmod, 4667static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5545 &omap44xx_l3_main_2_hwmod, 4668 .master = &omap44xx_l4_abe_hwmod,
5546 &omap44xx_l3_main_3_hwmod, 4669 .slave = &omap44xx_wd_timer3_hwmod,
5547 4670 .clk = "ocp_abe_iclk",
5548 /* l4 class */ 4671 .addr = omap44xx_wd_timer3_dma_addrs,
5549 &omap44xx_l4_abe_hwmod, 4672 .user = OCP_USER_SDMA,
5550 &omap44xx_l4_cfg_hwmod, 4673};
5551 &omap44xx_l4_per_hwmod, 4674
5552 &omap44xx_l4_wkup_hwmod, 4675static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5553 4676 &omap44xx_l3_main_1__dmm,
5554 /* mpu_bus class */ 4677 &omap44xx_mpu__dmm,
5555 &omap44xx_mpu_private_hwmod, 4678 &omap44xx_dmm__emif_fw,
5556 4679 &omap44xx_l4_cfg__emif_fw,
5557 /* aess class */ 4680 &omap44xx_iva__l3_instr,
5558/* &omap44xx_aess_hwmod, */ 4681 &omap44xx_l3_main_3__l3_instr,
5559 4682 &omap44xx_dsp__l3_main_1,
5560 /* bandgap class */ 4683 &omap44xx_dss__l3_main_1,
5561 &omap44xx_bandgap_hwmod, 4684 &omap44xx_l3_main_2__l3_main_1,
5562 4685 &omap44xx_l4_cfg__l3_main_1,
5563 /* counter class */ 4686 &omap44xx_mmc1__l3_main_1,
5564/* &omap44xx_counter_32k_hwmod, */ 4687 &omap44xx_mmc2__l3_main_1,
5565 4688 &omap44xx_mpu__l3_main_1,
5566 /* dma class */ 4689 &omap44xx_dma_system__l3_main_2,
5567 &omap44xx_dma_system_hwmod, 4690 &omap44xx_hsi__l3_main_2,
5568 4691 &omap44xx_ipu__l3_main_2,
5569 /* dmic class */ 4692 &omap44xx_iss__l3_main_2,
5570 &omap44xx_dmic_hwmod, 4693 &omap44xx_iva__l3_main_2,
5571 4694 &omap44xx_l3_main_1__l3_main_2,
5572 /* dsp class */ 4695 &omap44xx_l4_cfg__l3_main_2,
5573 &omap44xx_dsp_hwmod, 4696 &omap44xx_usb_host_hs__l3_main_2,
5574 &omap44xx_dsp_c0_hwmod, 4697 &omap44xx_usb_otg_hs__l3_main_2,
5575 4698 &omap44xx_l3_main_1__l3_main_3,
5576 /* dss class */ 4699 &omap44xx_l3_main_2__l3_main_3,
5577 &omap44xx_dss_hwmod, 4700 &omap44xx_l4_cfg__l3_main_3,
5578 &omap44xx_dss_dispc_hwmod, 4701 &omap44xx_aess__l4_abe,
5579 &omap44xx_dss_dsi1_hwmod, 4702 &omap44xx_dsp__l4_abe,
5580 &omap44xx_dss_dsi2_hwmod, 4703 &omap44xx_l3_main_1__l4_abe,
5581 &omap44xx_dss_hdmi_hwmod, 4704 &omap44xx_mpu__l4_abe,
5582 &omap44xx_dss_rfbi_hwmod, 4705 &omap44xx_l3_main_1__l4_cfg,
5583 &omap44xx_dss_venc_hwmod, 4706 &omap44xx_l3_main_2__l4_per,
5584 4707 &omap44xx_l4_cfg__l4_wkup,
5585 /* gpio class */ 4708 &omap44xx_mpu__mpu_private,
5586 &omap44xx_gpio1_hwmod, 4709 &omap44xx_l4_abe__aess,
5587 &omap44xx_gpio2_hwmod, 4710 &omap44xx_l4_abe__aess_dma,
5588 &omap44xx_gpio3_hwmod, 4711 &omap44xx_l4_wkup__counter_32k,
5589 &omap44xx_gpio4_hwmod, 4712 &omap44xx_l4_cfg__dma_system,
5590 &omap44xx_gpio5_hwmod, 4713 &omap44xx_l4_abe__dmic,
5591 &omap44xx_gpio6_hwmod, 4714 &omap44xx_l4_abe__dmic_dma,
5592 4715 &omap44xx_dsp__iva,
5593 /* hsi class */ 4716 &omap44xx_l4_cfg__dsp,
5594/* &omap44xx_hsi_hwmod, */ 4717 &omap44xx_l3_main_2__dss,
5595 4718 &omap44xx_l4_per__dss,
5596 /* i2c class */ 4719 &omap44xx_l3_main_2__dss_dispc,
5597 &omap44xx_i2c1_hwmod, 4720 &omap44xx_l4_per__dss_dispc,
5598 &omap44xx_i2c2_hwmod, 4721 &omap44xx_l3_main_2__dss_dsi1,
5599 &omap44xx_i2c3_hwmod, 4722 &omap44xx_l4_per__dss_dsi1,
5600 &omap44xx_i2c4_hwmod, 4723 &omap44xx_l3_main_2__dss_dsi2,
5601 4724 &omap44xx_l4_per__dss_dsi2,
5602 /* ipu class */ 4725 &omap44xx_l3_main_2__dss_hdmi,
5603 &omap44xx_ipu_hwmod, 4726 &omap44xx_l4_per__dss_hdmi,
5604 &omap44xx_ipu_c0_hwmod, 4727 &omap44xx_l3_main_2__dss_rfbi,
5605 &omap44xx_ipu_c1_hwmod, 4728 &omap44xx_l4_per__dss_rfbi,
5606 4729 &omap44xx_l3_main_2__dss_venc,
5607 /* iss class */ 4730 &omap44xx_l4_per__dss_venc,
5608/* &omap44xx_iss_hwmod, */ 4731 &omap44xx_l4_wkup__gpio1,
5609 4732 &omap44xx_l4_per__gpio2,
5610 /* iva class */ 4733 &omap44xx_l4_per__gpio3,
5611 &omap44xx_iva_hwmod, 4734 &omap44xx_l4_per__gpio4,
5612 &omap44xx_iva_seq0_hwmod, 4735 &omap44xx_l4_per__gpio5,
5613 &omap44xx_iva_seq1_hwmod, 4736 &omap44xx_l4_per__gpio6,
5614 4737 &omap44xx_l4_cfg__hsi,
5615 /* kbd class */ 4738 &omap44xx_l4_per__i2c1,
5616 &omap44xx_kbd_hwmod, 4739 &omap44xx_l4_per__i2c2,
5617 4740 &omap44xx_l4_per__i2c3,
5618 /* mailbox class */ 4741 &omap44xx_l4_per__i2c4,
5619 &omap44xx_mailbox_hwmod, 4742 &omap44xx_l3_main_2__ipu,
5620 4743 &omap44xx_l3_main_2__iss,
5621 /* mcbsp class */ 4744 &omap44xx_l3_main_2__iva,
5622 &omap44xx_mcbsp1_hwmod, 4745 &omap44xx_l4_wkup__kbd,
5623 &omap44xx_mcbsp2_hwmod, 4746 &omap44xx_l4_cfg__mailbox,
5624 &omap44xx_mcbsp3_hwmod, 4747 &omap44xx_l4_abe__mcbsp1,
5625 &omap44xx_mcbsp4_hwmod, 4748 &omap44xx_l4_abe__mcbsp1_dma,
5626 4749 &omap44xx_l4_abe__mcbsp2,
5627 /* mcpdm class */ 4750 &omap44xx_l4_abe__mcbsp2_dma,
5628 &omap44xx_mcpdm_hwmod, 4751 &omap44xx_l4_abe__mcbsp3,
5629 4752 &omap44xx_l4_abe__mcbsp3_dma,
5630 /* mcspi class */ 4753 &omap44xx_l4_per__mcbsp4,
5631 &omap44xx_mcspi1_hwmod, 4754 &omap44xx_l4_abe__mcpdm,
5632 &omap44xx_mcspi2_hwmod, 4755 &omap44xx_l4_abe__mcpdm_dma,
5633 &omap44xx_mcspi3_hwmod, 4756 &omap44xx_l4_per__mcspi1,
5634 &omap44xx_mcspi4_hwmod, 4757 &omap44xx_l4_per__mcspi2,
5635 4758 &omap44xx_l4_per__mcspi3,
5636 /* mmc class */ 4759 &omap44xx_l4_per__mcspi4,
5637 &omap44xx_mmc1_hwmod, 4760 &omap44xx_l4_per__mmc1,
5638 &omap44xx_mmc2_hwmod, 4761 &omap44xx_l4_per__mmc2,
5639 &omap44xx_mmc3_hwmod, 4762 &omap44xx_l4_per__mmc3,
5640 &omap44xx_mmc4_hwmod, 4763 &omap44xx_l4_per__mmc4,
5641 &omap44xx_mmc5_hwmod, 4764 &omap44xx_l4_per__mmc5,
5642 4765 &omap44xx_l4_cfg__smartreflex_core,
5643 /* mpu class */ 4766 &omap44xx_l4_cfg__smartreflex_iva,
5644 &omap44xx_mpu_hwmod, 4767 &omap44xx_l4_cfg__smartreflex_mpu,
5645 4768 &omap44xx_l4_cfg__spinlock,
5646 /* smartreflex class */ 4769 &omap44xx_l4_wkup__timer1,
5647 &omap44xx_smartreflex_core_hwmod, 4770 &omap44xx_l4_per__timer2,
5648 &omap44xx_smartreflex_iva_hwmod, 4771 &omap44xx_l4_per__timer3,
5649 &omap44xx_smartreflex_mpu_hwmod, 4772 &omap44xx_l4_per__timer4,
5650 4773 &omap44xx_l4_abe__timer5,
5651 /* spinlock class */ 4774 &omap44xx_l4_abe__timer5_dma,
5652 &omap44xx_spinlock_hwmod, 4775 &omap44xx_l4_abe__timer6,
5653 4776 &omap44xx_l4_abe__timer6_dma,
5654 /* timer class */ 4777 &omap44xx_l4_abe__timer7,
5655 &omap44xx_timer1_hwmod, 4778 &omap44xx_l4_abe__timer7_dma,
5656 &omap44xx_timer2_hwmod, 4779 &omap44xx_l4_abe__timer8,
5657 &omap44xx_timer3_hwmod, 4780 &omap44xx_l4_abe__timer8_dma,
5658 &omap44xx_timer4_hwmod, 4781 &omap44xx_l4_per__timer9,
5659 &omap44xx_timer5_hwmod, 4782 &omap44xx_l4_per__timer10,
5660 &omap44xx_timer6_hwmod, 4783 &omap44xx_l4_per__timer11,
5661 &omap44xx_timer7_hwmod, 4784 &omap44xx_l4_per__uart1,
5662 &omap44xx_timer8_hwmod, 4785 &omap44xx_l4_per__uart2,
5663 &omap44xx_timer9_hwmod, 4786 &omap44xx_l4_per__uart3,
5664 &omap44xx_timer10_hwmod, 4787 &omap44xx_l4_per__uart4,
5665 &omap44xx_timer11_hwmod, 4788 &omap44xx_l4_cfg__usb_host_hs,
5666 4789 &omap44xx_l4_cfg__usb_otg_hs,
5667 /* uart class */ 4790 &omap44xx_l4_cfg__usb_tll_hs,
5668 &omap44xx_uart1_hwmod, 4791 &omap44xx_l4_wkup__wd_timer2,
5669 &omap44xx_uart2_hwmod, 4792 &omap44xx_l4_abe__wd_timer3,
5670 &omap44xx_uart3_hwmod, 4793 &omap44xx_l4_abe__wd_timer3_dma,
5671 &omap44xx_uart4_hwmod,
5672
5673 /* usb host class */
5674 &omap44xx_usb_host_hs_hwmod,
5675 &omap44xx_usb_tll_hs_hwmod,
5676
5677 /* usb_otg_hs class */
5678 &omap44xx_usb_otg_hs_hwmod,
5679
5680 /* wd_timer class */
5681 &omap44xx_wd_timer2_hwmod,
5682 &omap44xx_wd_timer3_hwmod,
5683 NULL, 4794 NULL,
5684}; 4795};
5685 4796
5686int __init omap44xx_hwmod_init(void) 4797int __init omap44xx_hwmod_init(void)
5687{ 4798{
5688 return omap_hwmod_register(omap44xx_hwmods); 4799 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
5689} 4800}
5690 4801
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index ad5d8f04c0b..7aa9156d50a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -19,18 +19,6 @@
19#include "display.h" 19#include "display.h"
20 20
21/* Common address space across OMAP2xxx */ 21/* Common address space across OMAP2xxx */
22extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
23extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
24extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
25extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
26extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
27extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
28extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
29extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
30extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
31extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
32extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
33extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
34extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[]; 22extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
35 23
36/* Common address space across OMAP2xxx/3xxx */ 24/* Common address space across OMAP2xxx/3xxx */
@@ -54,6 +42,64 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
54/* Common IP block data across OMAP2xxx */ 42/* Common IP block data across OMAP2xxx */
55extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[]; 43extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
56extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[]; 44extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
45extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
46extern struct omap_hwmod omap2xxx_l3_main_hwmod;
47extern struct omap_hwmod omap2xxx_l4_core_hwmod;
48extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
49extern struct omap_hwmod omap2xxx_mpu_hwmod;
50extern struct omap_hwmod omap2xxx_iva_hwmod;
51extern struct omap_hwmod omap2xxx_timer1_hwmod;
52extern struct omap_hwmod omap2xxx_timer2_hwmod;
53extern struct omap_hwmod omap2xxx_timer3_hwmod;
54extern struct omap_hwmod omap2xxx_timer4_hwmod;
55extern struct omap_hwmod omap2xxx_timer5_hwmod;
56extern struct omap_hwmod omap2xxx_timer6_hwmod;
57extern struct omap_hwmod omap2xxx_timer7_hwmod;
58extern struct omap_hwmod omap2xxx_timer8_hwmod;
59extern struct omap_hwmod omap2xxx_timer9_hwmod;
60extern struct omap_hwmod omap2xxx_timer10_hwmod;
61extern struct omap_hwmod omap2xxx_timer11_hwmod;
62extern struct omap_hwmod omap2xxx_timer12_hwmod;
63extern struct omap_hwmod omap2xxx_wd_timer2_hwmod;
64extern struct omap_hwmod omap2xxx_uart1_hwmod;
65extern struct omap_hwmod omap2xxx_uart2_hwmod;
66extern struct omap_hwmod omap2xxx_uart3_hwmod;
67extern struct omap_hwmod omap2xxx_dss_core_hwmod;
68extern struct omap_hwmod omap2xxx_dss_dispc_hwmod;
69extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod;
70extern struct omap_hwmod omap2xxx_dss_venc_hwmod;
71extern struct omap_hwmod omap2xxx_gpio1_hwmod;
72extern struct omap_hwmod omap2xxx_gpio2_hwmod;
73extern struct omap_hwmod omap2xxx_gpio3_hwmod;
74extern struct omap_hwmod omap2xxx_gpio4_hwmod;
75extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
76extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
77
78/* Common interface data across OMAP2xxx */
79extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
80extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main;
81extern struct omap_hwmod_ocp_if omap2xxx_dss__l3;
82extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup;
83extern struct omap_hwmod_ocp_if omap2_l4_core__uart1;
84extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
85extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
86extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
87extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
88extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2;
89extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
90extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
91extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
92extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6;
93extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7;
94extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8;
95extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9;
96extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10;
97extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11;
98extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12;
99extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
100extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
101extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
102extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
57 103
58/* Common IP block data */ 104/* Common IP block data */
59extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[]; 105extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
@@ -94,6 +140,7 @@ extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
94extern struct omap_hwmod_irq_info omap2_dma_system_irqs[]; 140extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
95extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[]; 141extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
96extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[]; 142extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
143extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
97 144
98/* OMAP hwmod classes - forward declarations */ 145/* OMAP hwmod classes - forward declarations */
99extern struct omap_hwmod_class l3_hwmod_class; 146extern struct omap_hwmod_class l3_hwmod_class;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 36fa90b6ece..78564895e91 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -38,27 +38,6 @@ static inline int omap4_opp_init(void)
38} 38}
39#endif 39#endif
40 40
41/*
42 * cpuidle mach specific parameters
43 *
44 * The board code can override the default C-states definition using
45 * omap3_pm_init_cpuidle
46 */
47struct cpuidle_params {
48 u32 exit_latency; /* exit_latency = sleep + wake-up latencies */
49 u32 target_residency;
50 u8 valid; /* validates the C-state */
51};
52
53#if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
54extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params);
55#else
56static
57inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
58{
59}
60#endif
61
62extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); 41extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
63extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); 42extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
64 43
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 95442b69ae2..facfffca9ea 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -171,8 +171,6 @@ static int omap2_allow_mpu_retention(void)
171 171
172static void omap2_enter_mpu_retention(void) 172static void omap2_enter_mpu_retention(void)
173{ 173{
174 int only_idle = 0;
175
176 /* Putting MPU into the WFI state while a transfer is active 174 /* Putting MPU into the WFI state while a transfer is active
177 * seems to cause the I2C block to timeout. Why? Good question. */ 175 * seems to cause the I2C block to timeout. Why? Good question. */
178 if (omap2_i2c_active()) 176 if (omap2_i2c_active())
@@ -195,7 +193,6 @@ static void omap2_enter_mpu_retention(void)
195 193
196 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, 194 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
197 OMAP2_PM_PWSTCTRL); 195 OMAP2_PM_PWSTCTRL);
198 only_idle = 1;
199 } 196 }
200 197
201 omap2_sram_idle(); 198 omap2_sram_idle();
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 703bd109925..8b43aefba0e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -273,7 +273,7 @@ void omap_sram_idle(void)
273 int per_next_state = PWRDM_POWER_ON; 273 int per_next_state = PWRDM_POWER_ON;
274 int core_next_state = PWRDM_POWER_ON; 274 int core_next_state = PWRDM_POWER_ON;
275 int per_going_off; 275 int per_going_off;
276 int core_prev_state, per_prev_state; 276 int core_prev_state;
277 u32 sdrc_pwr = 0; 277 u32 sdrc_pwr = 0;
278 278
279 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 279 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
@@ -375,10 +375,8 @@ void omap_sram_idle(void)
375 pwrdm_post_transition(); 375 pwrdm_post_transition();
376 376
377 /* PER */ 377 /* PER */
378 if (per_next_state < PWRDM_POWER_ON) { 378 if (per_next_state < PWRDM_POWER_ON)
379 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
380 omap2_gpio_resume_after_idle(); 379 omap2_gpio_resume_after_idle();
381 }
382 380
383 /* Disable IO-PAD and IO-CHAIN wakeup */ 381 /* Disable IO-PAD and IO-CHAIN wakeup */
384 if (omap3_has_io_wakeup() && 382 if (omap3_has_io_wakeup() &&
@@ -702,7 +700,7 @@ static void __init pm_errata_configure(void)
702static int __init omap3_pm_init(void) 700static int __init omap3_pm_init(void)
703{ 701{
704 struct power_state *pwrst, *tmp; 702 struct power_state *pwrst, *tmp;
705 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 703 struct clockdomain *neon_clkdm, *mpu_clkdm;
706 int ret; 704 int ret;
707 705
708 if (!cpu_is_omap34xx()) 706 if (!cpu_is_omap34xx())
@@ -757,8 +755,6 @@ static int __init omap3_pm_init(void)
757 755
758 neon_clkdm = clkdm_lookup("neon_clkdm"); 756 neon_clkdm = clkdm_lookup("neon_clkdm");
759 mpu_clkdm = clkdm_lookup("mpu_clkdm"); 757 mpu_clkdm = clkdm_lookup("mpu_clkdm");
760 per_clkdm = clkdm_lookup("per_clkdm");
761 core_clkdm = clkdm_lookup("core_clkdm");
762 758
763#ifdef CONFIG_SUSPEND 759#ifdef CONFIG_SUSPEND
764 omap_pm_suspend = omap3_pm_suspend; 760 omap_pm_suspend = omap3_pm_suspend;
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index d28f848897d..dfe00ddb5c6 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -237,7 +237,7 @@ void omap_prcm_irq_complete(void)
237 */ 237 */
238int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) 238int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
239{ 239{
240 int nr_regs = irq_setup->nr_regs; 240 int nr_regs;
241 u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG]; 241 u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
242 int offset, i; 242 int offset, i;
243 struct irq_chip_generic *gc; 243 struct irq_chip_generic *gc;
@@ -246,6 +246,8 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
246 if (!irq_setup) 246 if (!irq_setup)
247 return -EINVAL; 247 return -EINVAL;
248 248
249 nr_regs = irq_setup->nr_regs;
250
249 if (prcm_irq_setup) { 251 if (prcm_irq_setup) {
250 pr_err("PRCM: already initialized; won't reinitialize\n"); 252 pr_err("PRCM: already initialized; won't reinitialize\n");
251 return -EINVAL; 253 return -EINVAL;
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 9fc2f44188c..678dd1d612e 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -133,7 +133,7 @@ static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
133static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {} 133static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
134#endif 134#endif
135 135
136char *cmdline_find_option(char *str) 136static char *cmdline_find_option(char *str)
137{ 137{
138 extern char *saved_command_line; 138 extern char *saved_command_line;
139 139
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index c512bac69ec..ecec873e78c 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -145,8 +145,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
145{ 145{
146 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 146 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
147 struct omap_hwmod *oh; 147 struct omap_hwmod *oh;
148 struct resource irq_rsrc, mem_rsrc;
148 size_t size; 149 size_t size;
149 int res = 0; 150 int res = 0;
151 int r;
150 152
151 sprintf(name, "timer%d", gptimer_id); 153 sprintf(name, "timer%d", gptimer_id);
152 omap_hwmod_setup_one(name); 154 omap_hwmod_setup_one(name);
@@ -154,9 +156,16 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
154 if (!oh) 156 if (!oh)
155 return -ENODEV; 157 return -ENODEV;
156 158
157 timer->irq = oh->mpu_irqs[0].irq; 159 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
158 timer->phys_base = oh->slaves[0]->addr->pa_start; 160 if (r)
159 size = oh->slaves[0]->addr->pa_end - timer->phys_base; 161 return -ENXIO;
162 timer->irq = irq_rsrc.start;
163
164 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
165 if (r)
166 return -ENXIO;
167 timer->phys_base = mem_rsrc.start;
168 size = mem_rsrc.end - mem_rsrc.start;
160 169
161 /* Static mapping, never released */ 170 /* Static mapping, never released */
162 timer->io_base = ioremap(timer->phys_base, size); 171 timer->io_base = ioremap(timer->phys_base, size);
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 994d8f591a1..db84a46ce7f 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -126,7 +126,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
126 tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps; 126 tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
127 if (tmp > 4) 127 if (tmp > 4)
128 return -ERANGE; 128 return -ERANGE;
129 if (tmp <= 0) 129 if (tmp == 0)
130 tmp = 1; 130 tmp = 1;
131 t.page_burst_access = (fclk_ps * tmp) / 1000; 131 t.page_burst_access = (fclk_ps * tmp) / 1000;
132 132
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-09 09:44:18 -0500