1 files changed, 23 insertions, 23 deletions
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 5b828dfe950..80e00c16d36 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -27,15 +27,15 @@
 #define OMAP4430_PRCM_MPU_BASE                  0x48243000
-#define OMAP44XX_PRCM_MPU_REGADDR(module, reg)                          \
+#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg)                            \
-        OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
+        OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
 /* PRCM_MPU instances */
-#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD   0x0000
+#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST  0x0000
-#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD        0x0200
+#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST       0x0200
-#define OMAP4430_PRCM_MPU_CPU0_MOD              0x0400
+#define OMAP4430_PRCM_MPU_CPU0_INST             0x0400
-#define OMAP4430_PRCM_MPU_CPU1_MOD              0x0800
+#define OMAP4430_PRCM_MPU_CPU1_INST             0x0800
 /*
 * PRCM_MPU
@@ -48,44 +48,44 @@
 /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
 #define OMAP4_REVISION_PRCM_OFFSET                      0x0000
-#define OMAP4430_REVISION_PRCM                          OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000)
+#define OMAP4430_REVISION_PRCM                          OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
 /* PRCM_MPU.DEVICE_PRM register offsets */
 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET                 0x0000
-#define OMAP4430_PRCM_MPU_PRM_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
+#define OMAP4430_PRCM_MPU_PRM_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
 #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET           0x0004
-#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT               OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)
+#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT               OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
 /* PRCM_MPU.CPU0 register offsets */
 #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET                  0x0000
-#define OMAP4430_PM_CPU0_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000)
+#define OMAP4430_PM_CPU0_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
 #define OMAP4_PM_CPU0_PWRSTST_OFFSET                    0x0004
-#define OMAP4430_PM_CPU0_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004)
+#define OMAP4430_PM_CPU0_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
 #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET               0x0008
-#define OMAP4430_RM_CPU0_CPU0_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008)
+#define OMAP4430_RM_CPU0_CPU0_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
 #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET               0x000c
-#define OMAP4430_RM_CPU0_CPU0_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c)
+#define OMAP4430_RM_CPU0_CPU0_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
 #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET                 0x0010
-#define OMAP4430_RM_CPU0_CPU0_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010)
+#define OMAP4430_RM_CPU0_CPU0_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
 #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET               0x0014
-#define OMAP4430_CM_CPU0_CPU0_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014)
+#define OMAP4430_CM_CPU0_CPU0_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
 #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET                  0x0018
-#define OMAP4430_CM_CPU0_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018)
+#define OMAP4430_CM_CPU0_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
 /* PRCM_MPU.CPU1 register offsets */
 #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET                  0x0000
-#define OMAP4430_PM_CPU1_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000)
+#define OMAP4430_PM_CPU1_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
 #define OMAP4_PM_CPU1_PWRSTST_OFFSET                    0x0004
-#define OMAP4430_PM_CPU1_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004)
+#define OMAP4430_PM_CPU1_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
 #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET               0x0008
-#define OMAP4430_RM_CPU1_CPU1_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008)
+#define OMAP4430_RM_CPU1_CPU1_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
 #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET               0x000c
-#define OMAP4430_RM_CPU1_CPU1_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c)
+#define OMAP4430_RM_CPU1_CPU1_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
 #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET                 0x0010
-#define OMAP4430_RM_CPU1_CPU1_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010)
+#define OMAP4430_RM_CPU1_CPU1_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
 #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET               0x0014
-#define OMAP4430_CM_CPU1_CPU1_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014)
+#define OMAP4430_CM_CPU1_CPU1_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
 #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET                  0x0018
-#define OMAP4430_CM_CPU1_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018)
+#define OMAP4430_CM_CPU1_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
 #endif

diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h index 5b828dfe950..80e00c16d36 100644 --- a/arch/arm/mach-omap2/prcm_mpu44xx.h +++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -27,15 +27,15 @@
27		27
28	#define OMAP4430_PRCM_MPU_BASE 0x48243000	28	#define OMAP4430_PRCM_MPU_BASE 0x48243000
29		29
30	#define OMAP44XX_PRCM_MPU_REGADDR(module, reg) \	30	#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
31	OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))	31	OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
32		32
33	/* PRCM_MPU instances */	33	/* PRCM_MPU instances */
34		34
35	#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD 0x0000	35	#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
36	#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD 0x0200	36	#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
37	#define OMAP4430_PRCM_MPU_CPU0_MOD 0x0400	37	#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
38	#define OMAP4430_PRCM_MPU_CPU1_MOD 0x0800	38	#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39		39
40	/*	40	/*
41	* PRCM_MPU	41	* PRCM_MPU
@@ -48,44 +48,44 @@
48		48
49	/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */	49	/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
50	#define OMAP4_REVISION_PRCM_OFFSET 0x0000	50	#define OMAP4_REVISION_PRCM_OFFSET 0x0000
51	#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000)	51	#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
52		52
53	/* PRCM_MPU.DEVICE_PRM register offsets */	53	/* PRCM_MPU.DEVICE_PRM register offsets */
54	#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000	54	#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
55	#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)	55	#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
56	#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004	56	#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
57	#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)	57	#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
58		58
59	/* PRCM_MPU.CPU0 register offsets */	59	/* PRCM_MPU.CPU0 register offsets */
60	#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000	60	#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
61	#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000)	61	#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
62	#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004	62	#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
63	#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004)	63	#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
64	#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008	64	#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
65	#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008)	65	#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
66	#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c	66	#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
67	#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c)	67	#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
68	#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010	68	#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
69	#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010)	69	#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
70	#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014	70	#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
71	#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014)	71	#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
72	#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018	72	#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
73	#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018)	73	#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
74		74
75	/* PRCM_MPU.CPU1 register offsets */	75	/* PRCM_MPU.CPU1 register offsets */
76	#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000	76	#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
77	#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000)	77	#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
78	#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004	78	#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
79	#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004)	79	#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
80	#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008	80	#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
81	#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008)	81	#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
82	#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c	82	#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
83	#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c)	83	#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
84	#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010	84	#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
85	#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010)	85	#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
86	#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014	86	#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
87	#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014)	87	#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
88	#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018	88	#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
89	#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018)	89	#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
90		90
91	#endif	91	#endif