diff options
Diffstat (limited to 'arch/arm/mach-omap2/prcm-common.h')
| -rw-r--r-- | arch/arm/mach-omap2/prcm-common.h | 164 |
1 files changed, 78 insertions, 86 deletions
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 90f603d434c..995b7edbf18 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h | |||
| @@ -112,83 +112,75 @@ | |||
| 112 | 112 | ||
| 113 | #define OMAP4430_SCRM_SCRM_MOD 0x0000 | 113 | #define OMAP4430_SCRM_SCRM_MOD 0x0000 |
| 114 | 114 | ||
| 115 | /* CHIRONSS instances */ | 115 | /* PRCM_MPU instances */ |
| 116 | 116 | ||
| 117 | #define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD 0x0000 | 117 | #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD 0x0000 |
| 118 | #define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD 0x0200 | 118 | #define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD 0x0200 |
| 119 | #define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400 | 119 | #define OMAP4430_PRCM_MPU_CPU0_MOD 0x0400 |
| 120 | #define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800 | 120 | #define OMAP4430_PRCM_MPU_CPU1_MOD 0x0800 |
| 121 | |||
| 122 | /* Base Addresses for the OMAP4 */ | ||
| 123 | |||
| 124 | #define OMAP4430_CM1_BASE 0x4a004000 | ||
| 125 | #define OMAP4430_CM2_BASE 0x4a008000 | ||
| 126 | #define OMAP4430_PRM_BASE 0x4a306000 | ||
| 127 | #define OMAP4430_SCRM_BASE 0x4a30a000 | ||
| 128 | #define OMAP4430_CHIRONSS_BASE 0x48243000 | ||
| 129 | 121 | ||
| 130 | 122 | ||
| 131 | /* 24XX register bits shared between CM & PRM registers */ | 123 | /* 24XX register bits shared between CM & PRM registers */ |
| 132 | 124 | ||
| 133 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | 125 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ |
| 134 | #define OMAP2420_EN_MMC_SHIFT 26 | 126 | #define OMAP2420_EN_MMC_SHIFT 26 |
| 135 | #define OMAP2420_EN_MMC (1 << 26) | 127 | #define OMAP2420_EN_MMC_MASK (1 << 26) |
| 136 | #define OMAP24XX_EN_UART2_SHIFT 22 | 128 | #define OMAP24XX_EN_UART2_SHIFT 22 |
| 137 | #define OMAP24XX_EN_UART2 (1 << 22) | 129 | #define OMAP24XX_EN_UART2_MASK (1 << 22) |
| 138 | #define OMAP24XX_EN_UART1_SHIFT 21 | 130 | #define OMAP24XX_EN_UART1_SHIFT 21 |
| 139 | #define OMAP24XX_EN_UART1 (1 << 21) | 131 | #define OMAP24XX_EN_UART1_MASK (1 << 21) |
| 140 | #define OMAP24XX_EN_MCSPI2_SHIFT 18 | 132 | #define OMAP24XX_EN_MCSPI2_SHIFT 18 |
| 141 | #define OMAP24XX_EN_MCSPI2 (1 << 18) | 133 | #define OMAP24XX_EN_MCSPI2_MASK (1 << 18) |
| 142 | #define OMAP24XX_EN_MCSPI1_SHIFT 17 | 134 | #define OMAP24XX_EN_MCSPI1_SHIFT 17 |
| 143 | #define OMAP24XX_EN_MCSPI1 (1 << 17) | 135 | #define OMAP24XX_EN_MCSPI1_MASK (1 << 17) |
| 144 | #define OMAP24XX_EN_MCBSP2_SHIFT 16 | 136 | #define OMAP24XX_EN_MCBSP2_SHIFT 16 |
| 145 | #define OMAP24XX_EN_MCBSP2 (1 << 16) | 137 | #define OMAP24XX_EN_MCBSP2_MASK (1 << 16) |
| 146 | #define OMAP24XX_EN_MCBSP1_SHIFT 15 | 138 | #define OMAP24XX_EN_MCBSP1_SHIFT 15 |
| 147 | #define OMAP24XX_EN_MCBSP1 (1 << 15) | 139 | #define OMAP24XX_EN_MCBSP1_MASK (1 << 15) |
| 148 | #define OMAP24XX_EN_GPT12_SHIFT 14 | 140 | #define OMAP24XX_EN_GPT12_SHIFT 14 |
| 149 | #define OMAP24XX_EN_GPT12 (1 << 14) | 141 | #define OMAP24XX_EN_GPT12_MASK (1 << 14) |
| 150 | #define OMAP24XX_EN_GPT11_SHIFT 13 | 142 | #define OMAP24XX_EN_GPT11_SHIFT 13 |
| 151 | #define OMAP24XX_EN_GPT11 (1 << 13) | 143 | #define OMAP24XX_EN_GPT11_MASK (1 << 13) |
| 152 | #define OMAP24XX_EN_GPT10_SHIFT 12 | 144 | #define OMAP24XX_EN_GPT10_SHIFT 12 |
| 153 | #define OMAP24XX_EN_GPT10 (1 << 12) | 145 | #define OMAP24XX_EN_GPT10_MASK (1 << 12) |
| 154 | #define OMAP24XX_EN_GPT9_SHIFT 11 | 146 | #define OMAP24XX_EN_GPT9_SHIFT 11 |
| 155 | #define OMAP24XX_EN_GPT9 (1 << 11) | 147 | #define OMAP24XX_EN_GPT9_MASK (1 << 11) |
| 156 | #define OMAP24XX_EN_GPT8_SHIFT 10 | 148 | #define OMAP24XX_EN_GPT8_SHIFT 10 |
| 157 | #define OMAP24XX_EN_GPT8 (1 << 10) | 149 | #define OMAP24XX_EN_GPT8_MASK (1 << 10) |
| 158 | #define OMAP24XX_EN_GPT7_SHIFT 9 | 150 | #define OMAP24XX_EN_GPT7_SHIFT 9 |
| 159 | #define OMAP24XX_EN_GPT7 (1 << 9) | 151 | #define OMAP24XX_EN_GPT7_MASK (1 << 9) |
| 160 | #define OMAP24XX_EN_GPT6_SHIFT 8 | 152 | #define OMAP24XX_EN_GPT6_SHIFT 8 |
| 161 | #define OMAP24XX_EN_GPT6 (1 << 8) | 153 | #define OMAP24XX_EN_GPT6_MASK (1 << 8) |
| 162 | #define OMAP24XX_EN_GPT5_SHIFT 7 | 154 | #define OMAP24XX_EN_GPT5_SHIFT 7 |
| 163 | #define OMAP24XX_EN_GPT5 (1 << 7) | 155 | #define OMAP24XX_EN_GPT5_MASK (1 << 7) |
| 164 | #define OMAP24XX_EN_GPT4_SHIFT 6 | 156 | #define OMAP24XX_EN_GPT4_SHIFT 6 |
| 165 | #define OMAP24XX_EN_GPT4 (1 << 6) | 157 | #define OMAP24XX_EN_GPT4_MASK (1 << 6) |
| 166 | #define OMAP24XX_EN_GPT3_SHIFT 5 | 158 | #define OMAP24XX_EN_GPT3_SHIFT 5 |
| 167 | #define OMAP24XX_EN_GPT3 (1 << 5) | 159 | #define OMAP24XX_EN_GPT3_MASK (1 << 5) |
| 168 | #define OMAP24XX_EN_GPT2_SHIFT 4 | 160 | #define OMAP24XX_EN_GPT2_SHIFT 4 |
| 169 | #define OMAP24XX_EN_GPT2 (1 << 4) | 161 | #define OMAP24XX_EN_GPT2_MASK (1 << 4) |
| 170 | #define OMAP2420_EN_VLYNQ_SHIFT 3 | 162 | #define OMAP2420_EN_VLYNQ_SHIFT 3 |
| 171 | #define OMAP2420_EN_VLYNQ (1 << 3) | 163 | #define OMAP2420_EN_VLYNQ_MASK (1 << 3) |
| 172 | 164 | ||
| 173 | /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ | 165 | /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ |
| 174 | #define OMAP2430_EN_GPIO5_SHIFT 10 | 166 | #define OMAP2430_EN_GPIO5_SHIFT 10 |
| 175 | #define OMAP2430_EN_GPIO5 (1 << 10) | 167 | #define OMAP2430_EN_GPIO5_MASK (1 << 10) |
| 176 | #define OMAP2430_EN_MCSPI3_SHIFT 9 | 168 | #define OMAP2430_EN_MCSPI3_SHIFT 9 |
| 177 | #define OMAP2430_EN_MCSPI3 (1 << 9) | 169 | #define OMAP2430_EN_MCSPI3_MASK (1 << 9) |
| 178 | #define OMAP2430_EN_MMCHS2_SHIFT 8 | 170 | #define OMAP2430_EN_MMCHS2_SHIFT 8 |
| 179 | #define OMAP2430_EN_MMCHS2 (1 << 8) | 171 | #define OMAP2430_EN_MMCHS2_MASK (1 << 8) |
| 180 | #define OMAP2430_EN_MMCHS1_SHIFT 7 | 172 | #define OMAP2430_EN_MMCHS1_SHIFT 7 |
| 181 | #define OMAP2430_EN_MMCHS1 (1 << 7) | 173 | #define OMAP2430_EN_MMCHS1_MASK (1 << 7) |
| 182 | #define OMAP24XX_EN_UART3_SHIFT 2 | 174 | #define OMAP24XX_EN_UART3_SHIFT 2 |
| 183 | #define OMAP24XX_EN_UART3 (1 << 2) | 175 | #define OMAP24XX_EN_UART3_MASK (1 << 2) |
| 184 | #define OMAP24XX_EN_USB_SHIFT 0 | 176 | #define OMAP24XX_EN_USB_SHIFT 0 |
| 185 | #define OMAP24XX_EN_USB (1 << 0) | 177 | #define OMAP24XX_EN_USB_MASK (1 << 0) |
| 186 | 178 | ||
| 187 | /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ | 179 | /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ |
| 188 | #define OMAP2430_EN_MDM_INTC_SHIFT 11 | 180 | #define OMAP2430_EN_MDM_INTC_SHIFT 11 |
| 189 | #define OMAP2430_EN_MDM_INTC (1 << 11) | 181 | #define OMAP2430_EN_MDM_INTC_MASK (1 << 11) |
| 190 | #define OMAP2430_EN_USBHS_SHIFT 6 | 182 | #define OMAP2430_EN_USBHS_SHIFT 6 |
| 191 | #define OMAP2430_EN_USBHS (1 << 6) | 183 | #define OMAP2430_EN_USBHS_MASK (1 << 6) |
| 192 | 184 | ||
| 193 | /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ | 185 | /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ |
| 194 | #define OMAP2420_ST_MMC_SHIFT 26 | 186 | #define OMAP2420_ST_MMC_SHIFT 26 |
| @@ -246,9 +238,9 @@ | |||
| 246 | 238 | ||
| 247 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | 239 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ |
| 248 | #define OMAP24XX_EN_GPIOS_SHIFT 2 | 240 | #define OMAP24XX_EN_GPIOS_SHIFT 2 |
| 249 | #define OMAP24XX_EN_GPIOS (1 << 2) | 241 | #define OMAP24XX_EN_GPIOS_MASK (1 << 2) |
| 250 | #define OMAP24XX_EN_GPT1_SHIFT 0 | 242 | #define OMAP24XX_EN_GPT1_SHIFT 0 |
| 251 | #define OMAP24XX_EN_GPT1 (1 << 0) | 243 | #define OMAP24XX_EN_GPT1_MASK (1 << 0) |
| 252 | 244 | ||
| 253 | /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ | 245 | /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ |
| 254 | #define OMAP24XX_ST_GPIOS_SHIFT (1 << 2) | 246 | #define OMAP24XX_ST_GPIOS_SHIFT (1 << 2) |
| @@ -267,47 +259,47 @@ | |||
| 267 | #define OMAP3430_REV_MASK (0xff << 0) | 259 | #define OMAP3430_REV_MASK (0xff << 0) |
| 268 | 260 | ||
| 269 | /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ | 261 | /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ |
| 270 | #define OMAP3430_AUTOIDLE (1 << 0) | 262 | #define OMAP3430_AUTOIDLE_MASK (1 << 0) |
| 271 | 263 | ||
| 272 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | 264 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ |
| 273 | #define OMAP3430_EN_MMC2 (1 << 25) | 265 | #define OMAP3430_EN_MMC2_MASK (1 << 25) |
| 274 | #define OMAP3430_EN_MMC2_SHIFT 25 | 266 | #define OMAP3430_EN_MMC2_SHIFT 25 |
| 275 | #define OMAP3430_EN_MMC1 (1 << 24) | 267 | #define OMAP3430_EN_MMC1_MASK (1 << 24) |
| 276 | #define OMAP3430_EN_MMC1_SHIFT 24 | 268 | #define OMAP3430_EN_MMC1_SHIFT 24 |
| 277 | #define OMAP3430_EN_MCSPI4 (1 << 21) | 269 | #define OMAP3430_EN_MCSPI4_MASK (1 << 21) |
| 278 | #define OMAP3430_EN_MCSPI4_SHIFT 21 | 270 | #define OMAP3430_EN_MCSPI4_SHIFT 21 |
| 279 | #define OMAP3430_EN_MCSPI3 (1 << 20) | 271 | #define OMAP3430_EN_MCSPI3_MASK (1 << 20) |
| 280 | #define OMAP3430_EN_MCSPI3_SHIFT 20 | 272 | #define OMAP3430_EN_MCSPI3_SHIFT 20 |
| 281 | #define OMAP3430_EN_MCSPI2 (1 << 19) | 273 | #define OMAP3430_EN_MCSPI2_MASK (1 << 19) |
| 282 | #define OMAP3430_EN_MCSPI2_SHIFT 19 | 274 | #define OMAP3430_EN_MCSPI2_SHIFT 19 |
| 283 | #define OMAP3430_EN_MCSPI1 (1 << 18) | 275 | #define OMAP3430_EN_MCSPI1_MASK (1 << 18) |
| 284 | #define OMAP3430_EN_MCSPI1_SHIFT 18 | 276 | #define OMAP3430_EN_MCSPI1_SHIFT 18 |
| 285 | #define OMAP3430_EN_I2C3 (1 << 17) | 277 | #define OMAP3430_EN_I2C3_MASK (1 << 17) |
| 286 | #define OMAP3430_EN_I2C3_SHIFT 17 | 278 | #define OMAP3430_EN_I2C3_SHIFT 17 |
| 287 | #define OMAP3430_EN_I2C2 (1 << 16) | 279 | #define OMAP3430_EN_I2C2_MASK (1 << 16) |
| 288 | #define OMAP3430_EN_I2C2_SHIFT 16 | 280 | #define OMAP3430_EN_I2C2_SHIFT 16 |
| 289 | #define OMAP3430_EN_I2C1 (1 << 15) | 281 | #define OMAP3430_EN_I2C1_MASK (1 << 15) |
| 290 | #define OMAP3430_EN_I2C1_SHIFT 15 | 282 | #define OMAP3430_EN_I2C1_SHIFT 15 |
| 291 | #define OMAP3430_EN_UART2 (1 << 14) | 283 | #define OMAP3430_EN_UART2_MASK (1 << 14) |
| 292 | #define OMAP3430_EN_UART2_SHIFT 14 | 284 | #define OMAP3430_EN_UART2_SHIFT 14 |
| 293 | #define OMAP3430_EN_UART1 (1 << 13) | 285 | #define OMAP3430_EN_UART1_MASK (1 << 13) |
| 294 | #define OMAP3430_EN_UART1_SHIFT 13 | 286 | #define OMAP3430_EN_UART1_SHIFT 13 |
| 295 | #define OMAP3430_EN_GPT11 (1 << 12) | 287 | #define OMAP3430_EN_GPT11_MASK (1 << 12) |
| 296 | #define OMAP3430_EN_GPT11_SHIFT 12 | 288 | #define OMAP3430_EN_GPT11_SHIFT 12 |
| 297 | #define OMAP3430_EN_GPT10 (1 << 11) | 289 | #define OMAP3430_EN_GPT10_MASK (1 << 11) |
| 298 | #define OMAP3430_EN_GPT10_SHIFT 11 | 290 | #define OMAP3430_EN_GPT10_SHIFT 11 |
| 299 | #define OMAP3430_EN_MCBSP5 (1 << 10) | 291 | #define OMAP3430_EN_MCBSP5_MASK (1 << 10) |
| 300 | #define OMAP3430_EN_MCBSP5_SHIFT 10 | 292 | #define OMAP3430_EN_MCBSP5_SHIFT 10 |
| 301 | #define OMAP3430_EN_MCBSP1 (1 << 9) | 293 | #define OMAP3430_EN_MCBSP1_MASK (1 << 9) |
| 302 | #define OMAP3430_EN_MCBSP1_SHIFT 9 | 294 | #define OMAP3430_EN_MCBSP1_SHIFT 9 |
| 303 | #define OMAP3430_EN_FSHOSTUSB (1 << 5) | 295 | #define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5) |
| 304 | #define OMAP3430_EN_FSHOSTUSB_SHIFT 5 | 296 | #define OMAP3430_EN_FSHOSTUSB_SHIFT 5 |
| 305 | #define OMAP3430_EN_D2D (1 << 3) | 297 | #define OMAP3430_EN_D2D_MASK (1 << 3) |
| 306 | #define OMAP3430_EN_D2D_SHIFT 3 | 298 | #define OMAP3430_EN_D2D_SHIFT 3 |
| 307 | 299 | ||
| 308 | /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | 300 | /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ |
| 309 | #define OMAP3430_EN_HSOTGUSB (1 << 4) | 301 | #define OMAP3430_EN_HSOTGUSB_MASK (1 << 4) |
| 310 | #define OMAP3430_EN_HSOTGUSB_SHIFT 4 | 302 | #define OMAP3430_EN_HSOTGUSB_SHIFT 4 |
| 311 | 303 | ||
| 312 | /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ | 304 | /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ |
| 313 | #define OMAP3430_ST_MMC2_SHIFT 25 | 305 | #define OMAP3430_ST_MMC2_SHIFT 25 |
| @@ -352,21 +344,21 @@ | |||
| 352 | #define OMAP3430_ST_D2D_MASK (1 << 3) | 344 | #define OMAP3430_ST_D2D_MASK (1 << 3) |
| 353 | 345 | ||
| 354 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | 346 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ |
| 355 | #define OMAP3430_EN_GPIO1 (1 << 3) | 347 | #define OMAP3430_EN_GPIO1_MASK (1 << 3) |
| 356 | #define OMAP3430_EN_GPIO1_SHIFT 3 | 348 | #define OMAP3430_EN_GPIO1_SHIFT 3 |
| 357 | #define OMAP3430_EN_GPT12 (1 << 1) | 349 | #define OMAP3430_EN_GPT12_MASK (1 << 1) |
| 358 | #define OMAP3430_EN_GPT12_SHIFT 1 | 350 | #define OMAP3430_EN_GPT12_SHIFT 1 |
| 359 | #define OMAP3430_EN_GPT1 (1 << 0) | 351 | #define OMAP3430_EN_GPT1_MASK (1 << 0) |
| 360 | #define OMAP3430_EN_GPT1_SHIFT 0 | 352 | #define OMAP3430_EN_GPT1_SHIFT 0 |
| 361 | 353 | ||
| 362 | /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ | 354 | /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ |
| 363 | #define OMAP3430_EN_SR2 (1 << 7) | 355 | #define OMAP3430_EN_SR2_MASK (1 << 7) |
| 364 | #define OMAP3430_EN_SR2_SHIFT 7 | 356 | #define OMAP3430_EN_SR2_SHIFT 7 |
| 365 | #define OMAP3430_EN_SR1 (1 << 6) | 357 | #define OMAP3430_EN_SR1_MASK (1 << 6) |
| 366 | #define OMAP3430_EN_SR1_SHIFT 6 | 358 | #define OMAP3430_EN_SR1_SHIFT 6 |
| 367 | 359 | ||
| 368 | /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | 360 | /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ |
| 369 | #define OMAP3430_EN_GPT12 (1 << 1) | 361 | #define OMAP3430_EN_GPT12_MASK (1 << 1) |
| 370 | #define OMAP3430_EN_GPT12_SHIFT 1 | 362 | #define OMAP3430_EN_GPT12_SHIFT 1 |
| 371 | 363 | ||
| 372 | /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ | 364 | /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ |
| @@ -386,47 +378,47 @@ | |||
| 386 | * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, | 378 | * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, |
| 387 | * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits | 379 | * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits |
| 388 | */ | 380 | */ |
| 389 | #define OMAP3430_EN_MPU (1 << 1) | 381 | #define OMAP3430_EN_MPU_MASK (1 << 1) |
| 390 | #define OMAP3430_EN_MPU_SHIFT 1 | 382 | #define OMAP3430_EN_MPU_SHIFT 1 |
| 391 | 383 | ||
| 392 | /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ | 384 | /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ |
| 393 | #define OMAP3430_EN_GPIO6 (1 << 17) | 385 | #define OMAP3430_EN_GPIO6_MASK (1 << 17) |
| 394 | #define OMAP3430_EN_GPIO6_SHIFT 17 | 386 | #define OMAP3430_EN_GPIO6_SHIFT 17 |
| 395 | #define OMAP3430_EN_GPIO5 (1 << 16) | 387 | #define OMAP3430_EN_GPIO5_MASK (1 << 16) |
| 396 | #define OMAP3430_EN_GPIO5_SHIFT 16 | 388 | #define OMAP3430_EN_GPIO5_SHIFT 16 |
| 397 | #define OMAP3430_EN_GPIO4 (1 << 15) | 389 | #define OMAP3430_EN_GPIO4_MASK (1 << 15) |
| 398 | #define OMAP3430_EN_GPIO4_SHIFT 15 | 390 | #define OMAP3430_EN_GPIO4_SHIFT 15 |
| 399 | #define OMAP3430_EN_GPIO3 (1 << 14) | 391 | #define OMAP3430_EN_GPIO3_MASK (1 << 14) |
| 400 | #define OMAP3430_EN_GPIO3_SHIFT 14 | 392 | #define OMAP3430_EN_GPIO3_SHIFT 14 |
| 401 | #define OMAP3430_EN_GPIO2 (1 << 13) | 393 | #define OMAP3430_EN_GPIO2_MASK (1 << 13) |
| 402 | #define OMAP3430_EN_GPIO2_SHIFT 13 | 394 | #define OMAP3430_EN_GPIO2_SHIFT 13 |
| 403 | #define OMAP3430_EN_UART3 (1 << 11) | 395 | #define OMAP3430_EN_UART3_MASK (1 << 11) |
| 404 | #define OMAP3430_EN_UART3_SHIFT 11 | 396 | #define OMAP3430_EN_UART3_SHIFT 11 |
| 405 | #define OMAP3430_EN_GPT9 (1 << 10) | 397 | #define OMAP3430_EN_GPT9_MASK (1 << 10) |
| 406 | #define OMAP3430_EN_GPT9_SHIFT 10 | 398 | #define OMAP3430_EN_GPT9_SHIFT 10 |
| 407 | #define OMAP3430_EN_GPT8 (1 << 9) | 399 | #define OMAP3430_EN_GPT8_MASK (1 << 9) |
| 408 | #define OMAP3430_EN_GPT8_SHIFT 9 | 400 | #define OMAP3430_EN_GPT8_SHIFT 9 |
| 409 | #define OMAP3430_EN_GPT7 (1 << 8) | 401 | #define OMAP3430_EN_GPT7_MASK (1 << 8) |
| 410 | #define OMAP3430_EN_GPT7_SHIFT 8 | 402 | #define OMAP3430_EN_GPT7_SHIFT 8 |
| 411 | #define OMAP3430_EN_GPT6 (1 << 7) | 403 | #define OMAP3430_EN_GPT6_MASK (1 << 7) |
| 412 | #define OMAP3430_EN_GPT6_SHIFT 7 | 404 | #define OMAP3430_EN_GPT6_SHIFT 7 |
| 413 | #define OMAP3430_EN_GPT5 (1 << 6) | 405 | #define OMAP3430_EN_GPT5_MASK (1 << 6) |
| 414 | #define OMAP3430_EN_GPT5_SHIFT 6 | 406 | #define OMAP3430_EN_GPT5_SHIFT 6 |
| 415 | #define OMAP3430_EN_GPT4 (1 << 5) | 407 | #define OMAP3430_EN_GPT4_MASK (1 << 5) |
| 416 | #define OMAP3430_EN_GPT4_SHIFT 5 | 408 | #define OMAP3430_EN_GPT4_SHIFT 5 |
| 417 | #define OMAP3430_EN_GPT3 (1 << 4) | 409 | #define OMAP3430_EN_GPT3_MASK (1 << 4) |
| 418 | #define OMAP3430_EN_GPT3_SHIFT 4 | 410 | #define OMAP3430_EN_GPT3_SHIFT 4 |
| 419 | #define OMAP3430_EN_GPT2 (1 << 3) | 411 | #define OMAP3430_EN_GPT2_MASK (1 << 3) |
| 420 | #define OMAP3430_EN_GPT2_SHIFT 3 | 412 | #define OMAP3430_EN_GPT2_SHIFT 3 |
| 421 | 413 | ||
| 422 | /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ | 414 | /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ |
| 423 | /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits | 415 | /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits |
| 424 | * be ST_* bits instead? */ | 416 | * be ST_* bits instead? */ |
| 425 | #define OMAP3430_EN_MCBSP4 (1 << 2) | 417 | #define OMAP3430_EN_MCBSP4_MASK (1 << 2) |
| 426 | #define OMAP3430_EN_MCBSP4_SHIFT 2 | 418 | #define OMAP3430_EN_MCBSP4_SHIFT 2 |
| 427 | #define OMAP3430_EN_MCBSP3 (1 << 1) | 419 | #define OMAP3430_EN_MCBSP3_MASK (1 << 1) |
| 428 | #define OMAP3430_EN_MCBSP3_SHIFT 1 | 420 | #define OMAP3430_EN_MCBSP3_SHIFT 1 |
| 429 | #define OMAP3430_EN_MCBSP2 (1 << 0) | 421 | #define OMAP3430_EN_MCBSP2_MASK (1 << 0) |
| 430 | #define OMAP3430_EN_MCBSP2_SHIFT 0 | 422 | #define OMAP3430_EN_MCBSP2_SHIFT 0 |
| 431 | 423 | ||
| 432 | /* CM_IDLEST_PER, PM_WKST_PER shared bits */ | 424 | /* CM_IDLEST_PER, PM_WKST_PER shared bits */ |