diff options
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c | 110 |
1 files changed, 54 insertions, 56 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c index 102d76e9e9e..8851bbb6bb2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c | |||
@@ -13,9 +13,7 @@ | |||
13 | #include <plat/serial.h> | 13 | #include <plat/serial.h> |
14 | #include <plat/dma.h> | 14 | #include <plat/dma.h> |
15 | #include <plat/common.h> | 15 | #include <plat/common.h> |
16 | #include <plat/hdq1w.h> | 16 | #include "hdq1w.h" |
17 | |||
18 | #include <mach/irqs.h> | ||
19 | 17 | ||
20 | #include "omap_hwmod_common_data.h" | 18 | #include "omap_hwmod_common_data.h" |
21 | 19 | ||
@@ -182,126 +180,126 @@ struct omap_hwmod_class iva_hwmod_class = { | |||
182 | /* Common MPU IRQ line data */ | 180 | /* Common MPU IRQ line data */ |
183 | 181 | ||
184 | struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = { | 182 | struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = { |
185 | { .irq = 37, }, | 183 | { .irq = 37 + OMAP_INTC_START, }, |
186 | { .irq = -1 } | 184 | { .irq = -1 }, |
187 | }; | 185 | }; |
188 | 186 | ||
189 | struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = { | 187 | struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = { |
190 | { .irq = 38, }, | 188 | { .irq = 38 + OMAP_INTC_START, }, |
191 | { .irq = -1 } | 189 | { .irq = -1 }, |
192 | }; | 190 | }; |
193 | 191 | ||
194 | struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = { | 192 | struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = { |
195 | { .irq = 39, }, | 193 | { .irq = 39 + OMAP_INTC_START, }, |
196 | { .irq = -1 } | 194 | { .irq = -1 }, |
197 | }; | 195 | }; |
198 | 196 | ||
199 | struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = { | 197 | struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = { |
200 | { .irq = 40, }, | 198 | { .irq = 40 + OMAP_INTC_START, }, |
201 | { .irq = -1 } | 199 | { .irq = -1 }, |
202 | }; | 200 | }; |
203 | 201 | ||
204 | struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = { | 202 | struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = { |
205 | { .irq = 41, }, | 203 | { .irq = 41 + OMAP_INTC_START, }, |
206 | { .irq = -1 } | 204 | { .irq = -1 }, |
207 | }; | 205 | }; |
208 | 206 | ||
209 | struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = { | 207 | struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = { |
210 | { .irq = 42, }, | 208 | { .irq = 42 + OMAP_INTC_START, }, |
211 | { .irq = -1 } | 209 | { .irq = -1 }, |
212 | }; | 210 | }; |
213 | 211 | ||
214 | struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = { | 212 | struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = { |
215 | { .irq = 43, }, | 213 | { .irq = 43 + OMAP_INTC_START, }, |
216 | { .irq = -1 } | 214 | { .irq = -1 }, |
217 | }; | 215 | }; |
218 | 216 | ||
219 | struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = { | 217 | struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = { |
220 | { .irq = 44, }, | 218 | { .irq = 44 + OMAP_INTC_START, }, |
221 | { .irq = -1 } | 219 | { .irq = -1 }, |
222 | }; | 220 | }; |
223 | 221 | ||
224 | struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = { | 222 | struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = { |
225 | { .irq = 45, }, | 223 | { .irq = 45 + OMAP_INTC_START, }, |
226 | { .irq = -1 } | 224 | { .irq = -1 }, |
227 | }; | 225 | }; |
228 | 226 | ||
229 | struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = { | 227 | struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = { |
230 | { .irq = 46, }, | 228 | { .irq = 46 + OMAP_INTC_START, }, |
231 | { .irq = -1 } | 229 | { .irq = -1 }, |
232 | }; | 230 | }; |
233 | 231 | ||
234 | struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = { | 232 | struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = { |
235 | { .irq = 47, }, | 233 | { .irq = 47 + OMAP_INTC_START, }, |
236 | { .irq = -1 } | 234 | { .irq = -1 }, |
237 | }; | 235 | }; |
238 | 236 | ||
239 | struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = { | 237 | struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = { |
240 | { .irq = INT_24XX_UART1_IRQ, }, | 238 | { .irq = 72 + OMAP_INTC_START, }, |
241 | { .irq = -1 } | 239 | { .irq = -1 }, |
242 | }; | 240 | }; |
243 | 241 | ||
244 | struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = { | 242 | struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = { |
245 | { .irq = INT_24XX_UART2_IRQ, }, | 243 | { .irq = 73 + OMAP_INTC_START, }, |
246 | { .irq = -1 } | 244 | { .irq = -1 }, |
247 | }; | 245 | }; |
248 | 246 | ||
249 | struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = { | 247 | struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = { |
250 | { .irq = INT_24XX_UART3_IRQ, }, | 248 | { .irq = 74 + OMAP_INTC_START, }, |
251 | { .irq = -1 } | 249 | { .irq = -1 }, |
252 | }; | 250 | }; |
253 | 251 | ||
254 | struct omap_hwmod_irq_info omap2_dispc_irqs[] = { | 252 | struct omap_hwmod_irq_info omap2_dispc_irqs[] = { |
255 | { .irq = 25 }, | 253 | { .irq = 25 + OMAP_INTC_START, }, |
256 | { .irq = -1 } | 254 | { .irq = -1 }, |
257 | }; | 255 | }; |
258 | 256 | ||
259 | struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = { | 257 | struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = { |
260 | { .irq = INT_24XX_I2C1_IRQ, }, | 258 | { .irq = 56 + OMAP_INTC_START, }, |
261 | { .irq = -1 } | 259 | { .irq = -1 }, |
262 | }; | 260 | }; |
263 | 261 | ||
264 | struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = { | 262 | struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = { |
265 | { .irq = INT_24XX_I2C2_IRQ, }, | 263 | { .irq = 57 + OMAP_INTC_START, }, |
266 | { .irq = -1 } | 264 | { .irq = -1 }, |
267 | }; | 265 | }; |
268 | 266 | ||
269 | struct omap_hwmod_irq_info omap2_gpio1_irqs[] = { | 267 | struct omap_hwmod_irq_info omap2_gpio1_irqs[] = { |
270 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ | 268 | { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */ |
271 | { .irq = -1 } | 269 | { .irq = -1 }, |
272 | }; | 270 | }; |
273 | 271 | ||
274 | struct omap_hwmod_irq_info omap2_gpio2_irqs[] = { | 272 | struct omap_hwmod_irq_info omap2_gpio2_irqs[] = { |
275 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ | 273 | { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */ |
276 | { .irq = -1 } | 274 | { .irq = -1 }, |
277 | }; | 275 | }; |
278 | 276 | ||
279 | struct omap_hwmod_irq_info omap2_gpio3_irqs[] = { | 277 | struct omap_hwmod_irq_info omap2_gpio3_irqs[] = { |
280 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ | 278 | { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */ |
281 | { .irq = -1 } | 279 | { .irq = -1 }, |
282 | }; | 280 | }; |
283 | 281 | ||
284 | struct omap_hwmod_irq_info omap2_gpio4_irqs[] = { | 282 | struct omap_hwmod_irq_info omap2_gpio4_irqs[] = { |
285 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ | 283 | { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */ |
286 | { .irq = -1 } | 284 | { .irq = -1 }, |
287 | }; | 285 | }; |
288 | 286 | ||
289 | struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { | 287 | struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { |
290 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | 288 | { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */ |
291 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | 289 | { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */ |
292 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | 290 | { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */ |
293 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | 291 | { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */ |
294 | { .irq = -1 } | 292 | { .irq = -1 }, |
295 | }; | 293 | }; |
296 | 294 | ||
297 | struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = { | 295 | struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = { |
298 | { .irq = 65 }, | 296 | { .irq = 65 + OMAP_INTC_START, }, |
299 | { .irq = -1 } | 297 | { .irq = -1 }, |
300 | }; | 298 | }; |
301 | 299 | ||
302 | struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = { | 300 | struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = { |
303 | { .irq = 66 }, | 301 | { .irq = 66 + OMAP_INTC_START, }, |
304 | { .irq = -1 } | 302 | { .irq = -1 }, |
305 | }; | 303 | }; |
306 | 304 | ||
307 | struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { | 305 | struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { |
@@ -320,7 +318,7 @@ struct omap_hwmod_class omap2_hdq1w_class = { | |||
320 | }; | 318 | }; |
321 | 319 | ||
322 | struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = { | 320 | struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = { |
323 | { .irq = 58, }, | 321 | { .irq = 58 + OMAP_INTC_START, }, |
324 | { .irq = -1 } | 322 | { .irq = -1 }, |
325 | }; | 323 | }; |
326 | 324 | ||