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-rw-r--r--arch/arm/mach-omap2/cm-regbits-44xx.h659
1 files changed, 290 insertions, 369 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 9d47a05b17b..65597a74563 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -22,22 +22,18 @@
22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
24 24
25/* 25/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
26 * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
27 * CM_TESLA_DYNAMICDEP
28 */
29#define OMAP4430_ABE_DYNDEP_SHIFT 3 26#define OMAP4430_ABE_DYNDEP_SHIFT 3
30#define OMAP4430_ABE_DYNDEP_MASK (1 << 3) 27#define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
31 28
32/* 29/*
33 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 30 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
34 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 31 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
35 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
36 */ 32 */
37#define OMAP4430_ABE_STATDEP_SHIFT 3 33#define OMAP4430_ABE_STATDEP_SHIFT 3
38#define OMAP4430_ABE_STATDEP_MASK (1 << 3) 34#define OMAP4430_ABE_STATDEP_MASK (1 << 3)
39 35
40/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 36/* Used by CM_L4CFG_DYNAMICDEP */
41#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 37#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
42#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) 38#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
43 39
@@ -47,14 +43,13 @@
47 43
48/* 44/*
49 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, 45 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
50 * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY, 46 * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
51 * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, 47 * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
52 * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
53 */ 48 */
54#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 49#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
55#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) 50#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
56 51
57/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 52/* Used by CM_L4CFG_DYNAMICDEP */
58#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 53#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
59#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) 54#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
60 55
@@ -82,15 +77,15 @@
82#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 77#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
83#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) 78#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
84 79
85/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 80/* Used by CM_MEMIF_CLKSTCTRL */
86#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 81#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
87#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) 82#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
88 83
89/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 84/* Used by CM_MEMIF_CLKSTCTRL */
90#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 85#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
91#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) 86#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
92 87
93/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 88/* Used by CM_MEMIF_CLKSTCTRL */
94#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 89#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
95#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) 90#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
96 91
@@ -106,35 +101,39 @@
106#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 101#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
107#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) 102#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9)
108 103
104/* Used by CM_L4CFG_CLKSTCTRL */
105#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9
106#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9)
107
109/* Used by CM_CEFUSE_CLKSTCTRL */ 108/* Used by CM_CEFUSE_CLKSTCTRL */
110#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 109#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
111#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) 110#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
112 111
113/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 112/* Used by CM_MEMIF_CLKSTCTRL */
114#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 113#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
115#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) 114#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9)
116 115
117/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 116/* Used by CM_L4PER_CLKSTCTRL */
118#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 117#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
119#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) 118#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9)
120 119
121/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 120/* Used by CM_L4PER_CLKSTCTRL */
122#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 121#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
123#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) 122#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10)
124 123
125/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 124/* Used by CM_L4PER_CLKSTCTRL */
126#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 125#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
127#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) 126#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11)
128 127
129/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 128/* Used by CM_L4PER_CLKSTCTRL */
130#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 129#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
131#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) 130#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12)
132 131
133/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 132/* Used by CM_L4PER_CLKSTCTRL */
134#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 133#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
135#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) 134#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13)
136 135
137/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 136/* Used by CM_L4PER_CLKSTCTRL */
138#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 137#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
139#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) 138#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14)
140 139
@@ -158,7 +157,7 @@
158#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 157#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
159#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) 158#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10)
160 159
161/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 160/* Used by CM_L4PER_CLKSTCTRL */
162#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 161#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
163#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) 162#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15)
164 163
@@ -170,55 +169,55 @@
170#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 169#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
171#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) 170#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11)
172 171
173/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 172/* Used by CM_L3INIT_CLKSTCTRL */
174#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 173#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
175#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) 174#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
176 175
177/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 176/* Used by CM_L3INIT_CLKSTCTRL */
178#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 177#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
179#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) 178#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
180 179
181/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 180/* Used by CM_L3INIT_CLKSTCTRL */
182#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 181#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
183#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) 182#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
184 183
185/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 184/* Used by CM_L3INIT_CLKSTCTRL */
186#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 185#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
187#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) 186#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
188 187
189/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 188/* Used by CM_L3INIT_CLKSTCTRL */
190#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 189#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
191#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) 190#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13)
192 191
193/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 192/* Used by CM_L3INIT_CLKSTCTRL */
194#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 193#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
195#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) 194#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12)
196 195
197/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 196/* Used by CM_L3INIT_CLKSTCTRL */
198#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 197#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
199#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) 198#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28)
200 199
201/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 200/* Used by CM_L3INIT_CLKSTCTRL */
202#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 201#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
203#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) 202#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29)
204 203
205/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 204/* Used by CM_L3INIT_CLKSTCTRL */
206#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 205#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
207#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) 206#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11)
208 207
209/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 208/* Used by CM_L3INIT_CLKSTCTRL */
210#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 209#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
211#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) 210#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16)
212 211
213/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 212/* Used by CM_L3INIT_CLKSTCTRL */
214#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 213#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
215#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) 214#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17)
216 215
217/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 216/* Used by CM_L3INIT_CLKSTCTRL */
218#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 217#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
219#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) 218#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18)
220 219
221/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 220/* Used by CM_L3INIT_CLKSTCTRL */
222#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 221#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
223#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) 222#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19)
224 223
@@ -234,11 +233,11 @@
234#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 233#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10
235#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) 234#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10)
236 235
237/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ 236/* Used by CM_L3_1_CLKSTCTRL */
238#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 237#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
239#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) 238#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8)
240 239
241/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ 240/* Used by CM_L3_2_CLKSTCTRL */
242#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 241#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
243#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) 242#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8)
244 243
@@ -254,7 +253,7 @@
254#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 253#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
255#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) 254#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8)
256 255
257/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 256/* Used by CM_MEMIF_CLKSTCTRL */
258#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 257#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
259#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) 258#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8)
260 259
@@ -262,7 +261,7 @@
262#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 261#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
263#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) 262#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8)
264 263
265/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 264/* Used by CM_L3INIT_CLKSTCTRL */
266#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 265#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
267#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) 266#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8)
268 267
@@ -282,7 +281,7 @@
282#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 281#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
283#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) 282#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
284 283
285/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ 284/* Used by CM_L4CFG_CLKSTCTRL */
286#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 285#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
287#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) 286#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8)
288 287
@@ -290,11 +289,11 @@
290#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 289#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
291#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) 290#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9)
292 291
293/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 292/* Used by CM_L3INIT_CLKSTCTRL */
294#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 293#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
295#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) 294#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9)
296 295
297/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 296/* Used by CM_L4PER_CLKSTCTRL */
298#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 297#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
299#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) 298#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8)
300 299
@@ -306,7 +305,7 @@
306#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 305#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
307#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) 306#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12)
308 307
309/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ 308/* Used by CM_MPU_CLKSTCTRL */
310#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 309#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
311#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) 310#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8)
312 311
@@ -314,43 +313,43 @@
314#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 313#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
315#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) 314#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9)
316 315
317/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 316/* Used by CM_L4PER_CLKSTCTRL */
318#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 317#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
319#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) 318#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16)
320 319
321/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 320/* Used by CM_L4PER_CLKSTCTRL */
322#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 321#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
323#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) 322#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
324 323
325/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 324/* Used by CM_L4PER_CLKSTCTRL */
326#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 325#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
327#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) 326#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
328 327
329/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 328/* Used by CM_L4PER_CLKSTCTRL */
330#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 329#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
331#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) 330#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
332 331
333/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 332/* Used by CM_L4PER_CLKSTCTRL */
334#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 333#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
335#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) 334#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25)
336 335
337/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 336/* Used by CM_L4PER_CLKSTCTRL */
338#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 337#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
339#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) 338#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20)
340 339
341/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 340/* Used by CM_L4PER_CLKSTCTRL */
342#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 341#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21
343#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) 342#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21)
344 343
345/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 344/* Used by CM_L4PER_CLKSTCTRL */
346#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 345#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
347#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) 346#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22)
348 347
349/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 348/* Used by CM_L4PER_CLKSTCTRL */
350#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 349#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
351#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) 350#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24)
352 351
353/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 352/* Used by CM_MEMIF_CLKSTCTRL */
354#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 353#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
355#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) 354#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10)
356 355
@@ -378,27 +377,27 @@
378#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 377#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
379#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) 378#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8)
380 379
381/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 380/* Used by CM_L3INIT_CLKSTCTRL */
382#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 381#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
383#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) 382#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
384 383
385/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 384/* Used by CM_L3INIT_CLKSTCTRL */
386#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 385#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
387#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) 386#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
388 387
389/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 388/* Used by CM_L3INIT_CLKSTCTRL */
390#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 389#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
391#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) 390#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
392 391
393/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 392/* Used by CM_L3INIT_CLKSTCTRL */
394#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 393#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10
395#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) 394#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10)
396 395
397/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 396/* Used by CM_L3INIT_CLKSTCTRL */
398#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 397#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
399#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) 398#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
400 399
401/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 400/* Used by CM_L3INIT_CLKSTCTRL */
402#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 401#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
403#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) 402#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
404 403
@@ -406,11 +405,11 @@
406#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 405#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
407#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) 406#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10)
408 407
409/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 408/* Used by CM_L3INIT_CLKSTCTRL */
410#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 409#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
411#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) 410#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
412 411
413/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 412/* Used by CM_L3INIT_CLKSTCTRL */
414#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 413#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
415#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) 414#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
416 415
@@ -418,6 +417,10 @@
418#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 417#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11
419#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) 418#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11)
420 419
420/* Used by CM_WKUP_CLKSTCTRL */
421#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13
422#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13)
423
421/* 424/*
422 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, 425 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
423 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, 426 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
@@ -432,7 +435,7 @@
432 435
433/* 436/*
434 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, 437 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
435 * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ 438 * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
436 */ 439 */
437#define OMAP4430_CLKSEL_0_0_SHIFT 0 440#define OMAP4430_CLKSEL_0_0_SHIFT 0
438#define OMAP4430_CLKSEL_0_0_MASK (1 << 0) 441#define OMAP4430_CLKSEL_0_0_MASK (1 << 0)
@@ -449,18 +452,19 @@
449#define OMAP4430_CLKSEL_60M_SHIFT 24 452#define OMAP4430_CLKSEL_60M_SHIFT 24
450#define OMAP4430_CLKSEL_60M_MASK (1 << 24) 453#define OMAP4430_CLKSEL_60M_MASK (1 << 24)
451 454
455/* Used by CM_MPU_MPU_CLKCTRL */
456#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25
457#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
458
452/* Used by CM1_ABE_AESS_CLKCTRL */ 459/* Used by CM1_ABE_AESS_CLKCTRL */
453#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 460#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
454#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) 461#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
455 462
456/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 463/* Used by CM_CLKSEL_CORE */
457#define OMAP4430_CLKSEL_CORE_SHIFT 0 464#define OMAP4430_CLKSEL_CORE_SHIFT 0
458#define OMAP4430_CLKSEL_CORE_MASK (1 << 0) 465#define OMAP4430_CLKSEL_CORE_MASK (1 << 0)
459 466
460/* 467/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
461 * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
462 * CM_SHADOW_FREQ_CONFIG2
463 */
464#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 468#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
465#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) 469#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1)
466 470
@@ -468,6 +472,10 @@
468#define OMAP4430_CLKSEL_DIV_SHIFT 24 472#define OMAP4430_CLKSEL_DIV_SHIFT 24
469#define OMAP4430_CLKSEL_DIV_MASK (1 << 24) 473#define OMAP4430_CLKSEL_DIV_MASK (1 << 24)
470 474
475/* Used by CM_MPU_MPU_CLKCTRL */
476#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24
477#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
478
471/* Used by CM_CAM_FDIF_CLKCTRL */ 479/* Used by CM_CAM_FDIF_CLKCTRL */
472#define OMAP4430_CLKSEL_FCLK_SHIFT 24 480#define OMAP4430_CLKSEL_FCLK_SHIFT 24
473#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) 481#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24)
@@ -484,18 +492,15 @@
484#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 492#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
485#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) 493#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26)
486 494
487/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 495/* Used by CM_CLKSEL_CORE */
488#define OMAP4430_CLKSEL_L3_SHIFT 4 496#define OMAP4430_CLKSEL_L3_SHIFT 4
489#define OMAP4430_CLKSEL_L3_MASK (1 << 4) 497#define OMAP4430_CLKSEL_L3_MASK (1 << 4)
490 498
491/* 499/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
492 * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
493 * CM_SHADOW_FREQ_CONFIG2
494 */
495#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 500#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
496#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) 501#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2)
497 502
498/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 503/* Used by CM_CLKSEL_CORE */
499#define OMAP4430_CLKSEL_L4_SHIFT 8 504#define OMAP4430_CLKSEL_L4_SHIFT 8
500#define OMAP4430_CLKSEL_L4_MASK (1 << 8) 505#define OMAP4430_CLKSEL_L4_MASK (1 << 8)
501 506
@@ -526,11 +531,11 @@
526#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 531#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
527#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) 532#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
528 533
529/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 534/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
530#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 535#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
531#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) 536#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24)
532 537
533/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 538/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
534#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 539#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
535#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) 540#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25)
536 541
@@ -538,13 +543,10 @@
538 * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, 543 * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
539 * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, 544 * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
540 * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, 545 * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
541 * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL, 546 * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
542 * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL, 547 * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
543 * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE, 548 * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
544 * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL, 549 * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
545 * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
546 * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
547 * CM_WKUP_CLKSTCTRL
548 */ 550 */
549#define OMAP4430_CLKTRCTRL_SHIFT 0 551#define OMAP4430_CLKTRCTRL_SHIFT 0
550#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 552#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
@@ -561,10 +563,7 @@
561#define OMAP4430_CUSTOM_SHIFT 6 563#define OMAP4430_CUSTOM_SHIFT 6
562#define OMAP4430_CUSTOM_MASK (0x3 << 6) 564#define OMAP4430_CUSTOM_MASK (0x3 << 6)
563 565
564/* 566/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
565 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
566 * CM_L4CFG_DYNAMICDEP_RESTORE
567 */
568#define OMAP4430_D2D_DYNDEP_SHIFT 18 567#define OMAP4430_D2D_DYNDEP_SHIFT 18
569#define OMAP4430_D2D_DYNDEP_MASK (1 << 18) 568#define OMAP4430_D2D_DYNDEP_MASK (1 << 18)
570 569
@@ -572,33 +571,43 @@
572#define OMAP4430_D2D_STATDEP_SHIFT 18 571#define OMAP4430_D2D_STATDEP_SHIFT 18
573#define OMAP4430_D2D_STATDEP_MASK (1 << 18) 572#define OMAP4430_D2D_STATDEP_MASK (1 << 18)
574 573
574/* Used by CM_CLKSEL_DPLL_MPU */
575#define OMAP4460_DCC_COUNT_MAX_SHIFT 24
576#define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24)
577
578/* Used by CM_CLKSEL_DPLL_MPU */
579#define OMAP4460_DCC_EN_SHIFT 22
580#define OMAP4460_DCC_EN_MASK (1 << 22)
581
575/* 582/*
576 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, 583 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
577 * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY, 584 * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
578 * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, 585 * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
579 * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, 586 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
580 * CM_SSC_DELTAMSTEP_DPLL_USB
581 */ 587 */
582#define OMAP4430_DELTAMSTEP_SHIFT 0 588#define OMAP4430_DELTAMSTEP_SHIFT 0
583#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) 589#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
584 590
585/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 591/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
586#define OMAP4430_DLL_OVERRIDE_SHIFT 2 592#define OMAP4460_DELTAMSTEP_0_20_SHIFT 0
587#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2) 593#define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
588 594
589/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ 595/* Used by CM_DLL_CTRL */
590#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 596#define OMAP4430_DLL_OVERRIDE_SHIFT 0
591#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0) 597#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0)
592 598
593/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 599/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
600#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2
601#define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2)
602
603/* Used by CM_SHADOW_FREQ_CONFIG1 */
594#define OMAP4430_DLL_RESET_SHIFT 3 604#define OMAP4430_DLL_RESET_SHIFT 3
595#define OMAP4430_DLL_RESET_MASK (1 << 3) 605#define OMAP4430_DLL_RESET_MASK (1 << 3)
596 606
597/* 607/*
598 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 608 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
599 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 609 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
600 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, 610 * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
601 * CM_CLKSEL_DPLL_USB
602 */ 611 */
603#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 612#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
604#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) 613#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23)
@@ -607,28 +616,19 @@
607#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 616#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
608#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) 617#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
609 618
610/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */ 619/* Used by CM_CLKSEL_DPLL_CORE */
611#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 620#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
612#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) 621#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
613 622
614/* 623/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
615 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
616 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
617 */
618#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 624#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
619#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) 625#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
620 626
621/* 627/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
622 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
623 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
624 */
625#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 628#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
626#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) 629#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5)
627 630
628/* 631/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
629 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
630 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
631 */
632#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 632#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
633#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) 633#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8)
634 634
@@ -637,9 +637,8 @@
637#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) 637#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
638 638
639/* 639/*
640 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 640 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
641 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 641 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
642 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
643 */ 642 */
644#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 643#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
645#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 644#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
@@ -649,9 +648,8 @@
649#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) 648#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
650 649
651/* 650/*
652 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 651 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
653 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 652 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
654 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
655 */ 653 */
656#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 654#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
657#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) 655#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
@@ -661,29 +659,28 @@
661#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) 659#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7)
662 660
663/* 661/*
664 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 662 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
665 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 663 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
666 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
667 */ 664 */
668#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 665#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
669#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) 666#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
670 667
671/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 668/* Used by CM_SHADOW_FREQ_CONFIG1 */
672#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 669#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
673#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) 670#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
674 671
675/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 672/* Used by CM_SHADOW_FREQ_CONFIG1 */
676#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 673#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
677#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) 674#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
678 675
679/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ 676/* Used by CM_SHADOW_FREQ_CONFIG2 */
680#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 677#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
681#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) 678#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3)
682 679
683/* 680/*
684 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 681 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
685 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 682 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
686 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO 683 * CM_CLKSEL_DPLL_UNIPRO
687 */ 684 */
688#define OMAP4430_DPLL_DIV_SHIFT 0 685#define OMAP4430_DPLL_DIV_SHIFT 0
689#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) 686#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
@@ -693,9 +690,8 @@
693#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) 690#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
694 691
695/* 692/*
696 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 693 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
697 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 694 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
698 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
699 */ 695 */
700#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 696#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
701#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 697#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
@@ -705,26 +701,25 @@
705#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) 701#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3)
706 702
707/* 703/*
708 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 704 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
709 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 705 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
710 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 706 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
711 * CM_CLKMODE_DPLL_USB
712 */ 707 */
713#define OMAP4430_DPLL_EN_SHIFT 0 708#define OMAP4430_DPLL_EN_SHIFT 0
714#define OMAP4430_DPLL_EN_MASK (0x7 << 0) 709#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
715 710
716/* 711/*
717 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 712 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
718 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 713 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
719 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO 714 * CM_CLKMODE_DPLL_UNIPRO
720 */ 715 */
721#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 716#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
722#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) 717#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
723 718
724/* 719/*
725 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 720 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
726 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 721 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
727 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO 722 * CM_CLKSEL_DPLL_UNIPRO
728 */ 723 */
729#define OMAP4430_DPLL_MULT_SHIFT 8 724#define OMAP4430_DPLL_MULT_SHIFT 8
730#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) 725#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
@@ -734,9 +729,9 @@
734#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) 729#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
735 730
736/* 731/*
737 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 732 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
738 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 733 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
739 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO 734 * CM_CLKMODE_DPLL_UNIPRO
740 */ 735 */
741#define OMAP4430_DPLL_REGM4XEN_SHIFT 11 736#define OMAP4430_DPLL_REGM4XEN_SHIFT 11
742#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) 737#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
@@ -746,55 +741,46 @@
746#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) 741#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
747 742
748/* 743/*
749 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 744 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
750 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 745 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
751 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 746 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
752 * CM_CLKMODE_DPLL_USB
753 */ 747 */
754#define OMAP4430_DPLL_SSC_ACK_SHIFT 13 748#define OMAP4430_DPLL_SSC_ACK_SHIFT 13
755#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) 749#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13)
756 750
757/* 751/*
758 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 752 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
759 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 753 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
760 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 754 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
761 * CM_CLKMODE_DPLL_USB
762 */ 755 */
763#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 756#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
764#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) 757#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
765 758
766/* 759/*
767 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 760 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
768 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 761 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
769 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 762 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
770 * CM_CLKMODE_DPLL_USB
771 */ 763 */
772#define OMAP4430_DPLL_SSC_EN_SHIFT 12 764#define OMAP4430_DPLL_SSC_EN_SHIFT 12
773#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) 765#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12)
774 766
775/* 767/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
776 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
777 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
778 */
779#define OMAP4430_DSS_DYNDEP_SHIFT 8 768#define OMAP4430_DSS_DYNDEP_SHIFT 8
780#define OMAP4430_DSS_DYNDEP_MASK (1 << 8) 769#define OMAP4430_DSS_DYNDEP_MASK (1 << 8)
781 770
782/* 771/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
783 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
784 * CM_SDMA_STATICDEP_RESTORE
785 */
786#define OMAP4430_DSS_STATDEP_SHIFT 8 772#define OMAP4430_DSS_STATDEP_SHIFT 8
787#define OMAP4430_DSS_STATDEP_MASK (1 << 8) 773#define OMAP4430_DSS_STATDEP_MASK (1 << 8)
788 774
789/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 775/* Used by CM_L3_2_DYNAMICDEP */
790#define OMAP4430_DUCATI_DYNDEP_SHIFT 0 776#define OMAP4430_DUCATI_DYNDEP_SHIFT 0
791#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) 777#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0)
792 778
793/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */ 779/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
794#define OMAP4430_DUCATI_STATDEP_SHIFT 0 780#define OMAP4430_DUCATI_STATDEP_SHIFT 0
795#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) 781#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0)
796 782
797/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 783/* Used by CM_SHADOW_FREQ_CONFIG1 */
798#define OMAP4430_FREQ_UPDATE_SHIFT 0 784#define OMAP4430_FREQ_UPDATE_SHIFT 0
799#define OMAP4430_FREQ_UPDATE_MASK (1 << 0) 785#define OMAP4430_FREQ_UPDATE_MASK (1 << 0)
800 786
@@ -802,7 +788,7 @@
802#define OMAP4430_FUNC_SHIFT 16 788#define OMAP4430_FUNC_SHIFT 16
803#define OMAP4430_FUNC_MASK (0xfff << 16) 789#define OMAP4430_FUNC_MASK (0xfff << 16)
804 790
805/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 791/* Used by CM_L3_2_DYNAMICDEP */
806#define OMAP4430_GFX_DYNDEP_SHIFT 10 792#define OMAP4430_GFX_DYNDEP_SHIFT 10
807#define OMAP4430_GFX_DYNDEP_MASK (1 << 10) 793#define OMAP4430_GFX_DYNDEP_MASK (1 << 10)
808 794
@@ -810,119 +796,95 @@
810#define OMAP4430_GFX_STATDEP_SHIFT 10 796#define OMAP4430_GFX_STATDEP_SHIFT 10
811#define OMAP4430_GFX_STATDEP_MASK (1 << 10) 797#define OMAP4430_GFX_STATDEP_MASK (1 << 10)
812 798
813/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ 799/* Used by CM_SHADOW_FREQ_CONFIG2 */
814#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 800#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
815#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) 801#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0)
816 802
817/* 803/*
818 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 804 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
819 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 805 * CM_DIV_M4_DPLL_PER
820 */ 806 */
821#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 807#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
822#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) 808#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
823 809
824/* 810/*
825 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 811 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
826 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 812 * CM_DIV_M4_DPLL_PER
827 */ 813 */
828#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 814#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
829#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) 815#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
830 816
831/* 817/*
832 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 818 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
833 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 819 * CM_DIV_M4_DPLL_PER
834 */ 820 */
835#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 821#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
836#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) 822#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
837 823
838/* 824/*
839 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 825 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
840 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 826 * CM_DIV_M4_DPLL_PER
841 */ 827 */
842#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 828#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
843#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) 829#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
844 830
845/* 831/*
846 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 832 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
847 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 833 * CM_DIV_M5_DPLL_PER
848 */ 834 */
849#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 835#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
850#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) 836#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
851 837
852/* 838/*
853 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 839 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
854 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 840 * CM_DIV_M5_DPLL_PER
855 */ 841 */
856#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 842#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
857#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) 843#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
858 844
859/* 845/*
860 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 846 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
861 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 847 * CM_DIV_M5_DPLL_PER
862 */ 848 */
863#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 849#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
864#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) 850#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
865 851
866/* 852/*
867 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 853 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
868 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 854 * CM_DIV_M5_DPLL_PER
869 */ 855 */
870#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 856#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
871#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) 857#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
872 858
873/* 859/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
874 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
875 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
876 */
877#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 860#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
878#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) 861#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
879 862
880/* 863/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
881 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
882 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
883 */
884#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 864#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
885#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) 865#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
886 866
887/* 867/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
888 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
889 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
890 */
891#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 868#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
892#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) 869#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
893 870
894/* 871/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
895 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
896 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
897 */
898#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 872#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
899#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) 873#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
900 874
901/* 875/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
902 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
903 * CM_DIV_M7_DPLL_PER
904 */
905#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 876#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
906#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) 877#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
907 878
908/* 879/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
909 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
910 * CM_DIV_M7_DPLL_PER
911 */
912#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 880#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
913#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) 881#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5)
914 882
915/* 883/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
916 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
917 * CM_DIV_M7_DPLL_PER
918 */
919#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 884#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
920#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) 885#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8)
921 886
922/* 887/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
923 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
924 * CM_DIV_M7_DPLL_PER
925 */
926#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 888#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
927#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) 889#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12)
928 890
@@ -934,8 +896,7 @@
934 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, 896 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
935 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, 897 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
936 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 898 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
937 * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, 899 * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
938 * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
939 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, 900 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
940 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 901 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
941 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, 902 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
@@ -944,30 +905,24 @@
944 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 905 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
945 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 906 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
946 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 907 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
947 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, 908 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
948 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, 909 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
949 * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, 910 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
950 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
951 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
952 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
953 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, 911 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
954 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, 912 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
955 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, 913 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
956 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, 914 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
957 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, 915 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
958 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, 916 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
959 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 917 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
960 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 918 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
961 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 919 * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
962 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, 920 * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
963 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 921 * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
964 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, 922 * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
965 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, 923 * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
966 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, 924 * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
967 * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, 925 * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
968 * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
969 * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
970 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
971 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, 926 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
972 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, 927 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
973 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, 928 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
@@ -983,166 +938,148 @@
983#define OMAP4430_IDLEST_SHIFT 16 938#define OMAP4430_IDLEST_SHIFT 16
984#define OMAP4430_IDLEST_MASK (0x3 << 16) 939#define OMAP4430_IDLEST_MASK (0x3 << 16)
985 940
986/* 941/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
987 * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
988 * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
989 */
990#define OMAP4430_ISS_DYNDEP_SHIFT 9 942#define OMAP4430_ISS_DYNDEP_SHIFT 9
991#define OMAP4430_ISS_DYNDEP_MASK (1 << 9) 943#define OMAP4430_ISS_DYNDEP_MASK (1 << 9)
992 944
993/* 945/*
994 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 946 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
995 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 947 * CM_TESLA_STATICDEP
996 */ 948 */
997#define OMAP4430_ISS_STATDEP_SHIFT 9 949#define OMAP4430_ISS_STATDEP_SHIFT 9
998#define OMAP4430_ISS_STATDEP_MASK (1 << 9) 950#define OMAP4430_ISS_STATDEP_MASK (1 << 9)
999 951
1000/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */ 952/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
1001#define OMAP4430_IVAHD_DYNDEP_SHIFT 2 953#define OMAP4430_IVAHD_DYNDEP_SHIFT 2
1002#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) 954#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2)
1003 955
1004/* 956/*
1005 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 957 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1006 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, 958 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
1007 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 959 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1008 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1009 */ 960 */
1010#define OMAP4430_IVAHD_STATDEP_SHIFT 2 961#define OMAP4430_IVAHD_STATDEP_SHIFT 2
1011#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) 962#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2)
1012 963
1013/* 964/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1014 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1015 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
1016 */
1017#define OMAP4430_L3INIT_DYNDEP_SHIFT 7 965#define OMAP4430_L3INIT_DYNDEP_SHIFT 7
1018#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) 966#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7)
1019 967
1020/* 968/*
1021 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 969 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
1022 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, 970 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1023 * CM_TESLA_STATICDEP
1024 */ 971 */
1025#define OMAP4430_L3INIT_STATDEP_SHIFT 7 972#define OMAP4430_L3INIT_STATDEP_SHIFT 7
1026#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) 973#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7)
1027 974
1028/* 975/*
1029 * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, 976 * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
1030 * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 977 * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1031 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1032 */ 978 */
1033#define OMAP4430_L3_1_DYNDEP_SHIFT 5 979#define OMAP4430_L3_1_DYNDEP_SHIFT 5
1034#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) 980#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5)
1035 981
1036/* 982/*
1037 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 983 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1038 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 984 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1039 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 985 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1040 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 986 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1041 */ 987 */
1042#define OMAP4430_L3_1_STATDEP_SHIFT 5 988#define OMAP4430_L3_1_STATDEP_SHIFT 5
1043#define OMAP4430_L3_1_STATDEP_MASK (1 << 5) 989#define OMAP4430_L3_1_STATDEP_MASK (1 << 5)
1044 990
1045/* 991/*
1046 * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, 992 * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
1047 * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, 993 * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
1048 * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, 994 * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1049 * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 995 * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
1050 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
1051 */ 996 */
1052#define OMAP4430_L3_2_DYNDEP_SHIFT 6 997#define OMAP4430_L3_2_DYNDEP_SHIFT 6
1053#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) 998#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6)
1054 999
1055/* 1000/*
1056 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 1001 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1057 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 1002 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1058 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 1003 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1059 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1004 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1060 */ 1005 */
1061#define OMAP4430_L3_2_STATDEP_SHIFT 6 1006#define OMAP4430_L3_2_STATDEP_SHIFT 6
1062#define OMAP4430_L3_2_STATDEP_MASK (1 << 6) 1007#define OMAP4430_L3_2_STATDEP_MASK (1 << 6)
1063 1008
1064/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */ 1009/* Used by CM_L3_1_DYNAMICDEP */
1065#define OMAP4430_L4CFG_DYNDEP_SHIFT 12 1010#define OMAP4430_L4CFG_DYNDEP_SHIFT 12
1066#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) 1011#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12)
1067 1012
1068/* 1013/*
1069 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 1014 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
1070 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 1015 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1071 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1072 */ 1016 */
1073#define OMAP4430_L4CFG_STATDEP_SHIFT 12 1017#define OMAP4430_L4CFG_STATDEP_SHIFT 12
1074#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) 1018#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12)
1075 1019
1076/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 1020/* Used by CM_L3_2_DYNAMICDEP */
1077#define OMAP4430_L4PER_DYNDEP_SHIFT 13 1021#define OMAP4430_L4PER_DYNDEP_SHIFT 13
1078#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) 1022#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13)
1079 1023
1080/* 1024/*
1081 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 1025 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
1082 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 1026 * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1083 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1084 */ 1027 */
1085#define OMAP4430_L4PER_STATDEP_SHIFT 13 1028#define OMAP4430_L4PER_STATDEP_SHIFT 13
1086#define OMAP4430_L4PER_STATDEP_MASK (1 << 13) 1029#define OMAP4430_L4PER_STATDEP_MASK (1 << 13)
1087 1030
1088/* 1031/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1089 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1090 * CM_L4PER_DYNAMICDEP_RESTORE
1091 */
1092#define OMAP4430_L4SEC_DYNDEP_SHIFT 14 1032#define OMAP4430_L4SEC_DYNDEP_SHIFT 14
1093#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) 1033#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14)
1094 1034
1095/* 1035/*
1096 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, 1036 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1097 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE 1037 * CM_SDMA_STATICDEP
1098 */ 1038 */
1099#define OMAP4430_L4SEC_STATDEP_SHIFT 14 1039#define OMAP4430_L4SEC_STATDEP_SHIFT 14
1100#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) 1040#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14)
1101 1041
1102/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1042/* Used by CM_L4CFG_DYNAMICDEP */
1103#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 1043#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
1104#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) 1044#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15)
1105 1045
1106/* 1046/*
1107 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, 1047 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1108 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1048 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1109 */ 1049 */
1110#define OMAP4430_L4WKUP_STATDEP_SHIFT 15 1050#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
1111#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) 1051#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15)
1112 1052
1113/* 1053/*
1114 * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP, 1054 * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1115 * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1055 * CM_MPU_DYNAMICDEP
1116 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
1117 */ 1056 */
1118#define OMAP4430_MEMIF_DYNDEP_SHIFT 4 1057#define OMAP4430_MEMIF_DYNDEP_SHIFT 4
1119#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) 1058#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4)
1120 1059
1121/* 1060/*
1122 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 1061 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1123 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 1062 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1124 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 1063 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1125 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1064 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1126 */ 1065 */
1127#define OMAP4430_MEMIF_STATDEP_SHIFT 4 1066#define OMAP4430_MEMIF_STATDEP_SHIFT 4
1128#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) 1067#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4)
1129 1068
1130/* 1069/*
1131 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1070 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1132 * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, 1071 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
1133 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, 1072 * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
1134 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1073 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1135 * CM_SSC_MODFREQDIV_DPLL_USB
1136 */ 1074 */
1137#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 1075#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
1138#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) 1076#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
1139 1077
1140/* 1078/*
1141 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1079 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1142 * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, 1080 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
1143 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, 1081 * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
1144 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1082 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1145 * CM_SSC_MODFREQDIV_DPLL_USB
1146 */ 1083 */
1147#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 1084#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
1148#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) 1085#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
@@ -1155,8 +1092,7 @@
1155 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, 1092 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
1156 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, 1093 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
1157 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 1094 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
1158 * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, 1095 * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
1159 * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
1160 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, 1096 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
1161 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 1097 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1162 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, 1098 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
@@ -1165,30 +1101,24 @@
1165 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1101 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1166 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1102 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1167 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 1103 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
1168 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, 1104 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
1169 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, 1105 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
1170 * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, 1106 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
1171 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
1172 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
1173 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
1174 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, 1107 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
1175 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, 1108 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
1176 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, 1109 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
1177 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, 1110 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
1178 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, 1111 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
1179 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, 1112 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
1180 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1113 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
1181 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 1114 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
1182 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1115 * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
1183 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, 1116 * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
1184 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 1117 * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
1185 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, 1118 * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
1186 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, 1119 * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
1187 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, 1120 * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
1188 * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, 1121 * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
1189 * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
1190 * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
1191 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
1192 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, 1122 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
1193 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, 1123 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1194 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, 1124 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
@@ -1204,6 +1134,10 @@
1204#define OMAP4430_MODULEMODE_SHIFT 0 1134#define OMAP4430_MODULEMODE_SHIFT 0
1205#define OMAP4430_MODULEMODE_MASK (0x3 << 0) 1135#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
1206 1136
1137/* Used by CM_L4CFG_DYNAMICDEP */
1138#define OMAP4460_MPU_DYNDEP_SHIFT 19
1139#define OMAP4460_MPU_DYNDEP_MASK (1 << 19)
1140
1207/* Used by CM_DSS_DSS_CLKCTRL */ 1141/* Used by CM_DSS_DSS_CLKCTRL */
1208#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 1142#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
1209#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) 1143#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
@@ -1221,11 +1155,9 @@
1221#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) 1155#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
1222 1156
1223/* 1157/*
1224 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1158 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
1225 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 1159 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
1226 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1160 * CM_WKUP_GPIO1_CLKCTRL
1227 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
1228 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
1229 */ 1161 */
1230#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 1162#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
1231#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) 1163#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8)
@@ -1254,23 +1186,23 @@
1254#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 1186#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
1255#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) 1187#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10)
1256 1188
1257/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1189/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1258#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 1190#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
1259#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) 1191#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15)
1260 1192
1261/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1193/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1262#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 1194#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
1263#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) 1195#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
1264 1196
1265/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1197/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1266#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 1198#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
1267#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) 1199#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
1268 1200
1269/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1201/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1270#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 1202#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
1271#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) 1203#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
1272 1204
1273/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1205/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1274#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 1206#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
1275#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) 1207#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
1276 1208
@@ -1298,6 +1230,10 @@
1298#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 1230#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
1299#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) 1231#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
1300 1232
1233/* Used by CM_WKUP_BANDGAP_CLKCTRL */
1234#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8
1235#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8)
1236
1301/* Used by CM_DSS_DSS_CLKCTRL */ 1237/* Used by CM_DSS_DSS_CLKCTRL */
1302#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 1238#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
1303#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) 1239#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11)
@@ -1306,27 +1242,27 @@
1306#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 1242#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
1307#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) 1243#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8)
1308 1244
1309/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1245/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1310#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 1246#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
1311#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) 1247#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
1312 1248
1313/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1249/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1314#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 1250#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
1315#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) 1251#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
1316 1252
1317/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1253/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1318#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 1254#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
1319#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) 1255#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
1320 1256
1321/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1257/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1322#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 1258#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
1323#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) 1259#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
1324 1260
1325/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1261/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1326#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 1262#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
1327#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) 1263#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
1328 1264
1329/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1265/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1330#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 1266#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
1331#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) 1267#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
1332 1268
@@ -1374,7 +1310,7 @@
1374#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 1310#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
1375#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) 1311#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22)
1376 1312
1377/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */ 1313/* Used by CM_DYN_DEP_PRESCAL */
1378#define OMAP4430_PRESCAL_SHIFT 0 1314#define OMAP4430_PRESCAL_SHIFT 0
1379#define OMAP4430_PRESCAL_MASK (0x3f << 0) 1315#define OMAP4430_PRESCAL_MASK (0x3f << 0)
1380 1316
@@ -1382,10 +1318,7 @@
1382#define OMAP4430_R_RTL_SHIFT 11 1318#define OMAP4430_R_RTL_SHIFT 11
1383#define OMAP4430_R_RTL_MASK (0x1f << 11) 1319#define OMAP4430_R_RTL_MASK (0x1f << 11)
1384 1320
1385/* 1321/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
1386 * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
1387 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
1388 */
1389#define OMAP4430_SAR_MODE_SHIFT 4 1322#define OMAP4430_SAR_MODE_SHIFT 4
1390#define OMAP4430_SAR_MODE_MASK (1 << 4) 1323#define OMAP4430_SAR_MODE_MASK (1 << 4)
1391 1324
@@ -1397,7 +1330,7 @@
1397#define OMAP4430_SCHEME_SHIFT 30 1330#define OMAP4430_SCHEME_SHIFT 30
1398#define OMAP4430_SCHEME_MASK (0x3 << 30) 1331#define OMAP4430_SCHEME_MASK (0x3 << 30)
1399 1332
1400/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1333/* Used by CM_L4CFG_DYNAMICDEP */
1401#define OMAP4430_SDMA_DYNDEP_SHIFT 11 1334#define OMAP4430_SDMA_DYNDEP_SHIFT 11
1402#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) 1335#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11)
1403 1336
@@ -1417,10 +1350,10 @@
1417 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1350 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1418 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1351 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1419 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1352 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1420 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, 1353 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1421 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, 1354 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
1422 * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, 1355 * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1423 * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL 1356 * CM_TESLA_TESLA_CLKCTRL
1424 */ 1357 */
1425#define OMAP4430_STBYST_SHIFT 18 1358#define OMAP4430_STBYST_SHIFT 18
1426#define OMAP4430_STBYST_MASK (1 << 18) 1359#define OMAP4430_STBYST_MASK (1 << 18)
@@ -1438,17 +1371,13 @@
1438#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) 1371#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
1439 1372
1440/* 1373/*
1441 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 1374 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
1442 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 1375 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1443 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1444 */ 1376 */
1445#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 1377#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
1446#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) 1378#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9)
1447 1379
1448/* 1380/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
1449 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
1450 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
1451 */
1452#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 1381#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
1453#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) 1382#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9)
1454 1383
@@ -1457,30 +1386,24 @@
1457#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) 1386#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11)
1458 1387
1459/* 1388/*
1460 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 1389 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
1461 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 1390 * CM_DIV_M4_DPLL_PER
1462 */ 1391 */
1463#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 1392#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
1464#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) 1393#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
1465 1394
1466/* 1395/*
1467 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 1396 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
1468 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 1397 * CM_DIV_M5_DPLL_PER
1469 */ 1398 */
1470#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 1399#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
1471#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) 1400#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
1472 1401
1473/* 1402/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
1474 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
1475 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
1476 */
1477#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 1403#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
1478#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) 1404#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
1479 1405
1480/* 1406/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
1481 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
1482 * CM_DIV_M7_DPLL_PER
1483 */
1484#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 1407#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
1485#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) 1408#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9)
1486 1409
@@ -1496,7 +1419,7 @@
1496#define OMAP4430_SYS_CLKSEL_SHIFT 0 1419#define OMAP4430_SYS_CLKSEL_SHIFT 0
1497#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) 1420#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0)
1498 1421
1499/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1422/* Used by CM_L4CFG_DYNAMICDEP */
1500#define OMAP4430_TESLA_DYNDEP_SHIFT 1 1423#define OMAP4430_TESLA_DYNDEP_SHIFT 1
1501#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) 1424#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1)
1502 1425
@@ -1505,11 +1428,9 @@
1505#define OMAP4430_TESLA_STATDEP_MASK (1 << 1) 1428#define OMAP4430_TESLA_STATDEP_MASK (1 << 1)
1506 1429
1507/* 1430/*
1508 * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP, 1431 * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
1509 * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, 1432 * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1510 * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1433 * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1511 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1512 * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1513 */ 1434 */
1514#define OMAP4430_WINDOWSIZE_SHIFT 24 1435#define OMAP4430_WINDOWSIZE_SHIFT 24
1515#define OMAP4430_WINDOWSIZE_MASK (0xf << 24) 1436#define OMAP4430_WINDOWSIZE_MASK (0xf << 24)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-02 17:44:00 -0400