diff options
Diffstat (limited to 'arch/arm/mach-omap2/clkt2xxx_dpllcore.c')
-rw-r--r-- | arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 530a76bc4a6..4ae43922208 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c | |||
@@ -54,7 +54,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) | |||
54 | 54 | ||
55 | core_clk = omap2_get_dpll_rate(clk); | 55 | core_clk = omap2_get_dpll_rate(clk); |
56 | 56 | ||
57 | v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 57 | v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
58 | v &= OMAP24XX_CORE_CLK_SRC_MASK; | 58 | v &= OMAP24XX_CORE_CLK_SRC_MASK; |
59 | 59 | ||
60 | if (v == CORE_CLK_SRC_32K) | 60 | if (v == CORE_CLK_SRC_32K) |
@@ -73,7 +73,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) | |||
73 | { | 73 | { |
74 | u32 high, low, core_clk_src; | 74 | u32 high, low, core_clk_src; |
75 | 75 | ||
76 | core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 76 | core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
77 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; | 77 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; |
78 | 78 | ||
79 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ | 79 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ |
@@ -111,7 +111,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |||
111 | const struct dpll_data *dd; | 111 | const struct dpll_data *dd; |
112 | 112 | ||
113 | cur_rate = omap2xxx_clk_get_core_rate(dclk); | 113 | cur_rate = omap2xxx_clk_get_core_rate(dclk); |
114 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 114 | mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
115 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | 115 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; |
116 | 116 | ||
117 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | 117 | if ((rate == (cur_rate / 2)) && (mult == 2)) { |
@@ -136,7 +136,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |||
136 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | 136 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | |
137 | dd->div1_mask); | 137 | dd->div1_mask); |
138 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); | 138 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); |
139 | tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 139 | tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
140 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; | 140 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; |
141 | if (rate > low) { | 141 | if (rate > low) { |
142 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; | 142 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; |