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-rw-r--r--arch/arm/mach-mxs/gpio.c331
1 files changed, 0 insertions, 331 deletions
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
deleted file mode 100644
index 2c950fef71a..00000000000
--- a/arch/arm/mach-mxs/gpio.c
+++ /dev/null
@@ -1,331 +0,0 @@
1/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/gpio.h>
28#include <mach/mx23.h>
29#include <mach/mx28.h>
30#include <asm-generic/bug.h>
31
32#include "gpio.h"
33
34static struct mxs_gpio_port *mxs_gpio_ports;
35static int gpio_table_size;
36
37#define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
38#define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
39#define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
40#define PINCTRL_PIN2IRQ(n) ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
41#define PINCTRL_IRQEN(n) ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
42#define PINCTRL_IRQLEV(n) ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
43#define PINCTRL_IRQPOL(n) ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
44#define PINCTRL_IRQSTAT(n) ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
45
46#define GPIO_INT_FALL_EDGE 0x0
47#define GPIO_INT_LOW_LEV 0x1
48#define GPIO_INT_RISE_EDGE 0x2
49#define GPIO_INT_HIGH_LEV 0x3
50#define GPIO_INT_LEV_MASK (1 << 0)
51#define GPIO_INT_POL_MASK (1 << 1)
52
53/* Note: This driver assumes 32 GPIOs are handled in one register */
54
55static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
56{
57 __mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id));
58}
59
60static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
61 int enable)
62{
63 if (enable) {
64 __mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id));
65 __mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id));
66 } else {
67 __mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id));
68 }
69}
70
71static void mxs_gpio_ack_irq(struct irq_data *d)
72{
73 u32 gpio = irq_to_gpio(d->irq);
74 clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f);
75}
76
77static void mxs_gpio_mask_irq(struct irq_data *d)
78{
79 u32 gpio = irq_to_gpio(d->irq);
80 set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0);
81}
82
83static void mxs_gpio_unmask_irq(struct irq_data *d)
84{
85 u32 gpio = irq_to_gpio(d->irq);
86 set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1);
87}
88
89static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
90
91static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
92{
93 u32 gpio = irq_to_gpio(d->irq);
94 u32 pin_mask = 1 << (gpio & 31);
95 struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
96 void __iomem *pin_addr;
97 int edge;
98
99 switch (type) {
100 case IRQ_TYPE_EDGE_RISING:
101 edge = GPIO_INT_RISE_EDGE;
102 break;
103 case IRQ_TYPE_EDGE_FALLING:
104 edge = GPIO_INT_FALL_EDGE;
105 break;
106 case IRQ_TYPE_LEVEL_LOW:
107 edge = GPIO_INT_LOW_LEV;
108 break;
109 case IRQ_TYPE_LEVEL_HIGH:
110 edge = GPIO_INT_HIGH_LEV;
111 break;
112 default:
113 return -EINVAL;
114 }
115
116 /* set level or edge */
117 pin_addr = port->base + PINCTRL_IRQLEV(port->id);
118 if (edge & GPIO_INT_LEV_MASK)
119 __mxs_setl(pin_mask, pin_addr);
120 else
121 __mxs_clrl(pin_mask, pin_addr);
122
123 /* set polarity */
124 pin_addr = port->base + PINCTRL_IRQPOL(port->id);
125 if (edge & GPIO_INT_POL_MASK)
126 __mxs_setl(pin_mask, pin_addr);
127 else
128 __mxs_clrl(pin_mask, pin_addr);
129
130 clear_gpio_irqstatus(port, gpio & 0x1f);
131
132 return 0;
133}
134
135/* MXS has one interrupt *per* gpio port */
136static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
137{
138 u32 irq_stat;
139 struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq);
140 u32 gpio_irq_no_base = port->virtual_irq_start;
141
142 desc->irq_data.chip->irq_ack(&desc->irq_data);
143
144 irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) &
145 __raw_readl(port->base + PINCTRL_IRQEN(port->id));
146
147 while (irq_stat != 0) {
148 int irqoffset = fls(irq_stat) - 1;
149 generic_handle_irq(gpio_irq_no_base + irqoffset);
150 irq_stat &= ~(1 << irqoffset);
151 }
152}
153
154/*
155 * Set interrupt number "irq" in the GPIO as a wake-up source.
156 * While system is running, all registered GPIO interrupts need to have
157 * wake-up enabled. When system is suspended, only selected GPIO interrupts
158 * need to have wake-up enabled.
159 * @param irq interrupt source number
160 * @param enable enable as wake-up if equal to non-zero
161 * @return This function returns 0 on success.
162 */
163static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
164{
165 u32 gpio = irq_to_gpio(d->irq);
166 u32 gpio_idx = gpio & 0x1f;
167 struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
168
169 if (enable) {
170 if (port->irq_high && (gpio_idx >= 16))
171 enable_irq_wake(port->irq_high);
172 else
173 enable_irq_wake(port->irq);
174 } else {
175 if (port->irq_high && (gpio_idx >= 16))
176 disable_irq_wake(port->irq_high);
177 else
178 disable_irq_wake(port->irq);
179 }
180
181 return 0;
182}
183
184static struct irq_chip gpio_irq_chip = {
185 .name = "mxs gpio",
186 .irq_ack = mxs_gpio_ack_irq,
187 .irq_mask = mxs_gpio_mask_irq,
188 .irq_unmask = mxs_gpio_unmask_irq,
189 .irq_set_type = mxs_gpio_set_irq_type,
190 .irq_set_wake = mxs_gpio_set_wake_irq,
191};
192
193static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
194 int dir)
195{
196 struct mxs_gpio_port *port =
197 container_of(chip, struct mxs_gpio_port, chip);
198 void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);
199
200 if (dir)
201 __mxs_setl(1 << offset, pin_addr);
202 else
203 __mxs_clrl(1 << offset, pin_addr);
204}
205
206static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
207{
208 struct mxs_gpio_port *port =
209 container_of(chip, struct mxs_gpio_port, chip);
210
211 return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
212}
213
214static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
215{
216 struct mxs_gpio_port *port =
217 container_of(chip, struct mxs_gpio_port, chip);
218 void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);
219
220 if (value)
221 __mxs_setl(1 << offset, pin_addr);
222 else
223 __mxs_clrl(1 << offset, pin_addr);
224}
225
226static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
227{
228 struct mxs_gpio_port *port =
229 container_of(chip, struct mxs_gpio_port, chip);
230
231 return port->virtual_irq_start + offset;
232}
233
234static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
235{
236 mxs_set_gpio_direction(chip, offset, 0);
237 return 0;
238}
239
240static int mxs_gpio_direction_output(struct gpio_chip *chip,
241 unsigned offset, int value)
242{
243 mxs_gpio_set(chip, offset, value);
244 mxs_set_gpio_direction(chip, offset, 1);
245 return 0;
246}
247
248int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
249{
250 int i, j;
251
252 /* save for local usage */
253 mxs_gpio_ports = port;
254 gpio_table_size = cnt;
255
256 pr_info("MXS GPIO hardware\n");
257
258 for (i = 0; i < cnt; i++) {
259 /* disable the interrupt and clear the status */
260 __raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i));
261 __raw_writel(0, port[i].base + PINCTRL_IRQEN(i));
262
263 /* clear address has to be used to clear IRQSTAT bits */
264 __mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i));
265
266 for (j = port[i].virtual_irq_start;
267 j < port[i].virtual_irq_start + 32; j++) {
268 irq_set_chip_and_handler(j, &gpio_irq_chip,
269 handle_level_irq);
270 set_irq_flags(j, IRQF_VALID);
271 }
272
273 /* setup one handler for each entry */
274 irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler);
275 irq_set_handler_data(port[i].irq, &port[i]);
276
277 /* register gpio chip */
278 port[i].chip.direction_input = mxs_gpio_direction_input;
279 port[i].chip.direction_output = mxs_gpio_direction_output;
280 port[i].chip.get = mxs_gpio_get;
281 port[i].chip.set = mxs_gpio_set;
282 port[i].chip.to_irq = mxs_gpio_to_irq;
283 port[i].chip.base = i * 32;
284 port[i].chip.ngpio = 32;
285
286 /* its a serious configuration bug when it fails */
287 BUG_ON(gpiochip_add(&port[i].chip) < 0);
288 }
289
290 return 0;
291}
292
293#define MX23_GPIO_BASE MX23_IO_ADDRESS(MX23_PINCTRL_BASE_ADDR)
294#define MX28_GPIO_BASE MX28_IO_ADDRESS(MX28_PINCTRL_BASE_ADDR)
295
296#define DEFINE_MXS_GPIO_PORT(_base, _irq, _id) \
297 { \
298 .chip.label = "gpio-" #_id, \
299 .id = _id, \
300 .irq = _irq, \
301 .base = _base, \
302 .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \
303 }
304
305#ifdef CONFIG_SOC_IMX23
306static struct mxs_gpio_port mx23_gpio_ports[] = {
307 DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO0, 0),
308 DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO1, 1),
309 DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO2, 2),
310};
311
312int __init mx23_register_gpios(void)
313{
314 return mxs_gpio_init(mx23_gpio_ports, ARRAY_SIZE(mx23_gpio_ports));
315}
316#endif
317
318#ifdef CONFIG_SOC_IMX28
319static struct mxs_gpio_port mx28_gpio_ports[] = {
320 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO0, 0),
321 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO1, 1),
322 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO2, 2),
323 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO3, 3),
324 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO4, 4),
325};
326
327int __init mx28_register_gpios(void)
328{
329 return mxs_gpio_init(mx28_gpio_ports, ARRAY_SIZE(mx28_gpio_ports));
330}
331#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-03 00:49:44 -0400