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-rw-r--r--arch/arm/mach-msm/board-msm8x60.c7
-rw-r--r--arch/arm/mach-msm/include/mach/smp.h4
-rw-r--r--arch/arm/mach-msm/timer.c5
3 files changed, 5 insertions, 11 deletions
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 7486a681cc7..9b5eb2b4ae1 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -28,8 +28,6 @@
28#include <mach/board.h> 28#include <mach/board.h>
29#include <mach/msm_iomap.h> 29#include <mach/msm_iomap.h>
30 30
31void __iomem *gic_cpu_base_addr;
32
33unsigned long clk_get_max_axi_khz(void) 31unsigned long clk_get_max_axi_khz(void)
34{ 32{
35 return 0; 33 return 0;
@@ -44,9 +42,8 @@ static void __init msm8x60_init_irq(void)
44{ 42{
45 unsigned int i; 43 unsigned int i;
46 44
47 gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START); 45 gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
48 gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE; 46 (void *)MSM_QGIC_CPU_BASE);
49 gic_cpu_init(0, MSM_QGIC_CPU_BASE);
50 47
51 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ 48 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
52 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); 49 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h
index 3ff7bf5e679..a95f7b9efe3 100644
--- a/arch/arm/mach-msm/include/mach/smp.h
+++ b/arch/arm/mach-msm/include/mach/smp.h
@@ -31,9 +31,9 @@
31 31
32#include <asm/hardware/gic.h> 32#include <asm/hardware/gic.h>
33 33
34static inline void smp_cross_call(const struct cpumask *mask) 34static inline void smp_cross_call(const struct cpumask *mask, int ipi)
35{ 35{
36 gic_raise_softirq(mask, 1); 36 gic_raise_softirq(mask, ipi);
37} 37}
38 38
39#endif 39#endif
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 950100f19d0..595be7fea31 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -137,7 +137,6 @@ static struct msm_clock msm_clocks[] = {
137 .rating = 200, 137 .rating = 200,
138 .read = msm_gpt_read, 138 .read = msm_gpt_read,
139 .mask = CLOCKSOURCE_MASK(32), 139 .mask = CLOCKSOURCE_MASK(32),
140 .shift = 17,
141 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 140 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
142 }, 141 },
143 .irq = { 142 .irq = {
@@ -164,7 +163,6 @@ static struct msm_clock msm_clocks[] = {
164 .rating = 300, 163 .rating = 300,
165 .read = msm_dgt_read, 164 .read = msm_dgt_read,
166 .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)), 165 .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
167 .shift = 24 - MSM_DGT_SHIFT,
168 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 166 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
169 }, 167 },
170 .irq = { 168 .irq = {
@@ -205,8 +203,7 @@ static void __init msm_timer_init(void)
205 ce->min_delta_ns = clockevent_delta2ns(4, ce); 203 ce->min_delta_ns = clockevent_delta2ns(4, ce);
206 ce->cpumask = cpumask_of(0); 204 ce->cpumask = cpumask_of(0);
207 205
208 cs->mult = clocksource_hz2mult(clock->freq, cs->shift); 206 res = clocksource_register_hz(cs, clock->freq);
209 res = clocksource_register(cs);
210 if (res) 207 if (res)
211 printk(KERN_ERR "msm_timer_init: clocksource_register " 208 printk(KERN_ERR "msm_timer_init: clocksource_register "
212 "failed for %s\n", cs->name); 209 "failed for %s\n", cs->name);