diff options
Diffstat (limited to 'arch/arm/mach-msm/include/mach')
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | 10 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap-7x30.h | 10 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | 10 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap.h | 2 |
4 files changed, 14 insertions, 18 deletions
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h index 8f99d97615a..94fe9fe6feb 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | |||
@@ -55,13 +55,11 @@ | |||
55 | #define MSM_DMOV_PHYS 0xA9700000 | 55 | #define MSM_DMOV_PHYS 0xA9700000 |
56 | #define MSM_DMOV_SIZE SZ_4K | 56 | #define MSM_DMOV_SIZE SZ_4K |
57 | 57 | ||
58 | #define MSM_GPIO1_BASE IOMEM(0xE0003000) | 58 | #define MSM7X00_GPIO1_PHYS 0xA9200000 |
59 | #define MSM_GPIO1_PHYS 0xA9200000 | 59 | #define MSM7X00_GPIO1_SIZE SZ_4K |
60 | #define MSM_GPIO1_SIZE SZ_4K | ||
61 | 60 | ||
62 | #define MSM_GPIO2_BASE IOMEM(0xE0004000) | 61 | #define MSM7X00_GPIO2_PHYS 0xA9300000 |
63 | #define MSM_GPIO2_PHYS 0xA9300000 | 62 | #define MSM7X00_GPIO2_SIZE SZ_4K |
64 | #define MSM_GPIO2_SIZE SZ_4K | ||
65 | 63 | ||
66 | #define MSM_CLK_CTL_BASE IOMEM(0xE0005000) | 64 | #define MSM_CLK_CTL_BASE IOMEM(0xE0005000) |
67 | #define MSM_CLK_CTL_PHYS 0xA8600000 | 65 | #define MSM_CLK_CTL_PHYS 0xA8600000 |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h index 4d84be15955..37694442d1b 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h | |||
@@ -46,13 +46,11 @@ | |||
46 | #define MSM_DMOV_PHYS 0xAC400000 | 46 | #define MSM_DMOV_PHYS 0xAC400000 |
47 | #define MSM_DMOV_SIZE SZ_4K | 47 | #define MSM_DMOV_SIZE SZ_4K |
48 | 48 | ||
49 | #define MSM_GPIO1_BASE IOMEM(0xE0003000) | 49 | #define MSM7X30_GPIO1_PHYS 0xAC001000 |
50 | #define MSM_GPIO1_PHYS 0xAC001000 | 50 | #define MSM7X30_GPIO1_SIZE SZ_4K |
51 | #define MSM_GPIO1_SIZE SZ_4K | ||
52 | 51 | ||
53 | #define MSM_GPIO2_BASE IOMEM(0xE0004000) | 52 | #define MSM7X30_GPIO2_PHYS 0xAC101000 |
54 | #define MSM_GPIO2_PHYS 0xAC101000 | 53 | #define MSM7X30_GPIO2_SIZE SZ_4K |
55 | #define MSM_GPIO2_SIZE SZ_4K | ||
56 | 54 | ||
57 | #define MSM_CLK_CTL_BASE IOMEM(0xE0005000) | 55 | #define MSM_CLK_CTL_BASE IOMEM(0xE0005000) |
58 | #define MSM_CLK_CTL_PHYS 0xAB800000 | 56 | #define MSM_CLK_CTL_PHYS 0xAB800000 |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index d4143201999..d67cd73316f 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | |||
@@ -46,13 +46,11 @@ | |||
46 | #define MSM_DMOV_PHYS 0xA9700000 | 46 | #define MSM_DMOV_PHYS 0xA9700000 |
47 | #define MSM_DMOV_SIZE SZ_4K | 47 | #define MSM_DMOV_SIZE SZ_4K |
48 | 48 | ||
49 | #define MSM_GPIO1_BASE IOMEM(0xE0003000) | 49 | #define QSD8X50_GPIO1_PHYS 0xA9000000 |
50 | #define MSM_GPIO1_PHYS 0xA9000000 | 50 | #define QSD8X50_GPIO1_SIZE SZ_4K |
51 | #define MSM_GPIO1_SIZE SZ_4K | ||
52 | 51 | ||
53 | #define MSM_GPIO2_BASE IOMEM(0xE0004000) | 52 | #define QSD8X50_GPIO2_PHYS 0xA9100000 |
54 | #define MSM_GPIO2_PHYS 0xA9100000 | 53 | #define QSD8X50_GPIO2_SIZE SZ_4K |
55 | #define MSM_GPIO2_SIZE SZ_4K | ||
56 | 54 | ||
57 | #define MSM_CLK_CTL_BASE IOMEM(0xE0005000) | 55 | #define MSM_CLK_CTL_BASE IOMEM(0xE0005000) |
58 | #define MSM_CLK_CTL_PHYS 0xA8600000 | 56 | #define MSM_CLK_CTL_PHYS 0xA8600000 |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index 2f494b6a9d0..4ded15238b6 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h | |||
@@ -61,5 +61,7 @@ | |||
61 | #define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) | 61 | #define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) |
62 | #define MSM_TMR_BASE IOMEM(0xF0200000) | 62 | #define MSM_TMR_BASE IOMEM(0xF0200000) |
63 | #define MSM_TMR0_BASE IOMEM(0xF0201000) | 63 | #define MSM_TMR0_BASE IOMEM(0xF0201000) |
64 | #define MSM_GPIO1_BASE IOMEM(0xE0003000) | ||
65 | #define MSM_GPIO2_BASE IOMEM(0xE0004000) | ||
64 | 66 | ||
65 | #endif | 67 | #endif |