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-rw-r--r--arch/arm/mach-mmp/Kconfig3
-rw-r--r--arch/arm/mach-mmp/Makefile8
-rw-r--r--arch/arm/mach-mmp/aspenite.c2
-rw-r--r--arch/arm/mach-mmp/clock-mmp2.c111
-rw-r--r--arch/arm/mach-mmp/clock-pxa168.c91
-rw-r--r--arch/arm/mach-mmp/clock-pxa910.c67
-rw-r--r--arch/arm/mach-mmp/common.h3
-rw-r--r--arch/arm/mach-mmp/include/mach/debug-macro.S12
-rw-r--r--arch/arm/mach-mmp/include/mach/mmp2.h2
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa168.h4
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa910.h2
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apbc.h95
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apmu.h15
-rw-r--r--arch/arm/mach-mmp/include/mach/sram.h35
-rw-r--r--arch/arm/mach-mmp/irq.c4
-rw-r--r--arch/arm/mach-mmp/mmp2.c73
-rw-r--r--arch/arm/mach-mmp/pxa168.c58
-rw-r--r--arch/arm/mach-mmp/pxa910.c44
-rw-r--r--arch/arm/mach-mmp/sram.c2
-rw-r--r--arch/arm/mach-mmp/teton_bga.c2
-rw-r--r--arch/arm/mach-mmp/ttc_dkb.c10
21 files changed, 329 insertions, 314 deletions
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 7fddd01b85b..d697d07a1bf 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -108,18 +108,21 @@ endmenu
108config CPU_PXA168 108config CPU_PXA168
109 bool 109 bool
110 select CPU_MOHAWK 110 select CPU_MOHAWK
111 select COMMON_CLK
111 help 112 help
112 Select code specific to PXA168 113 Select code specific to PXA168
113 114
114config CPU_PXA910 115config CPU_PXA910
115 bool 116 bool
116 select CPU_MOHAWK 117 select CPU_MOHAWK
118 select COMMON_CLK
117 help 119 help
118 Select code specific to PXA910 120 Select code specific to PXA910
119 121
120config CPU_MMP2 122config CPU_MMP2
121 bool 123 bool
122 select CPU_PJ4 124 select CPU_PJ4
125 select COMMON_CLK
123 help 126 help
124 Select code specific to MMP2. MMP2 is ARMv7 compatible. 127 Select code specific to MMP2. MMP2 is ARMv7 compatible.
125 128
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index b786f7e6cd1..095c155d6fb 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,13 +2,19 @@
2# Makefile for Marvell's PXA168 processors line 2# Makefile for Marvell's PXA168 processors line
3# 3#
4 4
5obj-y += common.o clock.o devices.o time.o irq.o 5obj-y += common.o devices.o time.o irq.o
6 6
7# SoC support 7# SoC support
8obj-$(CONFIG_CPU_PXA168) += pxa168.o 8obj-$(CONFIG_CPU_PXA168) += pxa168.o
9obj-$(CONFIG_CPU_PXA910) += pxa910.o 9obj-$(CONFIG_CPU_PXA910) += pxa910.o
10obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o 10obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o
11 11
12ifeq ($(CONFIG_COMMON_CLK), )
13obj-y += clock.o
14obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o
15obj-$(CONFIG_CPU_PXA910) += clock-pxa910.o
16obj-$(CONFIG_CPU_MMP2) += clock-mmp2.o
17endif
12ifeq ($(CONFIG_PM),y) 18ifeq ($(CONFIG_PM),y)
13obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o 19obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
14obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o 20obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 223090b1444..e5dba9c5dc5 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -27,7 +27,7 @@
27#include <mach/irqs.h> 27#include <mach/irqs.h>
28#include <video/pxa168fb.h> 28#include <video/pxa168fb.h>
29#include <linux/input.h> 29#include <linux/input.h>
30#include <plat/pxa27x_keypad.h> 30#include <linux/platform_data/keypad-pxa27x.h>
31 31
32#include "common.h" 32#include "common.h"
33 33
diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c
new file mode 100644
index 00000000000..21d22002cd1
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-mmp2.c
@@ -0,0 +1,111 @@
1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/list.h>
5#include <linux/io.h>
6#include <linux/clk.h>
7
8#include <mach/addr-map.h>
9
10#include "common.h"
11#include "clock.h"
12
13/*
14 * APB Clock register offsets for MMP2
15 */
16#define APBC_RTC APBC_REG(0x000)
17#define APBC_TWSI1 APBC_REG(0x004)
18#define APBC_TWSI2 APBC_REG(0x008)
19#define APBC_TWSI3 APBC_REG(0x00c)
20#define APBC_TWSI4 APBC_REG(0x010)
21#define APBC_KPC APBC_REG(0x018)
22#define APBC_UART1 APBC_REG(0x02c)
23#define APBC_UART2 APBC_REG(0x030)
24#define APBC_UART3 APBC_REG(0x034)
25#define APBC_GPIO APBC_REG(0x038)
26#define APBC_PWM0 APBC_REG(0x03c)
27#define APBC_PWM1 APBC_REG(0x040)
28#define APBC_PWM2 APBC_REG(0x044)
29#define APBC_PWM3 APBC_REG(0x048)
30#define APBC_SSP0 APBC_REG(0x04c)
31#define APBC_SSP1 APBC_REG(0x050)
32#define APBC_SSP2 APBC_REG(0x054)
33#define APBC_SSP3 APBC_REG(0x058)
34#define APBC_SSP4 APBC_REG(0x05c)
35#define APBC_SSP5 APBC_REG(0x060)
36#define APBC_TWSI5 APBC_REG(0x07c)
37#define APBC_TWSI6 APBC_REG(0x080)
38#define APBC_UART4 APBC_REG(0x088)
39
40#define APMU_USB APMU_REG(0x05c)
41#define APMU_NAND APMU_REG(0x060)
42#define APMU_SDH0 APMU_REG(0x054)
43#define APMU_SDH1 APMU_REG(0x058)
44#define APMU_SDH2 APMU_REG(0x0e8)
45#define APMU_SDH3 APMU_REG(0x0ec)
46
47static void sdhc_clk_enable(struct clk *clk)
48{
49 uint32_t clk_rst;
50
51 clk_rst = __raw_readl(clk->clk_rst);
52 clk_rst |= clk->enable_val;
53 __raw_writel(clk_rst, clk->clk_rst);
54}
55
56static void sdhc_clk_disable(struct clk *clk)
57{
58 uint32_t clk_rst;
59
60 clk_rst = __raw_readl(clk->clk_rst);
61 clk_rst &= ~clk->enable_val;
62 __raw_writel(clk_rst, clk->clk_rst);
63}
64
65struct clkops sdhc_clk_ops = {
66 .enable = sdhc_clk_enable,
67 .disable = sdhc_clk_disable,
68};
69
70/* APB peripheral clocks */
71static APBC_CLK(uart1, UART1, 1, 26000000);
72static APBC_CLK(uart2, UART2, 1, 26000000);
73static APBC_CLK(uart3, UART3, 1, 26000000);
74static APBC_CLK(uart4, UART4, 1, 26000000);
75static APBC_CLK(twsi1, TWSI1, 0, 26000000);
76static APBC_CLK(twsi2, TWSI2, 0, 26000000);
77static APBC_CLK(twsi3, TWSI3, 0, 26000000);
78static APBC_CLK(twsi4, TWSI4, 0, 26000000);
79static APBC_CLK(twsi5, TWSI5, 0, 26000000);
80static APBC_CLK(twsi6, TWSI6, 0, 26000000);
81static APBC_CLK(gpio, GPIO, 0, 26000000);
82
83static APMU_CLK(nand, NAND, 0xbf, 100000000);
84static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
85static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
86static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
87static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
88
89static struct clk_lookup mmp2_clkregs[] = {
90 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
91 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
92 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
93 INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
94 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
95 INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
96 INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
97 INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
98 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
99 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
100 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
101 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
102 INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
103 INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
104 INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
105 INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
106};
107
108void __init mmp2_clk_init(void)
109{
110 clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
111}
diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
new file mode 100644
index 00000000000..5e6c18ccebd
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa168.c
@@ -0,0 +1,91 @@
1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/list.h>
5#include <linux/io.h>
6#include <linux/clk.h>
7
8#include <mach/addr-map.h>
9
10#include "common.h"
11#include "clock.h"
12
13/*
14 * APB clock register offsets for PXA168
15 */
16#define APBC_UART1 APBC_REG(0x000)
17#define APBC_UART2 APBC_REG(0x004)
18#define APBC_GPIO APBC_REG(0x008)
19#define APBC_PWM1 APBC_REG(0x00c)
20#define APBC_PWM2 APBC_REG(0x010)
21#define APBC_PWM3 APBC_REG(0x014)
22#define APBC_PWM4 APBC_REG(0x018)
23#define APBC_RTC APBC_REG(0x028)
24#define APBC_TWSI0 APBC_REG(0x02c)
25#define APBC_KPC APBC_REG(0x030)
26#define APBC_TWSI1 APBC_REG(0x06c)
27#define APBC_UART3 APBC_REG(0x070)
28#define APBC_SSP1 APBC_REG(0x81c)
29#define APBC_SSP2 APBC_REG(0x820)
30#define APBC_SSP3 APBC_REG(0x84c)
31#define APBC_SSP4 APBC_REG(0x858)
32#define APBC_SSP5 APBC_REG(0x85c)
33
34#define APMU_NAND APMU_REG(0x060)
35#define APMU_LCD APMU_REG(0x04c)
36#define APMU_ETH APMU_REG(0x0fc)
37#define APMU_USB APMU_REG(0x05c)
38
39/* APB peripheral clocks */
40static APBC_CLK(uart1, UART1, 1, 14745600);
41static APBC_CLK(uart2, UART2, 1, 14745600);
42static APBC_CLK(uart3, UART3, 1, 14745600);
43static APBC_CLK(twsi0, TWSI0, 1, 33000000);
44static APBC_CLK(twsi1, TWSI1, 1, 33000000);
45static APBC_CLK(pwm1, PWM1, 1, 13000000);
46static APBC_CLK(pwm2, PWM2, 1, 13000000);
47static APBC_CLK(pwm3, PWM3, 1, 13000000);
48static APBC_CLK(pwm4, PWM4, 1, 13000000);
49static APBC_CLK(ssp1, SSP1, 4, 0);
50static APBC_CLK(ssp2, SSP2, 4, 0);
51static APBC_CLK(ssp3, SSP3, 4, 0);
52static APBC_CLK(ssp4, SSP4, 4, 0);
53static APBC_CLK(ssp5, SSP5, 4, 0);
54static APBC_CLK(gpio, GPIO, 0, 13000000);
55static APBC_CLK(keypad, KPC, 0, 32000);
56static APBC_CLK(rtc, RTC, 8, 32768);
57
58static APMU_CLK(nand, NAND, 0x19b, 156000000);
59static APMU_CLK(lcd, LCD, 0x7f, 312000000);
60static APMU_CLK(eth, ETH, 0x09, 0);
61static APMU_CLK(usb, USB, 0x12, 0);
62
63/* device and clock bindings */
64static struct clk_lookup pxa168_clkregs[] = {
65 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
66 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
67 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
68 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
69 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
70 INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
71 INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
72 INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
73 INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
74 INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
75 INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
76 INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
77 INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
78 INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
79 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
80 INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
81 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
82 INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
83 INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
84 INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
85 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
86};
87
88void __init pxa168_clk_init(void)
89{
90 clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
91}
diff --git a/arch/arm/mach-mmp/clock-pxa910.c b/arch/arm/mach-mmp/clock-pxa910.c
new file mode 100644
index 00000000000..933ea71d0b5
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa910.c
@@ -0,0 +1,67 @@
1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/list.h>
5#include <linux/io.h>
6#include <linux/clk.h>
7
8#include <mach/addr-map.h>
9
10#include "common.h"
11#include "clock.h"
12
13/*
14 * APB Clock register offsets for PXA910
15 */
16#define APBC_UART0 APBC_REG(0x000)
17#define APBC_UART1 APBC_REG(0x004)
18#define APBC_GPIO APBC_REG(0x008)
19#define APBC_PWM1 APBC_REG(0x00c)
20#define APBC_PWM2 APBC_REG(0x010)
21#define APBC_PWM3 APBC_REG(0x014)
22#define APBC_PWM4 APBC_REG(0x018)
23#define APBC_SSP1 APBC_REG(0x01c)
24#define APBC_SSP2 APBC_REG(0x020)
25#define APBC_RTC APBC_REG(0x028)
26#define APBC_TWSI0 APBC_REG(0x02c)
27#define APBC_KPC APBC_REG(0x030)
28#define APBC_SSP3 APBC_REG(0x04c)
29#define APBC_TWSI1 APBC_REG(0x06c)
30
31#define APMU_NAND APMU_REG(0x060)
32#define APMU_USB APMU_REG(0x05c)
33
34static APBC_CLK(uart1, UART0, 1, 14745600);
35static APBC_CLK(uart2, UART1, 1, 14745600);
36static APBC_CLK(twsi0, TWSI0, 1, 33000000);
37static APBC_CLK(twsi1, TWSI1, 1, 33000000);
38static APBC_CLK(pwm1, PWM1, 1, 13000000);
39static APBC_CLK(pwm2, PWM2, 1, 13000000);
40static APBC_CLK(pwm3, PWM3, 1, 13000000);
41static APBC_CLK(pwm4, PWM4, 1, 13000000);
42static APBC_CLK(gpio, GPIO, 0, 13000000);
43static APBC_CLK(rtc, RTC, 8, 32768);
44
45static APMU_CLK(nand, NAND, 0x19b, 156000000);
46static APMU_CLK(u2o, USB, 0x1b, 480000000);
47
48/* device and clock bindings */
49static struct clk_lookup pxa910_clkregs[] = {
50 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
51 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
52 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
53 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
54 INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
55 INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
56 INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
57 INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
58 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
59 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
60 INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
61 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
62};
63
64void __init pxa910_clk_init(void)
65{
66 clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
67}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 1c9d6c1ea97..bd453274fca 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -7,3 +7,6 @@ extern void timer_init(int irq);
7extern void __init icu_init_irq(void); 7extern void __init icu_init_irq(void);
8extern void __init mmp_map_io(void); 8extern void __init mmp_map_io(void);
9extern void mmp_restart(char, const char *); 9extern void mmp_restart(char, const char *);
10extern void __init pxa168_clk_init(void);
11extern void __init pxa910_clk_init(void);
12extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
index b6f14d203c2..5c3cc29688a 100644
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -9,13 +9,21 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#if defined(CONFIG_DEBUG_MMP_UART2)
13#define MMP_UART_OFFSET 0x00017000
14#elif defined(CONFIG_DEBUG_MMP_UART3)
15#define MMP_UART_OFFSET 0x00018000
16#else
17#error "Select uart for DEBUG_LL"
18#endif
19
12#include <mach/addr-map.h> 20#include <mach/addr-map.h>
13 21
14 .macro addruart, rp, rv, tmp 22 .macro addruart, rp, rv, tmp
15 ldr \rp, =APB_PHYS_BASE @ physical 23 ldr \rp, =APB_PHYS_BASE @ physical
16 ldr \rv, =APB_VIRT_BASE @ virtual 24 ldr \rv, =APB_VIRT_BASE @ virtual
17 orr \rp, \rp, #0x00017000 25 orr \rp, \rp, #MMP_UART_OFFSET
18 orr \rv, \rv, #0x00017000 26 orr \rv, \rv, #MMP_UART_OFFSET
19 .endm 27 .endm
20 28
21#define UART_SHIFT 2 29#define UART_SHIFT 2
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
index cba22fed226..c4ca4d17194 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -13,7 +13,7 @@ extern void mmp2_clear_pmic_int(void);
13#include <linux/i2c.h> 13#include <linux/i2c.h>
14#include <linux/i2c/pxa-i2c.h> 14#include <linux/i2c/pxa-i2c.h>
15#include <mach/devices.h> 15#include <mach/devices.h>
16#include <mach/sram.h> 16#include <linux/platform_data/dma-mmp_tdma.h>
17 17
18extern struct pxa_device_desc mmp2_device_uart1; 18extern struct pxa_device_desc mmp2_device_uart1;
19extern struct pxa_device_desc mmp2_device_uart2; 19extern struct pxa_device_desc mmp2_device_uart2;
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 09dcd6e2b6a..37632d964d5 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -11,9 +11,9 @@ extern void pxa168_clear_keypad_wakeup(void);
11#include <linux/i2c.h> 11#include <linux/i2c.h>
12#include <linux/i2c/pxa-i2c.h> 12#include <linux/i2c/pxa-i2c.h>
13#include <mach/devices.h> 13#include <mach/devices.h>
14#include <plat/pxa3xx_nand.h> 14#include <linux/platform_data/mtd-nand-pxa3xx.h>
15#include <video/pxa168fb.h> 15#include <video/pxa168fb.h>
16#include <plat/pxa27x_keypad.h> 16#include <linux/platform_data/keypad-pxa27x.h>
17#include <mach/cputype.h> 17#include <mach/cputype.h>
18#include <linux/pxa168_eth.h> 18#include <linux/pxa168_eth.h>
19#include <linux/platform_data/mv_usb.h> 19#include <linux/platform_data/mv_usb.h>
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index 793634c837e..3b58a3b2d7d 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -9,7 +9,7 @@ extern void __init pxa910_init_irq(void);
9#include <linux/i2c.h> 9#include <linux/i2c.h>
10#include <linux/i2c/pxa-i2c.h> 10#include <linux/i2c/pxa-i2c.h>
11#include <mach/devices.h> 11#include <mach/devices.h>
12#include <plat/pxa3xx_nand.h> 12#include <linux/platform_data/mtd-nand-pxa3xx.h>
13 13
14extern struct pxa_device_desc pxa910_device_uart1; 14extern struct pxa_device_desc pxa910_device_uart1;
15extern struct pxa_device_desc pxa910_device_uart2; 15extern struct pxa_device_desc pxa910_device_uart2;
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 68b0c93ec6a..ddc812f4034 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -13,101 +13,6 @@
13 13
14#include <mach/addr-map.h> 14#include <mach/addr-map.h>
15 15
16/*
17 * APB clock register offsets for PXA168
18 */
19#define APBC_PXA168_UART1 APBC_REG(0x000)
20#define APBC_PXA168_UART2 APBC_REG(0x004)
21#define APBC_PXA168_GPIO APBC_REG(0x008)
22#define APBC_PXA168_PWM1 APBC_REG(0x00c)
23#define APBC_PXA168_PWM2 APBC_REG(0x010)
24#define APBC_PXA168_PWM3 APBC_REG(0x014)
25#define APBC_PXA168_PWM4 APBC_REG(0x018)
26#define APBC_PXA168_RTC APBC_REG(0x028)
27#define APBC_PXA168_TWSI0 APBC_REG(0x02c)
28#define APBC_PXA168_KPC APBC_REG(0x030)
29#define APBC_PXA168_TIMERS APBC_REG(0x034)
30#define APBC_PXA168_AIB APBC_REG(0x03c)
31#define APBC_PXA168_SW_JTAG APBC_REG(0x040)
32#define APBC_PXA168_ONEWIRE APBC_REG(0x048)
33#define APBC_PXA168_ASFAR APBC_REG(0x050)
34#define APBC_PXA168_ASSAR APBC_REG(0x054)
35#define APBC_PXA168_TWSI1 APBC_REG(0x06c)
36#define APBC_PXA168_UART3 APBC_REG(0x070)
37#define APBC_PXA168_AC97 APBC_REG(0x084)
38#define APBC_PXA168_SSP1 APBC_REG(0x81c)
39#define APBC_PXA168_SSP2 APBC_REG(0x820)
40#define APBC_PXA168_SSP3 APBC_REG(0x84c)
41#define APBC_PXA168_SSP4 APBC_REG(0x858)
42#define APBC_PXA168_SSP5 APBC_REG(0x85c)
43
44/*
45 * APB Clock register offsets for PXA910
46 */
47#define APBC_PXA910_UART0 APBC_REG(0x000)
48#define APBC_PXA910_UART1 APBC_REG(0x004)
49#define APBC_PXA910_GPIO APBC_REG(0x008)
50#define APBC_PXA910_PWM1 APBC_REG(0x00c)
51#define APBC_PXA910_PWM2 APBC_REG(0x010)
52#define APBC_PXA910_PWM3 APBC_REG(0x014)
53#define APBC_PXA910_PWM4 APBC_REG(0x018)
54#define APBC_PXA910_SSP1 APBC_REG(0x01c)
55#define APBC_PXA910_SSP2 APBC_REG(0x020)
56#define APBC_PXA910_IPC APBC_REG(0x024)
57#define APBC_PXA910_RTC APBC_REG(0x028)
58#define APBC_PXA910_TWSI0 APBC_REG(0x02c)
59#define APBC_PXA910_KPC APBC_REG(0x030)
60#define APBC_PXA910_TIMERS APBC_REG(0x034)
61#define APBC_PXA910_TBROT APBC_REG(0x038)
62#define APBC_PXA910_AIB APBC_REG(0x03c)
63#define APBC_PXA910_SW_JTAG APBC_REG(0x040)
64#define APBC_PXA910_TIMERS1 APBC_REG(0x044)
65#define APBC_PXA910_ONEWIRE APBC_REG(0x048)
66#define APBC_PXA910_SSP3 APBC_REG(0x04c)
67#define APBC_PXA910_ASFAR APBC_REG(0x050)
68#define APBC_PXA910_ASSAR APBC_REG(0x054)
69
70/*
71 * APB Clock register offsets for MMP2
72 */
73#define APBC_MMP2_RTC APBC_REG(0x000)
74#define APBC_MMP2_TWSI1 APBC_REG(0x004)
75#define APBC_MMP2_TWSI2 APBC_REG(0x008)
76#define APBC_MMP2_TWSI3 APBC_REG(0x00c)
77#define APBC_MMP2_TWSI4 APBC_REG(0x010)
78#define APBC_MMP2_ONEWIRE APBC_REG(0x014)
79#define APBC_MMP2_KPC APBC_REG(0x018)
80#define APBC_MMP2_TB_ROTARY APBC_REG(0x01c)
81#define APBC_MMP2_SW_JTAG APBC_REG(0x020)
82#define APBC_MMP2_TIMERS APBC_REG(0x024)
83#define APBC_MMP2_UART1 APBC_REG(0x02c)
84#define APBC_MMP2_UART2 APBC_REG(0x030)
85#define APBC_MMP2_UART3 APBC_REG(0x034)
86#define APBC_MMP2_GPIO APBC_REG(0x038)
87#define APBC_MMP2_PWM0 APBC_REG(0x03c)
88#define APBC_MMP2_PWM1 APBC_REG(0x040)
89#define APBC_MMP2_PWM2 APBC_REG(0x044)
90#define APBC_MMP2_PWM3 APBC_REG(0x048)
91#define APBC_MMP2_SSP0 APBC_REG(0x04c)
92#define APBC_MMP2_SSP1 APBC_REG(0x050)
93#define APBC_MMP2_SSP2 APBC_REG(0x054)
94#define APBC_MMP2_SSP3 APBC_REG(0x058)
95#define APBC_MMP2_SSP4 APBC_REG(0x05c)
96#define APBC_MMP2_SSP5 APBC_REG(0x060)
97#define APBC_MMP2_AIB APBC_REG(0x064)
98#define APBC_MMP2_ASFAR APBC_REG(0x068)
99#define APBC_MMP2_ASSAR APBC_REG(0x06c)
100#define APBC_MMP2_USIM APBC_REG(0x070)
101#define APBC_MMP2_MPMU APBC_REG(0x074)
102#define APBC_MMP2_IPC APBC_REG(0x078)
103#define APBC_MMP2_TWSI5 APBC_REG(0x07c)
104#define APBC_MMP2_TWSI6 APBC_REG(0x080)
105#define APBC_MMP2_TWSI_INTSTS APBC_REG(0x084)
106#define APBC_MMP2_UART4 APBC_REG(0x088)
107#define APBC_MMP2_RIPC APBC_REG(0x08c)
108#define APBC_MMP2_THSENS1 APBC_REG(0x090) /* Thermal Sensor */
109#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4)
110
111/* Common APB clock register bit definitions */ 16/* Common APB clock register bit definitions */
112#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ 17#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
113#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ 18#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 7af8deb63e8..93c8d0e29bb 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -13,21 +13,6 @@
13 13
14#include <mach/addr-map.h> 14#include <mach/addr-map.h>
15 15
16/* Clock Reset Control */
17#define APMU_IRE APMU_REG(0x048)
18#define APMU_LCD APMU_REG(0x04c)
19#define APMU_CCIC APMU_REG(0x050)
20#define APMU_SDH0 APMU_REG(0x054)
21#define APMU_SDH1 APMU_REG(0x058)
22#define APMU_USB APMU_REG(0x05c)
23#define APMU_NAND APMU_REG(0x060)
24#define APMU_DMA APMU_REG(0x064)
25#define APMU_GEU APMU_REG(0x068)
26#define APMU_BUS APMU_REG(0x06c)
27#define APMU_SDH2 APMU_REG(0x0e8)
28#define APMU_SDH3 APMU_REG(0x0ec)
29#define APMU_ETH APMU_REG(0x0fc)
30
31#define APMU_FNCLK_EN (1 << 4) 16#define APMU_FNCLK_EN (1 << 4)
32#define APMU_AXICLK_EN (1 << 3) 17#define APMU_AXICLK_EN (1 << 3)
33#define APMU_FNRST_DIS (1 << 1) 18#define APMU_FNRST_DIS (1 << 1)
diff --git a/arch/arm/mach-mmp/include/mach/sram.h b/arch/arm/mach-mmp/include/mach/sram.h
deleted file mode 100644
index 239e0fc1bb1..00000000000
--- a/arch/arm/mach-mmp/include/mach/sram.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/sram.h
3 *
4 * SRAM Memory Management
5 *
6 * Copyright (c) 2011 Marvell Semiconductors Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#ifndef __ASM_ARCH_SRAM_H
15#define __ASM_ARCH_SRAM_H
16
17#include <linux/genalloc.h>
18
19/* ARBITRARY: SRAM allocations are multiples of this 2^N size */
20#define SRAM_GRANULARITY 512
21
22enum sram_type {
23 MMP_SRAM_UNDEFINED = 0,
24 MMP_ASRAM,
25 MMP_ISRAM,
26};
27
28struct sram_platdata {
29 char *pool_name;
30 int granularity;
31};
32
33extern struct gen_pool *sram_get_gpool(char *pool_name);
34
35#endif /* __ASM_ARCH_SRAM_H */
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
index e60c7d98922..3c71246cd99 100644
--- a/arch/arm/mach-mmp/irq.c
+++ b/arch/arm/mach-mmp/irq.c
@@ -153,10 +153,8 @@ static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
153 status = readl_relaxed(data->reg_status) & ~mask; 153 status = readl_relaxed(data->reg_status) & ~mask;
154 if (status == 0) 154 if (status == 0)
155 break; 155 break;
156 n = find_first_bit(&status, BITS_PER_LONG); 156 for_each_set_bit(n, &status, BITS_PER_LONG) {
157 while (n < BITS_PER_LONG) {
158 generic_handle_irq(icu_data[i].virq_base + n); 157 generic_handle_irq(icu_data[i].virq_base + n);
159 n = find_next_bit(&status, BITS_PER_LONG, n + 1);
160 } 158 }
161 } 159 }
162} 160}
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index c709a24a9d2..3a3768c7a19 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -20,7 +20,6 @@
20#include <asm/mach/time.h> 20#include <asm/mach/time.h>
21#include <mach/addr-map.h> 21#include <mach/addr-map.h>
22#include <mach/regs-apbc.h> 22#include <mach/regs-apbc.h>
23#include <mach/regs-apmu.h>
24#include <mach/cputype.h> 23#include <mach/cputype.h>
25#include <mach/irqs.h> 24#include <mach/irqs.h>
26#include <mach/dma.h> 25#include <mach/dma.h>
@@ -29,7 +28,6 @@
29#include <mach/mmp2.h> 28#include <mach/mmp2.h>
30 29
31#include "common.h" 30#include "common.h"
32#include "clock.h"
33 31
34#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) 32#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
35 33
@@ -98,95 +96,36 @@ void __init mmp2_init_irq(void)
98 mmp2_init_icu(); 96 mmp2_init_icu();
99} 97}
100 98
101static void sdhc_clk_enable(struct clk *clk)
102{
103 uint32_t clk_rst;
104
105 clk_rst = __raw_readl(clk->clk_rst);
106 clk_rst |= clk->enable_val;
107 __raw_writel(clk_rst, clk->clk_rst);
108}
109
110static void sdhc_clk_disable(struct clk *clk)
111{
112 uint32_t clk_rst;
113
114 clk_rst = __raw_readl(clk->clk_rst);
115 clk_rst &= ~clk->enable_val;
116 __raw_writel(clk_rst, clk->clk_rst);
117}
118
119struct clkops sdhc_clk_ops = {
120 .enable = sdhc_clk_enable,
121 .disable = sdhc_clk_disable,
122};
123
124/* APB peripheral clocks */
125static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
126static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
127static APBC_CLK(uart3, MMP2_UART3, 1, 26000000);
128static APBC_CLK(uart4, MMP2_UART4, 1, 26000000);
129static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000);
130static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000);
131static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
132static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
133static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
134static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
135static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000);
136
137static APMU_CLK(nand, NAND, 0xbf, 100000000);
138static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
139static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
140static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
141static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
142
143static struct clk_lookup mmp2_clkregs[] = {
144 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
145 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
146 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
147 INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
148 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
149 INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
150 INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
151 INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
152 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
153 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
154 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
155 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
156 INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
157 INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
158 INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
159 INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
160};
161
162static int __init mmp2_init(void) 99static int __init mmp2_init(void)
163{ 100{
164 if (cpu_is_mmp2()) { 101 if (cpu_is_mmp2()) {
165#ifdef CONFIG_CACHE_TAUROS2 102#ifdef CONFIG_CACHE_TAUROS2
166 tauros2_init(); 103 tauros2_init(0);
167#endif 104#endif
168 mfp_init_base(MFPR_VIRT_BASE); 105 mfp_init_base(MFPR_VIRT_BASE);
169 mfp_init_addr(mmp2_addr_map); 106 mfp_init_addr(mmp2_addr_map);
170 pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16); 107 pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16);
171 clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); 108 mmp2_clk_init();
172 } 109 }
173 110
174 return 0; 111 return 0;
175} 112}
176postcore_initcall(mmp2_init); 113postcore_initcall(mmp2_init);
177 114
115#define APBC_TIMERS APBC_REG(0x024)
116
178static void __init mmp2_timer_init(void) 117static void __init mmp2_timer_init(void)
179{ 118{
180 unsigned long clk_rst; 119 unsigned long clk_rst;
181 120
182 __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); 121 __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
183 122
184 /* 123 /*
185 * enable bus/functional clock, enable 6.5MHz (divider 4), 124 * enable bus/functional clock, enable 6.5MHz (divider 4),
186 * release reset 125 * release reset
187 */ 126 */
188 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); 127 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
189 __raw_writel(clk_rst, APBC_MMP2_TIMERS); 128 __raw_writel(clk_rst, APBC_TIMERS);
190 129
191 timer_init(IRQ_MMP2_TIMER1); 130 timer_init(IRQ_MMP2_TIMER1);
192} 131}
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 62d787c3447..b7f074f1549 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -18,8 +18,8 @@
18 18
19#include <asm/mach/time.h> 19#include <asm/mach/time.h>
20#include <asm/system_misc.h> 20#include <asm/system_misc.h>
21#include <mach/addr-map.h>
22#include <mach/cputype.h> 21#include <mach/cputype.h>
22#include <mach/addr-map.h>
23#include <mach/regs-apbc.h> 23#include <mach/regs-apbc.h>
24#include <mach/regs-apmu.h> 24#include <mach/regs-apmu.h>
25#include <mach/irqs.h> 25#include <mach/irqs.h>
@@ -50,62 +50,13 @@ void __init pxa168_init_irq(void)
50 icu_init_irq(); 50 icu_init_irq();
51} 51}
52 52
53/* APB peripheral clocks */
54static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
55static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
56static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
57static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
58static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
59static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
60static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
61static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
62static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
63static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
64static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
65static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
66static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
67static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
68static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
69static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
70static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
71
72static APMU_CLK(nand, NAND, 0x19b, 156000000);
73static APMU_CLK(lcd, LCD, 0x7f, 312000000);
74static APMU_CLK(eth, ETH, 0x09, 0);
75static APMU_CLK(usb, USB, 0x12, 0);
76
77/* device and clock bindings */
78static struct clk_lookup pxa168_clkregs[] = {
79 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
80 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
81 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
82 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
83 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
84 INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
85 INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
86 INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
87 INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
88 INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
89 INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
90 INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
91 INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
92 INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
93 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
94 INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
95 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
96 INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
97 INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
98 INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
99 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
100};
101
102static int __init pxa168_init(void) 53static int __init pxa168_init(void)
103{ 54{
104 if (cpu_is_pxa168()) { 55 if (cpu_is_pxa168()) {
105 mfp_init_base(MFPR_VIRT_BASE); 56 mfp_init_base(MFPR_VIRT_BASE);
106 mfp_init_addr(pxa168_mfp_addr_map); 57 mfp_init_addr(pxa168_mfp_addr_map);
107 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); 58 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
108 clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); 59 pxa168_clk_init();
109 } 60 }
110 61
111 return 0; 62 return 0;
@@ -114,6 +65,7 @@ postcore_initcall(pxa168_init);
114 65
115/* system timer - clock enabled, 3.25MHz */ 66/* system timer - clock enabled, 3.25MHz */
116#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) 67#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
68#define APBC_TIMERS APBC_REG(0x34)
117 69
118static void __init pxa168_timer_init(void) 70static void __init pxa168_timer_init(void)
119{ 71{
@@ -121,10 +73,10 @@ static void __init pxa168_timer_init(void)
121 * ourselves instead of using clk_* API. Clock rate is defined 73 * ourselves instead of using clk_* API. Clock rate is defined
122 * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running 74 * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
123 */ 75 */
124 __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); 76 __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
125 77
126 /* 3.25MHz, bus/functional clock enabled, release reset */ 78 /* 3.25MHz, bus/functional clock enabled, release reset */
127 __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); 79 __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
128 80
129 timer_init(IRQ_PXA168_TIMER1); 81 timer_init(IRQ_PXA168_TIMER1);
130} 82}
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 6da52e9f2bd..8b1e16fbb7a 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -14,10 +14,10 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16 16
17#include <asm/hardware/cache-tauros2.h>
17#include <asm/mach/time.h> 18#include <asm/mach/time.h>
18#include <mach/addr-map.h> 19#include <mach/addr-map.h>
19#include <mach/regs-apbc.h> 20#include <mach/regs-apbc.h>
20#include <mach/regs-apmu.h>
21#include <mach/cputype.h> 21#include <mach/cputype.h>
22#include <mach/irqs.h> 22#include <mach/irqs.h>
23#include <mach/dma.h> 23#include <mach/dma.h>
@@ -25,7 +25,6 @@
25#include <mach/devices.h> 25#include <mach/devices.h>
26 26
27#include "common.h" 27#include "common.h"
28#include "clock.h"
29 28
30#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) 29#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
31 30
@@ -82,44 +81,16 @@ void __init pxa910_init_irq(void)
82 icu_init_irq(); 81 icu_init_irq();
83} 82}
84 83
85/* APB peripheral clocks */
86static APBC_CLK(uart1, PXA910_UART0, 1, 14745600);
87static APBC_CLK(uart2, PXA910_UART1, 1, 14745600);
88static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
89static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
90static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000);
91static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
92static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
93static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
94static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000);
95static APBC_CLK(rtc, PXA910_RTC, 8, 32768);
96
97static APMU_CLK(nand, NAND, 0x19b, 156000000);
98static APMU_CLK(u2o, USB, 0x1b, 480000000);
99
100/* device and clock bindings */
101static struct clk_lookup pxa910_clkregs[] = {
102 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
103 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
104 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
105 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
106 INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
107 INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
108 INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
109 INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
110 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
111 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
112 INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
113 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
114};
115
116static int __init pxa910_init(void) 84static int __init pxa910_init(void)
117{ 85{
118 if (cpu_is_pxa910()) { 86 if (cpu_is_pxa910()) {
87#ifdef CONFIG_CACHE_TAUROS2
88 tauros2_init(0);
89#endif
119 mfp_init_base(MFPR_VIRT_BASE); 90 mfp_init_base(MFPR_VIRT_BASE);
120 mfp_init_addr(pxa910_mfp_addr_map); 91 mfp_init_addr(pxa910_mfp_addr_map);
121 pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); 92 pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
122 clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs)); 93 pxa910_clk_init();
123 } 94 }
124 95
125 return 0; 96 return 0;
@@ -128,12 +99,13 @@ postcore_initcall(pxa910_init);
128 99
129/* system timer - clock enabled, 3.25MHz */ 100/* system timer - clock enabled, 3.25MHz */
130#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) 101#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
102#define APBC_TIMERS APBC_REG(0x34)
131 103
132static void __init pxa910_timer_init(void) 104static void __init pxa910_timer_init(void)
133{ 105{
134 /* reset and configure */ 106 /* reset and configure */
135 __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS); 107 __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
136 __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS); 108 __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
137 109
138 timer_init(IRQ_PXA910_AP1_TIMER1); 110 timer_init(IRQ_PXA910_AP1_TIMER1);
139} 111}
diff --git a/arch/arm/mach-mmp/sram.c b/arch/arm/mach-mmp/sram.c
index 7e8a5a2e1ec..a6c08ede449 100644
--- a/arch/arm/mach-mmp/sram.c
+++ b/arch/arm/mach-mmp/sram.c
@@ -22,7 +22,7 @@
22#include <linux/slab.h> 22#include <linux/slab.h>
23#include <linux/genalloc.h> 23#include <linux/genalloc.h>
24 24
25#include <mach/sram.h> 25#include <linux/platform_data/dma-mmp_tdma.h>
26 26
27struct sram_bank_info { 27struct sram_bank_info {
28 char *pool_name; 28 char *pool_name;
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
index 42bef6674ec..dd30ea74785 100644
--- a/arch/arm/mach-mmp/teton_bga.c
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -17,7 +17,7 @@
17#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/gpio.h> 18#include <linux/gpio.h>
19#include <linux/input.h> 19#include <linux/input.h>
20#include <plat/pxa27x_keypad.h> 20#include <linux/platform_data/keypad-pxa27x.h>
21#include <linux/i2c.h> 21#include <linux/i2c.h>
22 22
23#include <asm/mach-types.h> 23#include <asm/mach-types.h>
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 7a7de2b12a6..ce55fd8821c 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -177,12 +177,22 @@ static struct mv_usb_platform_data ttc_usb_pdata = {
177#endif 177#endif
178#endif 178#endif
179 179
180#ifdef CONFIG_MTD_NAND_PXA3xx
181static struct pxa3xx_nand_platform_data dkb_nand_info = {
182 .enable_arbiter = 1,
183 .num_cs = 1,
184};
185#endif
186
180static void __init ttc_dkb_init(void) 187static void __init ttc_dkb_init(void)
181{ 188{
182 mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config)); 189 mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
183 190
184 /* on-chip devices */ 191 /* on-chip devices */
185 pxa910_add_uart(1); 192 pxa910_add_uart(1);
193#ifdef CONFIG_MTD_NAND_PXA3xx
194 pxa910_add_nand(&dkb_nand_info);
195#endif
186 196
187 /* off-chip devices */ 197 /* off-chip devices */
188 pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info)); 198 pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 11:24:00 -0400