diff options
Diffstat (limited to 'arch/arm/mach-mmp/include/mach/regs-apbc.h')
-rw-r--r-- | arch/arm/mach-mmp/include/mach/regs-apbc.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index 712af03fd1a..1a96585336b 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h | |||
@@ -26,8 +26,6 @@ | |||
26 | #define APBC_PXA168_PWM2 APBC_REG(0x010) | 26 | #define APBC_PXA168_PWM2 APBC_REG(0x010) |
27 | #define APBC_PXA168_PWM3 APBC_REG(0x014) | 27 | #define APBC_PXA168_PWM3 APBC_REG(0x014) |
28 | #define APBC_PXA168_PWM4 APBC_REG(0x018) | 28 | #define APBC_PXA168_PWM4 APBC_REG(0x018) |
29 | #define APBC_PXA168_SSP1 APBC_REG(0x01c) | ||
30 | #define APBC_PXA168_SSP2 APBC_REG(0x020) | ||
31 | #define APBC_PXA168_RTC APBC_REG(0x028) | 29 | #define APBC_PXA168_RTC APBC_REG(0x028) |
32 | #define APBC_PXA168_TWSI0 APBC_REG(0x02c) | 30 | #define APBC_PXA168_TWSI0 APBC_REG(0x02c) |
33 | #define APBC_PXA168_KPC APBC_REG(0x030) | 31 | #define APBC_PXA168_KPC APBC_REG(0x030) |
@@ -35,14 +33,16 @@ | |||
35 | #define APBC_PXA168_AIB APBC_REG(0x03c) | 33 | #define APBC_PXA168_AIB APBC_REG(0x03c) |
36 | #define APBC_PXA168_SW_JTAG APBC_REG(0x040) | 34 | #define APBC_PXA168_SW_JTAG APBC_REG(0x040) |
37 | #define APBC_PXA168_ONEWIRE APBC_REG(0x048) | 35 | #define APBC_PXA168_ONEWIRE APBC_REG(0x048) |
38 | #define APBC_PXA168_SSP3 APBC_REG(0x04c) | ||
39 | #define APBC_PXA168_ASFAR APBC_REG(0x050) | 36 | #define APBC_PXA168_ASFAR APBC_REG(0x050) |
40 | #define APBC_PXA168_ASSAR APBC_REG(0x054) | 37 | #define APBC_PXA168_ASSAR APBC_REG(0x054) |
41 | #define APBC_PXA168_SSP4 APBC_REG(0x058) | ||
42 | #define APBC_PXA168_SSP5 APBC_REG(0x05c) | ||
43 | #define APBC_PXA168_TWSI1 APBC_REG(0x06c) | 38 | #define APBC_PXA168_TWSI1 APBC_REG(0x06c) |
44 | #define APBC_PXA168_UART3 APBC_REG(0x070) | 39 | #define APBC_PXA168_UART3 APBC_REG(0x070) |
45 | #define APBC_PXA168_AC97 APBC_REG(0x084) | 40 | #define APBC_PXA168_AC97 APBC_REG(0x084) |
41 | #define APBC_PXA168_SSP1 APBC_REG(0x81c) | ||
42 | #define APBC_PXA168_SSP2 APBC_REG(0x820) | ||
43 | #define APBC_PXA168_SSP3 APBC_REG(0x84c) | ||
44 | #define APBC_PXA168_SSP4 APBC_REG(0x858) | ||
45 | #define APBC_PXA168_SSP5 APBC_REG(0x85c) | ||
46 | 46 | ||
47 | /* | 47 | /* |
48 | * APB Clock register offsets for PXA910 | 48 | * APB Clock register offsets for PXA910 |