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-rw-r--r--arch/arm/mach-exynos4/platsmp.c30
1 files changed, 29 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index a79863cb7f7..a7f312c1289 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -28,9 +28,12 @@
28 28
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
31#include <mach/regs-pmu.h>
31 32
32extern void exynos4_secondary_startup(void); 33extern void exynos4_secondary_startup(void);
33 34
35#define CPU1_BOOT_REG S5P_VA_SYSRAM
36
34/* 37/*
35 * control for which core is the next to come out of the secondary 38 * control for which core is the next to come out of the secondary
36 * boot "holding pen" 39 * boot "holding pen"
@@ -125,16 +128,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
125 */ 128 */
126 write_pen_release(cpu); 129 write_pen_release(cpu);
127 130
131 if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
132 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
133 S5P_ARM_CORE1_CONFIGURATION);
134
135 timeout = 10;
136
137 /* wait max 10 ms until cpu1 is on */
138 while ((__raw_readl(S5P_ARM_CORE1_STATUS)
139 & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
140 if (timeout-- == 0)
141 break;
142
143 mdelay(1);
144 }
145
146 if (timeout == 0) {
147 printk(KERN_ERR "cpu1 power enable failed");
148 spin_unlock(&boot_lock);
149 return -ETIMEDOUT;
150 }
151 }
128 /* 152 /*
129 * Send the secondary CPU a soft interrupt, thereby causing 153 * Send the secondary CPU a soft interrupt, thereby causing
130 * the boot monitor to read the system wide flags register, 154 * the boot monitor to read the system wide flags register,
131 * and branch to the address found there. 155 * and branch to the address found there.
132 */ 156 */
133 gic_raise_softirq(cpumask_of(cpu), 1);
134 157
135 timeout = jiffies + (1 * HZ); 158 timeout = jiffies + (1 * HZ);
136 while (time_before(jiffies, timeout)) { 159 while (time_before(jiffies, timeout)) {
137 smp_rmb(); 160 smp_rmb();
161
162 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
163 CPU1_BOOT_REG);
164 gic_raise_softirq(cpumask_of(cpu), 1);
165
138 if (pen_release == -1) 166 if (pen_release == -1)
139 break; 167 break;
140 168