diff options
Diffstat (limited to 'arch/arm/mach-exynos4/cpu.c')
-rw-r--r-- | arch/arm/mach-exynos4/cpu.c | 50 |
1 files changed, 39 insertions, 11 deletions
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index bfd621460ab..746d6fc6d39 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c | |||
@@ -16,16 +16,21 @@ | |||
16 | 16 | ||
17 | #include <asm/proc-fns.h> | 17 | #include <asm/proc-fns.h> |
18 | #include <asm/hardware/cache-l2x0.h> | 18 | #include <asm/hardware/cache-l2x0.h> |
19 | #include <asm/hardware/gic.h> | ||
19 | 20 | ||
20 | #include <plat/cpu.h> | 21 | #include <plat/cpu.h> |
21 | #include <plat/clock.h> | 22 | #include <plat/clock.h> |
23 | #include <plat/devs.h> | ||
22 | #include <plat/exynos4.h> | 24 | #include <plat/exynos4.h> |
25 | #include <plat/adc-core.h> | ||
23 | #include <plat/sdhci.h> | 26 | #include <plat/sdhci.h> |
24 | #include <plat/devs.h> | 27 | #include <plat/fb-core.h> |
25 | #include <plat/fimc-core.h> | 28 | #include <plat/fimc-core.h> |
26 | #include <plat/iic-core.h> | 29 | #include <plat/iic-core.h> |
30 | #include <plat/reset.h> | ||
27 | 31 | ||
28 | #include <mach/regs-irq.h> | 32 | #include <mach/regs-irq.h> |
33 | #include <mach/regs-pmu.h> | ||
29 | 34 | ||
30 | extern int combiner_init(unsigned int combiner_nr, void __iomem *base, | 35 | extern int combiner_init(unsigned int combiner_nr, void __iomem *base, |
31 | unsigned int irq_start); | 36 | unsigned int irq_start); |
@@ -103,7 +108,17 @@ static struct map_desc exynos4_iodesc[] __initdata = { | |||
103 | .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), | 108 | .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), |
104 | .length = SZ_4K, | 109 | .length = SZ_4K, |
105 | .type = MT_DEVICE, | 110 | .type = MT_DEVICE, |
106 | } | 111 | }, { |
112 | .virtual = (unsigned long)S5P_VA_GIC_CPU, | ||
113 | .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU), | ||
114 | .length = SZ_64K, | ||
115 | .type = MT_DEVICE, | ||
116 | }, { | ||
117 | .virtual = (unsigned long)S5P_VA_GIC_DIST, | ||
118 | .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST), | ||
119 | .length = SZ_64K, | ||
120 | .type = MT_DEVICE, | ||
121 | }, | ||
107 | }; | 122 | }; |
108 | 123 | ||
109 | static void exynos4_idle(void) | 124 | static void exynos4_idle(void) |
@@ -114,6 +129,11 @@ static void exynos4_idle(void) | |||
114 | local_irq_enable(); | 129 | local_irq_enable(); |
115 | } | 130 | } |
116 | 131 | ||
132 | static void exynos4_sw_reset(void) | ||
133 | { | ||
134 | __raw_writel(0x1, S5P_SWRESET); | ||
135 | } | ||
136 | |||
117 | /* | 137 | /* |
118 | * exynos4_map_io | 138 | * exynos4_map_io |
119 | * | 139 | * |
@@ -129,6 +149,8 @@ void __init exynos4_map_io(void) | |||
129 | exynos4_default_sdhci2(); | 149 | exynos4_default_sdhci2(); |
130 | exynos4_default_sdhci3(); | 150 | exynos4_default_sdhci3(); |
131 | 151 | ||
152 | s3c_adc_setname("samsung-adc-v3"); | ||
153 | |||
132 | s3c_fimc_setname(0, "exynos4-fimc"); | 154 | s3c_fimc_setname(0, "exynos4-fimc"); |
133 | s3c_fimc_setname(1, "exynos4-fimc"); | 155 | s3c_fimc_setname(1, "exynos4-fimc"); |
134 | s3c_fimc_setname(2, "exynos4-fimc"); | 156 | s3c_fimc_setname(2, "exynos4-fimc"); |
@@ -138,6 +160,8 @@ void __init exynos4_map_io(void) | |||
138 | s3c_i2c0_setname("s3c2440-i2c"); | 160 | s3c_i2c0_setname("s3c2440-i2c"); |
139 | s3c_i2c1_setname("s3c2440-i2c"); | 161 | s3c_i2c1_setname("s3c2440-i2c"); |
140 | s3c_i2c2_setname("s3c2440-i2c"); | 162 | s3c_i2c2_setname("s3c2440-i2c"); |
163 | |||
164 | s5p_fb_setname(0, "exynos4-fb"); | ||
141 | } | 165 | } |
142 | 166 | ||
143 | void __init exynos4_init_clocks(int xtal) | 167 | void __init exynos4_init_clocks(int xtal) |
@@ -150,22 +174,23 @@ void __init exynos4_init_clocks(int xtal) | |||
150 | exynos4_setup_clocks(); | 174 | exynos4_setup_clocks(); |
151 | } | 175 | } |
152 | 176 | ||
177 | static void exynos4_gic_irq_eoi(struct irq_data *d) | ||
178 | { | ||
179 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); | ||
180 | |||
181 | gic_data->cpu_base = S5P_VA_GIC_CPU + | ||
182 | (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); | ||
183 | } | ||
184 | |||
153 | void __init exynos4_init_irq(void) | 185 | void __init exynos4_init_irq(void) |
154 | { | 186 | { |
155 | int irq; | 187 | int irq; |
156 | 188 | ||
157 | gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); | 189 | gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); |
190 | gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi; | ||
158 | 191 | ||
159 | for (irq = 0; irq < MAX_COMBINER_NR; irq++) { | 192 | for (irq = 0; irq < MAX_COMBINER_NR; irq++) { |
160 | 193 | ||
161 | /* | ||
162 | * From SPI(0) to SPI(39) and SPI(51), SPI(53) are | ||
163 | * connected to the interrupt combiner. These irqs | ||
164 | * should be initialized to support cascade interrupt. | ||
165 | */ | ||
166 | if ((irq >= 40) && !(irq == 51) && !(irq == 53)) | ||
167 | continue; | ||
168 | |||
169 | combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), | 194 | combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), |
170 | COMBINER_IRQ(irq, 0)); | 195 | COMBINER_IRQ(irq, 0)); |
171 | combiner_cascade_irq(irq, IRQ_SPI(irq)); | 196 | combiner_cascade_irq(irq, IRQ_SPI(irq)); |
@@ -222,5 +247,8 @@ int __init exynos4_init(void) | |||
222 | /* set idle function */ | 247 | /* set idle function */ |
223 | pm_idle = exynos4_idle; | 248 | pm_idle = exynos4_idle; |
224 | 249 | ||
250 | /* set sw_reset function */ | ||
251 | s5p_reset_hook = exynos4_sw_reset; | ||
252 | |||
225 | return sysdev_register(&exynos4_sysdev); | 253 | return sysdev_register(&exynos4_sysdev); |
226 | } | 254 | } |