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-rw-r--r--arch/arm/mach-ep93xx/Makefile3
-rw-r--r--arch/arm/mach-ep93xx/adssphere.c1
-rw-r--r--arch/arm/mach-ep93xx/clock.c1
-rw-r--r--arch/arm/mach-ep93xx/core.c54
-rw-r--r--arch/arm/mach-ep93xx/crunch-bits.S305
-rw-r--r--arch/arm/mach-ep93xx/crunch.c90
-rw-r--r--arch/arm/mach-ep93xx/dma.c2
-rw-r--r--arch/arm/mach-ep93xx/edb93xx.c1
-rw-r--r--arch/arm/mach-ep93xx/gesbc9312.c1
-rw-r--r--arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h191
-rw-r--r--arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h10
-rw-r--r--arch/arm/mach-ep93xx/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-ep93xx/include/mach/platform.h16
-rw-r--r--arch/arm/mach-ep93xx/micro9.c1
-rw-r--r--arch/arm/mach-ep93xx/simone.c2
-rw-r--r--arch/arm/mach-ep93xx/snappercl15.c2
-rw-r--r--arch/arm/mach-ep93xx/soc.h213
-rw-r--r--arch/arm/mach-ep93xx/ts72xx.c1
-rw-r--r--arch/arm/mach-ep93xx/vision_ep9307.c4
19 files changed, 676 insertions, 223 deletions
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 574209d9e24..0dc51f9462d 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -8,6 +8,9 @@ obj- :=
8 8
9obj-$(CONFIG_EP93XX_DMA) += dma.o 9obj-$(CONFIG_EP93XX_DMA) += dma.o
10 10
11obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
12AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
13
11obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o 14obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o
12obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o 15obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o
13obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o 16obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 681e939407d..2d45947a303 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -20,6 +20,7 @@
20#include <asm/mach-types.h> 20#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
22 22
23#include "soc.h"
23 24
24static struct ep93xx_eth_data __initdata adssphere_eth_data = { 25static struct ep93xx_eth_data __initdata adssphere_eth_data = {
25 .phy_id = 1, 26 .phy_id = 1,
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index ca4de710509..c95dbce2468 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -25,6 +25,7 @@
25 25
26#include <asm/div64.h> 26#include <asm/div64.h>
27 27
28#include "soc.h"
28 29
29struct clk { 30struct clk {
30 struct clk *parent; 31 struct clk *parent;
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 903edb02fe4..8d258958871 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -46,6 +46,7 @@
46 46
47#include <asm/hardware/vic.h> 47#include <asm/hardware/vic.h>
48 48
49#include "soc.h"
49 50
50/************************************************************************* 51/*************************************************************************
51 * Static I/O mappings that are needed for all EP93xx platforms 52 * Static I/O mappings that are needed for all EP93xx platforms
@@ -204,7 +205,6 @@ void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
204 205
205 spin_unlock_irqrestore(&syscon_swlock, flags); 206 spin_unlock_irqrestore(&syscon_swlock, flags);
206} 207}
207EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
208 208
209void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits) 209void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
210{ 210{
@@ -221,7 +221,6 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
221 221
222 spin_unlock_irqrestore(&syscon_swlock, flags); 222 spin_unlock_irqrestore(&syscon_swlock, flags);
223} 223}
224EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
225 224
226/** 225/**
227 * ep93xx_chip_revision() - returns the EP93xx chip revision 226 * ep93xx_chip_revision() - returns the EP93xx chip revision
@@ -648,9 +647,19 @@ static struct platform_device ep93xx_fb_device = {
648 .resource = ep93xx_fb_resource, 647 .resource = ep93xx_fb_resource,
649}; 648};
650 649
650/* The backlight use a single register in the framebuffer's register space */
651#define EP93XX_RASTER_REG_BRIGHTNESS 0x20
652
653static struct resource ep93xx_bl_resources[] = {
654 DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE +
655 EP93XX_RASTER_REG_BRIGHTNESS, 0x04),
656};
657
651static struct platform_device ep93xx_bl_device = { 658static struct platform_device ep93xx_bl_device = {
652 .name = "ep93xx-bl", 659 .name = "ep93xx-bl",
653 .id = -1, 660 .id = -1,
661 .num_resources = ARRAY_SIZE(ep93xx_bl_resources),
662 .resource = ep93xx_bl_resources,
654}; 663};
655 664
656/** 665/**
@@ -783,23 +792,12 @@ void __init ep93xx_register_i2s(void)
783#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \ 792#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
784 EP93XX_SYSCON_I2SCLKDIV_SPOL) 793 EP93XX_SYSCON_I2SCLKDIV_SPOL)
785 794
786int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config) 795int ep93xx_i2s_acquire(void)
787{ 796{
788 unsigned val; 797 unsigned val;
789 798
790 /* Sanity check */ 799 ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97,
791 if (i2s_pins & ~EP93XX_SYSCON_DEVCFG_I2S_MASK) 800 EP93XX_SYSCON_DEVCFG_I2S_MASK);
792 return -EINVAL;
793 if (i2s_config & ~EP93XX_I2SCLKDIV_MASK)
794 return -EINVAL;
795
796 /* Must have only one of I2SONSSP/I2SONAC97 set */
797 if ((i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONSSP) ==
798 (i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONAC97))
799 return -EINVAL;
800
801 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
802 ep93xx_devcfg_set_bits(i2s_pins);
803 801
804 /* 802 /*
805 * This is potentially racy with the clock api for i2s_mclk, sclk and 803 * This is potentially racy with the clock api for i2s_mclk, sclk and
@@ -809,7 +807,7 @@ int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config)
809 */ 807 */
810 val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV); 808 val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
811 val &= ~EP93XX_I2SCLKDIV_MASK; 809 val &= ~EP93XX_I2SCLKDIV_MASK;
812 val |= i2s_config; 810 val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
813 ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV); 811 ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
814 812
815 return 0; 813 return 0;
@@ -856,11 +854,32 @@ void __init ep93xx_register_ac97(void)
856 platform_device_register(&ep93xx_pcm_device); 854 platform_device_register(&ep93xx_pcm_device);
857} 855}
858 856
857/*************************************************************************
858 * EP93xx Watchdog
859 *************************************************************************/
860static struct resource ep93xx_wdt_resources[] = {
861 DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08),
862};
863
864static struct platform_device ep93xx_wdt_device = {
865 .name = "ep93xx-wdt",
866 .id = -1,
867 .num_resources = ARRAY_SIZE(ep93xx_wdt_resources),
868 .resource = ep93xx_wdt_resources,
869};
870
859void __init ep93xx_init_devices(void) 871void __init ep93xx_init_devices(void)
860{ 872{
861 /* Disallow access to MaverickCrunch initially */ 873 /* Disallow access to MaverickCrunch initially */
862 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); 874 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
863 875
876 /* Default all ports to GPIO */
877 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
878 EP93XX_SYSCON_DEVCFG_GONK |
879 EP93XX_SYSCON_DEVCFG_EONIDE |
880 EP93XX_SYSCON_DEVCFG_GONIDE |
881 EP93XX_SYSCON_DEVCFG_HONIDE);
882
864 /* Get the GPIO working early, other devices need it */ 883 /* Get the GPIO working early, other devices need it */
865 platform_device_register(&ep93xx_gpio_device); 884 platform_device_register(&ep93xx_gpio_device);
866 885
@@ -871,6 +890,7 @@ void __init ep93xx_init_devices(void)
871 platform_device_register(&ep93xx_rtc_device); 890 platform_device_register(&ep93xx_rtc_device);
872 platform_device_register(&ep93xx_ohci_device); 891 platform_device_register(&ep93xx_ohci_device);
873 platform_device_register(&ep93xx_leds); 892 platform_device_register(&ep93xx_leds);
893 platform_device_register(&ep93xx_wdt_device);
874} 894}
875 895
876void ep93xx_restart(char mode, const char *cmd) 896void ep93xx_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-ep93xx/crunch-bits.S b/arch/arm/mach-ep93xx/crunch-bits.S
new file mode 100644
index 00000000000..0ec9bb48fab
--- /dev/null
+++ b/arch/arm/mach-ep93xx/crunch-bits.S
@@ -0,0 +1,305 @@
1/*
2 * arch/arm/kernel/crunch-bits.S
3 * Cirrus MaverickCrunch context switching and handling
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 *
7 * Shamelessly stolen from the iWMMXt code by Nicolas Pitre, which is
8 * Copyright (c) 2003-2004, MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/linkage.h>
16#include <asm/ptrace.h>
17#include <asm/thread_info.h>
18#include <asm/asm-offsets.h>
19#include <mach/ep93xx-regs.h>
20
21/*
22 * We can't use hex constants here due to a bug in gas.
23 */
24#define CRUNCH_MVDX0 0
25#define CRUNCH_MVDX1 8
26#define CRUNCH_MVDX2 16
27#define CRUNCH_MVDX3 24
28#define CRUNCH_MVDX4 32
29#define CRUNCH_MVDX5 40
30#define CRUNCH_MVDX6 48
31#define CRUNCH_MVDX7 56
32#define CRUNCH_MVDX8 64
33#define CRUNCH_MVDX9 72
34#define CRUNCH_MVDX10 80
35#define CRUNCH_MVDX11 88
36#define CRUNCH_MVDX12 96
37#define CRUNCH_MVDX13 104
38#define CRUNCH_MVDX14 112
39#define CRUNCH_MVDX15 120
40#define CRUNCH_MVAX0L 128
41#define CRUNCH_MVAX0M 132
42#define CRUNCH_MVAX0H 136
43#define CRUNCH_MVAX1L 140
44#define CRUNCH_MVAX1M 144
45#define CRUNCH_MVAX1H 148
46#define CRUNCH_MVAX2L 152
47#define CRUNCH_MVAX2M 156
48#define CRUNCH_MVAX2H 160
49#define CRUNCH_MVAX3L 164
50#define CRUNCH_MVAX3M 168
51#define CRUNCH_MVAX3H 172
52#define CRUNCH_DSPSC 176
53
54#define CRUNCH_SIZE 184
55
56 .text
57
58/*
59 * Lazy switching of crunch coprocessor context
60 *
61 * r10 = struct thread_info pointer
62 * r9 = ret_from_exception
63 * lr = undefined instr exit
64 *
65 * called from prefetch exception handler with interrupts disabled
66 */
67ENTRY(crunch_task_enable)
68 ldr r8, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr
69
70 ldr r1, [r8, #0x80]
71 tst r1, #0x00800000 @ access to crunch enabled?
72 movne pc, lr @ if so no business here
73 mov r3, #0xaa @ unlock syscon swlock
74 str r3, [r8, #0xc0]
75 orr r1, r1, #0x00800000 @ enable access to crunch
76 str r1, [r8, #0x80]
77
78 ldr r3, =crunch_owner
79 add r0, r10, #TI_CRUNCH_STATE @ get task crunch save area
80 ldr r2, [sp, #60] @ current task pc value
81 ldr r1, [r3] @ get current crunch owner
82 str r0, [r3] @ this task now owns crunch
83 sub r2, r2, #4 @ adjust pc back
84 str r2, [sp, #60]
85
86 ldr r2, [r8, #0x80]
87 mov r2, r2 @ flush out enable (@@@)
88
89 teq r1, #0 @ test for last ownership
90 mov lr, r9 @ normal exit from exception
91 beq crunch_load @ no owner, skip save
92
93crunch_save:
94 cfstr64 mvdx0, [r1, #CRUNCH_MVDX0] @ save 64b registers
95 cfstr64 mvdx1, [r1, #CRUNCH_MVDX1]
96 cfstr64 mvdx2, [r1, #CRUNCH_MVDX2]
97 cfstr64 mvdx3, [r1, #CRUNCH_MVDX3]
98 cfstr64 mvdx4, [r1, #CRUNCH_MVDX4]
99 cfstr64 mvdx5, [r1, #CRUNCH_MVDX5]
100 cfstr64 mvdx6, [r1, #CRUNCH_MVDX6]
101 cfstr64 mvdx7, [r1, #CRUNCH_MVDX7]
102 cfstr64 mvdx8, [r1, #CRUNCH_MVDX8]
103 cfstr64 mvdx9, [r1, #CRUNCH_MVDX9]
104 cfstr64 mvdx10, [r1, #CRUNCH_MVDX10]
105 cfstr64 mvdx11, [r1, #CRUNCH_MVDX11]
106 cfstr64 mvdx12, [r1, #CRUNCH_MVDX12]
107 cfstr64 mvdx13, [r1, #CRUNCH_MVDX13]
108 cfstr64 mvdx14, [r1, #CRUNCH_MVDX14]
109 cfstr64 mvdx15, [r1, #CRUNCH_MVDX15]
110
111#ifdef __ARMEB__
112#error fix me for ARMEB
113#endif
114
115 cfmv32al mvfx0, mvax0 @ save 72b accumulators
116 cfstr32 mvfx0, [r1, #CRUNCH_MVAX0L]
117 cfmv32am mvfx0, mvax0
118 cfstr32 mvfx0, [r1, #CRUNCH_MVAX0M]
119 cfmv32ah mvfx0, mvax0
120 cfstr32 mvfx0, [r1, #CRUNCH_MVAX0H]
121 cfmv32al mvfx0, mvax1
122 cfstr32 mvfx0, [r1, #CRUNCH_MVAX1L]
123 cfmv32am mvfx0, mvax1
124 cfstr32 mvfx0, [r1, #CRUNCH_MVAX1M]
125 cfmv32ah mvfx0, mvax1
126 cfstr32 mvfx0, [r1, #CRUNCH_MVAX1H]
127 cfmv32al mvfx0, mvax2
128 cfstr32 mvfx0, [r1, #CRUNCH_MVAX2L]
129 cfmv32am mvfx0, mvax2
130 cfstr32 mvfx0, [r1, #CRUNCH_MVAX2M]
131 cfmv32ah mvfx0, mvax2
132 cfstr32 mvfx0, [r1, #CRUNCH_MVAX2H]
133 cfmv32al mvfx0, mvax3
134 cfstr32 mvfx0, [r1, #CRUNCH_MVAX3L]
135 cfmv32am mvfx0, mvax3
136 cfstr32 mvfx0, [r1, #CRUNCH_MVAX3M]
137 cfmv32ah mvfx0, mvax3
138 cfstr32 mvfx0, [r1, #CRUNCH_MVAX3H]
139
140 cfmv32sc mvdx0, dspsc @ save status word
141 cfstr64 mvdx0, [r1, #CRUNCH_DSPSC]
142
143 teq r0, #0 @ anything to load?
144 cfldr64eq mvdx0, [r1, #CRUNCH_MVDX0] @ mvdx0 was clobbered
145 moveq pc, lr
146
147crunch_load:
148 cfldr64 mvdx0, [r0, #CRUNCH_DSPSC] @ load status word
149 cfmvsc32 dspsc, mvdx0
150
151 cfldr32 mvfx0, [r0, #CRUNCH_MVAX0L] @ load 72b accumulators
152 cfmval32 mvax0, mvfx0
153 cfldr32 mvfx0, [r0, #CRUNCH_MVAX0M]
154 cfmvam32 mvax0, mvfx0
155 cfldr32 mvfx0, [r0, #CRUNCH_MVAX0H]
156 cfmvah32 mvax0, mvfx0
157 cfldr32 mvfx0, [r0, #CRUNCH_MVAX1L]
158 cfmval32 mvax1, mvfx0
159 cfldr32 mvfx0, [r0, #CRUNCH_MVAX1M]
160 cfmvam32 mvax1, mvfx0
161 cfldr32 mvfx0, [r0, #CRUNCH_MVAX1H]
162 cfmvah32 mvax1, mvfx0
163 cfldr32 mvfx0, [r0, #CRUNCH_MVAX2L]
164 cfmval32 mvax2, mvfx0
165 cfldr32 mvfx0, [r0, #CRUNCH_MVAX2M]
166 cfmvam32 mvax2, mvfx0
167 cfldr32 mvfx0, [r0, #CRUNCH_MVAX2H]
168 cfmvah32 mvax2, mvfx0
169 cfldr32 mvfx0, [r0, #CRUNCH_MVAX3L]
170 cfmval32 mvax3, mvfx0
171 cfldr32 mvfx0, [r0, #CRUNCH_MVAX3M]
172 cfmvam32 mvax3, mvfx0
173 cfldr32 mvfx0, [r0, #CRUNCH_MVAX3H]
174 cfmvah32 mvax3, mvfx0
175
176 cfldr64 mvdx0, [r0, #CRUNCH_MVDX0] @ load 64b registers
177 cfldr64 mvdx1, [r0, #CRUNCH_MVDX1]
178 cfldr64 mvdx2, [r0, #CRUNCH_MVDX2]
179 cfldr64 mvdx3, [r0, #CRUNCH_MVDX3]
180 cfldr64 mvdx4, [r0, #CRUNCH_MVDX4]
181 cfldr64 mvdx5, [r0, #CRUNCH_MVDX5]
182 cfldr64 mvdx6, [r0, #CRUNCH_MVDX6]
183 cfldr64 mvdx7, [r0, #CRUNCH_MVDX7]
184 cfldr64 mvdx8, [r0, #CRUNCH_MVDX8]
185 cfldr64 mvdx9, [r0, #CRUNCH_MVDX9]
186 cfldr64 mvdx10, [r0, #CRUNCH_MVDX10]
187 cfldr64 mvdx11, [r0, #CRUNCH_MVDX11]
188 cfldr64 mvdx12, [r0, #CRUNCH_MVDX12]
189 cfldr64 mvdx13, [r0, #CRUNCH_MVDX13]
190 cfldr64 mvdx14, [r0, #CRUNCH_MVDX14]
191 cfldr64 mvdx15, [r0, #CRUNCH_MVDX15]
192
193 mov pc, lr
194
195/*
196 * Back up crunch regs to save area and disable access to them
197 * (mainly for gdb or sleep mode usage)
198 *
199 * r0 = struct thread_info pointer of target task or NULL for any
200 */
201ENTRY(crunch_task_disable)
202 stmfd sp!, {r4, r5, lr}
203
204 mrs ip, cpsr
205 orr r2, ip, #PSR_I_BIT @ disable interrupts
206 msr cpsr_c, r2
207
208 ldr r4, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr
209
210 ldr r3, =crunch_owner
211 add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area
212 ldr r1, [r3] @ get current crunch owner
213 teq r1, #0 @ any current owner?
214 beq 1f @ no: quit
215 teq r0, #0 @ any owner?
216 teqne r1, r2 @ or specified one?
217 bne 1f @ no: quit
218
219 ldr r5, [r4, #0x80] @ enable access to crunch
220 mov r2, #0xaa
221 str r2, [r4, #0xc0]
222 orr r5, r5, #0x00800000
223 str r5, [r4, #0x80]
224
225 mov r0, #0 @ nothing to load
226 str r0, [r3] @ no more current owner
227 ldr r2, [r4, #0x80] @ flush out enable (@@@)
228 mov r2, r2
229 bl crunch_save
230
231 mov r2, #0xaa @ disable access to crunch
232 str r2, [r4, #0xc0]
233 bic r5, r5, #0x00800000
234 str r5, [r4, #0x80]
235 ldr r5, [r4, #0x80] @ flush out enable (@@@)
236 mov r5, r5
237
2381: msr cpsr_c, ip @ restore interrupt mode
239 ldmfd sp!, {r4, r5, pc}
240
241/*
242 * Copy crunch state to given memory address
243 *
244 * r0 = struct thread_info pointer of target task
245 * r1 = memory address where to store crunch state
246 *
247 * this is called mainly in the creation of signal stack frames
248 */
249ENTRY(crunch_task_copy)
250 mrs ip, cpsr
251 orr r2, ip, #PSR_I_BIT @ disable interrupts
252 msr cpsr_c, r2
253
254 ldr r3, =crunch_owner
255 add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area
256 ldr r3, [r3] @ get current crunch owner
257 teq r2, r3 @ does this task own it...
258 beq 1f
259
260 @ current crunch values are in the task save area
261 msr cpsr_c, ip @ restore interrupt mode
262 mov r0, r1
263 mov r1, r2
264 mov r2, #CRUNCH_SIZE
265 b memcpy
266
2671: @ this task owns crunch regs -- grab a copy from there
268 mov r0, #0 @ nothing to load
269 mov r3, lr @ preserve return address
270 bl crunch_save
271 msr cpsr_c, ip @ restore interrupt mode
272 mov pc, r3
273
274/*
275 * Restore crunch state from given memory address
276 *
277 * r0 = struct thread_info pointer of target task
278 * r1 = memory address where to get crunch state from
279 *
280 * this is used to restore crunch state when unwinding a signal stack frame
281 */
282ENTRY(crunch_task_restore)
283 mrs ip, cpsr
284 orr r2, ip, #PSR_I_BIT @ disable interrupts
285 msr cpsr_c, r2
286
287 ldr r3, =crunch_owner
288 add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area
289 ldr r3, [r3] @ get current crunch owner
290 teq r2, r3 @ does this task own it...
291 beq 1f
292
293 @ this task doesn't own crunch regs -- use its save area
294 msr cpsr_c, ip @ restore interrupt mode
295 mov r0, r2
296 mov r2, #CRUNCH_SIZE
297 b memcpy
298
2991: @ this task owns crunch regs -- load them directly
300 mov r0, r1
301 mov r1, #0 @ nothing to save
302 mov r3, lr @ preserve return address
303 bl crunch_load
304 msr cpsr_c, ip @ restore interrupt mode
305 mov pc, r3
diff --git a/arch/arm/mach-ep93xx/crunch.c b/arch/arm/mach-ep93xx/crunch.c
new file mode 100644
index 00000000000..74753e2df60
--- /dev/null
+++ b/arch/arm/mach-ep93xx/crunch.c
@@ -0,0 +1,90 @@
1/*
2 * arch/arm/kernel/crunch.c
3 * Cirrus MaverickCrunch context switching and handling
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/signal.h>
16#include <linux/sched.h>
17#include <linux/init.h>
18#include <linux/io.h>
19
20#include <asm/thread_notify.h>
21
22#include "soc.h"
23
24struct crunch_state *crunch_owner;
25
26void crunch_task_release(struct thread_info *thread)
27{
28 local_irq_disable();
29 if (crunch_owner == &thread->crunchstate)
30 crunch_owner = NULL;
31 local_irq_enable();
32}
33
34static int crunch_enabled(u32 devcfg)
35{
36 return !!(devcfg & EP93XX_SYSCON_DEVCFG_CPENA);
37}
38
39static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t)
40{
41 struct thread_info *thread = (struct thread_info *)t;
42 struct crunch_state *crunch_state;
43 u32 devcfg;
44
45 crunch_state = &thread->crunchstate;
46
47 switch (cmd) {
48 case THREAD_NOTIFY_FLUSH:
49 memset(crunch_state, 0, sizeof(*crunch_state));
50
51 /*
52 * FALLTHROUGH: Ensure we don't try to overwrite our newly
53 * initialised state information on the first fault.
54 */
55
56 case THREAD_NOTIFY_EXIT:
57 crunch_task_release(thread);
58 break;
59
60 case THREAD_NOTIFY_SWITCH:
61 devcfg = __raw_readl(EP93XX_SYSCON_DEVCFG);
62 if (crunch_enabled(devcfg) || crunch_owner == crunch_state) {
63 /*
64 * We don't use ep93xx_syscon_swlocked_write() here
65 * because we are on the context switch path and
66 * preemption is already disabled.
67 */
68 devcfg ^= EP93XX_SYSCON_DEVCFG_CPENA;
69 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
70 __raw_writel(devcfg, EP93XX_SYSCON_DEVCFG);
71 }
72 break;
73 }
74
75 return NOTIFY_DONE;
76}
77
78static struct notifier_block crunch_notifier_block = {
79 .notifier_call = crunch_do,
80};
81
82static int __init crunch_init(void)
83{
84 thread_register_notifier(&crunch_notifier_block);
85 elf_hwcap |= HWCAP_CRUNCH;
86
87 return 0;
88}
89
90late_initcall(crunch_init);
diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c
index 5a257088125..16976d7bdc8 100644
--- a/arch/arm/mach-ep93xx/dma.c
+++ b/arch/arm/mach-ep93xx/dma.c
@@ -28,6 +28,8 @@
28#include <mach/dma.h> 28#include <mach/dma.h>
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30 30
31#include "soc.h"
32
31#define DMA_CHANNEL(_name, _base, _irq) \ 33#define DMA_CHANNEL(_name, _base, _irq) \
32 { .name = (_name), .base = (_base), .irq = (_irq) } 34 { .name = (_name), .base = (_base), .irq = (_irq) }
33 35
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index d115653edca..da9047d726f 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -43,6 +43,7 @@
43#include <asm/mach-types.h> 43#include <asm/mach-types.h>
44#include <asm/mach/arch.h> 44#include <asm/mach/arch.h>
45 45
46#include "soc.h"
46 47
47static void __init edb93xx_register_flash(void) 48static void __init edb93xx_register_flash(void)
48{ 49{
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index af46970dc58..fcdffbe49dc 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -20,6 +20,7 @@
20#include <asm/mach-types.h> 20#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
22 22
23#include "soc.h"
23 24
24static struct ep93xx_eth_data __initdata gesbc9312_eth_data = { 25static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
25 .phy_id = 1, 26 .phy_id = 1,
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index c4a7b84ef06..c64d7424660 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -6,40 +6,6 @@
6#define __ASM_ARCH_EP93XX_REGS_H 6#define __ASM_ARCH_EP93XX_REGS_H
7 7
8/* 8/*
9 * EP93xx Physical Memory Map:
10 *
11 * The ASDO pin is sampled at system reset to select a synchronous or
12 * asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up)
13 * the synchronous boot mode is selected. When ASDO is "0" (i.e
14 * pulled-down) the asynchronous boot mode is selected.
15 *
16 * In synchronous boot mode nSDCE3 is decoded starting at physical address
17 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
18 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
19 * decoded at 0xf0000000.
20 *
21 * There is known errata for the EP93xx dealing with External Memory
22 * Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design
23 * Guidelines" for more information. This document can be found at:
24 *
25 * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
26 */
27
28#define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
29#define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
30#define EP93XX_CS1_PHYS_BASE 0x10000000
31#define EP93XX_CS2_PHYS_BASE 0x20000000
32#define EP93XX_CS3_PHYS_BASE 0x30000000
33#define EP93XX_PCMCIA_PHYS_BASE 0x40000000
34#define EP93XX_CS6_PHYS_BASE 0x60000000
35#define EP93XX_CS7_PHYS_BASE 0x70000000
36#define EP93XX_SDCE0_PHYS_BASE 0xc0000000
37#define EP93XX_SDCE1_PHYS_BASE 0xd0000000
38#define EP93XX_SDCE2_PHYS_BASE 0xe0000000
39#define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
40#define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
41
42/*
43 * EP93xx linux memory map: 9 * EP93xx linux memory map:
44 * 10 *
45 * virt phys size 11 * virt phys size
@@ -62,58 +28,7 @@
62#define EP93XX_APB_PHYS(x) (EP93XX_APB_PHYS_BASE + (x)) 28#define EP93XX_APB_PHYS(x) (EP93XX_APB_PHYS_BASE + (x))
63#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x)) 29#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x))
64 30
65 31/* APB UARTs */
66/* AHB peripherals */
67#define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
68
69#define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000)
70#define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
71
72#define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000)
73#define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
74
75#define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000)
76#define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
77
78#define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
79
80#define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
81
82#define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
83
84#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
85
86#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
87
88#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
89
90#define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
91
92
93/* APB peripherals */
94#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
95
96#define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000)
97#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
98
99#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
100
101#define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000)
102#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)
103#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
104#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c)
105#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0)
106#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc)
107#define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8)
108
109#define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000)
110#define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
111
112#define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000)
113#define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
114
115#define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
116
117#define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000) 32#define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000)
118#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000) 33#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000)
119 34
@@ -123,108 +38,4 @@
123#define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000) 38#define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000)
124#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000) 39#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000)
125 40
126#define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000)
127#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
128
129#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
130#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
131
132#define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000)
133#define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
134
135#define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000)
136#define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
137
138#define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
139#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
140#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
141#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
142#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
143#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
144#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
145#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
146#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
147#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
148#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
149#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
150#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
151#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
152#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
153#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
154#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
155#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
156#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
157#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
158#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
159#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
160#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
161#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
162#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
163#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
164#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
165#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
166#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
167#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
168#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
169#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
170#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
171#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
172#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
173#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
174#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
175#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
176#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
177#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
178#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
179#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
180#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
181#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
182#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
183#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
184#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
185#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
186#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
187#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
188#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
189#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
190#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
191#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
192#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
193#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
194#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
195#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
196#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15)
197#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
198#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
199#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
200#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
201#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31)
202#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
203#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
204#define EP93XX_I2SCLKDIV_SDIV (1 << 16)
205#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
206#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
207#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
208#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
209#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
210#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
211#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
212#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
213#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
214#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
215#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
216#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
217#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
218#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
219#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
220#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
221#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
222#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
223#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
224#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
225#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
226
227#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
228
229
230#endif 41#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h b/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
index 8aff2ea3587..6d7c571a519 100644
--- a/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
+++ b/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
@@ -3,6 +3,16 @@
3#ifndef __GPIO_EP93XX_H 3#ifndef __GPIO_EP93XX_H
4#define __GPIO_EP93XX_H 4#define __GPIO_EP93XX_H
5 5
6#include <mach/ep93xx-regs.h>
7
8#define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000)
9#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)
10#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
11#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c)
12#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0)
13#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc)
14#define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8)
15
6/* GPIO port A. */ 16/* GPIO port A. */
7#define EP93XX_GPIO_LINE_A(x) ((x) + 0) 17#define EP93XX_GPIO_LINE_A(x) ((x) + 0)
8#define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0) 18#define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0)
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index 4df842897ea..efcd47815a9 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -5,7 +5,6 @@
5#ifndef __ASM_ARCH_HARDWARE_H 5#ifndef __ASM_ARCH_HARDWARE_H
6#define __ASM_ARCH_HARDWARE_H 6#define __ASM_ARCH_HARDWARE_H
7 7
8#include <mach/ep93xx-regs.h>
9#include <mach/platform.h> 8#include <mach/platform.h>
10 9
11/* 10/*
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index d4c934931f9..602bd87fd0a 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -21,20 +21,6 @@ struct ep93xx_eth_data
21void ep93xx_map_io(void); 21void ep93xx_map_io(void);
22void ep93xx_init_irq(void); 22void ep93xx_init_irq(void);
23 23
24/* EP93xx System Controller software locked register write */
25void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
26void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
27
28static inline void ep93xx_devcfg_set_bits(unsigned int bits)
29{
30 ep93xx_devcfg_set_clear(bits, 0x00);
31}
32
33static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
34{
35 ep93xx_devcfg_set_clear(0x00, bits);
36}
37
38#define EP93XX_CHIP_REV_D0 3 24#define EP93XX_CHIP_REV_D0 3
39#define EP93XX_CHIP_REV_D1 4 25#define EP93XX_CHIP_REV_D1 4
40#define EP93XX_CHIP_REV_E0 5 26#define EP93XX_CHIP_REV_E0 5
@@ -59,7 +45,7 @@ void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data);
59int ep93xx_keypad_acquire_gpio(struct platform_device *pdev); 45int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
60void ep93xx_keypad_release_gpio(struct platform_device *pdev); 46void ep93xx_keypad_release_gpio(struct platform_device *pdev);
61void ep93xx_register_i2s(void); 47void ep93xx_register_i2s(void);
62int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config); 48int ep93xx_i2s_acquire(void);
63void ep93xx_i2s_release(void); 49void ep93xx_i2s_release(void);
64void ep93xx_register_ac97(void); 50void ep93xx_register_ac97(void);
65 51
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 7b98084f0c9..dc431c5f04c 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -22,6 +22,7 @@
22#include <asm/mach-types.h> 22#include <asm/mach-types.h>
23#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24 24
25#include "soc.h"
25 26
26/************************************************************************* 27/*************************************************************************
27 * Micro9 NOR Flash 28 * Micro9 NOR Flash
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index f4e553eca21..f40c2987e54 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -29,6 +29,8 @@
29#include <asm/mach-types.h> 29#include <asm/mach-types.h>
30#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
31 31
32#include "soc.h"
33
32static struct ep93xx_eth_data __initdata simone_eth_data = { 34static struct ep93xx_eth_data __initdata simone_eth_data = {
33 .phy_id = 1, 35 .phy_id = 1,
34}; 36};
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index fd846331ddf..0c00852ef16 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -35,6 +35,8 @@
35#include <asm/mach-types.h> 35#include <asm/mach-types.h>
36#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
37 37
38#include "soc.h"
39
38#define SNAPPERCL15_NAND_BASE (EP93XX_CS7_PHYS_BASE + SZ_16M) 40#define SNAPPERCL15_NAND_BASE (EP93XX_CS7_PHYS_BASE + SZ_16M)
39 41
40#define SNAPPERCL15_NAND_WPN (1 << 8) /* Write protect (active low) */ 42#define SNAPPERCL15_NAND_WPN (1 << 8) /* Write protect (active low) */
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
new file mode 100644
index 00000000000..979fba72292
--- /dev/null
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -0,0 +1,213 @@
1/*
2 * arch/arm/mach-ep93xx/soc.h
3 *
4 * Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
5 * Copyright (C) 2012 Ryan Mallon <rmallon@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
13#ifndef _EP93XX_SOC_H
14#define _EP93XX_SOC_H
15
16#include <mach/ep93xx-regs.h>
17
18/*
19 * EP93xx Physical Memory Map:
20 *
21 * The ASDO pin is sampled at system reset to select a synchronous or
22 * asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up)
23 * the synchronous boot mode is selected. When ASDO is "0" (i.e
24 * pulled-down) the asynchronous boot mode is selected.
25 *
26 * In synchronous boot mode nSDCE3 is decoded starting at physical address
27 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
28 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
29 * decoded at 0xf0000000.
30 *
31 * There is known errata for the EP93xx dealing with External Memory
32 * Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design
33 * Guidelines" for more information. This document can be found at:
34 *
35 * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
36 */
37
38#define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
39#define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
40#define EP93XX_CS1_PHYS_BASE 0x10000000
41#define EP93XX_CS2_PHYS_BASE 0x20000000
42#define EP93XX_CS3_PHYS_BASE 0x30000000
43#define EP93XX_PCMCIA_PHYS_BASE 0x40000000
44#define EP93XX_CS6_PHYS_BASE 0x60000000
45#define EP93XX_CS7_PHYS_BASE 0x70000000
46#define EP93XX_SDCE0_PHYS_BASE 0xc0000000
47#define EP93XX_SDCE1_PHYS_BASE 0xd0000000
48#define EP93XX_SDCE2_PHYS_BASE 0xe0000000
49#define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
50#define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
51
52/* AHB peripherals */
53#define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
54
55#define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000)
56#define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
57
58#define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000)
59#define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
60
61#define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000)
62#define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
63
64#define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
65
66#define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
67
68#define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
69
70#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
71
72#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
73
74#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
75
76#define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
77
78/* APB peripherals */
79#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
80
81#define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000)
82#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
83
84#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
85
86#define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000)
87#define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
88
89#define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000)
90#define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
91
92#define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
93
94#define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000)
95#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
96
97#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
98#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
99
100#define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000)
101#define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
102
103#define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000)
104#define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
105
106#define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000)
107#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
108
109/* System controller */
110#define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
111#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
112#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
113#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
114#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
115#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
116#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
117#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
118#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
119#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
120#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
121#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
122#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
123#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
124#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
125#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
126#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
127#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
128#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
129#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
130#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
131#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
132#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
133#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
134#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
135#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
136#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
137#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
138#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
139#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
140#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
141#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
142#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
143#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
144#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
145#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
146#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
147#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
148#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
149#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
150#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
151#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
152#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
153#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
154#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
155#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
156#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
157#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
158#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
159#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
160#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
161#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
162#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
163#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
164#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
165#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
166#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
167#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
168#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15)
169#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
170#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
171#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
172#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
173#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31)
174#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
175#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
176#define EP93XX_I2SCLKDIV_SDIV (1 << 16)
177#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
178#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
179#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
180#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
181#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
182#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
183#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
184#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
185#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
186#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
187#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
188#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
189#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
190#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
191#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
192#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
193#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
194#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
195#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
196#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
197#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
198
199/* EP93xx System Controller software locked register write */
200void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
201void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
202
203static inline void ep93xx_devcfg_set_bits(unsigned int bits)
204{
205 ep93xx_devcfg_set_clear(bits, 0x00);
206}
207
208static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
209{
210 ep93xx_devcfg_set_clear(0x00, bits);
211}
212
213#endif /* _EP93XX_SOC_H */
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 79f8ecf07a1..5ea790942e9 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -28,6 +28,7 @@
28#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
30 30
31#include "soc.h"
31 32
32static struct map_desc ts72xx_io_desc[] __initdata = { 33static struct map_desc ts72xx_io_desc[] __initdata = {
33 { 34 {
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index d5fb44f16d3..ba156eb225e 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -34,10 +34,13 @@
34#include <mach/ep93xx_spi.h> 34#include <mach/ep93xx_spi.h>
35#include <mach/gpio-ep93xx.h> 35#include <mach/gpio-ep93xx.h>
36 36
37#include <asm/hardware/vic.h>
37#include <asm/mach-types.h> 38#include <asm/mach-types.h>
38#include <asm/mach/map.h> 39#include <asm/mach/map.h>
39#include <asm/mach/arch.h> 40#include <asm/mach/arch.h>
40 41
42#include "soc.h"
43
41/************************************************************************* 44/*************************************************************************
42 * Static I/O mappings for the FPGA 45 * Static I/O mappings for the FPGA
43 *************************************************************************/ 46 *************************************************************************/
@@ -361,6 +364,7 @@ MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
361 .atag_offset = 0x100, 364 .atag_offset = 0x100,
362 .map_io = vision_map_io, 365 .map_io = vision_map_io,
363 .init_irq = ep93xx_init_irq, 366 .init_irq = ep93xx_init_irq,
367 .handle_irq = vic_handle_irq,
364 .timer = &ep93xx_timer, 368 .timer = &ep93xx_timer,
365 .init_machine = vision_init_machine, 369 .init_machine = vision_init_machine,
366 .restart = ep93xx_restart, 370 .restart = ep93xx_restart,
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 07:38:22 -0400