aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-ep93xx
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-ep93xx')
-rw-r--r--arch/arm/mach-ep93xx/Makefile4
-rw-r--r--arch/arm/mach-ep93xx/core.c37
-rw-r--r--arch/arm/mach-ep93xx/dma-m2p.c411
-rw-r--r--arch/arm/mach-ep93xx/dma.c108
-rw-r--r--arch/arm/mach-ep93xx/gpio.c410
-rw-r--r--arch/arm/mach-ep93xx/include/mach/dma.h190
-rw-r--r--arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h1
-rw-r--r--arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h2
-rw-r--r--arch/arm/mach-ep93xx/simone.c4
-rw-r--r--arch/arm/mach-ep93xx/snappercl15.c4
10 files changed, 212 insertions, 959 deletions
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 33ee2c863d1..3cedcf2d39e 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -1,11 +1,13 @@
1# 1#
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4obj-y := core.o clock.o dma-m2p.o gpio.o 4obj-y := core.o clock.o
5obj-m := 5obj-m :=
6obj-n := 6obj-n :=
7obj- := 7obj- :=
8 8
9obj-$(CONFIG_EP93XX_DMA) += dma.o
10
9obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o 11obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o
10obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o 12obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o
11obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o 13obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 1d4b65fd673..c60f081e930 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -174,14 +174,10 @@ struct sys_timer ep93xx_timer = {
174/************************************************************************* 174/*************************************************************************
175 * EP93xx IRQ handling 175 * EP93xx IRQ handling
176 *************************************************************************/ 176 *************************************************************************/
177extern void ep93xx_gpio_init_irq(void);
178
179void __init ep93xx_init_irq(void) 177void __init ep93xx_init_irq(void)
180{ 178{
181 vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); 179 vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
182 vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); 180 vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
183
184 ep93xx_gpio_init_irq();
185} 181}
186 182
187 183
@@ -241,6 +237,24 @@ unsigned int ep93xx_chip_revision(void)
241} 237}
242 238
243/************************************************************************* 239/*************************************************************************
240 * EP93xx GPIO
241 *************************************************************************/
242static struct resource ep93xx_gpio_resource[] = {
243 {
244 .start = EP93XX_GPIO_PHYS_BASE,
245 .end = EP93XX_GPIO_PHYS_BASE + 0xcc - 1,
246 .flags = IORESOURCE_MEM,
247 },
248};
249
250static struct platform_device ep93xx_gpio_device = {
251 .name = "gpio-ep93xx",
252 .id = -1,
253 .num_resources = ARRAY_SIZE(ep93xx_gpio_resource),
254 .resource = ep93xx_gpio_resource,
255};
256
257/*************************************************************************
244 * EP93xx peripheral handling 258 * EP93xx peripheral handling
245 *************************************************************************/ 259 *************************************************************************/
246#define EP93XX_UART_MCR_OFFSET (0x0100) 260#define EP93XX_UART_MCR_OFFSET (0x0100)
@@ -251,9 +265,9 @@ static void ep93xx_uart_set_mctrl(struct amba_device *dev,
251 unsigned int mcr; 265 unsigned int mcr;
252 266
253 mcr = 0; 267 mcr = 0;
254 if (!(mctrl & TIOCM_RTS)) 268 if (mctrl & TIOCM_RTS)
255 mcr |= 2; 269 mcr |= 2;
256 if (!(mctrl & TIOCM_DTR)) 270 if (mctrl & TIOCM_DTR)
257 mcr |= 1; 271 mcr |= 1;
258 272
259 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); 273 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
@@ -492,11 +506,15 @@ static struct resource ep93xx_spi_resources[] = {
492 }, 506 },
493}; 507};
494 508
509static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
510
495static struct platform_device ep93xx_spi_device = { 511static struct platform_device ep93xx_spi_device = {
496 .name = "ep93xx-spi", 512 .name = "ep93xx-spi",
497 .id = 0, 513 .id = 0,
498 .dev = { 514 .dev = {
499 .platform_data = &ep93xx_spi_master_data, 515 .platform_data = &ep93xx_spi_master_data,
516 .coherent_dma_mask = DMA_BIT_MASK(32),
517 .dma_mask = &ep93xx_spi_dma_mask,
500 }, 518 },
501 .num_resources = ARRAY_SIZE(ep93xx_spi_resources), 519 .num_resources = ARRAY_SIZE(ep93xx_spi_resources),
502 .resource = ep93xx_spi_resources, 520 .resource = ep93xx_spi_resources,
@@ -870,14 +888,13 @@ void __init ep93xx_register_ac97(void)
870 platform_device_register(&ep93xx_pcm_device); 888 platform_device_register(&ep93xx_pcm_device);
871} 889}
872 890
873extern void ep93xx_gpio_init(void);
874
875void __init ep93xx_init_devices(void) 891void __init ep93xx_init_devices(void)
876{ 892{
877 /* Disallow access to MaverickCrunch initially */ 893 /* Disallow access to MaverickCrunch initially */
878 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); 894 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
879 895
880 ep93xx_gpio_init(); 896 /* Get the GPIO working early, other devices need it */
897 platform_device_register(&ep93xx_gpio_device);
881 898
882 amba_device_register(&uart1_device, &iomem_resource); 899 amba_device_register(&uart1_device, &iomem_resource);
883 amba_device_register(&uart2_device, &iomem_resource); 900 amba_device_register(&uart2_device, &iomem_resource);
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c
deleted file mode 100644
index a696d354b1f..00000000000
--- a/arch/arm/mach-ep93xx/dma-m2p.c
+++ /dev/null
@@ -1,411 +0,0 @@
1/*
2 * arch/arm/mach-ep93xx/dma-m2p.c
3 * M2P DMA handling for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Copyright (C) 2006 Applied Data Systems
7 *
8 * Copyright (C) 2009 Ryan Mallon <ryan@bluewatersys.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 */
15
16/*
17 * On the EP93xx chip the following peripherals my be allocated to the 10
18 * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
19 *
20 * I2S contains 3 Tx and 3 Rx DMA Channels
21 * AAC contains 3 Tx and 3 Rx DMA Channels
22 * UART1 contains 1 Tx and 1 Rx DMA Channels
23 * UART2 contains 1 Tx and 1 Rx DMA Channels
24 * UART3 contains 1 Tx and 1 Rx DMA Channels
25 * IrDA contains 1 Tx and 1 Rx DMA Channels
26 *
27 * SSP and IDE use the Memory to Memory (M2M) channels and are not covered
28 * with this implementation.
29 */
30
31#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
32
33#include <linux/kernel.h>
34#include <linux/clk.h>
35#include <linux/err.h>
36#include <linux/interrupt.h>
37#include <linux/module.h>
38#include <linux/io.h>
39
40#include <mach/dma.h>
41#include <mach/hardware.h>
42
43#define M2P_CONTROL 0x00
44#define M2P_CONTROL_STALL_IRQ_EN (1 << 0)
45#define M2P_CONTROL_NFB_IRQ_EN (1 << 1)
46#define M2P_CONTROL_ERROR_IRQ_EN (1 << 3)
47#define M2P_CONTROL_ENABLE (1 << 4)
48#define M2P_INTERRUPT 0x04
49#define M2P_INTERRUPT_STALL (1 << 0)
50#define M2P_INTERRUPT_NFB (1 << 1)
51#define M2P_INTERRUPT_ERROR (1 << 3)
52#define M2P_PPALLOC 0x08
53#define M2P_STATUS 0x0c
54#define M2P_REMAIN 0x14
55#define M2P_MAXCNT0 0x20
56#define M2P_BASE0 0x24
57#define M2P_MAXCNT1 0x30
58#define M2P_BASE1 0x34
59
60#define STATE_IDLE 0 /* Channel is inactive. */
61#define STATE_STALL 1 /* Channel is active, no buffers pending. */
62#define STATE_ON 2 /* Channel is active, one buffer pending. */
63#define STATE_NEXT 3 /* Channel is active, two buffers pending. */
64
65struct m2p_channel {
66 char *name;
67 void __iomem *base;
68 int irq;
69
70 struct clk *clk;
71 spinlock_t lock;
72
73 void *client;
74 unsigned next_slot:1;
75 struct ep93xx_dma_buffer *buffer_xfer;
76 struct ep93xx_dma_buffer *buffer_next;
77 struct list_head buffers_pending;
78};
79
80static struct m2p_channel m2p_rx[] = {
81 {"m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1},
82 {"m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3},
83 {"m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5},
84 {"m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7},
85 {"m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9},
86 {NULL},
87};
88
89static struct m2p_channel m2p_tx[] = {
90 {"m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0},
91 {"m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2},
92 {"m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4},
93 {"m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6},
94 {"m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8},
95 {NULL},
96};
97
98static void feed_buf(struct m2p_channel *ch, struct ep93xx_dma_buffer *buf)
99{
100 if (ch->next_slot == 0) {
101 writel(buf->size, ch->base + M2P_MAXCNT0);
102 writel(buf->bus_addr, ch->base + M2P_BASE0);
103 } else {
104 writel(buf->size, ch->base + M2P_MAXCNT1);
105 writel(buf->bus_addr, ch->base + M2P_BASE1);
106 }
107 ch->next_slot ^= 1;
108}
109
110static void choose_buffer_xfer(struct m2p_channel *ch)
111{
112 struct ep93xx_dma_buffer *buf;
113
114 ch->buffer_xfer = NULL;
115 if (!list_empty(&ch->buffers_pending)) {
116 buf = list_entry(ch->buffers_pending.next,
117 struct ep93xx_dma_buffer, list);
118 list_del(&buf->list);
119 feed_buf(ch, buf);
120 ch->buffer_xfer = buf;
121 }
122}
123
124static void choose_buffer_next(struct m2p_channel *ch)
125{
126 struct ep93xx_dma_buffer *buf;
127
128 ch->buffer_next = NULL;
129 if (!list_empty(&ch->buffers_pending)) {
130 buf = list_entry(ch->buffers_pending.next,
131 struct ep93xx_dma_buffer, list);
132 list_del(&buf->list);
133 feed_buf(ch, buf);
134 ch->buffer_next = buf;
135 }
136}
137
138static inline void m2p_set_control(struct m2p_channel *ch, u32 v)
139{
140 /*
141 * The control register must be read immediately after being written so
142 * that the internal state machine is correctly updated. See the ep93xx
143 * users' guide for details.
144 */
145 writel(v, ch->base + M2P_CONTROL);
146 readl(ch->base + M2P_CONTROL);
147}
148
149static inline int m2p_channel_state(struct m2p_channel *ch)
150{
151 return (readl(ch->base + M2P_STATUS) >> 4) & 0x3;
152}
153
154static irqreturn_t m2p_irq(int irq, void *dev_id)
155{
156 struct m2p_channel *ch = dev_id;
157 struct ep93xx_dma_m2p_client *cl;
158 u32 irq_status, v;
159 int error = 0;
160
161 cl = ch->client;
162
163 spin_lock(&ch->lock);
164 irq_status = readl(ch->base + M2P_INTERRUPT);
165
166 if (irq_status & M2P_INTERRUPT_ERROR) {
167 writel(M2P_INTERRUPT_ERROR, ch->base + M2P_INTERRUPT);
168 error = 1;
169 }
170
171 if ((irq_status & (M2P_INTERRUPT_STALL | M2P_INTERRUPT_NFB)) == 0) {
172 spin_unlock(&ch->lock);
173 return IRQ_NONE;
174 }
175
176 switch (m2p_channel_state(ch)) {
177 case STATE_IDLE:
178 pr_crit("dma interrupt without a dma buffer\n");
179 BUG();
180 break;
181
182 case STATE_STALL:
183 cl->buffer_finished(cl->cookie, ch->buffer_xfer, 0, error);
184 if (ch->buffer_next != NULL) {
185 cl->buffer_finished(cl->cookie, ch->buffer_next,
186 0, error);
187 }
188 choose_buffer_xfer(ch);
189 choose_buffer_next(ch);
190 if (ch->buffer_xfer != NULL)
191 cl->buffer_started(cl->cookie, ch->buffer_xfer);
192 break;
193
194 case STATE_ON:
195 cl->buffer_finished(cl->cookie, ch->buffer_xfer, 0, error);
196 ch->buffer_xfer = ch->buffer_next;
197 choose_buffer_next(ch);
198 cl->buffer_started(cl->cookie, ch->buffer_xfer);
199 break;
200
201 case STATE_NEXT:
202 pr_crit("dma interrupt while next\n");
203 BUG();
204 break;
205 }
206
207 v = readl(ch->base + M2P_CONTROL) & ~(M2P_CONTROL_STALL_IRQ_EN |
208 M2P_CONTROL_NFB_IRQ_EN);
209 if (ch->buffer_xfer != NULL)
210 v |= M2P_CONTROL_STALL_IRQ_EN;
211 if (ch->buffer_next != NULL)
212 v |= M2P_CONTROL_NFB_IRQ_EN;
213 m2p_set_control(ch, v);
214
215 spin_unlock(&ch->lock);
216 return IRQ_HANDLED;
217}
218
219static struct m2p_channel *find_free_channel(struct ep93xx_dma_m2p_client *cl)
220{
221 struct m2p_channel *ch;
222 int i;
223
224 if (cl->flags & EP93XX_DMA_M2P_RX)
225 ch = m2p_rx;
226 else
227 ch = m2p_tx;
228
229 for (i = 0; ch[i].base; i++) {
230 struct ep93xx_dma_m2p_client *client;
231
232 client = ch[i].client;
233 if (client != NULL) {
234 int port;
235
236 port = cl->flags & EP93XX_DMA_M2P_PORT_MASK;
237 if (port == (client->flags &
238 EP93XX_DMA_M2P_PORT_MASK)) {
239 pr_warning("DMA channel already used by %s\n",
240 cl->name ? : "unknown client");
241 return ERR_PTR(-EBUSY);
242 }
243 }
244 }
245
246 for (i = 0; ch[i].base; i++) {
247 if (ch[i].client == NULL)
248 return ch + i;
249 }
250
251 pr_warning("No free DMA channel for %s\n",
252 cl->name ? : "unknown client");
253 return ERR_PTR(-ENODEV);
254}
255
256static void channel_enable(struct m2p_channel *ch)
257{
258 struct ep93xx_dma_m2p_client *cl = ch->client;
259 u32 v;
260
261 clk_enable(ch->clk);
262
263 v = cl->flags & EP93XX_DMA_M2P_PORT_MASK;
264 writel(v, ch->base + M2P_PPALLOC);
265
266 v = cl->flags & EP93XX_DMA_M2P_ERROR_MASK;
267 v |= M2P_CONTROL_ENABLE | M2P_CONTROL_ERROR_IRQ_EN;
268 m2p_set_control(ch, v);
269}
270
271static void channel_disable(struct m2p_channel *ch)
272{
273 u32 v;
274
275 v = readl(ch->base + M2P_CONTROL);
276 v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN);
277 m2p_set_control(ch, v);
278
279 while (m2p_channel_state(ch) >= STATE_ON)
280 cpu_relax();
281
282 m2p_set_control(ch, 0x0);
283
284 while (m2p_channel_state(ch) == STATE_STALL)
285 cpu_relax();
286
287 clk_disable(ch->clk);
288}
289
290int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *cl)
291{
292 struct m2p_channel *ch;
293 int err;
294
295 ch = find_free_channel(cl);
296 if (IS_ERR(ch))
297 return PTR_ERR(ch);
298
299 err = request_irq(ch->irq, m2p_irq, 0, cl->name ? : "dma-m2p", ch);
300 if (err)
301 return err;
302
303 ch->client = cl;
304 ch->next_slot = 0;
305 ch->buffer_xfer = NULL;
306 ch->buffer_next = NULL;
307 INIT_LIST_HEAD(&ch->buffers_pending);
308
309 cl->channel = ch;
310
311 channel_enable(ch);
312
313 return 0;
314}
315EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_client_register);
316
317void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *cl)
318{
319 struct m2p_channel *ch = cl->channel;
320
321 channel_disable(ch);
322 free_irq(ch->irq, ch);
323 ch->client = NULL;
324}
325EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_client_unregister);
326
327void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *cl,
328 struct ep93xx_dma_buffer *buf)
329{
330 struct m2p_channel *ch = cl->channel;
331 unsigned long flags;
332 u32 v;
333
334 spin_lock_irqsave(&ch->lock, flags);
335 v = readl(ch->base + M2P_CONTROL);
336 if (ch->buffer_xfer == NULL) {
337 ch->buffer_xfer = buf;
338 feed_buf(ch, buf);
339 cl->buffer_started(cl->cookie, buf);
340
341 v |= M2P_CONTROL_STALL_IRQ_EN;
342 m2p_set_control(ch, v);
343
344 } else if (ch->buffer_next == NULL) {
345 ch->buffer_next = buf;
346 feed_buf(ch, buf);
347
348 v |= M2P_CONTROL_NFB_IRQ_EN;
349 m2p_set_control(ch, v);
350 } else {
351 list_add_tail(&buf->list, &ch->buffers_pending);
352 }
353 spin_unlock_irqrestore(&ch->lock, flags);
354}
355EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_submit);
356
357void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *cl,
358 struct ep93xx_dma_buffer *buf)
359{
360 struct m2p_channel *ch = cl->channel;
361
362 list_add_tail(&buf->list, &ch->buffers_pending);
363}
364EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_submit_recursive);
365
366void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *cl)
367{
368 struct m2p_channel *ch = cl->channel;
369
370 channel_disable(ch);
371 ch->next_slot = 0;
372 ch->buffer_xfer = NULL;
373 ch->buffer_next = NULL;
374 INIT_LIST_HEAD(&ch->buffers_pending);
375 channel_enable(ch);
376}
377EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_flush);
378
379static int init_channel(struct m2p_channel *ch)
380{
381 ch->clk = clk_get(NULL, ch->name);
382 if (IS_ERR(ch->clk))
383 return PTR_ERR(ch->clk);
384
385 spin_lock_init(&ch->lock);
386 ch->client = NULL;
387
388 return 0;
389}
390
391static int __init ep93xx_dma_m2p_init(void)
392{
393 int i;
394 int ret;
395
396 for (i = 0; m2p_rx[i].base; i++) {
397 ret = init_channel(m2p_rx + i);
398 if (ret)
399 return ret;
400 }
401
402 for (i = 0; m2p_tx[i].base; i++) {
403 ret = init_channel(m2p_tx + i);
404 if (ret)
405 return ret;
406 }
407
408 pr_info("M2P DMA subsystem initialized\n");
409 return 0;
410}
411arch_initcall(ep93xx_dma_m2p_init);
diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c
new file mode 100644
index 00000000000..5a257088125
--- /dev/null
+++ b/arch/arm/mach-ep93xx/dma.c
@@ -0,0 +1,108 @@
1/*
2 * arch/arm/mach-ep93xx/dma.c
3 *
4 * Platform support code for the EP93xx dmaengine driver.
5 *
6 * Copyright (C) 2011 Mika Westerberg
7 *
8 * This work is based on the original dma-m2p implementation with
9 * following copyrights:
10 *
11 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
12 * Copyright (C) 2006 Applied Data Systems
13 * Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or (at
18 * your option) any later version.
19 */
20
21#include <linux/dmaengine.h>
22#include <linux/dma-mapping.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/kernel.h>
26#include <linux/platform_device.h>
27
28#include <mach/dma.h>
29#include <mach/hardware.h>
30
31#define DMA_CHANNEL(_name, _base, _irq) \
32 { .name = (_name), .base = (_base), .irq = (_irq) }
33
34/*
35 * DMA M2P channels.
36 *
37 * On the EP93xx chip the following peripherals my be allocated to the 10
38 * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
39 *
40 * I2S contains 3 Tx and 3 Rx DMA Channels
41 * AAC contains 3 Tx and 3 Rx DMA Channels
42 * UART1 contains 1 Tx and 1 Rx DMA Channels
43 * UART2 contains 1 Tx and 1 Rx DMA Channels
44 * UART3 contains 1 Tx and 1 Rx DMA Channels
45 * IrDA contains 1 Tx and 1 Rx DMA Channels
46 *
47 * Registers are mapped statically in ep93xx_map_io().
48 */
49static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] = {
50 DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0),
51 DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1),
52 DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2),
53 DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3),
54 DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4),
55 DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5),
56 DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6),
57 DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7),
58 DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8),
59 DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9),
60};
61
62static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data = {
63 .channels = ep93xx_dma_m2p_channels,
64 .num_channels = ARRAY_SIZE(ep93xx_dma_m2p_channels),
65};
66
67static struct platform_device ep93xx_dma_m2p_device = {
68 .name = "ep93xx-dma-m2p",
69 .id = -1,
70 .dev = {
71 .platform_data = &ep93xx_dma_m2p_data,
72 },
73};
74
75/*
76 * DMA M2M channels.
77 *
78 * There are 2 M2M channels which support memcpy/memset and in addition simple
79 * hardware requests from/to SSP and IDE. We do not implement an external
80 * hardware requests.
81 *
82 * Registers are mapped statically in ep93xx_map_io().
83 */
84static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] = {
85 DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0),
86 DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1),
87};
88
89static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data = {
90 .channels = ep93xx_dma_m2m_channels,
91 .num_channels = ARRAY_SIZE(ep93xx_dma_m2m_channels),
92};
93
94static struct platform_device ep93xx_dma_m2m_device = {
95 .name = "ep93xx-dma-m2m",
96 .id = -1,
97 .dev = {
98 .platform_data = &ep93xx_dma_m2m_data,
99 },
100};
101
102static int __init ep93xx_dma_init(void)
103{
104 platform_device_register(&ep93xx_dma_m2p_device);
105 platform_device_register(&ep93xx_dma_m2m_device);
106 return 0;
107}
108arch_initcall(ep93xx_dma_init);
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
deleted file mode 100644
index 415dce37b88..00000000000
--- a/arch/arm/mach-ep93xx/gpio.c
+++ /dev/null
@@ -1,410 +0,0 @@
1/*
2 * linux/arch/arm/mach-ep93xx/gpio.c
3 *
4 * Generic EP93xx GPIO handling
5 *
6 * Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
7 *
8 * Based on code originally from:
9 * linux/arch/arm/mach-ep93xx/core.c
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/seq_file.h>
21#include <linux/io.h>
22#include <linux/gpio.h>
23#include <linux/irq.h>
24
25#include <mach/hardware.h>
26
27/*************************************************************************
28 * Interrupt handling for EP93xx on-chip GPIOs
29 *************************************************************************/
30static unsigned char gpio_int_unmasked[3];
31static unsigned char gpio_int_enabled[3];
32static unsigned char gpio_int_type1[3];
33static unsigned char gpio_int_type2[3];
34static unsigned char gpio_int_debounce[3];
35
36/* Port ordering is: A B F */
37static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
38static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
39static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
40static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
41static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
42
43static void ep93xx_gpio_update_int_params(unsigned port)
44{
45 BUG_ON(port > 2);
46
47 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
48
49 __raw_writeb(gpio_int_type2[port],
50 EP93XX_GPIO_REG(int_type2_register_offset[port]));
51
52 __raw_writeb(gpio_int_type1[port],
53 EP93XX_GPIO_REG(int_type1_register_offset[port]));
54
55 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
56 EP93XX_GPIO_REG(int_en_register_offset[port]));
57}
58
59static inline void ep93xx_gpio_int_mask(unsigned line)
60{
61 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
62}
63
64static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
65{
66 int line = irq_to_gpio(irq);
67 int port = line >> 3;
68 int port_mask = 1 << (line & 7);
69
70 if (enable)
71 gpio_int_debounce[port] |= port_mask;
72 else
73 gpio_int_debounce[port] &= ~port_mask;
74
75 __raw_writeb(gpio_int_debounce[port],
76 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
77}
78
79static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
80{
81 unsigned char status;
82 int i;
83
84 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
85 for (i = 0; i < 8; i++) {
86 if (status & (1 << i)) {
87 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
88 generic_handle_irq(gpio_irq);
89 }
90 }
91
92 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
93 for (i = 0; i < 8; i++) {
94 if (status & (1 << i)) {
95 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
96 generic_handle_irq(gpio_irq);
97 }
98 }
99}
100
101static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
102{
103 /*
104 * map discontiguous hw irq range to continuous sw irq range:
105 *
106 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
107 */
108 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
109 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
110
111 generic_handle_irq(gpio_irq);
112}
113
114static void ep93xx_gpio_irq_ack(struct irq_data *d)
115{
116 int line = irq_to_gpio(d->irq);
117 int port = line >> 3;
118 int port_mask = 1 << (line & 7);
119
120 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
121 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
122 ep93xx_gpio_update_int_params(port);
123 }
124
125 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
126}
127
128static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
129{
130 int line = irq_to_gpio(d->irq);
131 int port = line >> 3;
132 int port_mask = 1 << (line & 7);
133
134 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
135 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
136
137 gpio_int_unmasked[port] &= ~port_mask;
138 ep93xx_gpio_update_int_params(port);
139
140 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
141}
142
143static void ep93xx_gpio_irq_mask(struct irq_data *d)
144{
145 int line = irq_to_gpio(d->irq);
146 int port = line >> 3;
147
148 gpio_int_unmasked[port] &= ~(1 << (line & 7));
149 ep93xx_gpio_update_int_params(port);
150}
151
152static void ep93xx_gpio_irq_unmask(struct irq_data *d)
153{
154 int line = irq_to_gpio(d->irq);
155 int port = line >> 3;
156
157 gpio_int_unmasked[port] |= 1 << (line & 7);
158 ep93xx_gpio_update_int_params(port);
159}
160
161/*
162 * gpio_int_type1 controls whether the interrupt is level (0) or
163 * edge (1) triggered, while gpio_int_type2 controls whether it
164 * triggers on low/falling (0) or high/rising (1).
165 */
166static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
167{
168 const int gpio = irq_to_gpio(d->irq);
169 const int port = gpio >> 3;
170 const int port_mask = 1 << (gpio & 7);
171 irq_flow_handler_t handler;
172
173 gpio_direction_input(gpio);
174
175 switch (type) {
176 case IRQ_TYPE_EDGE_RISING:
177 gpio_int_type1[port] |= port_mask;
178 gpio_int_type2[port] |= port_mask;
179 handler = handle_edge_irq;
180 break;
181 case IRQ_TYPE_EDGE_FALLING:
182 gpio_int_type1[port] |= port_mask;
183 gpio_int_type2[port] &= ~port_mask;
184 handler = handle_edge_irq;
185 break;
186 case IRQ_TYPE_LEVEL_HIGH:
187 gpio_int_type1[port] &= ~port_mask;
188 gpio_int_type2[port] |= port_mask;
189 handler = handle_level_irq;
190 break;
191 case IRQ_TYPE_LEVEL_LOW:
192 gpio_int_type1[port] &= ~port_mask;
193 gpio_int_type2[port] &= ~port_mask;
194 handler = handle_level_irq;
195 break;
196 case IRQ_TYPE_EDGE_BOTH:
197 gpio_int_type1[port] |= port_mask;
198 /* set initial polarity based on current input level */
199 if (gpio_get_value(gpio))
200 gpio_int_type2[port] &= ~port_mask; /* falling */
201 else
202 gpio_int_type2[port] |= port_mask; /* rising */
203 handler = handle_edge_irq;
204 break;
205 default:
206 pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
207 return -EINVAL;
208 }
209
210 __irq_set_handler_locked(d->irq, handler);
211
212 gpio_int_enabled[port] |= port_mask;
213
214 ep93xx_gpio_update_int_params(port);
215
216 return 0;
217}
218
219static struct irq_chip ep93xx_gpio_irq_chip = {
220 .name = "GPIO",
221 .irq_ack = ep93xx_gpio_irq_ack,
222 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
223 .irq_mask = ep93xx_gpio_irq_mask,
224 .irq_unmask = ep93xx_gpio_irq_unmask,
225 .irq_set_type = ep93xx_gpio_irq_type,
226};
227
228void __init ep93xx_gpio_init_irq(void)
229{
230 int gpio_irq;
231
232 for (gpio_irq = gpio_to_irq(0);
233 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
234 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
235 handle_level_irq);
236 set_irq_flags(gpio_irq, IRQF_VALID);
237 }
238
239 irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
240 ep93xx_gpio_ab_irq_handler);
241 irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
242 ep93xx_gpio_f_irq_handler);
243 irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
244 ep93xx_gpio_f_irq_handler);
245 irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
246 ep93xx_gpio_f_irq_handler);
247 irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
248 ep93xx_gpio_f_irq_handler);
249 irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
250 ep93xx_gpio_f_irq_handler);
251 irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
252 ep93xx_gpio_f_irq_handler);
253 irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
254 ep93xx_gpio_f_irq_handler);
255 irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
256 ep93xx_gpio_f_irq_handler);
257}
258
259
260/*************************************************************************
261 * gpiolib interface for EP93xx on-chip GPIOs
262 *************************************************************************/
263struct ep93xx_gpio_chip {
264 struct gpio_chip chip;
265
266 void __iomem *data_reg;
267 void __iomem *data_dir_reg;
268};
269
270#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
271
272static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
273{
274 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
275 unsigned long flags;
276 u8 v;
277
278 local_irq_save(flags);
279 v = __raw_readb(ep93xx_chip->data_dir_reg);
280 v &= ~(1 << offset);
281 __raw_writeb(v, ep93xx_chip->data_dir_reg);
282 local_irq_restore(flags);
283
284 return 0;
285}
286
287static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
288 unsigned offset, int val)
289{
290 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
291 unsigned long flags;
292 int line;
293 u8 v;
294
295 local_irq_save(flags);
296
297 /* Set the value */
298 v = __raw_readb(ep93xx_chip->data_reg);
299 if (val)
300 v |= (1 << offset);
301 else
302 v &= ~(1 << offset);
303 __raw_writeb(v, ep93xx_chip->data_reg);
304
305 /* Drive as an output */
306 line = chip->base + offset;
307 if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
308 /* Ports A/B/F */
309 ep93xx_gpio_int_mask(line);
310 ep93xx_gpio_update_int_params(line >> 3);
311 }
312
313 v = __raw_readb(ep93xx_chip->data_dir_reg);
314 v |= (1 << offset);
315 __raw_writeb(v, ep93xx_chip->data_dir_reg);
316
317 local_irq_restore(flags);
318
319 return 0;
320}
321
322static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
323{
324 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
325
326 return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
327}
328
329static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
330{
331 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
332 unsigned long flags;
333 u8 v;
334
335 local_irq_save(flags);
336 v = __raw_readb(ep93xx_chip->data_reg);
337 if (val)
338 v |= (1 << offset);
339 else
340 v &= ~(1 << offset);
341 __raw_writeb(v, ep93xx_chip->data_reg);
342 local_irq_restore(flags);
343}
344
345static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
346 unsigned offset, unsigned debounce)
347{
348 int gpio = chip->base + offset;
349 int irq = gpio_to_irq(gpio);
350
351 if (irq < 0)
352 return -EINVAL;
353
354 ep93xx_gpio_int_debounce(irq, debounce ? true : false);
355
356 return 0;
357}
358
359#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \
360 { \
361 .chip = { \
362 .label = name, \
363 .direction_input = ep93xx_gpio_direction_input, \
364 .direction_output = ep93xx_gpio_direction_output, \
365 .get = ep93xx_gpio_get, \
366 .set = ep93xx_gpio_set, \
367 .base = base_gpio, \
368 .ngpio = 8, \
369 }, \
370 .data_reg = EP93XX_GPIO_REG(dr), \
371 .data_dir_reg = EP93XX_GPIO_REG(ddr), \
372 }
373
374static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
375 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
376 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
377 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40),
378 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
379 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
380 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16),
381 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
382 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
383};
384
385void __init ep93xx_gpio_init(void)
386{
387 int i;
388
389 /* Set Ports C, D, E, G, and H for GPIO use */
390 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
391 EP93XX_SYSCON_DEVCFG_GONK |
392 EP93XX_SYSCON_DEVCFG_EONIDE |
393 EP93XX_SYSCON_DEVCFG_GONIDE |
394 EP93XX_SYSCON_DEVCFG_HONIDE);
395
396 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
397 struct gpio_chip *chip = &ep93xx_gpio_banks[i].chip;
398
399 /*
400 * Ports A, B, and F support input debouncing when
401 * used as interrupts.
402 */
403 if (!strcmp(chip->label, "A") ||
404 !strcmp(chip->label, "B") ||
405 !strcmp(chip->label, "F"))
406 chip->set_debounce = ep93xx_gpio_set_debounce;
407
408 gpiochip_add(chip);
409 }
410}
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h
index 5e31b2b25da..46d4d876e6f 100644
--- a/arch/arm/mach-ep93xx/include/mach/dma.h
+++ b/arch/arm/mach-ep93xx/include/mach/dma.h
@@ -1,149 +1,93 @@
1/**
2 * DOC: EP93xx DMA M2P memory to peripheral and peripheral to memory engine
3 *
4 * The EP93xx DMA M2P subsystem handles DMA transfers between memory and
5 * peripherals. DMA M2P channels are available for audio, UARTs and IrDA.
6 * See chapter 10 of the EP93xx users guide for full details on the DMA M2P
7 * engine.
8 *
9 * See sound/soc/ep93xx/ep93xx-pcm.c for an example use of the DMA M2P code.
10 *
11 */
12
13#ifndef __ASM_ARCH_DMA_H 1#ifndef __ASM_ARCH_DMA_H
14#define __ASM_ARCH_DMA_H 2#define __ASM_ARCH_DMA_H
15 3
16#include <linux/list.h>
17#include <linux/types.h> 4#include <linux/types.h>
5#include <linux/dmaengine.h>
6#include <linux/dma-mapping.h>
18 7
19/** 8/*
20 * struct ep93xx_dma_buffer - Information about a buffer to be transferred 9 * M2P channels.
21 * using the DMA M2P engine
22 * 10 *
23 * @list: Entry in DMA buffer list 11 * Note that these values are also directly used for setting the PPALLOC
24 * @bus_addr: Physical address of the buffer 12 * register.
25 * @size: Size of the buffer in bytes
26 */ 13 */
27struct ep93xx_dma_buffer { 14#define EP93XX_DMA_I2S1 0
28 struct list_head list; 15#define EP93XX_DMA_I2S2 1
29 u32 bus_addr; 16#define EP93XX_DMA_AAC1 2
30 u16 size; 17#define EP93XX_DMA_AAC2 3
31}; 18#define EP93XX_DMA_AAC3 4
19#define EP93XX_DMA_I2S3 5
20#define EP93XX_DMA_UART1 6
21#define EP93XX_DMA_UART2 7
22#define EP93XX_DMA_UART3 8
23#define EP93XX_DMA_IRDA 9
24/* M2M channels */
25#define EP93XX_DMA_SSP 10
26#define EP93XX_DMA_IDE 11
32 27
33/** 28/**
34 * struct ep93xx_dma_m2p_client - Information about a DMA M2P client 29 * struct ep93xx_dma_data - configuration data for the EP93xx dmaengine
35 * 30 * @port: peripheral which is requesting the channel
36 * @name: Unique name for this client 31 * @direction: TX/RX channel
37 * @flags: Client flags 32 * @name: optional name for the channel, this is displayed in /proc/interrupts
38 * @cookie: User data to pass to callback functions 33 *
39 * @buffer_started: Non NULL function to call when a transfer is started. 34 * This information is passed as private channel parameter in a filter
40 * The arguments are the user data cookie and the DMA 35 * function. Note that this is only needed for slave/cyclic channels. For
41 * buffer which is starting. 36 * memcpy channels %NULL data should be passed.
42 * @buffer_finished: Non NULL function to call when a transfer is completed.
43 * The arguments are the user data cookie, the DMA buffer
44 * which has completed, and a boolean flag indicating if
45 * the transfer had an error.
46 */ 37 */
47struct ep93xx_dma_m2p_client { 38struct ep93xx_dma_data {
48 char *name; 39 int port;
49 u8 flags; 40 enum dma_data_direction direction;
50 void *cookie; 41 const char *name;
51 void (*buffer_started)(void *cookie,
52 struct ep93xx_dma_buffer *buf);
53 void (*buffer_finished)(void *cookie,
54 struct ep93xx_dma_buffer *buf,
55 int bytes, int error);
56
57 /* private: Internal use only */
58 void *channel;
59}; 42};
60 43
61/* DMA M2P ports */
62#define EP93XX_DMA_M2P_PORT_I2S1 0x00
63#define EP93XX_DMA_M2P_PORT_I2S2 0x01
64#define EP93XX_DMA_M2P_PORT_AAC1 0x02
65#define EP93XX_DMA_M2P_PORT_AAC2 0x03
66#define EP93XX_DMA_M2P_PORT_AAC3 0x04
67#define EP93XX_DMA_M2P_PORT_I2S3 0x05
68#define EP93XX_DMA_M2P_PORT_UART1 0x06
69#define EP93XX_DMA_M2P_PORT_UART2 0x07
70#define EP93XX_DMA_M2P_PORT_UART3 0x08
71#define EP93XX_DMA_M2P_PORT_IRDA 0x09
72#define EP93XX_DMA_M2P_PORT_MASK 0x0f
73
74/* DMA M2P client flags */
75#define EP93XX_DMA_M2P_TX 0x00 /* Memory to peripheral */
76#define EP93XX_DMA_M2P_RX 0x10 /* Peripheral to memory */
77
78/*
79 * DMA M2P client error handling flags. See the EP93xx users guide
80 * documentation on the DMA M2P CONTROL register for more details
81 */
82#define EP93XX_DMA_M2P_ABORT_ON_ERROR 0x20 /* Abort on peripheral error */
83#define EP93XX_DMA_M2P_IGNORE_ERROR 0x40 /* Ignore peripheral errors */
84#define EP93XX_DMA_M2P_ERROR_MASK 0x60 /* Mask of error bits */
85
86/** 44/**
87 * ep93xx_dma_m2p_client_register - Register a client with the DMA M2P 45 * struct ep93xx_dma_chan_data - platform specific data for a DMA channel
88 * subsystem 46 * @name: name of the channel, used for getting the right clock for the channel
89 * 47 * @base: mapped registers
90 * @m2p: Client information to register 48 * @irq: interrupt number used by this channel
91 * returns 0 on success
92 *
93 * The DMA M2P subsystem allocates a channel and an interrupt line for the DMA
94 * client
95 */ 49 */
96int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p); 50struct ep93xx_dma_chan_data {
51 const char *name;
52 void __iomem *base;
53 int irq;
54};
97 55
98/** 56/**
99 * ep93xx_dma_m2p_client_unregister - Unregister a client from the DMA M2P 57 * struct ep93xx_dma_platform_data - platform data for the dmaengine driver
100 * subsystem 58 * @channels: array of channels which are passed to the driver
101 * 59 * @num_channels: number of channels in the array
102 * @m2p: Client to unregister
103 * 60 *
104 * Any transfers currently in progress will be completed in hardware, but 61 * This structure is passed to the DMA engine driver via platform data. For
105 * ignored in software. 62 * M2P channels, contract is that even channels are for TX and odd for RX.
63 * There is no requirement for the M2M channels.
106 */ 64 */
107void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *m2p); 65struct ep93xx_dma_platform_data {
66 struct ep93xx_dma_chan_data *channels;
67 size_t num_channels;
68};
108 69
109/** 70static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan)
110 * ep93xx_dma_m2p_submit - Submit a DMA M2P transfer 71{
111 * 72 return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p");
112 * @m2p: DMA Client to submit the transfer on 73}
113 * @buf: DMA Buffer to submit
114 *
115 * If the current or next transfer positions are free on the M2P client then
116 * the transfer is started immediately. If not, the transfer is added to the
117 * list of pending transfers. This function must not be called from the
118 * buffer_finished callback for an M2P channel.
119 *
120 */
121void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *m2p,
122 struct ep93xx_dma_buffer *buf);
123 74
124/** 75/**
125 * ep93xx_dma_m2p_submit_recursive - Put a DMA transfer on the pending list 76 * ep93xx_dma_chan_direction - returns direction the channel can be used
126 * for an M2P channel 77 * @chan: channel
127 * 78 *
128 * @m2p: DMA Client to submit the transfer on 79 * This function can be used in filter functions to find out whether the
129 * @buf: DMA Buffer to submit 80 * channel supports given DMA direction. Only M2P channels have such
130 * 81 * limitation, for M2M channels the direction is configurable.
131 * This function must only be called from the buffer_finished callback for an
132 * M2P channel. It is commonly used to add the next transfer in a chained list
133 * of DMA transfers.
134 */ 82 */
135void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *m2p, 83static inline enum dma_data_direction
136 struct ep93xx_dma_buffer *buf); 84ep93xx_dma_chan_direction(struct dma_chan *chan)
85{
86 if (!ep93xx_dma_chan_is_m2p(chan))
87 return DMA_NONE;
137 88
138/** 89 /* even channels are for TX, odd for RX */
139 * ep93xx_dma_m2p_flush - Flush all pending transfers on a DMA M2P client 90 return (chan->chan_id % 2 == 0) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
140 * 91}
141 * @m2p: DMA client to flush transfers on
142 *
143 * Any transfers currently in progress will be completed in hardware, but
144 * ignored in software.
145 *
146 */
147void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *m2p);
148 92
149#endif /* __ASM_ARCH_DMA_H */ 93#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 9ac4d105509..c4a7b84ef06 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -98,6 +98,7 @@
98 98
99#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000) 99#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
100 100
101#define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000)
101#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000) 102#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)
102#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) 103#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
103#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) 104#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c)
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h b/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h
index 0a37961b345..9bb63ac13f0 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h
@@ -7,9 +7,11 @@ struct spi_device;
7 * struct ep93xx_spi_info - EP93xx specific SPI descriptor 7 * struct ep93xx_spi_info - EP93xx specific SPI descriptor
8 * @num_chipselect: number of chip selects on this board, must be 8 * @num_chipselect: number of chip selects on this board, must be
9 * at least one 9 * at least one
10 * @use_dma: use DMA for the transfers
10 */ 11 */
11struct ep93xx_spi_info { 12struct ep93xx_spi_info {
12 int num_chipselect; 13 int num_chipselect;
14 bool use_dma;
13}; 15};
14 16
15/** 17/**
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index d96dc1c5da2..8392e95d7ce 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -2,7 +2,7 @@
2 * arch/arm/mach-ep93xx/simone.c 2 * arch/arm/mach-ep93xx/simone.c
3 * Simplemachines Sim.One support. 3 * Simplemachines Sim.One support.
4 * 4 *
5 * Copyright (C) 2010 Ryan Mallon <ryan@bluewatersys.com> 5 * Copyright (C) 2010 Ryan Mallon
6 * 6 *
7 * Based on the 2.6.24.7 support: 7 * Based on the 2.6.24.7 support:
8 * Copyright (C) 2009 Simplemachines 8 * Copyright (C) 2009 Simplemachines
@@ -65,7 +65,7 @@ static void __init simone_init_machine(void)
65} 65}
66 66
67MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") 67MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
68/* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */ 68/* Maintainer: Ryan Mallon */
69 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, 69 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100,
70 .map_io = ep93xx_map_io, 70 .map_io = ep93xx_map_io,
71 .init_irq = ep93xx_init_irq, 71 .init_irq = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index ac601fe2b44..2e9c614757e 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -3,7 +3,7 @@
3 * Bluewater Systems Snapper CL15 system module 3 * Bluewater Systems Snapper CL15 system module
4 * 4 *
5 * Copyright (C) 2009 Bluewater Systems Ltd 5 * Copyright (C) 2009 Bluewater Systems Ltd
6 * Author: Ryan Mallon <ryan@bluewatersys.com> 6 * Author: Ryan Mallon
7 * 7 *
8 * NAND code adapted from driver by: 8 * NAND code adapted from driver by:
9 * Andre Renaud <andre@bluewatersys.com> 9 * Andre Renaud <andre@bluewatersys.com>
@@ -162,7 +162,7 @@ static void __init snappercl15_init_machine(void)
162} 162}
163 163
164MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15") 164MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
165 /* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */ 165 /* Maintainer: Ryan Mallon */
166 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, 166 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100,
167 .map_io = ep93xx_map_io, 167 .map_io = ep93xx_map_io,
168 .init_irq = ep93xx_init_irq, 168 .init_irq = ep93xx_init_irq,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 05:01:48 -0500