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-rw-r--r--arch/arm/mach-ep93xx/include/mach/clkdev.h11
-rw-r--r--arch/arm/mach-ep93xx/include/mach/dma.h190
-rw-r--r--arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h1
-rw-r--r--arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h2
-rw-r--r--arch/arm/mach-ep93xx/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-ep93xx/include/mach/ts72xx.h26
6 files changed, 92 insertions, 140 deletions
diff --git a/arch/arm/mach-ep93xx/include/mach/clkdev.h b/arch/arm/mach-ep93xx/include/mach/clkdev.h
deleted file mode 100644
index 50cb991eade..00000000000
--- a/arch/arm/mach-ep93xx/include/mach/clkdev.h
+++ /dev/null
@@ -1,11 +0,0 @@
1/*
2 * arch/arm/mach-ep93xx/include/mach/clkdev.h
3 */
4
5#ifndef __ASM_MACH_CLKDEV_H
6#define __ASM_MACH_CLKDEV_H
7
8#define __clk_get(clk) ({ 1; })
9#define __clk_put(clk) do { } while (0)
10
11#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h
index 5e31b2b25da..46d4d876e6f 100644
--- a/arch/arm/mach-ep93xx/include/mach/dma.h
+++ b/arch/arm/mach-ep93xx/include/mach/dma.h
@@ -1,149 +1,93 @@
1/**
2 * DOC: EP93xx DMA M2P memory to peripheral and peripheral to memory engine
3 *
4 * The EP93xx DMA M2P subsystem handles DMA transfers between memory and
5 * peripherals. DMA M2P channels are available for audio, UARTs and IrDA.
6 * See chapter 10 of the EP93xx users guide for full details on the DMA M2P
7 * engine.
8 *
9 * See sound/soc/ep93xx/ep93xx-pcm.c for an example use of the DMA M2P code.
10 *
11 */
12
13#ifndef __ASM_ARCH_DMA_H 1#ifndef __ASM_ARCH_DMA_H
14#define __ASM_ARCH_DMA_H 2#define __ASM_ARCH_DMA_H
15 3
16#include <linux/list.h>
17#include <linux/types.h> 4#include <linux/types.h>
5#include <linux/dmaengine.h>
6#include <linux/dma-mapping.h>
18 7
19/** 8/*
20 * struct ep93xx_dma_buffer - Information about a buffer to be transferred 9 * M2P channels.
21 * using the DMA M2P engine
22 * 10 *
23 * @list: Entry in DMA buffer list 11 * Note that these values are also directly used for setting the PPALLOC
24 * @bus_addr: Physical address of the buffer 12 * register.
25 * @size: Size of the buffer in bytes
26 */ 13 */
27struct ep93xx_dma_buffer { 14#define EP93XX_DMA_I2S1 0
28 struct list_head list; 15#define EP93XX_DMA_I2S2 1
29 u32 bus_addr; 16#define EP93XX_DMA_AAC1 2
30 u16 size; 17#define EP93XX_DMA_AAC2 3
31}; 18#define EP93XX_DMA_AAC3 4
19#define EP93XX_DMA_I2S3 5
20#define EP93XX_DMA_UART1 6
21#define EP93XX_DMA_UART2 7
22#define EP93XX_DMA_UART3 8
23#define EP93XX_DMA_IRDA 9
24/* M2M channels */
25#define EP93XX_DMA_SSP 10
26#define EP93XX_DMA_IDE 11
32 27
33/** 28/**
34 * struct ep93xx_dma_m2p_client - Information about a DMA M2P client 29 * struct ep93xx_dma_data - configuration data for the EP93xx dmaengine
35 * 30 * @port: peripheral which is requesting the channel
36 * @name: Unique name for this client 31 * @direction: TX/RX channel
37 * @flags: Client flags 32 * @name: optional name for the channel, this is displayed in /proc/interrupts
38 * @cookie: User data to pass to callback functions 33 *
39 * @buffer_started: Non NULL function to call when a transfer is started. 34 * This information is passed as private channel parameter in a filter
40 * The arguments are the user data cookie and the DMA 35 * function. Note that this is only needed for slave/cyclic channels. For
41 * buffer which is starting. 36 * memcpy channels %NULL data should be passed.
42 * @buffer_finished: Non NULL function to call when a transfer is completed.
43 * The arguments are the user data cookie, the DMA buffer
44 * which has completed, and a boolean flag indicating if
45 * the transfer had an error.
46 */ 37 */
47struct ep93xx_dma_m2p_client { 38struct ep93xx_dma_data {
48 char *name; 39 int port;
49 u8 flags; 40 enum dma_data_direction direction;
50 void *cookie; 41 const char *name;
51 void (*buffer_started)(void *cookie,
52 struct ep93xx_dma_buffer *buf);
53 void (*buffer_finished)(void *cookie,
54 struct ep93xx_dma_buffer *buf,
55 int bytes, int error);
56
57 /* private: Internal use only */
58 void *channel;
59}; 42};
60 43
61/* DMA M2P ports */
62#define EP93XX_DMA_M2P_PORT_I2S1 0x00
63#define EP93XX_DMA_M2P_PORT_I2S2 0x01
64#define EP93XX_DMA_M2P_PORT_AAC1 0x02
65#define EP93XX_DMA_M2P_PORT_AAC2 0x03
66#define EP93XX_DMA_M2P_PORT_AAC3 0x04
67#define EP93XX_DMA_M2P_PORT_I2S3 0x05
68#define EP93XX_DMA_M2P_PORT_UART1 0x06
69#define EP93XX_DMA_M2P_PORT_UART2 0x07
70#define EP93XX_DMA_M2P_PORT_UART3 0x08
71#define EP93XX_DMA_M2P_PORT_IRDA 0x09
72#define EP93XX_DMA_M2P_PORT_MASK 0x0f
73
74/* DMA M2P client flags */
75#define EP93XX_DMA_M2P_TX 0x00 /* Memory to peripheral */
76#define EP93XX_DMA_M2P_RX 0x10 /* Peripheral to memory */
77
78/*
79 * DMA M2P client error handling flags. See the EP93xx users guide
80 * documentation on the DMA M2P CONTROL register for more details
81 */
82#define EP93XX_DMA_M2P_ABORT_ON_ERROR 0x20 /* Abort on peripheral error */
83#define EP93XX_DMA_M2P_IGNORE_ERROR 0x40 /* Ignore peripheral errors */
84#define EP93XX_DMA_M2P_ERROR_MASK 0x60 /* Mask of error bits */
85
86/** 44/**
87 * ep93xx_dma_m2p_client_register - Register a client with the DMA M2P 45 * struct ep93xx_dma_chan_data - platform specific data for a DMA channel
88 * subsystem 46 * @name: name of the channel, used for getting the right clock for the channel
89 * 47 * @base: mapped registers
90 * @m2p: Client information to register 48 * @irq: interrupt number used by this channel
91 * returns 0 on success
92 *
93 * The DMA M2P subsystem allocates a channel and an interrupt line for the DMA
94 * client
95 */ 49 */
96int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p); 50struct ep93xx_dma_chan_data {
51 const char *name;
52 void __iomem *base;
53 int irq;
54};
97 55
98/** 56/**
99 * ep93xx_dma_m2p_client_unregister - Unregister a client from the DMA M2P 57 * struct ep93xx_dma_platform_data - platform data for the dmaengine driver
100 * subsystem 58 * @channels: array of channels which are passed to the driver
101 * 59 * @num_channels: number of channels in the array
102 * @m2p: Client to unregister
103 * 60 *
104 * Any transfers currently in progress will be completed in hardware, but 61 * This structure is passed to the DMA engine driver via platform data. For
105 * ignored in software. 62 * M2P channels, contract is that even channels are for TX and odd for RX.
63 * There is no requirement for the M2M channels.
106 */ 64 */
107void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *m2p); 65struct ep93xx_dma_platform_data {
66 struct ep93xx_dma_chan_data *channels;
67 size_t num_channels;
68};
108 69
109/** 70static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan)
110 * ep93xx_dma_m2p_submit - Submit a DMA M2P transfer 71{
111 * 72 return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p");
112 * @m2p: DMA Client to submit the transfer on 73}
113 * @buf: DMA Buffer to submit
114 *
115 * If the current or next transfer positions are free on the M2P client then
116 * the transfer is started immediately. If not, the transfer is added to the
117 * list of pending transfers. This function must not be called from the
118 * buffer_finished callback for an M2P channel.
119 *
120 */
121void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *m2p,
122 struct ep93xx_dma_buffer *buf);
123 74
124/** 75/**
125 * ep93xx_dma_m2p_submit_recursive - Put a DMA transfer on the pending list 76 * ep93xx_dma_chan_direction - returns direction the channel can be used
126 * for an M2P channel 77 * @chan: channel
127 * 78 *
128 * @m2p: DMA Client to submit the transfer on 79 * This function can be used in filter functions to find out whether the
129 * @buf: DMA Buffer to submit 80 * channel supports given DMA direction. Only M2P channels have such
130 * 81 * limitation, for M2M channels the direction is configurable.
131 * This function must only be called from the buffer_finished callback for an
132 * M2P channel. It is commonly used to add the next transfer in a chained list
133 * of DMA transfers.
134 */ 82 */
135void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *m2p, 83static inline enum dma_data_direction
136 struct ep93xx_dma_buffer *buf); 84ep93xx_dma_chan_direction(struct dma_chan *chan)
85{
86 if (!ep93xx_dma_chan_is_m2p(chan))
87 return DMA_NONE;
137 88
138/** 89 /* even channels are for TX, odd for RX */
139 * ep93xx_dma_m2p_flush - Flush all pending transfers on a DMA M2P client 90 return (chan->chan_id % 2 == 0) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
140 * 91}
141 * @m2p: DMA client to flush transfers on
142 *
143 * Any transfers currently in progress will be completed in hardware, but
144 * ignored in software.
145 *
146 */
147void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *m2p);
148 92
149#endif /* __ASM_ARCH_DMA_H */ 93#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 9ac4d105509..c4a7b84ef06 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -98,6 +98,7 @@
98 98
99#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000) 99#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
100 100
101#define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000)
101#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000) 102#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)
102#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) 103#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
103#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) 104#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c)
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h b/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h
index 0a37961b345..9bb63ac13f0 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h
@@ -7,9 +7,11 @@ struct spi_device;
7 * struct ep93xx_spi_info - EP93xx specific SPI descriptor 7 * struct ep93xx_spi_info - EP93xx specific SPI descriptor
8 * @num_chipselect: number of chip selects on this board, must be 8 * @num_chipselect: number of chip selects on this board, must be
9 * at least one 9 * at least one
10 * @use_dma: use DMA for the transfers
10 */ 11 */
11struct ep93xx_spi_info { 12struct ep93xx_spi_info {
12 int num_chipselect; 13 int num_chipselect;
14 bool use_dma;
13}; 15};
14 16
15/** 17/**
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index 5a3ce024b59..4df842897ea 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -8,8 +8,6 @@
8#include <mach/ep93xx-regs.h> 8#include <mach/ep93xx-regs.h>
9#include <mach/platform.h> 9#include <mach/platform.h>
10 10
11#define pcibios_assign_all_busses() 0
12
13/* 11/*
14 * The EP93xx has two external crystal oscillators. To generate the 12 * The EP93xx has two external crystal oscillators. To generate the
15 * required high-frequency clocks, the processor uses two phase-locked- 13 * required high-frequency clocks, the processor uses two phase-locked-
diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
index 0eabec62cd9..f1397a13e76 100644
--- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h
+++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
@@ -6,7 +6,7 @@
6 * TS72xx memory map: 6 * TS72xx memory map:
7 * 7 *
8 * virt phys size 8 * virt phys size
9 * febff000 22000000 4K model number register 9 * febff000 22000000 4K model number register (bits 0-2)
10 * febfe000 22400000 4K options register 10 * febfe000 22400000 4K options register
11 * febfd000 22800000 4K options register #2 11 * febfd000 22800000 4K options register #2
12 * febf9000 10800000 4K TS-5620 RTC index register 12 * febf9000 10800000 4K TS-5620 RTC index register
@@ -20,6 +20,9 @@
20#define TS72XX_MODEL_TS7200 0x00 20#define TS72XX_MODEL_TS7200 0x00
21#define TS72XX_MODEL_TS7250 0x01 21#define TS72XX_MODEL_TS7250 0x01
22#define TS72XX_MODEL_TS7260 0x02 22#define TS72XX_MODEL_TS7260 0x02
23#define TS72XX_MODEL_TS7300 0x03
24#define TS72XX_MODEL_TS7400 0x04
25#define TS72XX_MODEL_MASK 0x07
23 26
24 27
25#define TS72XX_OPTIONS_PHYS_BASE 0x22400000 28#define TS72XX_OPTIONS_PHYS_BASE 0x22400000
@@ -51,19 +54,34 @@
51 54
52#ifndef __ASSEMBLY__ 55#ifndef __ASSEMBLY__
53 56
57static inline int ts72xx_model(void)
58{
59 return __raw_readb(TS72XX_MODEL_VIRT_BASE) & TS72XX_MODEL_MASK;
60}
61
54static inline int board_is_ts7200(void) 62static inline int board_is_ts7200(void)
55{ 63{
56 return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7200; 64 return ts72xx_model() == TS72XX_MODEL_TS7200;
57} 65}
58 66
59static inline int board_is_ts7250(void) 67static inline int board_is_ts7250(void)
60{ 68{
61 return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7250; 69 return ts72xx_model() == TS72XX_MODEL_TS7250;
62} 70}
63 71
64static inline int board_is_ts7260(void) 72static inline int board_is_ts7260(void)
65{ 73{
66 return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7260; 74 return ts72xx_model() == TS72XX_MODEL_TS7260;
75}
76
77static inline int board_is_ts7300(void)
78{
79 return ts72xx_model() == TS72XX_MODEL_TS7300;
80}
81
82static inline int board_is_ts7400(void)
83{
84 return ts72xx_model() == TS72XX_MODEL_TS7400;
67} 85}
68 86
69static inline int is_max197_installed(void) 87static inline int is_max197_installed(void)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-08 14:13:33 -0400