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-rw-r--r--arch/arm/mach-davinci/Kconfig19
-rw-r--r--arch/arm/mach-davinci/Makefile3
-rw-r--r--arch/arm/mach-davinci/board-dm355-evm.c269
-rw-r--r--arch/arm/mach-davinci/board-dm355-leopard.c268
-rw-r--r--arch/arm/mach-davinci/dm355.c540
-rw-r--r--arch/arm/mach-davinci/include/mach/dm355.h23
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h2
7 files changed, 1123 insertions, 1 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0d8ad593a46..1c3ab40e2b6 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -10,6 +10,9 @@ comment "DaVinci Core Type"
10config ARCH_DAVINCI_DM644x 10config ARCH_DAVINCI_DM644x
11 bool "DaVinci 644x based system" 11 bool "DaVinci 644x based system"
12 12
13config ARCH_DAVINCI_DM355
14 bool "DaVinci 355 based system"
15
13comment "DaVinci Board Type" 16comment "DaVinci Board Type"
14 17
15config MACH_DAVINCI_EVM 18config MACH_DAVINCI_EVM
@@ -28,6 +31,22 @@ config MACH_SFFSDR
28 Say Y here to select the Lyrtech Small Form Factor 31 Say Y here to select the Lyrtech Small Form Factor
29 Software Defined Radio (SFFSDR) board. 32 Software Defined Radio (SFFSDR) board.
30 33
34config MACH_DAVINCI_DM355_EVM
35 bool "TI DM355 EVM"
36 default n
37 depends on ARCH_DAVINCI_DM355
38 help
39 Configure this option to specify the whether the board used
40 for development is a DM355 EVM
41
42config MACH_DM355_LEOPARD
43 bool "DM355 Leopard board"
44 default n
45 depends on ARCH_DAVINCI_DM355
46 help
47 Configure this option to specify the whether the board used
48 for development is a DM355 Leopard board.
49
31config DAVINCI_MUX 50config DAVINCI_MUX
32 bool "DAVINCI multiplexing support" 51 bool "DAVINCI multiplexing support"
33 depends on ARCH_DAVINCI 52 depends on ARCH_DAVINCI
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 2bb6ffa3faa..381c363d98a 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -12,7 +12,10 @@ obj-$(CONFIG_CP_INTC) += cp_intc.o
12 12
13# Chip specific 13# Chip specific
14obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o 14obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o
15obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o
15 16
16# Board specific 17# Board specific
17obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o 18obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
18obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o 19obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
20obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
21obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
new file mode 100644
index 00000000000..6af3c6c863a
--- /dev/null
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -0,0 +1,269 @@
1/*
2 * TI DaVinci EVM board support
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/dma-mapping.h>
15#include <linux/platform_device.h>
16#include <linux/mtd/mtd.h>
17#include <linux/mtd/partitions.h>
18#include <linux/mtd/nand.h>
19#include <linux/i2c.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/clk.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/eeprom.h>
25
26#include <asm/setup.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/flash.h>
31
32#include <mach/hardware.h>
33#include <mach/dm355.h>
34#include <mach/psc.h>
35#include <mach/common.h>
36#include <mach/i2c.h>
37#include <mach/serial.h>
38#include <mach/nand.h>
39
40#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
41#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
42
43/* NOTE: this is geared for the standard config, with a socketed
44 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
45 * swap chips, maybe with a different block size, partitioning may
46 * need to be changed.
47 */
48#define NAND_BLOCK_SIZE SZ_128K
49
50static struct mtd_partition davinci_nand_partitions[] = {
51 {
52 /* UBL (a few copies) plus U-Boot */
53 .name = "bootloader",
54 .offset = 0,
55 .size = 15 * NAND_BLOCK_SIZE,
56 .mask_flags = MTD_WRITEABLE, /* force read-only */
57 }, {
58 /* U-Boot environment */
59 .name = "params",
60 .offset = MTDPART_OFS_APPEND,
61 .size = 1 * NAND_BLOCK_SIZE,
62 .mask_flags = 0,
63 }, {
64 .name = "kernel",
65 .offset = MTDPART_OFS_APPEND,
66 .size = SZ_4M,
67 .mask_flags = 0,
68 }, {
69 .name = "filesystem1",
70 .offset = MTDPART_OFS_APPEND,
71 .size = SZ_512M,
72 .mask_flags = 0,
73 }, {
74 .name = "filesystem2",
75 .offset = MTDPART_OFS_APPEND,
76 .size = MTDPART_SIZ_FULL,
77 .mask_flags = 0,
78 }
79 /* two blocks with bad block table (and mirror) at the end */
80};
81
82static struct davinci_nand_pdata davinci_nand_data = {
83 .mask_chipsel = BIT(14),
84 .parts = davinci_nand_partitions,
85 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
86 .ecc_mode = NAND_ECC_HW_SYNDROME,
87 .options = NAND_USE_FLASH_BBT,
88};
89
90static struct resource davinci_nand_resources[] = {
91 {
92 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
93 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
94 .flags = IORESOURCE_MEM,
95 }, {
96 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
97 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
98 .flags = IORESOURCE_MEM,
99 },
100};
101
102static struct platform_device davinci_nand_device = {
103 .name = "davinci_nand",
104 .id = 0,
105
106 .num_resources = ARRAY_SIZE(davinci_nand_resources),
107 .resource = davinci_nand_resources,
108
109 .dev = {
110 .platform_data = &davinci_nand_data,
111 },
112};
113
114static struct davinci_i2c_platform_data i2c_pdata = {
115 .bus_freq = 400 /* kHz */,
116 .bus_delay = 0 /* usec */,
117};
118
119static int dm355evm_mmc_gpios = -EINVAL;
120
121static void dm355evm_mmcsd_gpios(unsigned gpio)
122{
123 gpio_request(gpio + 0, "mmc0_ro");
124 gpio_request(gpio + 1, "mmc0_cd");
125 gpio_request(gpio + 2, "mmc1_ro");
126 gpio_request(gpio + 3, "mmc1_cd");
127
128 /* we "know" these are input-only so we don't
129 * need to call gpio_direction_input()
130 */
131
132 dm355evm_mmc_gpios = gpio;
133}
134
135static struct i2c_board_info dm355evm_i2c_info[] = {
136 { I2C_BOARD_INFO("dm355evm_msp", 0x25),
137 .platform_data = dm355evm_mmcsd_gpios,
138 /* plus irq */ },
139 /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */
140 /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */
141};
142
143static void __init evm_init_i2c(void)
144{
145 davinci_init_i2c(&i2c_pdata);
146
147 gpio_request(5, "dm355evm_msp");
148 gpio_direction_input(5);
149 dm355evm_i2c_info[0].irq = gpio_to_irq(5);
150
151 i2c_register_board_info(1, dm355evm_i2c_info,
152 ARRAY_SIZE(dm355evm_i2c_info));
153}
154
155static struct resource dm355evm_dm9000_rsrc[] = {
156 {
157 /* addr */
158 .start = 0x04014000,
159 .end = 0x04014001,
160 .flags = IORESOURCE_MEM,
161 }, {
162 /* data */
163 .start = 0x04014002,
164 .end = 0x04014003,
165 .flags = IORESOURCE_MEM,
166 }, {
167 .flags = IORESOURCE_IRQ
168 | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */,
169 },
170};
171
172static struct platform_device dm355evm_dm9000 = {
173 .name = "dm9000",
174 .id = -1,
175 .resource = dm355evm_dm9000_rsrc,
176 .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc),
177};
178
179static struct platform_device *davinci_evm_devices[] __initdata = {
180 &dm355evm_dm9000,
181 &davinci_nand_device,
182};
183
184static struct davinci_uart_config uart_config __initdata = {
185 .enabled_uarts = (1 << 0),
186};
187
188static void __init dm355_evm_map_io(void)
189{
190 davinci_map_common_io();
191 dm355_init();
192}
193
194/* Don't connect anything to J10 unless you're only using USB host
195 * mode *and* have to do so with some kind of gender-bender. If
196 * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
197 * the ID pin won't need any help.
198 */
199#ifdef CONFIG_USB_MUSB_PERIPHERAL
200#define USB_ID_VALUE 0 /* ID pulled high; *should* float */
201#else
202#define USB_ID_VALUE 1 /* ID pulled low */
203#endif
204
205static struct spi_eeprom at25640a = {
206 .byte_len = SZ_64K / 8,
207 .name = "at25640a",
208 .page_size = 32,
209 .flags = EE_ADDR2,
210};
211
212static struct spi_board_info dm355_evm_spi_info[] __initconst = {
213 {
214 .modalias = "at25",
215 .platform_data = &at25640a,
216 .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */
217 .bus_num = 0,
218 .chip_select = 0,
219 .mode = SPI_MODE_0,
220 },
221};
222
223static __init void dm355_evm_init(void)
224{
225 struct clk *aemif;
226
227 gpio_request(1, "dm9000");
228 gpio_direction_input(1);
229 dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1);
230
231 aemif = clk_get(&dm355evm_dm9000.dev, "aemif");
232 if (IS_ERR(aemif))
233 WARN("%s: unable to get AEMIF clock\n", __func__);
234 else
235 clk_enable(aemif);
236
237 platform_add_devices(davinci_evm_devices,
238 ARRAY_SIZE(davinci_evm_devices));
239 evm_init_i2c();
240 davinci_serial_init(&uart_config);
241
242 /* NOTE: NAND flash timings set by the UBL are slower than
243 * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
244 * but could be 0x0400008c for about 25% faster page reads.
245 */
246
247 gpio_request(2, "usb_id_toggle");
248 gpio_direction_output(2, USB_ID_VALUE);
249 /* irlml6401 switches over 1A in under 8 msec */
250 setup_usb(500, 8);
251
252 dm355_init_spi0(BIT(0), dm355_evm_spi_info,
253 ARRAY_SIZE(dm355_evm_spi_info));
254}
255
256static __init void dm355_evm_irq_init(void)
257{
258 davinci_irq_init();
259}
260
261MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
262 .phys_io = IO_PHYS,
263 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
264 .boot_params = (0x80000100),
265 .map_io = dm355_evm_map_io,
266 .init_irq = dm355_evm_irq_init,
267 .timer = &davinci_timer,
268 .init_machine = dm355_evm_init,
269MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
new file mode 100644
index 00000000000..22f16f38a0b
--- /dev/null
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -0,0 +1,268 @@
1/*
2 * DM355 leopard board support
3 *
4 * Based on board-dm355-evm.c
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/dma-mapping.h>
14#include <linux/platform_device.h>
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/partitions.h>
17#include <linux/mtd/nand.h>
18#include <linux/i2c.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/clk.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/eeprom.h>
24
25#include <asm/setup.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/flash.h>
30
31#include <mach/hardware.h>
32#include <mach/dm355.h>
33#include <mach/psc.h>
34#include <mach/common.h>
35#include <mach/i2c.h>
36#include <mach/serial.h>
37#include <mach/nand.h>
38
39#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
40#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
41
42/* NOTE: this is geared for the standard config, with a socketed
43 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
44 * swap chips, maybe with a different block size, partitioning may
45 * need to be changed.
46 */
47#define NAND_BLOCK_SIZE SZ_128K
48
49static struct mtd_partition davinci_nand_partitions[] = {
50 {
51 /* UBL (a few copies) plus U-Boot */
52 .name = "bootloader",
53 .offset = 0,
54 .size = 15 * NAND_BLOCK_SIZE,
55 .mask_flags = MTD_WRITEABLE, /* force read-only */
56 }, {
57 /* U-Boot environment */
58 .name = "params",
59 .offset = MTDPART_OFS_APPEND,
60 .size = 1 * NAND_BLOCK_SIZE,
61 .mask_flags = 0,
62 }, {
63 .name = "kernel",
64 .offset = MTDPART_OFS_APPEND,
65 .size = SZ_4M,
66 .mask_flags = 0,
67 }, {
68 .name = "filesystem1",
69 .offset = MTDPART_OFS_APPEND,
70 .size = SZ_512M,
71 .mask_flags = 0,
72 }, {
73 .name = "filesystem2",
74 .offset = MTDPART_OFS_APPEND,
75 .size = MTDPART_SIZ_FULL,
76 .mask_flags = 0,
77 }
78 /* two blocks with bad block table (and mirror) at the end */
79};
80
81static struct davinci_nand_pdata davinci_nand_data = {
82 .mask_chipsel = BIT(14),
83 .parts = davinci_nand_partitions,
84 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
85 .ecc_mode = NAND_ECC_HW_SYNDROME,
86 .options = NAND_USE_FLASH_BBT,
87};
88
89static struct resource davinci_nand_resources[] = {
90 {
91 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
92 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
93 .flags = IORESOURCE_MEM,
94 }, {
95 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
96 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
97 .flags = IORESOURCE_MEM,
98 },
99};
100
101static struct platform_device davinci_nand_device = {
102 .name = "davinci_nand",
103 .id = 0,
104
105 .num_resources = ARRAY_SIZE(davinci_nand_resources),
106 .resource = davinci_nand_resources,
107
108 .dev = {
109 .platform_data = &davinci_nand_data,
110 },
111};
112
113static struct davinci_i2c_platform_data i2c_pdata = {
114 .bus_freq = 400 /* kHz */,
115 .bus_delay = 0 /* usec */,
116};
117
118static int leopard_mmc_gpio = -EINVAL;
119
120static void dm355leopard_mmcsd_gpios(unsigned gpio)
121{
122 gpio_request(gpio + 0, "mmc0_ro");
123 gpio_request(gpio + 1, "mmc0_cd");
124 gpio_request(gpio + 2, "mmc1_ro");
125 gpio_request(gpio + 3, "mmc1_cd");
126
127 /* we "know" these are input-only so we don't
128 * need to call gpio_direction_input()
129 */
130
131 leopard_mmc_gpio = gpio;
132}
133
134static struct i2c_board_info dm355leopard_i2c_info[] = {
135 { I2C_BOARD_INFO("dm355leopard_msp", 0x25),
136 .platform_data = dm355leopard_mmcsd_gpios,
137 /* plus irq */ },
138 /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */
139 /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */
140};
141
142static void __init leopard_init_i2c(void)
143{
144 davinci_init_i2c(&i2c_pdata);
145
146 gpio_request(5, "dm355leopard_msp");
147 gpio_direction_input(5);
148 dm355leopard_i2c_info[0].irq = gpio_to_irq(5);
149
150 i2c_register_board_info(1, dm355leopard_i2c_info,
151 ARRAY_SIZE(dm355leopard_i2c_info));
152}
153
154static struct resource dm355leopard_dm9000_rsrc[] = {
155 {
156 /* addr */
157 .start = 0x04000000,
158 .end = 0x04000001,
159 .flags = IORESOURCE_MEM,
160 }, {
161 /* data */
162 .start = 0x04000016,
163 .end = 0x04000017,
164 .flags = IORESOURCE_MEM,
165 }, {
166 .flags = IORESOURCE_IRQ
167 | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */,
168 },
169};
170
171static struct platform_device dm355leopard_dm9000 = {
172 .name = "dm9000",
173 .id = -1,
174 .resource = dm355leopard_dm9000_rsrc,
175 .num_resources = ARRAY_SIZE(dm355leopard_dm9000_rsrc),
176};
177
178static struct platform_device *davinci_leopard_devices[] __initdata = {
179 &dm355leopard_dm9000,
180 &davinci_nand_device,
181};
182
183static struct davinci_uart_config uart_config __initdata = {
184 .enabled_uarts = (1 << 0),
185};
186
187static void __init dm355_leopard_map_io(void)
188{
189 davinci_map_common_io();
190 dm355_init();
191}
192
193/* Don't connect anything to J10 unless you're only using USB host
194 * mode *and* have to do so with some kind of gender-bender. If
195 * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
196 * the ID pin won't need any help.
197 */
198#ifdef CONFIG_USB_MUSB_PERIPHERAL
199#define USB_ID_VALUE 0 /* ID pulled high; *should* float */
200#else
201#define USB_ID_VALUE 1 /* ID pulled low */
202#endif
203
204static struct spi_eeprom at25640a = {
205 .byte_len = SZ_64K / 8,
206 .name = "at25640a",
207 .page_size = 32,
208 .flags = EE_ADDR2,
209};
210
211static struct spi_board_info dm355_leopard_spi_info[] __initconst = {
212 {
213 .modalias = "at25",
214 .platform_data = &at25640a,
215 .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */
216 .bus_num = 0,
217 .chip_select = 0,
218 .mode = SPI_MODE_0,
219 },
220};
221
222static __init void dm355_leopard_init(void)
223{
224 struct clk *aemif;
225
226 gpio_request(9, "dm9000");
227 gpio_direction_input(9);
228 dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9);
229
230 aemif = clk_get(&dm355leopard_dm9000.dev, "aemif");
231 if (IS_ERR(aemif))
232 WARN("%s: unable to get AEMIF clock\n", __func__);
233 else
234 clk_enable(aemif);
235
236 platform_add_devices(davinci_leopard_devices,
237 ARRAY_SIZE(davinci_leopard_devices));
238 leopard_init_i2c();
239 davinci_serial_init(&uart_config);
240
241 /* NOTE: NAND flash timings set by the UBL are slower than
242 * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
243 * but could be 0x0400008c for about 25% faster page reads.
244 */
245
246 gpio_request(2, "usb_id_toggle");
247 gpio_direction_output(2, USB_ID_VALUE);
248 /* irlml6401 switches over 1A in under 8 msec */
249 setup_usb(500, 8);
250
251 dm355_init_spi0(BIT(0), dm355_leopard_spi_info,
252 ARRAY_SIZE(dm355_leopard_spi_info));
253}
254
255static __init void dm355_leopard_irq_init(void)
256{
257 davinci_irq_init();
258}
259
260MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
261 .phys_io = IO_PHYS,
262 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
263 .boot_params = (0x80000100),
264 .map_io = dm355_leopard_map_io,
265 .init_irq = dm355_leopard_irq_init,
266 .timer = &davinci_timer,
267 .init_machine = dm355_leopard_init,
268MACHINE_END
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
new file mode 100644
index 00000000000..c02115f1eb9
--- /dev/null
+++ b/arch/arm/mach-davinci/dm355.c
@@ -0,0 +1,540 @@
1/*
2 * TI DaVinci DM355 chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16
17#include <linux/spi/spi.h>
18
19#include <mach/dm355.h>
20#include <mach/clock.h>
21#include <mach/cputype.h>
22#include <mach/edma.h>
23#include <mach/psc.h>
24#include <mach/mux.h>
25#include <mach/irqs.h>
26
27#include "clock.h"
28#include "mux.h"
29
30/*
31 * Device specific clocks
32 */
33#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
34
35static struct pll_data pll1_data = {
36 .num = 1,
37 .phys_base = DAVINCI_PLL1_BASE,
38 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
39};
40
41static struct pll_data pll2_data = {
42 .num = 2,
43 .phys_base = DAVINCI_PLL2_BASE,
44 .flags = PLL_HAS_PREDIV,
45};
46
47static struct clk ref_clk = {
48 .name = "ref_clk",
49 /* FIXME -- crystal rate is board-specific */
50 .rate = DM355_REF_FREQ,
51};
52
53static struct clk pll1_clk = {
54 .name = "pll1",
55 .parent = &ref_clk,
56 .flags = CLK_PLL,
57 .pll_data = &pll1_data,
58};
59
60static struct clk pll1_aux_clk = {
61 .name = "pll1_aux_clk",
62 .parent = &pll1_clk,
63 .flags = CLK_PLL | PRE_PLL,
64};
65
66static struct clk pll1_sysclk1 = {
67 .name = "pll1_sysclk1",
68 .parent = &pll1_clk,
69 .flags = CLK_PLL,
70 .div_reg = PLLDIV1,
71};
72
73static struct clk pll1_sysclk2 = {
74 .name = "pll1_sysclk2",
75 .parent = &pll1_clk,
76 .flags = CLK_PLL,
77 .div_reg = PLLDIV2,
78};
79
80static struct clk pll1_sysclk3 = {
81 .name = "pll1_sysclk3",
82 .parent = &pll1_clk,
83 .flags = CLK_PLL,
84 .div_reg = PLLDIV3,
85};
86
87static struct clk pll1_sysclk4 = {
88 .name = "pll1_sysclk4",
89 .parent = &pll1_clk,
90 .flags = CLK_PLL,
91 .div_reg = PLLDIV4,
92};
93
94static struct clk pll1_sysclkbp = {
95 .name = "pll1_sysclkbp",
96 .parent = &pll1_clk,
97 .flags = CLK_PLL | PRE_PLL,
98 .div_reg = BPDIV
99};
100
101static struct clk vpss_dac_clk = {
102 .name = "vpss_dac",
103 .parent = &pll1_sysclk3,
104 .lpsc = DM355_LPSC_VPSS_DAC,
105};
106
107static struct clk vpss_master_clk = {
108 .name = "vpss_master",
109 .parent = &pll1_sysclk4,
110 .lpsc = DAVINCI_LPSC_VPSSMSTR,
111 .flags = CLK_PSC,
112};
113
114static struct clk vpss_slave_clk = {
115 .name = "vpss_slave",
116 .parent = &pll1_sysclk4,
117 .lpsc = DAVINCI_LPSC_VPSSSLV,
118};
119
120
121static struct clk clkout1_clk = {
122 .name = "clkout1",
123 .parent = &pll1_aux_clk,
124 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
125};
126
127static struct clk clkout2_clk = {
128 .name = "clkout2",
129 .parent = &pll1_sysclkbp,
130};
131
132static struct clk pll2_clk = {
133 .name = "pll2",
134 .parent = &ref_clk,
135 .flags = CLK_PLL,
136 .pll_data = &pll2_data,
137};
138
139static struct clk pll2_sysclk1 = {
140 .name = "pll2_sysclk1",
141 .parent = &pll2_clk,
142 .flags = CLK_PLL,
143 .div_reg = PLLDIV1,
144};
145
146static struct clk pll2_sysclkbp = {
147 .name = "pll2_sysclkbp",
148 .parent = &pll2_clk,
149 .flags = CLK_PLL | PRE_PLL,
150 .div_reg = BPDIV
151};
152
153static struct clk clkout3_clk = {
154 .name = "clkout3",
155 .parent = &pll2_sysclkbp,
156 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
157};
158
159static struct clk arm_clk = {
160 .name = "arm_clk",
161 .parent = &pll1_sysclk1,
162 .lpsc = DAVINCI_LPSC_ARM,
163 .flags = ALWAYS_ENABLED,
164};
165
166/*
167 * NOT LISTED below, and not touched by Linux
168 * - in SyncReset state by default
169 * .lpsc = DAVINCI_LPSC_TPCC,
170 * .lpsc = DAVINCI_LPSC_TPTC0,
171 * .lpsc = DAVINCI_LPSC_TPTC1,
172 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
173 * .lpsc = DAVINCI_LPSC_MEMSTICK,
174 * - in Enabled state by default
175 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
176 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
177 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
178 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
179 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
180 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
181 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
182 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
183 */
184
185static struct clk mjcp_clk = {
186 .name = "mjcp",
187 .parent = &pll1_sysclk1,
188 .lpsc = DAVINCI_LPSC_IMCOP,
189};
190
191static struct clk uart0_clk = {
192 .name = "uart0",
193 .parent = &pll1_aux_clk,
194 .lpsc = DAVINCI_LPSC_UART0,
195};
196
197static struct clk uart1_clk = {
198 .name = "uart1",
199 .parent = &pll1_aux_clk,
200 .lpsc = DAVINCI_LPSC_UART1,
201};
202
203static struct clk uart2_clk = {
204 .name = "uart2",
205 .parent = &pll1_sysclk2,
206 .lpsc = DAVINCI_LPSC_UART2,
207};
208
209static struct clk i2c_clk = {
210 .name = "i2c",
211 .parent = &pll1_aux_clk,
212 .lpsc = DAVINCI_LPSC_I2C,
213};
214
215static struct clk asp0_clk = {
216 .name = "asp0",
217 .parent = &pll1_sysclk2,
218 .lpsc = DAVINCI_LPSC_McBSP,
219};
220
221static struct clk asp1_clk = {
222 .name = "asp1",
223 .parent = &pll1_sysclk2,
224 .lpsc = DM355_LPSC_McBSP1,
225};
226
227static struct clk mmcsd0_clk = {
228 .name = "mmcsd0",
229 .parent = &pll1_sysclk2,
230 .lpsc = DAVINCI_LPSC_MMC_SD,
231};
232
233static struct clk mmcsd1_clk = {
234 .name = "mmcsd1",
235 .parent = &pll1_sysclk2,
236 .lpsc = DM355_LPSC_MMC_SD1,
237};
238
239static struct clk spi0_clk = {
240 .name = "spi0",
241 .parent = &pll1_sysclk2,
242 .lpsc = DAVINCI_LPSC_SPI,
243};
244
245static struct clk spi1_clk = {
246 .name = "spi1",
247 .parent = &pll1_sysclk2,
248 .lpsc = DM355_LPSC_SPI1,
249};
250
251static struct clk spi2_clk = {
252 .name = "spi2",
253 .parent = &pll1_sysclk2,
254 .lpsc = DM355_LPSC_SPI2,
255};
256
257static struct clk gpio_clk = {
258 .name = "gpio",
259 .parent = &pll1_sysclk2,
260 .lpsc = DAVINCI_LPSC_GPIO,
261};
262
263static struct clk aemif_clk = {
264 .name = "aemif",
265 .parent = &pll1_sysclk2,
266 .lpsc = DAVINCI_LPSC_AEMIF,
267};
268
269static struct clk pwm0_clk = {
270 .name = "pwm0",
271 .parent = &pll1_aux_clk,
272 .lpsc = DAVINCI_LPSC_PWM0,
273};
274
275static struct clk pwm1_clk = {
276 .name = "pwm1",
277 .parent = &pll1_aux_clk,
278 .lpsc = DAVINCI_LPSC_PWM1,
279};
280
281static struct clk pwm2_clk = {
282 .name = "pwm2",
283 .parent = &pll1_aux_clk,
284 .lpsc = DAVINCI_LPSC_PWM2,
285};
286
287static struct clk pwm3_clk = {
288 .name = "pwm3",
289 .parent = &pll1_aux_clk,
290 .lpsc = DM355_LPSC_PWM3,
291};
292
293static struct clk timer0_clk = {
294 .name = "timer0",
295 .parent = &pll1_aux_clk,
296 .lpsc = DAVINCI_LPSC_TIMER0,
297};
298
299static struct clk timer1_clk = {
300 .name = "timer1",
301 .parent = &pll1_aux_clk,
302 .lpsc = DAVINCI_LPSC_TIMER1,
303};
304
305static struct clk timer2_clk = {
306 .name = "timer2",
307 .parent = &pll1_aux_clk,
308 .lpsc = DAVINCI_LPSC_TIMER2,
309 .usecount = 1, /* REVISIT: why cant' this be disabled? */
310};
311
312static struct clk timer3_clk = {
313 .name = "timer3",
314 .parent = &pll1_aux_clk,
315 .lpsc = DM355_LPSC_TIMER3,
316};
317
318static struct clk rto_clk = {
319 .name = "rto",
320 .parent = &pll1_aux_clk,
321 .lpsc = DM355_LPSC_RTO,
322};
323
324static struct clk usb_clk = {
325 .name = "usb",
326 .parent = &pll1_sysclk2,
327 .lpsc = DAVINCI_LPSC_USB,
328};
329
330static struct davinci_clk dm355_clks[] = {
331 CLK(NULL, "ref", &ref_clk),
332 CLK(NULL, "pll1", &pll1_clk),
333 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
334 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
335 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
336 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
337 CLK(NULL, "pll1_aux", &pll1_aux_clk),
338 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
339 CLK(NULL, "vpss_dac", &vpss_dac_clk),
340 CLK(NULL, "vpss_master", &vpss_master_clk),
341 CLK(NULL, "vpss_slave", &vpss_slave_clk),
342 CLK(NULL, "clkout1", &clkout1_clk),
343 CLK(NULL, "clkout2", &clkout2_clk),
344 CLK(NULL, "pll2", &pll2_clk),
345 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
346 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
347 CLK(NULL, "clkout3", &clkout3_clk),
348 CLK(NULL, "arm", &arm_clk),
349 CLK(NULL, "mjcp", &mjcp_clk),
350 CLK(NULL, "uart0", &uart0_clk),
351 CLK(NULL, "uart1", &uart1_clk),
352 CLK(NULL, "uart2", &uart2_clk),
353 CLK("i2c_davinci.1", NULL, &i2c_clk),
354 CLK("soc-audio.0", NULL, &asp0_clk),
355 CLK("soc-audio.1", NULL, &asp1_clk),
356 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
357 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
358 CLK(NULL, "spi0", &spi0_clk),
359 CLK(NULL, "spi1", &spi1_clk),
360 CLK(NULL, "spi2", &spi2_clk),
361 CLK(NULL, "gpio", &gpio_clk),
362 CLK(NULL, "aemif", &aemif_clk),
363 CLK(NULL, "pwm0", &pwm0_clk),
364 CLK(NULL, "pwm1", &pwm1_clk),
365 CLK(NULL, "pwm2", &pwm2_clk),
366 CLK(NULL, "pwm3", &pwm3_clk),
367 CLK(NULL, "timer0", &timer0_clk),
368 CLK(NULL, "timer1", &timer1_clk),
369 CLK("watchdog", NULL, &timer2_clk),
370 CLK(NULL, "timer3", &timer3_clk),
371 CLK(NULL, "rto", &rto_clk),
372 CLK(NULL, "usb", &usb_clk),
373 CLK(NULL, NULL, NULL),
374};
375
376/*----------------------------------------------------------------------*/
377
378static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
379
380static struct resource dm355_spi0_resources[] = {
381 {
382 .start = 0x01c66000,
383 .end = 0x01c667ff,
384 .flags = IORESOURCE_MEM,
385 },
386 {
387 .start = IRQ_DM355_SPINT0_1,
388 .flags = IORESOURCE_IRQ,
389 },
390 /* Not yet used, so not included:
391 * IORESOURCE_IRQ:
392 * - IRQ_DM355_SPINT0_0
393 * IORESOURCE_DMA:
394 * - DAVINCI_DMA_SPI_SPIX
395 * - DAVINCI_DMA_SPI_SPIR
396 */
397};
398
399static struct platform_device dm355_spi0_device = {
400 .name = "spi_davinci",
401 .id = 0,
402 .dev = {
403 .dma_mask = &dm355_spi0_dma_mask,
404 .coherent_dma_mask = DMA_BIT_MASK(32),
405 },
406 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
407 .resource = dm355_spi0_resources,
408};
409
410void __init dm355_init_spi0(unsigned chipselect_mask,
411 struct spi_board_info *info, unsigned len)
412{
413 /* for now, assume we need MISO */
414 davinci_cfg_reg(DM355_SPI0_SDI);
415
416 /* not all slaves will be wired up */
417 if (chipselect_mask & BIT(0))
418 davinci_cfg_reg(DM355_SPI0_SDENA0);
419 if (chipselect_mask & BIT(1))
420 davinci_cfg_reg(DM355_SPI0_SDENA1);
421
422 spi_register_board_info(info, len);
423
424 platform_device_register(&dm355_spi0_device);
425}
426
427/*----------------------------------------------------------------------*/
428
429/*
430 * Device specific mux setup
431 *
432 * soc description mux mode mode mux dbg
433 * reg offset mask mode
434 */
435static const struct mux_config dm355_pins[] = {
436MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
437
438MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
439MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
440MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
441MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
442MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
443MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
444
445MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
446MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
447
448MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
449MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
450MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
451MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
452MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
453MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
454
455MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
456MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
457MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
458
459INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
460INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
461INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
462
463EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
464EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
465EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
466};
467
468/*----------------------------------------------------------------------*/
469
470static const s8 dma_chan_dm355_no_event[] = {
471 12, 13, 24, 56, 57,
472 58, 59, 60, 61, 62,
473 63,
474 -1
475};
476
477static struct edma_soc_info dm355_edma_info = {
478 .n_channel = 64,
479 .n_region = 4,
480 .n_slot = 128,
481 .n_tc = 2,
482 .noevent = dma_chan_dm355_no_event,
483};
484
485static struct resource edma_resources[] = {
486 {
487 .name = "edma_cc",
488 .start = 0x01c00000,
489 .end = 0x01c00000 + SZ_64K - 1,
490 .flags = IORESOURCE_MEM,
491 },
492 {
493 .name = "edma_tc0",
494 .start = 0x01c10000,
495 .end = 0x01c10000 + SZ_1K - 1,
496 .flags = IORESOURCE_MEM,
497 },
498 {
499 .name = "edma_tc1",
500 .start = 0x01c10400,
501 .end = 0x01c10400 + SZ_1K - 1,
502 .flags = IORESOURCE_MEM,
503 },
504 {
505 .start = IRQ_CCINT0,
506 .flags = IORESOURCE_IRQ,
507 },
508 {
509 .start = IRQ_CCERRINT,
510 .flags = IORESOURCE_IRQ,
511 },
512 /* not using (or muxing) TC*_ERR */
513};
514
515static struct platform_device dm355_edma_device = {
516 .name = "edma",
517 .id = -1,
518 .dev.platform_data = &dm355_edma_info,
519 .num_resources = ARRAY_SIZE(edma_resources),
520 .resource = edma_resources,
521};
522
523/*----------------------------------------------------------------------*/
524
525void __init dm355_init(void)
526{
527 davinci_clk_init(dm355_clks);
528 davinci_mux_register(dm355_pins, ARRAY_SIZE(dm355_pins));;
529}
530
531static int __init dm355_init_devices(void)
532{
533 if (!cpu_is_davinci_dm355())
534 return 0;
535
536 davinci_cfg_reg(DM355_INT_EDMA_CC);
537 platform_device_register(&dm355_edma_device);
538 return 0;
539}
540postcore_initcall(dm355_init_devices);
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
new file mode 100644
index 00000000000..f7100b65899
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm355.h
@@ -0,0 +1,23 @@
1/*
2 * Chip specific defines for DM355 SoC
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ASM_ARCH_DM355_H
12#define __ASM_ARCH_DM355_H
13
14#include <mach/hardware.h>
15
16void __init dm355_init(void);
17
18struct spi_board_info;
19
20void dm355_init_spi0(unsigned chipselect_mask,
21 struct spi_board_info *info, unsigned len);
22
23#endif /* __ASM_ARCH_DM355_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 632847d74a1..761ab2b483a 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -18,7 +18,7 @@
18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
20 20
21#define DM355_UART2_BASE (IO_PHYS + 0x206000) 21#define DM355_UART2_BASE (IO_PHYS + 0x206000)
22 22
23/* DaVinci UART register offsets */ 23/* DaVinci UART register offsets */
24#define UART_DAVINCI_PWREMU 0x0c 24#define UART_DAVINCI_PWREMU 0x0c
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 17:28:41 -0400