6 files changed, 78 insertions, 102 deletions

diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h
deleted file mode 100644
index 14a50488718..00000000000
--- a/arch/arm/mach-davinci/include/mach/clkdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-struct clk;
-
-static inline int __clk_get(struct clk *clk)
-{
-        return 1;
-}
-
-static inline void __clk_put(struct clk *clk)
-{
-}
-
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index ad64da713fc..eaca7d8b9d6 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -57,6 +57,7 @@ extern unsigned int da850_max_speed;
 #define DA8XX_SYSCFG1_BASE      (IO_PHYS + 0x22C000)
 #define DA8XX_SYSCFG1_VIRT(x)   (da8xx_syscfg1_base + (x))
 #define DA8XX_DEEPSLEEP_REG     0x8
+#define DA8XX_PWRDN_REG         0x18
 
 #define DA8XX_PSC0_BASE         0x01c10000
 #define DA8XX_PLL0_BASE         0x01c11000
@@ -89,6 +90,7 @@ int da850_register_cpufreq(char *async_clk);
 int da8xx_register_cpuidle(void);
 void __iomem * __init da8xx_get_mem_ctlr(void);
 int da850_register_pm(struct platform_device *pdev);
+int __init da850_register_sata(unsigned long refclkpn);
 
 extern struct platform_device da8xx_serial_device;
 extern struct emac_platform_data da8xx_emac_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 7a27f3f1391..2a00fe5ac25 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -15,7 +15,6 @@
 #include <mach/asp.h>
 #include <linux/i2c.h>
 #include <linux/videodev2.h>
-#include <linux/clk.h>
 #include <linux/davinci_emac.h>
 
 #define DM646X_EMAC_BASE                (0x01C80000)
@@ -31,7 +30,6 @@
 void __init dm646x_init(void);
 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
-void __init dm646x_board_setup_refclk(struct clk *clk);
 int __init dm646x_init_edma(struct edma_rsv_info *rsv);
 
 void dm646x_video_init(void);
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index fbdebc7cb40..e14c0dc0e12 100644
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -46,6 +46,3 @@
 #endif
 1002:
                 .endm
-
-                .macro  irq_prio_table
-                .endm
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 491249ef209..78731944a70 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -41,11 +41,4 @@
  */
 #define CONSISTENT_DMA_SIZE (14<<20)
 
-/*
- * Restrict DMA-able region to workaround silicon bug.  The bug
- * restricts buffers available for DMA to video hardware to be
- * below 128M
- */
-#define ARM_DMA_ZONE_SIZE       SZ_128M
-
 #endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index a47e6f29206..fa59c097223 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -30,47 +30,47 @@
 #define DAVINCI_PWR_SLEEP_CNTRL_BASE    0x01C41000
 
 /* Power and Sleep Controller (PSC) Domains */
-#define DAVINCI_GPSC_ARMDOMAIN      0
-#define DAVINCI_GPSC_DSPDOMAIN      1
+#define DAVINCI_GPSC_ARMDOMAIN          0
+#define DAVINCI_GPSC_DSPDOMAIN          1
 
-#define DAVINCI_LPSC_VPSSMSTR       0
-#define DAVINCI_LPSC_VPSSSLV        1
-#define DAVINCI_LPSC_TPCC           2
-#define DAVINCI_LPSC_TPTC0          3
-#define DAVINCI_LPSC_TPTC1          4
-#define DAVINCI_LPSC_EMAC           5
-#define DAVINCI_LPSC_EMAC_WRAPPER   6
-#define DAVINCI_LPSC_USB            9
-#define DAVINCI_LPSC_ATA            10
-#define DAVINCI_LPSC_VLYNQ          11
-#define DAVINCI_LPSC_UHPI           12
-#define DAVINCI_LPSC_DDR_EMIF       13
-#define DAVINCI_LPSC_AEMIF          14
-#define DAVINCI_LPSC_MMC_SD         15
-#define DAVINCI_LPSC_McBSP          17
-#define DAVINCI_LPSC_I2C            18
-#define DAVINCI_LPSC_UART0          19
-#define DAVINCI_LPSC_UART1          20
-#define DAVINCI_LPSC_UART2          21
-#define DAVINCI_LPSC_SPI            22
-#define DAVINCI_LPSC_PWM0           23
-#define DAVINCI_LPSC_PWM1           24
-#define DAVINCI_LPSC_PWM2           25
-#define DAVINCI_LPSC_GPIO           26
-#define DAVINCI_LPSC_TIMER0         27
-#define DAVINCI_LPSC_TIMER1         28
-#define DAVINCI_LPSC_TIMER2         29
-#define DAVINCI_LPSC_SYSTEM_SUBSYS  30
-#define DAVINCI_LPSC_ARM            31
-#define DAVINCI_LPSC_SCR2           32
-#define DAVINCI_LPSC_SCR3           33
-#define DAVINCI_LPSC_SCR4           34
-#define DAVINCI_LPSC_CROSSBAR       35
-#define DAVINCI_LPSC_CFG27          36
-#define DAVINCI_LPSC_CFG3           37
-#define DAVINCI_LPSC_CFG5           38
-#define DAVINCI_LPSC_GEM            39
-#define DAVINCI_LPSC_IMCOP          40
+#define DAVINCI_LPSC_VPSSMSTR           0
+#define DAVINCI_LPSC_VPSSSLV            1
+#define DAVINCI_LPSC_TPCC               2
+#define DAVINCI_LPSC_TPTC0              3
+#define DAVINCI_LPSC_TPTC1              4
+#define DAVINCI_LPSC_EMAC               5
+#define DAVINCI_LPSC_EMAC_WRAPPER       6
+#define DAVINCI_LPSC_USB                9
+#define DAVINCI_LPSC_ATA                10
+#define DAVINCI_LPSC_VLYNQ              11
+#define DAVINCI_LPSC_UHPI               12
+#define DAVINCI_LPSC_DDR_EMIF           13
+#define DAVINCI_LPSC_AEMIF              14
+#define DAVINCI_LPSC_MMC_SD             15
+#define DAVINCI_LPSC_McBSP              17
+#define DAVINCI_LPSC_I2C                18
+#define DAVINCI_LPSC_UART0              19
+#define DAVINCI_LPSC_UART1              20
+#define DAVINCI_LPSC_UART2              21
+#define DAVINCI_LPSC_SPI                22
+#define DAVINCI_LPSC_PWM0               23
+#define DAVINCI_LPSC_PWM1               24
+#define DAVINCI_LPSC_PWM2               25
+#define DAVINCI_LPSC_GPIO               26
+#define DAVINCI_LPSC_TIMER0             27
+#define DAVINCI_LPSC_TIMER1             28
+#define DAVINCI_LPSC_TIMER2             29
+#define DAVINCI_LPSC_SYSTEM_SUBSYS      30
+#define DAVINCI_LPSC_ARM                31
+#define DAVINCI_LPSC_SCR2               32
+#define DAVINCI_LPSC_SCR3               33
+#define DAVINCI_LPSC_SCR4               34
+#define DAVINCI_LPSC_CROSSBAR           35
+#define DAVINCI_LPSC_CFG27              36
+#define DAVINCI_LPSC_CFG3               37
+#define DAVINCI_LPSC_CFG5               38
+#define DAVINCI_LPSC_GEM                39
+#define DAVINCI_LPSC_IMCOP              40
 
 #define DM355_LPSC_TIMER3               5
 #define DM355_LPSC_SPI1                 6
@@ -102,39 +102,39 @@
 /*
  * LPSC Assignments
  */
-#define DM646X_LPSC_ARM            0
-#define DM646X_LPSC_C64X_CPU       1
-#define DM646X_LPSC_HDVICP0        2
-#define DM646X_LPSC_HDVICP1        3
-#define DM646X_LPSC_TPCC           4
-#define DM646X_LPSC_TPTC0          5
-#define DM646X_LPSC_TPTC1          6
-#define DM646X_LPSC_TPTC2          7
-#define DM646X_LPSC_TPTC3          8
-#define DM646X_LPSC_PCI            13
-#define DM646X_LPSC_EMAC           14
-#define DM646X_LPSC_VDCE           15
-#define DM646X_LPSC_VPSSMSTR       16
-#define DM646X_LPSC_VPSSSLV        17
-#define DM646X_LPSC_TSIF0          18
-#define DM646X_LPSC_TSIF1          19
-#define DM646X_LPSC_DDR_EMIF       20
-#define DM646X_LPSC_AEMIF          21
-#define DM646X_LPSC_McASP0         22
-#define DM646X_LPSC_McASP1         23
-#define DM646X_LPSC_CRGEN0         24
-#define DM646X_LPSC_CRGEN1         25
-#define DM646X_LPSC_UART0          26
-#define DM646X_LPSC_UART1          27
-#define DM646X_LPSC_UART2          28
-#define DM646X_LPSC_PWM0           29
-#define DM646X_LPSC_PWM1           30
-#define DM646X_LPSC_I2C            31
-#define DM646X_LPSC_SPI            32
-#define DM646X_LPSC_GPIO           33
-#define DM646X_LPSC_TIMER0         34
-#define DM646X_LPSC_TIMER1         35
-#define DM646X_LPSC_ARM_INTC       45
+#define DM646X_LPSC_ARM         0
+#define DM646X_LPSC_C64X_CPU    1
+#define DM646X_LPSC_HDVICP0     2
+#define DM646X_LPSC_HDVICP1     3
+#define DM646X_LPSC_TPCC        4
+#define DM646X_LPSC_TPTC0       5
+#define DM646X_LPSC_TPTC1       6
+#define DM646X_LPSC_TPTC2       7
+#define DM646X_LPSC_TPTC3       8
+#define DM646X_LPSC_PCI         13
+#define DM646X_LPSC_EMAC        14
+#define DM646X_LPSC_VDCE        15
+#define DM646X_LPSC_VPSSMSTR    16
+#define DM646X_LPSC_VPSSSLV     17
+#define DM646X_LPSC_TSIF0       18
+#define DM646X_LPSC_TSIF1       19
+#define DM646X_LPSC_DDR_EMIF    20
+#define DM646X_LPSC_AEMIF       21
+#define DM646X_LPSC_McASP0      22
+#define DM646X_LPSC_McASP1      23
+#define DM646X_LPSC_CRGEN0      24
+#define DM646X_LPSC_CRGEN1      25
+#define DM646X_LPSC_UART0       26
+#define DM646X_LPSC_UART1       27
+#define DM646X_LPSC_UART2       28
+#define DM646X_LPSC_PWM0        29
+#define DM646X_LPSC_PWM1        30
+#define DM646X_LPSC_I2C         31
+#define DM646X_LPSC_SPI         32
+#define DM646X_LPSC_GPIO        33
+#define DM646X_LPSC_TIMER0      34
+#define DM646X_LPSC_TIMER1      35
+#define DM646X_LPSC_ARM_INTC    45
 
 /* PSC0 defines */
 #define DA8XX_LPSC0_TPCC                0
@@ -243,13 +243,14 @@
 #define PSC_STATE_DISABLE       2
 #define PSC_STATE_ENABLE        3
 
-#define MDSTAT_STATE_MASK 0x1f
+#define MDSTAT_STATE_MASK       0x3f
+#define MDCTL_FORCE             BIT(31)
 
 #ifndef __ASSEMBLER__
 
 extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
 extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
-                unsigned int id, u32 next_state);
+                unsigned int id, bool enable, u32 flags);
 
 #endif