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Diffstat (limited to 'arch/arm/mach-davinci/dm646x.c')
-rw-r--r--arch/arm/mach-davinci/dm646x.c53
1 files changed, 9 insertions, 44 deletions
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 893baf4ad37..94045656cff 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -311,7 +311,7 @@ static struct clk vpif1_clk = {
311 .flags = ALWAYS_ENABLED, 311 .flags = ALWAYS_ENABLED,
312}; 312};
313 313
314struct clk_lookup dm646x_clks[] = { 314static struct clk_lookup dm646x_clks[] = {
315 CLK(NULL, "ref", &ref_clk), 315 CLK(NULL, "ref", &ref_clk),
316 CLK(NULL, "aux", &aux_clkin), 316 CLK(NULL, "aux", &aux_clkin),
317 CLK(NULL, "pll1", &pll1_clk), 317 CLK(NULL, "pll1", &pll1_clk),
@@ -401,9 +401,6 @@ static struct platform_device dm646x_emac_device = {
401 .resource = dm646x_emac_resources, 401 .resource = dm646x_emac_resources,
402}; 402};
403 403
404#define PINMUX0 0x00
405#define PINMUX1 0x04
406
407/* 404/*
408 * Device specific mux setup 405 * Device specific mux setup
409 * 406 *
@@ -596,32 +593,6 @@ static struct platform_device dm646x_edma_device = {
596 .resource = edma_resources, 593 .resource = edma_resources,
597}; 594};
598 595
599static struct resource ide_resources[] = {
600 {
601 .start = DM646X_ATA_REG_BASE,
602 .end = DM646X_ATA_REG_BASE + 0x7ff,
603 .flags = IORESOURCE_MEM,
604 },
605 {
606 .start = IRQ_DM646X_IDE,
607 .end = IRQ_DM646X_IDE,
608 .flags = IORESOURCE_IRQ,
609 },
610};
611
612static u64 ide_dma_mask = DMA_BIT_MASK(32);
613
614static struct platform_device ide_dev = {
615 .name = "palm_bk3710",
616 .id = -1,
617 .resource = ide_resources,
618 .num_resources = ARRAY_SIZE(ide_resources),
619 .dev = {
620 .dma_mask = &ide_dma_mask,
621 .coherent_dma_mask = DMA_BIT_MASK(32),
622 },
623};
624
625static struct resource dm646x_mcasp0_resources[] = { 596static struct resource dm646x_mcasp0_resources[] = {
626 { 597 {
627 .name = "mcasp0", 598 .name = "mcasp0",
@@ -787,9 +758,7 @@ static struct davinci_id dm646x_ids[] = {
787 }, 758 },
788}; 759};
789 760
790static void __iomem *dm646x_psc_bases[] = { 761static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
791 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
792};
793 762
794/* 763/*
795 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers 764 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
@@ -797,7 +766,7 @@ static void __iomem *dm646x_psc_bases[] = {
797 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) 766 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
798 * T1_TOP: Timer 1, top : <unused> 767 * T1_TOP: Timer 1, top : <unused>
799 */ 768 */
800struct davinci_timer_info dm646x_timer_info = { 769static struct davinci_timer_info dm646x_timer_info = {
801 .timers = davinci_timer_instance, 770 .timers = davinci_timer_instance,
802 .clockevent_id = T0_BOT, 771 .clockevent_id = T0_BOT,
803 .clocksource_id = T0_TOP, 772 .clocksource_id = T0_TOP,
@@ -844,35 +813,31 @@ static struct platform_device dm646x_serial_device = {
844static struct davinci_soc_info davinci_soc_info_dm646x = { 813static struct davinci_soc_info davinci_soc_info_dm646x = {
845 .io_desc = dm646x_io_desc, 814 .io_desc = dm646x_io_desc,
846 .io_desc_num = ARRAY_SIZE(dm646x_io_desc), 815 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
847 .jtag_id_base = IO_ADDRESS(0x01c40028), 816 .jtag_id_reg = 0x01c40028,
848 .ids = dm646x_ids, 817 .ids = dm646x_ids,
849 .ids_num = ARRAY_SIZE(dm646x_ids), 818 .ids_num = ARRAY_SIZE(dm646x_ids),
850 .cpu_clks = dm646x_clks, 819 .cpu_clks = dm646x_clks,
851 .psc_bases = dm646x_psc_bases, 820 .psc_bases = dm646x_psc_bases,
852 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), 821 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
853 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), 822 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
854 .pinmux_pins = dm646x_pins, 823 .pinmux_pins = dm646x_pins,
855 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), 824 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
856 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), 825 .intc_base = DAVINCI_ARM_INTC_BASE,
857 .intc_type = DAVINCI_INTC_TYPE_AINTC, 826 .intc_type = DAVINCI_INTC_TYPE_AINTC,
858 .intc_irq_prios = dm646x_default_priorities, 827 .intc_irq_prios = dm646x_default_priorities,
859 .intc_irq_num = DAVINCI_N_AINTC_IRQ, 828 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
860 .timer_info = &dm646x_timer_info, 829 .timer_info = &dm646x_timer_info,
861 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), 830 .gpio_type = GPIO_TYPE_DAVINCI,
831 .gpio_base = DAVINCI_GPIO_BASE,
862 .gpio_num = 43, /* Only 33 usable */ 832 .gpio_num = 43, /* Only 33 usable */
863 .gpio_irq = IRQ_DM646X_GPIOBNK0, 833 .gpio_irq = IRQ_DM646X_GPIOBNK0,
864 .serial_dev = &dm646x_serial_device, 834 .serial_dev = &dm646x_serial_device,
865 .emac_pdata = &dm646x_emac_pdata, 835 .emac_pdata = &dm646x_emac_pdata,
866 .sram_dma = 0x10010000, 836 .sram_dma = 0x10010000,
867 .sram_len = SZ_32K, 837 .sram_len = SZ_32K,
838 .reset_device = &davinci_wdt_device,
868}; 839};
869 840
870void __init dm646x_init_ide()
871{
872 davinci_cfg_reg(DM646X_ATAEN);
873 platform_device_register(&ide_dev);
874}
875
876void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) 841void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
877{ 842{
878 dm646x_mcasp0_device.dev.platform_data = pdata; 843 dm646x_mcasp0_device.dev.platform_data = pdata;