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-rw-r--r--arch/arm/mach-davinci/clock.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 0dd22031ec6..a705f367a84 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -111,6 +111,7 @@ struct clk {
111#define CLK_PLL BIT(4) /* PLL-derived clock */ 111#define CLK_PLL BIT(4) /* PLL-derived clock */
112#define PRE_PLL BIT(5) /* source is before PLL mult/div */ 112#define PRE_PLL BIT(5) /* source is before PLL mult/div */
113#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */ 113#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
114#define PSC_FORCE BIT(7) /* Force module state transtition */
114 115
115#define CLK(dev, con, ck) \ 116#define CLK(dev, con, ck) \
116 { \ 117 { \
@@ -123,6 +124,8 @@ int davinci_clk_init(struct clk_lookup *clocks);
123int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, 124int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
124 unsigned int mult, unsigned int postdiv); 125 unsigned int mult, unsigned int postdiv);
125int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); 126int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
127int davinci_set_refclk_rate(unsigned long rate);
128int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
126 129
127extern struct platform_device davinci_wdt_device; 130extern struct platform_device davinci_wdt_device;
128extern void davinci_watchdog_reset(struct platform_device *); 131extern void davinci_watchdog_reset(struct platform_device *);