3 files changed, 234 insertions, 2 deletions
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
new file mode 100644
index 00000000000..3e0759122ba
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -0,0 +1,232 @@
+/*
+ *  This file contains the hardware definitions of the Cirrus Logic
+ *  ARM7 CLPS711X internal registers.
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __MACH_CLPS711X_H
+#define __MACH_CLPS711X_H
+#define CLPS711X_PHYS_BASE      (0x80000000)
+#define PADR            (0x0000)
+#define PBDR            (0x0001)
+#define PCDR            (0x0002)
+#define PDDR            (0x0003)
+#define PADDR           (0x0040)
+#define PBDDR           (0x0041)
+#define PCDDR           (0x0042)
+#define PDDDR           (0x0043)
+#define PEDR            (0x0080)
+#define PEDDR           (0x00c0)
+#define SYSCON1         (0x0100)
+#define SYSFLG1         (0x0140)
+#define MEMCFG1         (0x0180)
+#define MEMCFG2         (0x01c0)
+#define DRFPR           (0x0200)
+#define INTSR1          (0x0240)
+#define INTMR1          (0x0280)
+#define LCDCON          (0x02c0)
+#define TC1D            (0x0300)
+#define TC2D            (0x0340)
+#define RTCDR           (0x0380)
+#define RTCMR           (0x03c0)
+#define PMPCON          (0x0400)
+#define CODR            (0x0440)
+#define UARTDR1         (0x0480)
+#define UBRLCR1         (0x04c0)
+#define SYNCIO          (0x0500)
+#define PALLSW          (0x0540)
+#define PALMSW          (0x0580)
+#define STFCLR          (0x05c0)
+#define BLEOI           (0x0600)
+#define MCEOI           (0x0640)
+#define TEOI            (0x0680)
+#define TC1EOI          (0x06c0)
+#define TC2EOI          (0x0700)
+#define RTCEOI          (0x0740)
+#define UMSEOI          (0x0780)
+#define COEOI           (0x07c0)
+#define HALT            (0x0800)
+#define STDBY           (0x0840)
+#define FBADDR          (0x1000)
+#define SYSCON2         (0x1100)
+#define SYSFLG2         (0x1140)
+#define INTSR2          (0x1240)
+#define INTMR2          (0x1280)
+#define UARTDR2         (0x1480)
+#define UBRLCR2         (0x14c0)
+#define SS2DR           (0x1500)
+#define SRXEOF          (0x1600)
+#define SS2POP          (0x16c0)
+#define KBDEOI          (0x1700)
+#define DAIR            (0x2000)
+#define DAIR0           (0x2040)
+#define DAIDR1          (0x2080)
+#define DAIDR2          (0x20c0)
+#define DAISR           (0x2100)
+#define SYSCON3         (0x2200)
+#define INTSR3          (0x2240)
+#define INTMR3          (0x2280)
+#define LEDFLSH         (0x22c0)
+#define SDCONF          (0x2300)
+#define SDRFPR          (0x2340)
+/* common bits: SYSCON1 / SYSCON2 */
+#define SYSCON_UARTEN           (1 << 8)
+#define SYSCON1_KBDSCAN(x)      ((x) & 15)
+#define SYSCON1_KBDSCANMASK     (15)
+#define SYSCON1_TC1M            (1 << 4)
+#define SYSCON1_TC1S            (1 << 5)
+#define SYSCON1_TC2M            (1 << 6)
+#define SYSCON1_TC2S            (1 << 7)
+#define SYSCON1_UART1EN         SYSCON_UARTEN
+#define SYSCON1_BZTOG           (1 << 9)
+#define SYSCON1_BZMOD           (1 << 10)
+#define SYSCON1_DBGEN           (1 << 11)
+#define SYSCON1_LCDEN           (1 << 12)
+#define SYSCON1_CDENTX          (1 << 13)
+#define SYSCON1_CDENRX          (1 << 14)
+#define SYSCON1_SIREN           (1 << 15)
+#define SYSCON1_ADCKSEL(x)      (((x) & 3) << 16)
+#define SYSCON1_ADCKSEL_MASK    (3 << 16)
+#define SYSCON1_EXCKEN          (1 << 18)
+#define SYSCON1_WAKEDIS         (1 << 19)
+#define SYSCON1_IRTXM           (1 << 20)
+/* common bits: SYSFLG1 / SYSFLG2 */
+#define SYSFLG_UBUSY            (1 << 11)
+#define SYSFLG_URXFE            (1 << 22)
+#define SYSFLG_UTXFF            (1 << 23)
+#define SYSFLG1_MCDR            (1 << 0)
+#define SYSFLG1_DCDET           (1 << 1)
+#define SYSFLG1_WUDR            (1 << 2)
+#define SYSFLG1_WUON            (1 << 3)
+#define SYSFLG1_CTS             (1 << 8)
+#define SYSFLG1_DSR             (1 << 9)
+#define SYSFLG1_DCD             (1 << 10)
+#define SYSFLG1_UBUSY           SYSFLG_UBUSY
+#define SYSFLG1_NBFLG           (1 << 12)
+#define SYSFLG1_RSTFLG          (1 << 13)
+#define SYSFLG1_PFFLG           (1 << 14)
+#define SYSFLG1_CLDFLG          (1 << 15)
+#define SYSFLG1_URXFE           SYSFLG_URXFE
+#define SYSFLG1_UTXFF           SYSFLG_UTXFF
+#define SYSFLG1_CRXFE           (1 << 24)
+#define SYSFLG1_CTXFF           (1 << 25)
+#define SYSFLG1_SSIBUSY         (1 << 26)
+#define SYSFLG1_ID              (1 << 29)
+#define SYSFLG2_SSRXOF          (1 << 0)
+#define SYSFLG2_RESVAL          (1 << 1)
+#define SYSFLG2_RESFRM          (1 << 2)
+#define SYSFLG2_SS2RXFE         (1 << 3)
+#define SYSFLG2_SS2TXFF         (1 << 4)
+#define SYSFLG2_SS2TXUF         (1 << 5)
+#define SYSFLG2_CKMODE          (1 << 6)
+#define SYSFLG2_UBUSY           SYSFLG_UBUSY
+#define SYSFLG2_URXFE           SYSFLG_URXFE
+#define SYSFLG2_UTXFF           SYSFLG_UTXFF
+#define LCDCON_GSEN             (1 << 30)
+#define LCDCON_GSMD             (1 << 31)
+#define SYSCON2_SERSEL          (1 << 0)
+#define SYSCON2_KBD6            (1 << 1)
+#define SYSCON2_DRAMZ           (1 << 2)
+#define SYSCON2_KBWEN           (1 << 3)
+#define SYSCON2_SS2TXEN         (1 << 4)
+#define SYSCON2_PCCARD1         (1 << 5)
+#define SYSCON2_PCCARD2         (1 << 6)
+#define SYSCON2_SS2RXEN         (1 << 7)
+#define SYSCON2_UART2EN         SYSCON_UARTEN
+#define SYSCON2_SS2MAEN         (1 << 9)
+#define SYSCON2_OSTB            (1 << 12)
+#define SYSCON2_CLKENSL         (1 << 13)
+#define SYSCON2_BUZFREQ         (1 << 14)
+/* common bits: UARTDR1 / UARTDR2 */
+#define UARTDR_FRMERR           (1 << 8)
+#define UARTDR_PARERR           (1 << 9)
+#define UARTDR_OVERR            (1 << 10)
+/* common bits: UBRLCR1 / UBRLCR2 */
+#define UBRLCR_BAUD_MASK        ((1 << 12) - 1)
+#define UBRLCR_BREAK            (1 << 12)
+#define UBRLCR_PRTEN            (1 << 13)
+#define UBRLCR_EVENPRT          (1 << 14)
+#define UBRLCR_XSTOP            (1 << 15)
+#define UBRLCR_FIFOEN           (1 << 16)
+#define UBRLCR_WRDLEN5          (0 << 17)
+#define UBRLCR_WRDLEN6          (1 << 17)
+#define UBRLCR_WRDLEN7          (2 << 17)
+#define UBRLCR_WRDLEN8          (3 << 17)
+#define UBRLCR_WRDLEN_MASK      (3 << 17)
+#define SYNCIO_SMCKEN           (1 << 13)
+#define SYNCIO_TXFRMEN          (1 << 14)
+#define DAIR_DAIEN              (1 << 16)
+#define DAIR_ECS                (1 << 17)
+#define DAIR_LCTM               (1 << 19)
+#define DAIR_LCRM               (1 << 20)
+#define DAIR_RCTM               (1 << 21)
+#define DAIR_RCRM               (1 << 22)
+#define DAIR_LBM                (1 << 23)
+#define DAIDR2_FIFOEN           (1 << 15)
+#define DAIDR2_FIFOLEFT         (0x0d << 16)
+#define DAIDR2_FIFORIGHT        (0x11 << 16)
+#define DAISR_RCTS              (1 << 0)
+#define DAISR_RCRS              (1 << 1)
+#define DAISR_LCTS              (1 << 2)
+#define DAISR_LCRS              (1 << 3)
+#define DAISR_RCTU              (1 << 4)
+#define DAISR_RCRO              (1 << 5)
+#define DAISR_LCTU              (1 << 6)
+#define DAISR_LCRO              (1 << 7)
+#define DAISR_RCNF              (1 << 8)
+#define DAISR_RCNE              (1 << 9)
+#define DAISR_LCNF              (1 << 10)
+#define DAISR_LCNE              (1 << 11)
+#define DAISR_FIFO              (1 << 12)
+#define SYSCON3_ADCCON          (1 << 0)
+#define SYSCON3_DAISEL          (1 << 3)
+#define SYSCON3_ADCCKNSEN       (1 << 4)
+#define SYSCON3_FASTWAKE        (1 << 8)
+#define SYSCON3_DAIEN           (1 << 9)
+#define SDCONF_ACTIVE           (1 << 10)
+#define SDCONF_CLKCTL           (1 << 9)
+#define SDCONF_WIDTH_4          (0 << 7)
+#define SDCONF_WIDTH_8          (1 << 7)
+#define SDCONF_WIDTH_16         (2 << 7)
+#define SDCONF_WIDTH_32         (3 << 7)
+#define SDCONF_SIZE_16          (0 << 5)
+#define SDCONF_SIZE_64          (1 << 5)
+#define SDCONF_SIZE_128         (2 << 5)
+#define SDCONF_SIZE_256         (3 << 5)
+#define SDCONF_CASLAT_2         (2)
+#define SDCONF_CASLAT_3         (3)
+#endif /* __MACH_CLPS711X_H */
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index d31fc791f51..13a64fcd7dd 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -22,7 +22,7 @@
 #ifndef __MACH_HARDWARE_H
 #define __MACH_HARDWARE_H
-#include <asm/hardware/clps7111.h>
+#include <mach/clps711x.h>
 #define CLPS711X_VIRT_BASE      IOMEM(0xff000000)
diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h
index 263f8393ccb..7b28d6a4769 100644
--- a/arch/arm/mach-clps711x/include/mach/uncompress.h
+++ b/arch/arm/mach-clps711x/include/mach/uncompress.h
@@ -17,7 +17,7 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#include <asm/hardware/clps7111.h>
+#include <mach/clps711x.h>
 #ifdef CONFIG_DEBUG_CLPS711X_UART2
 #define SYSFLGx SYSFLG2

diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h new file mode 100644 index 00000000000..3e0759122ba --- /dev/null +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -0,0 +1,232 @@
		1	/*
		2	* This file contains the hardware definitions of the Cirrus Logic
		3	* ARM7 CLPS711X internal registers.
		4	*
		5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
		6	*
		7	* This program is free software; you can redistribute it and/or modify
		8	* it under the terms of the GNU General Public License as published by
		9	* the Free Software Foundation; either version 2 of the License, or
		10	* (at your option) any later version.
		11	*
		12	* This program is distributed in the hope that it will be useful,
		13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
		14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		15	* GNU General Public License for more details.
		16	*
		17	* You should have received a copy of the GNU General Public License
		18	* along with this program; if not, write to the Free Software
		19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		20	*/
		21	#ifndef __MACH_CLPS711X_H
		22	#define __MACH_CLPS711X_H
		23
		24	#define CLPS711X_PHYS_BASE (0x80000000)
		25
		26	#define PADR (0x0000)
		27	#define PBDR (0x0001)
		28	#define PCDR (0x0002)
		29	#define PDDR (0x0003)
		30	#define PADDR (0x0040)
		31	#define PBDDR (0x0041)
		32	#define PCDDR (0x0042)
		33	#define PDDDR (0x0043)
		34	#define PEDR (0x0080)
		35	#define PEDDR (0x00c0)
		36	#define SYSCON1 (0x0100)
		37	#define SYSFLG1 (0x0140)
		38	#define MEMCFG1 (0x0180)
		39	#define MEMCFG2 (0x01c0)
		40	#define DRFPR (0x0200)
		41	#define INTSR1 (0x0240)
		42	#define INTMR1 (0x0280)
		43	#define LCDCON (0x02c0)
		44	#define TC1D (0x0300)
		45	#define TC2D (0x0340)
		46	#define RTCDR (0x0380)
		47	#define RTCMR (0x03c0)
		48	#define PMPCON (0x0400)
		49	#define CODR (0x0440)
		50	#define UARTDR1 (0x0480)
		51	#define UBRLCR1 (0x04c0)
		52	#define SYNCIO (0x0500)
		53	#define PALLSW (0x0540)
		54	#define PALMSW (0x0580)
		55	#define STFCLR (0x05c0)
		56	#define BLEOI (0x0600)
		57	#define MCEOI (0x0640)
		58	#define TEOI (0x0680)
		59	#define TC1EOI (0x06c0)
		60	#define TC2EOI (0x0700)
		61	#define RTCEOI (0x0740)
		62	#define UMSEOI (0x0780)
		63	#define COEOI (0x07c0)
		64	#define HALT (0x0800)
		65	#define STDBY (0x0840)
		66
		67	#define FBADDR (0x1000)
		68	#define SYSCON2 (0x1100)
		69	#define SYSFLG2 (0x1140)
		70	#define INTSR2 (0x1240)
		71	#define INTMR2 (0x1280)
		72	#define UARTDR2 (0x1480)
		73	#define UBRLCR2 (0x14c0)
		74	#define SS2DR (0x1500)
		75	#define SRXEOF (0x1600)
		76	#define SS2POP (0x16c0)
		77	#define KBDEOI (0x1700)
		78
		79	#define DAIR (0x2000)
		80	#define DAIR0 (0x2040)
		81	#define DAIDR1 (0x2080)
		82	#define DAIDR2 (0x20c0)
		83	#define DAISR (0x2100)
		84	#define SYSCON3 (0x2200)
		85	#define INTSR3 (0x2240)
		86	#define INTMR3 (0x2280)
		87	#define LEDFLSH (0x22c0)
		88	#define SDCONF (0x2300)
		89	#define SDRFPR (0x2340)
		90
		91	/* common bits: SYSCON1 / SYSCON2 */
		92	#define SYSCON_UARTEN (1 << 8)
		93
		94	#define SYSCON1_KBDSCAN(x) ((x) & 15)
		95	#define SYSCON1_KBDSCANMASK (15)
		96	#define SYSCON1_TC1M (1 << 4)
		97	#define SYSCON1_TC1S (1 << 5)
		98	#define SYSCON1_TC2M (1 << 6)
		99	#define SYSCON1_TC2S (1 << 7)
		100	#define SYSCON1_UART1EN SYSCON_UARTEN
		101	#define SYSCON1_BZTOG (1 << 9)
		102	#define SYSCON1_BZMOD (1 << 10)
		103	#define SYSCON1_DBGEN (1 << 11)
		104	#define SYSCON1_LCDEN (1 << 12)
		105	#define SYSCON1_CDENTX (1 << 13)
		106	#define SYSCON1_CDENRX (1 << 14)
		107	#define SYSCON1_SIREN (1 << 15)
		108	#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
		109	#define SYSCON1_ADCKSEL_MASK (3 << 16)
		110	#define SYSCON1_EXCKEN (1 << 18)
		111	#define SYSCON1_WAKEDIS (1 << 19)
		112	#define SYSCON1_IRTXM (1 << 20)
		113
		114	/* common bits: SYSFLG1 / SYSFLG2 */
		115	#define SYSFLG_UBUSY (1 << 11)
		116	#define SYSFLG_URXFE (1 << 22)
		117	#define SYSFLG_UTXFF (1 << 23)
		118
		119	#define SYSFLG1_MCDR (1 << 0)
		120	#define SYSFLG1_DCDET (1 << 1)
		121	#define SYSFLG1_WUDR (1 << 2)
		122	#define SYSFLG1_WUON (1 << 3)
		123	#define SYSFLG1_CTS (1 << 8)
		124	#define SYSFLG1_DSR (1 << 9)
		125	#define SYSFLG1_DCD (1 << 10)
		126	#define SYSFLG1_UBUSY SYSFLG_UBUSY
		127	#define SYSFLG1_NBFLG (1 << 12)
		128	#define SYSFLG1_RSTFLG (1 << 13)
		129	#define SYSFLG1_PFFLG (1 << 14)
		130	#define SYSFLG1_CLDFLG (1 << 15)
		131	#define SYSFLG1_URXFE SYSFLG_URXFE
		132	#define SYSFLG1_UTXFF SYSFLG_UTXFF
		133	#define SYSFLG1_CRXFE (1 << 24)
		134	#define SYSFLG1_CTXFF (1 << 25)
		135	#define SYSFLG1_SSIBUSY (1 << 26)
		136	#define SYSFLG1_ID (1 << 29)
		137
		138	#define SYSFLG2_SSRXOF (1 << 0)
		139	#define SYSFLG2_RESVAL (1 << 1)
		140	#define SYSFLG2_RESFRM (1 << 2)
		141	#define SYSFLG2_SS2RXFE (1 << 3)
		142	#define SYSFLG2_SS2TXFF (1 << 4)
		143	#define SYSFLG2_SS2TXUF (1 << 5)
		144	#define SYSFLG2_CKMODE (1 << 6)
		145	#define SYSFLG2_UBUSY SYSFLG_UBUSY
		146	#define SYSFLG2_URXFE SYSFLG_URXFE
		147	#define SYSFLG2_UTXFF SYSFLG_UTXFF
		148
		149	#define LCDCON_GSEN (1 << 30)
		150	#define LCDCON_GSMD (1 << 31)
		151
		152	#define SYSCON2_SERSEL (1 << 0)
		153	#define SYSCON2_KBD6 (1 << 1)
		154	#define SYSCON2_DRAMZ (1 << 2)
		155	#define SYSCON2_KBWEN (1 << 3)
		156	#define SYSCON2_SS2TXEN (1 << 4)
		157	#define SYSCON2_PCCARD1 (1 << 5)
		158	#define SYSCON2_PCCARD2 (1 << 6)
		159	#define SYSCON2_SS2RXEN (1 << 7)
		160	#define SYSCON2_UART2EN SYSCON_UARTEN
		161	#define SYSCON2_SS2MAEN (1 << 9)
		162	#define SYSCON2_OSTB (1 << 12)
		163	#define SYSCON2_CLKENSL (1 << 13)
		164	#define SYSCON2_BUZFREQ (1 << 14)
		165
		166	/* common bits: UARTDR1 / UARTDR2 */
		167	#define UARTDR_FRMERR (1 << 8)
		168	#define UARTDR_PARERR (1 << 9)
		169	#define UARTDR_OVERR (1 << 10)
		170
		171	/* common bits: UBRLCR1 / UBRLCR2 */
		172	#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
		173	#define UBRLCR_BREAK (1 << 12)
		174	#define UBRLCR_PRTEN (1 << 13)
		175	#define UBRLCR_EVENPRT (1 << 14)
		176	#define UBRLCR_XSTOP (1 << 15)
		177	#define UBRLCR_FIFOEN (1 << 16)
		178	#define UBRLCR_WRDLEN5 (0 << 17)
		179	#define UBRLCR_WRDLEN6 (1 << 17)
		180	#define UBRLCR_WRDLEN7 (2 << 17)
		181	#define UBRLCR_WRDLEN8 (3 << 17)
		182	#define UBRLCR_WRDLEN_MASK (3 << 17)
		183
		184	#define SYNCIO_SMCKEN (1 << 13)
		185	#define SYNCIO_TXFRMEN (1 << 14)
		186
		187	#define DAIR_DAIEN (1 << 16)
		188	#define DAIR_ECS (1 << 17)
		189	#define DAIR_LCTM (1 << 19)
		190	#define DAIR_LCRM (1 << 20)
		191	#define DAIR_RCTM (1 << 21)
		192	#define DAIR_RCRM (1 << 22)
		193	#define DAIR_LBM (1 << 23)
		194
		195	#define DAIDR2_FIFOEN (1 << 15)
		196	#define DAIDR2_FIFOLEFT (0x0d << 16)
		197	#define DAIDR2_FIFORIGHT (0x11 << 16)
		198
		199	#define DAISR_RCTS (1 << 0)
		200	#define DAISR_RCRS (1 << 1)
		201	#define DAISR_LCTS (1 << 2)
		202	#define DAISR_LCRS (1 << 3)
		203	#define DAISR_RCTU (1 << 4)
		204	#define DAISR_RCRO (1 << 5)
		205	#define DAISR_LCTU (1 << 6)
		206	#define DAISR_LCRO (1 << 7)
		207	#define DAISR_RCNF (1 << 8)
		208	#define DAISR_RCNE (1 << 9)
		209	#define DAISR_LCNF (1 << 10)
		210	#define DAISR_LCNE (1 << 11)
		211	#define DAISR_FIFO (1 << 12)
		212
		213	#define SYSCON3_ADCCON (1 << 0)
		214	#define SYSCON3_DAISEL (1 << 3)
		215	#define SYSCON3_ADCCKNSEN (1 << 4)
		216	#define SYSCON3_FASTWAKE (1 << 8)
		217	#define SYSCON3_DAIEN (1 << 9)
		218
		219	#define SDCONF_ACTIVE (1 << 10)
		220	#define SDCONF_CLKCTL (1 << 9)
		221	#define SDCONF_WIDTH_4 (0 << 7)
		222	#define SDCONF_WIDTH_8 (1 << 7)
		223	#define SDCONF_WIDTH_16 (2 << 7)
		224	#define SDCONF_WIDTH_32 (3 << 7)
		225	#define SDCONF_SIZE_16 (0 << 5)
		226	#define SDCONF_SIZE_64 (1 << 5)
		227	#define SDCONF_SIZE_128 (2 << 5)
		228	#define SDCONF_SIZE_256 (3 << 5)
		229	#define SDCONF_CASLAT_2 (2)
		230	#define SDCONF_CASLAT_3 (3)
		231
		232	#endif /* __MACH_CLPS711X_H */


diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index d31fc791f51..13a64fcd7dd 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -22,7 +22,7 @@
22	#ifndef __MACH_HARDWARE_H	22	#ifndef __MACH_HARDWARE_H
23	#define __MACH_HARDWARE_H	23	#define __MACH_HARDWARE_H
24		24
25	#include <asm/hardware/clps7111.h>	25	#include <mach/clps711x.h>
26		26
27	#define CLPS711X_VIRT_BASE IOMEM(0xff000000)	27	#define CLPS711X_VIRT_BASE IOMEM(0xff000000)
28		28


diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h index 263f8393ccb..7b28d6a4769 100644 --- a/arch/arm/mach-clps711x/include/mach/uncompress.h +++ b/arch/arm/mach-clps711x/include/mach/uncompress.h
@@ -17,7 +17,7 @@
17	* along with this program; if not, write to the Free Software	17	* along with this program; if not, write to the Free Software
18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	*/	19	*/
20	#include <asm/hardware/clps7111.h>	20	#include <mach/clps711x.h>
21		21
22	#ifdef CONFIG_DEBUG_CLPS711X_UART2	22	#ifdef CONFIG_DEBUG_CLPS711X_UART2
23	#define SYSFLGx SYSFLG2	23	#define SYSFLGx SYSFLG2