diff options
Diffstat (limited to 'arch/arm/kernel/setup.c')
-rw-r--r-- | arch/arm/kernel/setup.c | 128 |
1 files changed, 72 insertions, 56 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index acbb447ac6b..5af79bd6a8b 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c | |||
@@ -280,18 +280,19 @@ static void __init cacheid_init(void) | |||
280 | if (arch >= CPU_ARCH_ARMv6) { | 280 | if (arch >= CPU_ARCH_ARMv6) { |
281 | if ((cachetype & (7 << 29)) == 4 << 29) { | 281 | if ((cachetype & (7 << 29)) == 4 << 29) { |
282 | /* ARMv7 register format */ | 282 | /* ARMv7 register format */ |
283 | arch = CPU_ARCH_ARMv7; | ||
283 | cacheid = CACHEID_VIPT_NONALIASING; | 284 | cacheid = CACHEID_VIPT_NONALIASING; |
284 | if ((cachetype & (3 << 14)) == 1 << 14) | 285 | if ((cachetype & (3 << 14)) == 1 << 14) |
285 | cacheid |= CACHEID_ASID_TAGGED; | 286 | cacheid |= CACHEID_ASID_TAGGED; |
286 | else if (cpu_has_aliasing_icache(CPU_ARCH_ARMv7)) | ||
287 | cacheid |= CACHEID_VIPT_I_ALIASING; | ||
288 | } else if (cachetype & (1 << 23)) { | ||
289 | cacheid = CACHEID_VIPT_ALIASING; | ||
290 | } else { | 287 | } else { |
291 | cacheid = CACHEID_VIPT_NONALIASING; | 288 | arch = CPU_ARCH_ARMv6; |
292 | if (cpu_has_aliasing_icache(CPU_ARCH_ARMv6)) | 289 | if (cachetype & (1 << 23)) |
293 | cacheid |= CACHEID_VIPT_I_ALIASING; | 290 | cacheid = CACHEID_VIPT_ALIASING; |
291 | else | ||
292 | cacheid = CACHEID_VIPT_NONALIASING; | ||
294 | } | 293 | } |
294 | if (cpu_has_aliasing_icache(arch)) | ||
295 | cacheid |= CACHEID_VIPT_I_ALIASING; | ||
295 | } else { | 296 | } else { |
296 | cacheid = CACHEID_VIVT; | 297 | cacheid = CACHEID_VIVT; |
297 | } | 298 | } |
@@ -343,54 +344,6 @@ static void __init feat_v6_fixup(void) | |||
343 | elf_hwcap &= ~HWCAP_TLS; | 344 | elf_hwcap &= ~HWCAP_TLS; |
344 | } | 345 | } |
345 | 346 | ||
346 | static void __init setup_processor(void) | ||
347 | { | ||
348 | struct proc_info_list *list; | ||
349 | |||
350 | /* | ||
351 | * locate processor in the list of supported processor | ||
352 | * types. The linker builds this table for us from the | ||
353 | * entries in arch/arm/mm/proc-*.S | ||
354 | */ | ||
355 | list = lookup_processor_type(read_cpuid_id()); | ||
356 | if (!list) { | ||
357 | printk("CPU configuration botched (ID %08x), unable " | ||
358 | "to continue.\n", read_cpuid_id()); | ||
359 | while (1); | ||
360 | } | ||
361 | |||
362 | cpu_name = list->cpu_name; | ||
363 | |||
364 | #ifdef MULTI_CPU | ||
365 | processor = *list->proc; | ||
366 | #endif | ||
367 | #ifdef MULTI_TLB | ||
368 | cpu_tlb = *list->tlb; | ||
369 | #endif | ||
370 | #ifdef MULTI_USER | ||
371 | cpu_user = *list->user; | ||
372 | #endif | ||
373 | #ifdef MULTI_CACHE | ||
374 | cpu_cache = *list->cache; | ||
375 | #endif | ||
376 | |||
377 | printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n", | ||
378 | cpu_name, read_cpuid_id(), read_cpuid_id() & 15, | ||
379 | proc_arch[cpu_architecture()], cr_alignment); | ||
380 | |||
381 | sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS); | ||
382 | sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS); | ||
383 | elf_hwcap = list->elf_hwcap; | ||
384 | #ifndef CONFIG_ARM_THUMB | ||
385 | elf_hwcap &= ~HWCAP_THUMB; | ||
386 | #endif | ||
387 | |||
388 | feat_v6_fixup(); | ||
389 | |||
390 | cacheid_init(); | ||
391 | cpu_proc_init(); | ||
392 | } | ||
393 | |||
394 | /* | 347 | /* |
395 | * cpu_init - initialise one CPU. | 348 | * cpu_init - initialise one CPU. |
396 | * | 349 | * |
@@ -406,6 +359,8 @@ void cpu_init(void) | |||
406 | BUG(); | 359 | BUG(); |
407 | } | 360 | } |
408 | 361 | ||
362 | cpu_proc_init(); | ||
363 | |||
409 | /* | 364 | /* |
410 | * Define the placement constraint for the inline asm directive below. | 365 | * Define the placement constraint for the inline asm directive below. |
411 | * In Thumb-2, msr with an immediate value is not allowed. | 366 | * In Thumb-2, msr with an immediate value is not allowed. |
@@ -442,6 +397,54 @@ void cpu_init(void) | |||
442 | : "r14"); | 397 | : "r14"); |
443 | } | 398 | } |
444 | 399 | ||
400 | static void __init setup_processor(void) | ||
401 | { | ||
402 | struct proc_info_list *list; | ||
403 | |||
404 | /* | ||
405 | * locate processor in the list of supported processor | ||
406 | * types. The linker builds this table for us from the | ||
407 | * entries in arch/arm/mm/proc-*.S | ||
408 | */ | ||
409 | list = lookup_processor_type(read_cpuid_id()); | ||
410 | if (!list) { | ||
411 | printk("CPU configuration botched (ID %08x), unable " | ||
412 | "to continue.\n", read_cpuid_id()); | ||
413 | while (1); | ||
414 | } | ||
415 | |||
416 | cpu_name = list->cpu_name; | ||
417 | |||
418 | #ifdef MULTI_CPU | ||
419 | processor = *list->proc; | ||
420 | #endif | ||
421 | #ifdef MULTI_TLB | ||
422 | cpu_tlb = *list->tlb; | ||
423 | #endif | ||
424 | #ifdef MULTI_USER | ||
425 | cpu_user = *list->user; | ||
426 | #endif | ||
427 | #ifdef MULTI_CACHE | ||
428 | cpu_cache = *list->cache; | ||
429 | #endif | ||
430 | |||
431 | printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n", | ||
432 | cpu_name, read_cpuid_id(), read_cpuid_id() & 15, | ||
433 | proc_arch[cpu_architecture()], cr_alignment); | ||
434 | |||
435 | sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS); | ||
436 | sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS); | ||
437 | elf_hwcap = list->elf_hwcap; | ||
438 | #ifndef CONFIG_ARM_THUMB | ||
439 | elf_hwcap &= ~HWCAP_THUMB; | ||
440 | #endif | ||
441 | |||
442 | feat_v6_fixup(); | ||
443 | |||
444 | cacheid_init(); | ||
445 | cpu_init(); | ||
446 | } | ||
447 | |||
445 | void __init dump_machine_table(void) | 448 | void __init dump_machine_table(void) |
446 | { | 449 | { |
447 | struct machine_desc *p; | 450 | struct machine_desc *p; |
@@ -887,6 +890,12 @@ void __init setup_arch(char **cmdline_p) | |||
887 | machine_desc = mdesc; | 890 | machine_desc = mdesc; |
888 | machine_name = mdesc->name; | 891 | machine_name = mdesc->name; |
889 | 892 | ||
893 | #ifdef CONFIG_ZONE_DMA | ||
894 | if (mdesc->dma_zone_size) { | ||
895 | extern unsigned long arm_dma_zone_size; | ||
896 | arm_dma_zone_size = mdesc->dma_zone_size; | ||
897 | } | ||
898 | #endif | ||
890 | if (mdesc->soft_reboot) | 899 | if (mdesc->soft_reboot) |
891 | reboot_setup("s"); | 900 | reboot_setup("s"); |
892 | 901 | ||
@@ -915,7 +924,6 @@ void __init setup_arch(char **cmdline_p) | |||
915 | #endif | 924 | #endif |
916 | reserve_crashkernel(); | 925 | reserve_crashkernel(); |
917 | 926 | ||
918 | cpu_init(); | ||
919 | tcm_init(); | 927 | tcm_init(); |
920 | 928 | ||
921 | #ifdef CONFIG_MULTI_IRQ_HANDLER | 929 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
@@ -979,6 +987,10 @@ static const char *hwcap_str[] = { | |||
979 | "neon", | 987 | "neon", |
980 | "vfpv3", | 988 | "vfpv3", |
981 | "vfpv3d16", | 989 | "vfpv3d16", |
990 | "tls", | ||
991 | "vfpv4", | ||
992 | "idiva", | ||
993 | "idivt", | ||
982 | NULL | 994 | NULL |
983 | }; | 995 | }; |
984 | 996 | ||
@@ -990,7 +1002,11 @@ static int c_show(struct seq_file *m, void *v) | |||
990 | cpu_name, read_cpuid_id() & 15, elf_platform); | 1002 | cpu_name, read_cpuid_id() & 15, elf_platform); |
991 | 1003 | ||
992 | #if defined(CONFIG_SMP) | 1004 | #if defined(CONFIG_SMP) |
1005 | # if defined(CONFIG_REPORT_PRESENT_CPUS) | ||
1006 | for_each_present_cpu(i) { | ||
1007 | # else | ||
993 | for_each_online_cpu(i) { | 1008 | for_each_online_cpu(i) { |
1009 | # endif | ||
994 | /* | 1010 | /* |
995 | * glibc reads /proc/cpuinfo to determine the number of | 1011 | * glibc reads /proc/cpuinfo to determine the number of |
996 | * online processors, looking for lines beginning with | 1012 | * online processors, looking for lines beginning with |