diff options
Diffstat (limited to 'arch/arm/kernel/perf_event_v7.c')
-rw-r--r-- | arch/arm/kernel/perf_event_v7.c | 145 |
1 files changed, 145 insertions, 0 deletions
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 460bbbb6b88..b2b764ec011 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c | |||
@@ -582,6 +582,130 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | |||
582 | }; | 582 | }; |
583 | 583 | ||
584 | /* | 584 | /* |
585 | * Cortex-A7 HW events mapping | ||
586 | */ | ||
587 | static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = { | ||
588 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, | ||
589 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, | ||
590 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, | ||
591 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, | ||
592 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, | ||
593 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
594 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, | ||
595 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED, | ||
596 | [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED, | ||
597 | }; | ||
598 | |||
599 | static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
600 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
601 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
602 | [C(L1D)] = { | ||
603 | /* | ||
604 | * The performance counters don't differentiate between read | ||
605 | * and write accesses/misses so this isn't strictly correct, | ||
606 | * but it's the best we can do. Writes and reads get | ||
607 | * combined. | ||
608 | */ | ||
609 | [C(OP_READ)] = { | ||
610 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, | ||
611 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, | ||
612 | }, | ||
613 | [C(OP_WRITE)] = { | ||
614 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, | ||
615 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, | ||
616 | }, | ||
617 | [C(OP_PREFETCH)] = { | ||
618 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
619 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
620 | }, | ||
621 | }, | ||
622 | [C(L1I)] = { | ||
623 | [C(OP_READ)] = { | ||
624 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, | ||
625 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, | ||
626 | }, | ||
627 | [C(OP_WRITE)] = { | ||
628 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, | ||
629 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, | ||
630 | }, | ||
631 | [C(OP_PREFETCH)] = { | ||
632 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
633 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
634 | }, | ||
635 | }, | ||
636 | [C(LL)] = { | ||
637 | [C(OP_READ)] = { | ||
638 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, | ||
639 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, | ||
640 | }, | ||
641 | [C(OP_WRITE)] = { | ||
642 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, | ||
643 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, | ||
644 | }, | ||
645 | [C(OP_PREFETCH)] = { | ||
646 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
647 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
648 | }, | ||
649 | }, | ||
650 | [C(DTLB)] = { | ||
651 | [C(OP_READ)] = { | ||
652 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
653 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
654 | }, | ||
655 | [C(OP_WRITE)] = { | ||
656 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
657 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
658 | }, | ||
659 | [C(OP_PREFETCH)] = { | ||
660 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
661 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
662 | }, | ||
663 | }, | ||
664 | [C(ITLB)] = { | ||
665 | [C(OP_READ)] = { | ||
666 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
667 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, | ||
668 | }, | ||
669 | [C(OP_WRITE)] = { | ||
670 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
671 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, | ||
672 | }, | ||
673 | [C(OP_PREFETCH)] = { | ||
674 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
675 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
676 | }, | ||
677 | }, | ||
678 | [C(BPU)] = { | ||
679 | [C(OP_READ)] = { | ||
680 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, | ||
681 | [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
682 | }, | ||
683 | [C(OP_WRITE)] = { | ||
684 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, | ||
685 | [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
686 | }, | ||
687 | [C(OP_PREFETCH)] = { | ||
688 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
689 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
690 | }, | ||
691 | }, | ||
692 | [C(NODE)] = { | ||
693 | [C(OP_READ)] = { | ||
694 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
695 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
696 | }, | ||
697 | [C(OP_WRITE)] = { | ||
698 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
699 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
700 | }, | ||
701 | [C(OP_PREFETCH)] = { | ||
702 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
703 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
704 | }, | ||
705 | }, | ||
706 | }; | ||
707 | |||
708 | /* | ||
585 | * Perf Events' indices | 709 | * Perf Events' indices |
586 | */ | 710 | */ |
587 | #define ARMV7_IDX_CYCLE_COUNTER 0 | 711 | #define ARMV7_IDX_CYCLE_COUNTER 0 |
@@ -1067,6 +1191,12 @@ static int armv7_a15_map_event(struct perf_event *event) | |||
1067 | &armv7_a15_perf_cache_map, 0xFF); | 1191 | &armv7_a15_perf_cache_map, 0xFF); |
1068 | } | 1192 | } |
1069 | 1193 | ||
1194 | static int armv7_a7_map_event(struct perf_event *event) | ||
1195 | { | ||
1196 | return map_cpu_event(event, &armv7_a7_perf_map, | ||
1197 | &armv7_a7_perf_cache_map, 0xFF); | ||
1198 | } | ||
1199 | |||
1070 | static struct arm_pmu armv7pmu = { | 1200 | static struct arm_pmu armv7pmu = { |
1071 | .handle_irq = armv7pmu_handle_irq, | 1201 | .handle_irq = armv7pmu_handle_irq, |
1072 | .enable = armv7pmu_enable_event, | 1202 | .enable = armv7pmu_enable_event, |
@@ -1127,6 +1257,16 @@ static struct arm_pmu *__init armv7_a15_pmu_init(void) | |||
1127 | armv7pmu.set_event_filter = armv7pmu_set_event_filter; | 1257 | armv7pmu.set_event_filter = armv7pmu_set_event_filter; |
1128 | return &armv7pmu; | 1258 | return &armv7pmu; |
1129 | } | 1259 | } |
1260 | |||
1261 | static struct arm_pmu *__init armv7_a7_pmu_init(void) | ||
1262 | { | ||
1263 | armv7pmu.id = ARM_PERF_PMU_ID_CA7; | ||
1264 | armv7pmu.name = "ARMv7 Cortex-A7"; | ||
1265 | armv7pmu.map_event = armv7_a7_map_event; | ||
1266 | armv7pmu.num_events = armv7_read_num_pmnc_events(); | ||
1267 | armv7pmu.set_event_filter = armv7pmu_set_event_filter; | ||
1268 | return &armv7pmu; | ||
1269 | } | ||
1130 | #else | 1270 | #else |
1131 | static struct arm_pmu *__init armv7_a8_pmu_init(void) | 1271 | static struct arm_pmu *__init armv7_a8_pmu_init(void) |
1132 | { | 1272 | { |
@@ -1147,4 +1287,9 @@ static struct arm_pmu *__init armv7_a15_pmu_init(void) | |||
1147 | { | 1287 | { |
1148 | return NULL; | 1288 | return NULL; |
1149 | } | 1289 | } |
1290 | |||
1291 | static struct arm_pmu *__init armv7_a7_pmu_init(void) | ||
1292 | { | ||
1293 | return NULL; | ||
1294 | } | ||
1150 | #endif /* CONFIG_CPU_V7 */ | 1295 | #endif /* CONFIG_CPU_V7 */ |