1 files changed, 52 insertions, 83 deletions

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 742b6108a00..239703dbdf4 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -21,6 +21,7 @@
 #include <asm/memory.h>
 #include <asm/thread_info.h>
 #include <asm/system.h>
+#include <asm/pgtable.h>
 
 #ifdef CONFIG_DEBUG_LL
 #include <mach/debug-macro.S>
@@ -38,11 +39,14 @@
 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
 #endif
 
+#define PG_DIR_SIZE     0x4000
+#define PMD_ORDER       2
+
         .globl  swapper_pg_dir
-        .equ    swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
+        .equ    swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
 
         .macro  pgtbl, rd, phys
-        add     \rd, \phys, #TEXT_OFFSET - 0x4000
+        add     \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
         .endm
 
 #ifdef CONFIG_XIP_KERNEL
@@ -148,11 +152,11 @@ __create_page_tables:
         pgtbl   r4, r8                          @ page table address
 
         /*
-         * Clear the 16K level 1 swapper page table
+         * Clear the swapper page table
          */
         mov     r0, r4
         mov     r3, #0
-        add     r6, r0, #0x4000
+        add     r6, r0, #PG_DIR_SIZE
 1:      str     r3, [r0], #4
         str     r3, [r0], #4
         str     r3, [r0], #4
@@ -171,30 +175,30 @@ __create_page_tables:
         sub     r0, r0, r3                      @ virt->phys offset
         add     r5, r5, r0                      @ phys __enable_mmu
         add     r6, r6, r0                      @ phys __enable_mmu_end
-        mov     r5, r5, lsr #20
-        mov     r6, r6, lsr #20
+        mov     r5, r5, lsr #SECTION_SHIFT
+        mov     r6, r6, lsr #SECTION_SHIFT
 
-1:      orr     r3, r7, r5, lsl #20             @ flags + kernel base
-        str     r3, [r4, r5, lsl #2]            @ identity mapping
-        teq     r5, r6
-        addne   r5, r5, #1                      @ next section
-        bne     1b
+1:      orr     r3, r7, r5, lsl #SECTION_SHIFT  @ flags + kernel base
+        str     r3, [r4, r5, lsl #PMD_ORDER]    @ identity mapping
+        cmp     r5, r6
+        addlo   r5, r5, #1                      @ next section
+        blo     1b
 
         /*
          * Now setup the pagetables for our kernel direct
          * mapped region.
          */
         mov     r3, pc
-        mov     r3, r3, lsr #20
-        orr     r3, r7, r3, lsl #20
-        add     r0, r4,  #(KERNEL_START & 0xff000000) >> 18
-        str     r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
+        mov     r3, r3, lsr #SECTION_SHIFT
+        orr     r3, r7, r3, lsl #SECTION_SHIFT
+        add     r0, r4,  #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
+        str     r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
         ldr     r6, =(KERNEL_END - 1)
-        add     r0, r0, #4
-        add     r6, r4, r6, lsr #18
+        add     r0, r0, #1 << PMD_ORDER
+        add     r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
 1:      cmp     r0, r6
-        add     r3, r3, #1 << 20
-        strls   r3, [r0], #4
+        add     r3, r3, #1 << SECTION_SHIFT
+        strls   r3, [r0], #1 << PMD_ORDER
         bls     1b
 
 #ifdef CONFIG_XIP_KERNEL
@@ -203,11 +207,11 @@ __create_page_tables:
          */
         add     r3, r8, #TEXT_OFFSET
         orr     r3, r3, r7
-        add     r0, r4,  #(KERNEL_RAM_VADDR & 0xff000000) >> 18
-        str     r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
+        add     r0, r4,  #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
+        str     r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]!
         ldr     r6, =(_end - 1)
         add     r0, r0, #4
-        add     r6, r4, r6, lsr #18
+        add     r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
 1:      cmp     r0, r6
         add     r3, r3, #1 << 20
         strls   r3, [r0], #4
@@ -218,12 +222,12 @@ __create_page_tables:
          * Then map boot params address in r2 or
          * the first 1MB of ram if boot params address is not specified.
          */
-        mov     r0, r2, lsr #20
-        movs    r0, r0, lsl #20
+        mov     r0, r2, lsr #SECTION_SHIFT
+        movs    r0, r0, lsl #SECTION_SHIFT
         moveq   r0, r8
         sub     r3, r0, r8
         add     r3, r3, #PAGE_OFFSET
-        add     r3, r4, r3, lsr #18
+        add     r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
         orr     r6, r7, r0
         str     r6, [r3]
 
@@ -236,21 +240,21 @@ __create_page_tables:
          */
         addruart r7, r3
 
-        mov     r3, r3, lsr #20
-        mov     r3, r3, lsl #2
+        mov     r3, r3, lsr #SECTION_SHIFT
+        mov     r3, r3, lsl #PMD_ORDER
 
         add     r0, r4, r3
         rsb     r3, r3, #0x4000                 @ PTRS_PER_PGD*sizeof(long)
         cmp     r3, #0x0800                     @ limit to 512MB
         movhi   r3, #0x0800
         add     r6, r0, r3
-        mov     r3, r7, lsr #20
+        mov     r3, r7, lsr #SECTION_SHIFT
         ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
-        orr     r3, r7, r3, lsl #20
+        orr     r3, r7, r3, lsl #SECTION_SHIFT
 1:      str     r3, [r0], #4
-        add     r3, r3, #1 << 20
-        teq     r0, r6
-        bne     1b
+        add     r3, r3, #1 << SECTION_SHIFT
+        cmp     r0, r6
+        blo     1b
 
 #else /* CONFIG_DEBUG_ICEDCC */
         /* we don't need any serial debugging mappings for ICEDCC */
@@ -262,7 +266,7 @@ __create_page_tables:
          * If we're using the NetWinder or CATS, we also need to map
          * in the 16550-type serial port for the debug messages
          */
-        add     r0, r4, #0xff000000 >> 18
+        add     r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
         orr     r3, r7, #0x7c000000
         str     r3, [r0]
 #endif
@@ -272,10 +276,10 @@ __create_page_tables:
          * Similar reasons here - for debug.  This is
          * only for Acorn RiscPC architectures.
          */
-        add     r0, r4, #0x02000000 >> 18
+        add     r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
         orr     r3, r7, #0x02000000
         str     r3, [r0]
-        add     r0, r4, #0xd8000000 >> 18
+        add     r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
         str     r3, [r0]
 #endif
 #endif
@@ -488,13 +492,8 @@ __fixup_pv_table:
         add     r5, r5, r3      @ adjust table end address
         add     r7, r7, r3      @ adjust __pv_phys_offset address
         str     r8, [r7]        @ save computed PHYS_OFFSET to __pv_phys_offset
-#ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
         mov     r6, r3, lsr #24 @ constant for add/sub instructions
         teq     r3, r6, lsl #24 @ must be 16MiB aligned
-#else
-        mov     r6, r3, lsr #16 @ constant for add/sub instructions
-        teq     r3, r6, lsl #16 @ must be 64kiB aligned
-#endif
 THUMB(  it      ne              @ cross section branch )
         bne     __error
         str     r6, [r7, #4]    @ save to __pv_offset
@@ -510,20 +509,8 @@ ENDPROC(__fixup_pv_table)
         .text
 __fixup_a_pv_table:
 #ifdef CONFIG_THUMB2_KERNEL
-#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
-        lsls    r0, r6, #24
-        lsr     r6, #8
-        beq     1f
-        clz     r7, r0
-        lsr     r0, #24
-        lsl     r0, r7
-        bic     r0, 0x0080
-        lsrs    r7, #1
-        orrcs   r0, #0x0080
-        orr     r0, r0, r7, lsl #12
-#endif
-1:      lsls    r6, #24
-        beq     4f
+        lsls    r6, #24
+        beq     2f
         clz     r7, r6
         lsr     r6, #24
         lsl     r6, r7
@@ -532,43 +519,25 @@ __fixup_a_pv_table:
         orrcs   r6, #0x0080
         orr     r6, r6, r7, lsl #12
         orr     r6, #0x4000
-        b       4f
-2:      @ at this point the C flag is always clear
-        add     r7, r3
-#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
-        ldrh    ip, [r7]
-        tst     ip, 0x0400      @ the i bit tells us LS or MS byte
-        beq     3f
-        cmp     r0, #0          @ set C flag, and ...
-        biceq   ip, 0x0400      @ immediate zero value has a special encoding
-        streqh  ip, [r7]        @ that requires the i bit cleared
-#endif
-3:      ldrh    ip, [r7, #2]
+        b       2f
+1:      add     r7, r3
+        ldrh    ip, [r7, #2]
         and     ip, 0x8f00
-        orrcc   ip, r6  @ mask in offset bits 31-24
-        orrcs   ip, r0  @ mask in offset bits 23-16
+        orr     ip, r6  @ mask in offset bits 31-24
         strh    ip, [r7, #2]
-4:      cmp     r4, r5
+2:      cmp     r4, r5
         ldrcc   r7, [r4], #4    @ use branch for delay slot
-        bcc     2b
+        bcc     1b
         bx      lr
 #else
-#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
-        and     r0, r6, #255    @ offset bits 23-16
-        mov     r6, r6, lsr #8  @ offset bits 31-24
-#else
-        mov     r0, #0          @ just in case...
-#endif
-        b       3f
-2:      ldr     ip, [r7, r3]
+        b       2f
+1:      ldr     ip, [r7, r3]
         bic     ip, ip, #0x000000ff
-        tst     ip, #0x400      @ rotate shift tells us LS or MS byte
-        orrne   ip, ip, r6      @ mask in offset bits 31-24
-        orreq   ip, ip, r0      @ mask in offset bits 23-16
+        orr     ip, ip, r6      @ mask in offset bits 31-24
         str     ip, [r7, r3]
-3:      cmp     r4, r5
+2:      cmp     r4, r5
         ldrcc   r7, [r4], #4    @ use branch for delay slot
-        bcc     2b
+        bcc     1b
         mov     pc, lr
 #endif
 ENDPROC(__fixup_a_pv_table)