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-rw-r--r--arch/arm/include/asm/assembler.h14
-rw-r--r--arch/arm/include/asm/atomic.h10
-rw-r--r--arch/arm/include/asm/bitops.h9
-rw-r--r--arch/arm/include/asm/cacheflush.h51
-rw-r--r--arch/arm/include/asm/clkdev.h5
-rw-r--r--arch/arm/include/asm/cpu_pm.h123
-rw-r--r--arch/arm/include/asm/delay.h4
-rw-r--r--arch/arm/include/asm/dma-mapping.h88
-rw-r--r--arch/arm/include/asm/dma.h11
-rw-r--r--arch/arm/include/asm/elf.h1
-rw-r--r--arch/arm/include/asm/entry-macro-multi.S14
-rw-r--r--arch/arm/include/asm/fiq_debugger.h64
-rw-r--r--arch/arm/include/asm/fiq_glue.h30
-rw-r--r--arch/arm/include/asm/futex.h34
-rw-r--r--arch/arm/include/asm/gpio.h4
-rw-r--r--arch/arm/include/asm/hardirq.h2
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h17
-rw-r--r--arch/arm/include/asm/hardware/coresight.h26
-rw-r--r--arch/arm/include/asm/hardware/gic.h15
-rw-r--r--arch/arm/include/asm/hardware/it8152.h2
-rw-r--r--arch/arm/include/asm/hardware/scoop.h1
-rw-r--r--arch/arm/include/asm/hwcap.h36
-rw-r--r--arch/arm/include/asm/i8253.h15
-rw-r--r--arch/arm/include/asm/irq.h4
-rw-r--r--arch/arm/include/asm/kprobes.h28
-rw-r--r--arch/arm/include/asm/localtimer.h2
-rw-r--r--arch/arm/include/asm/mach/arch.h11
-rw-r--r--arch/arm/include/asm/mach/mmc.h28
-rw-r--r--arch/arm/include/asm/mach/pci.h4
-rw-r--r--arch/arm/include/asm/memory.h16
-rw-r--r--arch/arm/include/asm/page.h2
-rw-r--r--arch/arm/include/asm/pci.h12
-rw-r--r--arch/arm/include/asm/perf_event.h2
-rw-r--r--arch/arm/include/asm/pgalloc.h4
-rw-r--r--arch/arm/include/asm/pgtable.h25
-rw-r--r--arch/arm/include/asm/pmu.h12
-rw-r--r--arch/arm/include/asm/proc-fns.h14
-rw-r--r--arch/arm/include/asm/prom.h5
-rw-r--r--arch/arm/include/asm/ptrace.h11
-rw-r--r--arch/arm/include/asm/scatterlist.h4
-rw-r--r--arch/arm/include/asm/setup.h8
-rw-r--r--arch/arm/include/asm/sizes.h3
-rw-r--r--arch/arm/include/asm/smp.h2
-rw-r--r--arch/arm/include/asm/suspend.h22
-rw-r--r--arch/arm/include/asm/tcm.h2
-rw-r--r--arch/arm/include/asm/tlbflush.h58
-rw-r--r--arch/arm/include/asm/traps.h3
-rw-r--r--arch/arm/include/asm/unistd.h4
-rw-r--r--arch/arm/include/asm/vga.h5
49 files changed, 592 insertions, 275 deletions
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 65c3f2474f5..7bb8bf972c0 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -137,6 +137,11 @@
137 disable_irq 137 disable_irq
138 .endm 138 .endm
139 139
140 .macro save_and_disable_irqs_notrace, oldcpsr
141 mrs \oldcpsr, cpsr
142 disable_irq_notrace
143 .endm
144
140/* 145/*
141 * Restore interrupt state previously stored in a register. We don't 146 * Restore interrupt state previously stored in a register. We don't
142 * guarantee that this will preserve the flags. 147 * guarantee that this will preserve the flags.
@@ -293,4 +298,13 @@
293 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 298 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
294 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 299 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
295 .endm 300 .endm
301
302/* Utility macro for declaring string literals */
303 .macro string name:req, string
304 .type \name , #object
305\name:
306 .asciz "\string"
307 .size \name , . - \name
308 .endm
309
296#endif /* __ASM_ASSEMBLER_H__ */ 310#endif /* __ASM_ASSEMBLER_H__ */
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 7e79503ab89..86976d03438 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -208,16 +208,15 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
208 208
209#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) 209#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
210 210
211static inline int atomic_add_unless(atomic_t *v, int a, int u) 211static inline int __atomic_add_unless(atomic_t *v, int a, int u)
212{ 212{
213 int c, old; 213 int c, old;
214 214
215 c = atomic_read(v); 215 c = atomic_read(v);
216 while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c) 216 while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
217 c = old; 217 c = old;
218 return c != u; 218 return c;
219} 219}
220#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
221 220
222#define atomic_inc(v) atomic_add(1, v) 221#define atomic_inc(v) atomic_add(1, v)
223#define atomic_dec(v) atomic_sub(1, v) 222#define atomic_dec(v) atomic_sub(1, v)
@@ -460,9 +459,6 @@ static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
460#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0) 459#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
461#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL) 460#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
462 461
463#else /* !CONFIG_GENERIC_ATOMIC64 */ 462#endif /* !CONFIG_GENERIC_ATOMIC64 */
464#include <asm-generic/atomic64.h>
465#endif
466#include <asm-generic/atomic-long.h>
467#endif 463#endif
468#endif 464#endif
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index b4892a06442..f7419ef9c8f 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -26,8 +26,8 @@
26#include <linux/compiler.h> 26#include <linux/compiler.h>
27#include <asm/system.h> 27#include <asm/system.h>
28 28
29#define smp_mb__before_clear_bit() mb() 29#define smp_mb__before_clear_bit() smp_mb()
30#define smp_mb__after_clear_bit() mb() 30#define smp_mb__after_clear_bit() smp_mb()
31 31
32/* 32/*
33 * These functions are the basis of our bit ops. 33 * These functions are the basis of our bit ops.
@@ -310,10 +310,7 @@ static inline int find_next_bit_le(const void *p, int size, int offset)
310/* 310/*
311 * Ext2 is defined to use little-endian byte ordering. 311 * Ext2 is defined to use little-endian byte ordering.
312 */ 312 */
313#define ext2_set_bit_atomic(lock, nr, p) \ 313#include <asm-generic/bitops/ext2-atomic-setbit.h>
314 test_and_set_bit_le(nr, p)
315#define ext2_clear_bit_atomic(lock, nr, p) \
316 test_and_clear_bit_le(nr, p)
317 314
318#endif /* __KERNEL__ */ 315#endif /* __KERNEL__ */
319 316
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index d5d8d5c7268..f91a748d073 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -249,7 +249,7 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr
249 * Harvard caches are synchronised for the user space address range. 249 * Harvard caches are synchronised for the user space address range.
250 * This is used for the ARM private sys_cacheflush system call. 250 * This is used for the ARM private sys_cacheflush system call.
251 */ 251 */
252#define flush_cache_user_range(vma,start,end) \ 252#define flush_cache_user_range(start,end) \
253 __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) 253 __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
254 254
255/* 255/*
@@ -344,4 +344,53 @@ static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
344 flush_cache_all(); 344 flush_cache_all();
345} 345}
346 346
347/*
348 * The set_memory_* API can be used to change various attributes of a virtual
349 * address range. The attributes include:
350 * Cachability : UnCached, WriteCombining, WriteBack
351 * Executability : eXeutable, NoteXecutable
352 * Read/Write : ReadOnly, ReadWrite
353 * Presence : NotPresent
354 *
355 * Within a catagory, the attributes are mutually exclusive.
356 *
357 * The implementation of this API will take care of various aspects that
358 * are associated with changing such attributes, such as:
359 * - Flushing TLBs
360 * - Flushing CPU caches
361 * - Making sure aliases of the memory behind the mapping don't violate
362 * coherency rules as defined by the CPU in the system.
363 *
364 * What this API does not do:
365 * - Provide exclusion between various callers - including callers that
366 * operation on other mappings of the same physical page
367 * - Restore default attributes when a page is freed
368 * - Guarantee that mappings other than the requested one are
369 * in any state, other than that these do not violate rules for
370 * the CPU you have. Do not depend on any effects on other mappings,
371 * CPUs other than the one you have may have more relaxed rules.
372 * The caller is required to take care of these.
373 */
374
375int set_memory_uc(unsigned long addr, int numpages);
376int set_memory_wc(unsigned long addr, int numpages);
377int set_memory_wb(unsigned long addr, int numpages);
378int set_memory_iwb(unsigned long addr, int numpages);
379int set_memory_x(unsigned long addr, int numpages);
380int set_memory_nx(unsigned long addr, int numpages);
381int set_memory_ro(unsigned long addr, int numpages);
382int set_memory_rw(unsigned long addr, int numpages);
383int set_memory_np(unsigned long addr, int numpages);
384int set_memory_4k(unsigned long addr, int numpages);
385
386int set_memory_array_uc(unsigned long *addr, int addrinarray);
387int set_memory_array_wc(unsigned long *addr, int addrinarray);
388int set_memory_array_wb(unsigned long *addr, int addrinarray);
389int set_memory_array_iwb(unsigned long *addr, int addrinarray);
390
391int set_pages_array_uc(struct page **pages, int addrinarray);
392int set_pages_array_wc(struct page **pages, int addrinarray);
393int set_pages_array_wb(struct page **pages, int addrinarray);
394int set_pages_array_iwb(struct page **pages, int addrinarray);
395
347#endif 396#endif
diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h
index 765d3322236..80751c15c30 100644
--- a/arch/arm/include/asm/clkdev.h
+++ b/arch/arm/include/asm/clkdev.h
@@ -14,7 +14,12 @@
14 14
15#include <linux/slab.h> 15#include <linux/slab.h>
16 16
17#ifdef CONFIG_HAVE_MACH_CLKDEV
17#include <mach/clkdev.h> 18#include <mach/clkdev.h>
19#else
20#define __clk_get(clk) ({ 1; })
21#define __clk_put(clk) do { } while (0)
22#endif
18 23
19static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) 24static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
20{ 25{
diff --git a/arch/arm/include/asm/cpu_pm.h b/arch/arm/include/asm/cpu_pm.h
new file mode 100644
index 00000000000..07b1b6ec025
--- /dev/null
+++ b/arch/arm/include/asm/cpu_pm.h
@@ -0,0 +1,123 @@
1/*
2 * Copyright (C) 2011 Google, Inc.
3 *
4 * Author:
5 * Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef _ASMARM_CPU_PM_H
19#define _ASMARM_CPU_PM_H
20
21#include <linux/kernel.h>
22#include <linux/notifier.h>
23
24/*
25 * When a CPU goes to a low power state that turns off power to the CPU's
26 * power domain, the contents of some blocks (floating point coprocessors,
27 * interrutp controllers, caches, timers) in the same power domain can
28 * be lost. The cpm_pm notifiers provide a method for platform idle, suspend,
29 * and hotplug implementations to notify the drivers for these blocks that
30 * they may be reset.
31 *
32 * All cpu_pm notifications must be called with interrupts disabled.
33 *
34 * The notifications are split into two classes, CPU notifications and CPU
35 * complex notifications.
36 *
37 * CPU notifications apply to a single CPU, and must be called on the affected
38 * CPU. They are used to save per-cpu context for affected blocks.
39 *
40 * CPU complex notifications apply to all CPUs in a single power domain. They
41 * are used to save any global context for affected blocks, and must be called
42 * after all the CPUs in the power domain have been notified of the low power
43 * state.
44 *
45 */
46
47/*
48 * Event codes passed as unsigned long val to notifier calls
49 */
50enum cpu_pm_event {
51 /* A single cpu is entering a low power state */
52 CPU_PM_ENTER,
53
54 /* A single cpu failed to enter a low power state */
55 CPU_PM_ENTER_FAILED,
56
57 /* A single cpu is exiting a low power state */
58 CPU_PM_EXIT,
59
60 /* A cpu power domain is entering a low power state */
61 CPU_COMPLEX_PM_ENTER,
62
63 /* A cpu power domain failed to enter a low power state */
64 CPU_COMPLEX_PM_ENTER_FAILED,
65
66 /* A cpu power domain is exiting a low power state */
67 CPU_COMPLEX_PM_EXIT,
68};
69
70int cpu_pm_register_notifier(struct notifier_block *nb);
71int cpu_pm_unregister_notifier(struct notifier_block *nb);
72
73/*
74 * cpm_pm_enter
75 *
76 * Notifies listeners that a single cpu is entering a low power state that may
77 * cause some blocks in the same power domain as the cpu to reset.
78 *
79 * Must be called on the affected cpu with interrupts disabled. Platform is
80 * responsible for ensuring that cpu_pm_enter is not called twice on the same
81 * cpu before cpu_pm_exit is called.
82 */
83int cpu_pm_enter(void);
84
85/*
86 * cpm_pm_exit
87 *
88 * Notifies listeners that a single cpu is exiting a low power state that may
89 * have caused some blocks in the same power domain as the cpu to reset.
90 *
91 * Must be called on the affected cpu with interrupts disabled.
92 */
93int cpu_pm_exit(void);
94
95/*
96 * cpm_complex_pm_enter
97 *
98 * Notifies listeners that all cpus in a power domain are entering a low power
99 * state that may cause some blocks in the same power domain to reset.
100 *
101 * Must be called after cpu_pm_enter has been called on all cpus in the power
102 * domain, and before cpu_pm_exit has been called on any cpu in the power
103 * domain.
104 *
105 * Must be called with interrupts disabled.
106 */
107int cpu_complex_pm_enter(void);
108
109/*
110 * cpm_pm_enter
111 *
112 * Notifies listeners that a single cpu is entering a low power state that may
113 * cause some blocks in the same power domain as the cpu to reset.
114 *
115 * Must be called after cpu_pm_enter has been called on all cpus in the power
116 * domain, and before cpu_pm_exit has been called on any cpu in the power
117 * domain.
118 *
119 * Must be called with interrupts disabled.
120 */
121int cpu_complex_pm_exit(void);
122
123#endif
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index b2deda18154..57f1fa0e983 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -8,6 +8,9 @@
8 8
9#include <asm/param.h> /* HZ */ 9#include <asm/param.h> /* HZ */
10 10
11#ifdef CONFIG_ARCH_PROVIDES_UDELAY
12#include <mach/delay.h>
13#else
11extern void __delay(int loops); 14extern void __delay(int loops);
12 15
13/* 16/*
@@ -40,5 +43,6 @@ extern void __const_udelay(unsigned long);
40 __const_udelay((n) * ((2199023U*HZ)>>11))) : \ 43 __const_udelay((n) * ((2199023U*HZ)>>11))) : \
41 __udelay(n)) 44 __udelay(n))
42 45
46#endif /* defined(ARCH_PROVIDES_UDELAY) */
43#endif /* defined(_ARM_DELAY_H) */ 47#endif /* defined(_ARM_DELAY_H) */
44 48
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 4fff837363e..7a21d0bf713 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -115,39 +115,8 @@ static inline void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
115 ___dma_page_dev_to_cpu(page, off, size, dir); 115 ___dma_page_dev_to_cpu(page, off, size, dir);
116} 116}
117 117
118/* 118extern int dma_supported(struct device *, u64);
119 * Return whether the given device DMA address mask can be supported 119extern int dma_set_mask(struct device *, u64);
120 * properly. For example, if your device can only drive the low 24-bits
121 * during bus mastering, then you would pass 0x00ffffff as the mask
122 * to this function.
123 *
124 * FIXME: This should really be a platform specific issue - we should
125 * return false if GFP_DMA allocations may not satisfy the supplied 'mask'.
126 */
127static inline int dma_supported(struct device *dev, u64 mask)
128{
129 if (mask < ISA_DMA_THRESHOLD)
130 return 0;
131 return 1;
132}
133
134static inline int dma_set_mask(struct device *dev, u64 dma_mask)
135{
136#ifdef CONFIG_DMABOUNCE
137 if (dev->archdata.dmabounce) {
138 if (dma_mask >= ISA_DMA_THRESHOLD)
139 return 0;
140 else
141 return -EIO;
142 }
143#endif
144 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
145 return -EIO;
146
147 *dev->dma_mask = dma_mask;
148
149 return 0;
150}
151 120
152/* 121/*
153 * DMA errors are defined by all-bits-set in the DMA address. 122 * DMA errors are defined by all-bits-set in the DMA address.
@@ -256,14 +225,14 @@ int dma_mmap_writecombine(struct device *, struct vm_area_struct *,
256 * @dev: valid struct device pointer 225 * @dev: valid struct device pointer
257 * @small_buf_size: size of buffers to use with small buffer pool 226 * @small_buf_size: size of buffers to use with small buffer pool
258 * @large_buf_size: size of buffers to use with large buffer pool (can be 0) 227 * @large_buf_size: size of buffers to use with large buffer pool (can be 0)
228 * @needs_bounce_fn: called to determine whether buffer needs bouncing
259 * 229 *
260 * This function should be called by low-level platform code to register 230 * This function should be called by low-level platform code to register
261 * a device as requireing DMA buffer bouncing. The function will allocate 231 * a device as requireing DMA buffer bouncing. The function will allocate
262 * appropriate DMA pools for the device. 232 * appropriate DMA pools for the device.
263 *
264 */ 233 */
265extern int dmabounce_register_dev(struct device *, unsigned long, 234extern int dmabounce_register_dev(struct device *, unsigned long,
266 unsigned long); 235 unsigned long, int (*)(struct device *, dma_addr_t, size_t));
267 236
268/** 237/**
269 * dmabounce_unregister_dev 238 * dmabounce_unregister_dev
@@ -277,31 +246,9 @@ extern int dmabounce_register_dev(struct device *, unsigned long,
277 */ 246 */
278extern void dmabounce_unregister_dev(struct device *); 247extern void dmabounce_unregister_dev(struct device *);
279 248
280/**
281 * dma_needs_bounce
282 *
283 * @dev: valid struct device pointer
284 * @dma_handle: dma_handle of unbounced buffer
285 * @size: size of region being mapped
286 *
287 * Platforms that utilize the dmabounce mechanism must implement
288 * this function.
289 *
290 * The dmabounce routines call this function whenever a dma-mapping
291 * is requested to determine whether a given buffer needs to be bounced
292 * or not. The function must return 0 if the buffer is OK for
293 * DMA access and 1 if the buffer needs to be bounced.
294 *
295 */
296extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
297
298/* 249/*
299 * The DMA API, implemented by dmabounce.c. See below for descriptions. 250 * The DMA API, implemented by dmabounce.c. See below for descriptions.
300 */ 251 */
301extern dma_addr_t __dma_map_single(struct device *, void *, size_t,
302 enum dma_data_direction);
303extern void __dma_unmap_single(struct device *, dma_addr_t, size_t,
304 enum dma_data_direction);
305extern dma_addr_t __dma_map_page(struct device *, struct page *, 252extern dma_addr_t __dma_map_page(struct device *, struct page *,
306 unsigned long, size_t, enum dma_data_direction); 253 unsigned long, size_t, enum dma_data_direction);
307extern void __dma_unmap_page(struct device *, dma_addr_t, size_t, 254extern void __dma_unmap_page(struct device *, dma_addr_t, size_t,
@@ -328,13 +275,6 @@ static inline int dmabounce_sync_for_device(struct device *d, dma_addr_t addr,
328} 275}
329 276
330 277
331static inline dma_addr_t __dma_map_single(struct device *dev, void *cpu_addr,
332 size_t size, enum dma_data_direction dir)
333{
334 __dma_single_cpu_to_dev(cpu_addr, size, dir);
335 return virt_to_dma(dev, cpu_addr);
336}
337
338static inline dma_addr_t __dma_map_page(struct device *dev, struct page *page, 278static inline dma_addr_t __dma_map_page(struct device *dev, struct page *page,
339 unsigned long offset, size_t size, enum dma_data_direction dir) 279 unsigned long offset, size_t size, enum dma_data_direction dir)
340{ 280{
@@ -342,12 +282,6 @@ static inline dma_addr_t __dma_map_page(struct device *dev, struct page *page,
342 return pfn_to_dma(dev, page_to_pfn(page)) + offset; 282 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
343} 283}
344 284
345static inline void __dma_unmap_single(struct device *dev, dma_addr_t handle,
346 size_t size, enum dma_data_direction dir)
347{
348 __dma_single_dev_to_cpu(dma_to_virt(dev, handle), size, dir);
349}
350
351static inline void __dma_unmap_page(struct device *dev, dma_addr_t handle, 285static inline void __dma_unmap_page(struct device *dev, dma_addr_t handle,
352 size_t size, enum dma_data_direction dir) 286 size_t size, enum dma_data_direction dir)
353{ 287{
@@ -373,14 +307,18 @@ static inline void __dma_unmap_page(struct device *dev, dma_addr_t handle,
373static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, 307static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
374 size_t size, enum dma_data_direction dir) 308 size_t size, enum dma_data_direction dir)
375{ 309{
310 unsigned long offset;
311 struct page *page;
376 dma_addr_t addr; 312 dma_addr_t addr;
377 313
314 BUG_ON(!virt_addr_valid(cpu_addr));
315 BUG_ON(!virt_addr_valid(cpu_addr + size - 1));
378 BUG_ON(!valid_dma_direction(dir)); 316 BUG_ON(!valid_dma_direction(dir));
379 317
380 addr = __dma_map_single(dev, cpu_addr, size, dir); 318 page = virt_to_page(cpu_addr);
381 debug_dma_map_page(dev, virt_to_page(cpu_addr), 319 offset = (unsigned long)cpu_addr & ~PAGE_MASK;
382 (unsigned long)cpu_addr & ~PAGE_MASK, size, 320 addr = __dma_map_page(dev, page, offset, size, dir);
383 dir, addr, true); 321 debug_dma_map_page(dev, page, offset, size, dir, addr, true);
384 322
385 return addr; 323 return addr;
386} 324}
@@ -430,7 +368,7 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
430 size_t size, enum dma_data_direction dir) 368 size_t size, enum dma_data_direction dir)
431{ 369{
432 debug_dma_unmap_page(dev, handle, size, dir, true); 370 debug_dma_unmap_page(dev, handle, size, dir, true);
433 __dma_unmap_single(dev, handle, size, dir); 371 __dma_unmap_page(dev, handle, size, dir);
434} 372}
435 373
436/** 374/**
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 42005542932..628670e9d7c 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -1,15 +1,16 @@
1#ifndef __ASM_ARM_DMA_H 1#ifndef __ASM_ARM_DMA_H
2#define __ASM_ARM_DMA_H 2#define __ASM_ARM_DMA_H
3 3
4#include <asm/memory.h>
5
6/* 4/*
7 * This is the maximum virtual address which can be DMA'd from. 5 * This is the maximum virtual address which can be DMA'd from.
8 */ 6 */
9#ifndef ARM_DMA_ZONE_SIZE 7#ifndef CONFIG_ZONE_DMA
10#define MAX_DMA_ADDRESS 0xffffffff 8#define MAX_DMA_ADDRESS 0xffffffffUL
11#else 9#else
12#define MAX_DMA_ADDRESS (PAGE_OFFSET + ARM_DMA_ZONE_SIZE) 10#define MAX_DMA_ADDRESS ({ \
11 extern unsigned long arm_dma_zone_size; \
12 arm_dma_zone_size ? \
13 (PAGE_OFFSET + arm_dma_zone_size) : 0xffffffffUL; })
13#endif 14#endif
14 15
15#ifdef CONFIG_ISA_DMA_API 16#ifdef CONFIG_ISA_DMA_API
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 0e9ce8d9686..0691cdce48e 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -52,6 +52,7 @@ typedef struct user_fp elf_fpregset_t;
52#define R_ARM_ABS32 2 52#define R_ARM_ABS32 2
53#define R_ARM_CALL 28 53#define R_ARM_CALL 28
54#define R_ARM_JUMP24 29 54#define R_ARM_JUMP24 29
55#define R_ARM_TARGET1 38
55#define R_ARM_V4BX 40 56#define R_ARM_V4BX 40
56#define R_ARM_PREL31 42 57#define R_ARM_PREL31 42
57#define R_ARM_MOVW_ABS_NC 43 58#define R_ARM_MOVW_ABS_NC 43
diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S
index 2da8547de6d..2f1e2098dfe 100644
--- a/arch/arm/include/asm/entry-macro-multi.S
+++ b/arch/arm/include/asm/entry-macro-multi.S
@@ -4,8 +4,8 @@
4 * Interrupt handling. Preserves r7, r8, r9 4 * Interrupt handling. Preserves r7, r8, r9
5 */ 5 */
6 .macro arch_irq_handler_default 6 .macro arch_irq_handler_default
7 get_irqnr_preamble r5, lr 7 get_irqnr_preamble r6, lr
81: get_irqnr_and_base r0, r6, r5, lr 81: get_irqnr_and_base r0, r2, r6, lr
9 movne r1, sp 9 movne r1, sp
10 @ 10 @
11 @ routine called with r0 = irq number, r1 = struct pt_regs * 11 @ routine called with r0 = irq number, r1 = struct pt_regs *
@@ -17,17 +17,17 @@
17 /* 17 /*
18 * XXX 18 * XXX
19 * 19 *
20 * this macro assumes that irqstat (r6) and base (r5) are 20 * this macro assumes that irqstat (r2) and base (r6) are
21 * preserved from get_irqnr_and_base above 21 * preserved from get_irqnr_and_base above
22 */ 22 */
23 ALT_SMP(test_for_ipi r0, r6, r5, lr) 23 ALT_SMP(test_for_ipi r0, r2, r6, lr)
24 ALT_UP_B(9997f) 24 ALT_UP_B(9997f)
25 movne r1, sp 25 movne r1, sp
26 adrne lr, BSYM(1b) 26 adrne lr, BSYM(1b)
27 bne do_IPI 27 bne do_IPI
28 28
29#ifdef CONFIG_LOCAL_TIMERS 29#ifdef CONFIG_LOCAL_TIMERS
30 test_for_ltirq r0, r6, r5, lr 30 test_for_ltirq r0, r2, r6, lr
31 movne r0, sp 31 movne r0, sp
32 adrne lr, BSYM(1b) 32 adrne lr, BSYM(1b)
33 bne do_local_timer 33 bne do_local_timer
@@ -40,7 +40,7 @@
40 .align 5 40 .align 5
41 .global \symbol_name 41 .global \symbol_name
42\symbol_name: 42\symbol_name:
43 mov r4, lr 43 mov r8, lr
44 arch_irq_handler_default 44 arch_irq_handler_default
45 mov pc, r4 45 mov pc, r8
46 .endm 46 .endm
diff --git a/arch/arm/include/asm/fiq_debugger.h b/arch/arm/include/asm/fiq_debugger.h
new file mode 100644
index 00000000000..4d274883ba6
--- /dev/null
+++ b/arch/arm/include/asm/fiq_debugger.h
@@ -0,0 +1,64 @@
1/*
2 * arch/arm/include/asm/fiq_debugger.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef _ARCH_ARM_MACH_TEGRA_FIQ_DEBUGGER_H_
19#define _ARCH_ARM_MACH_TEGRA_FIQ_DEBUGGER_H_
20
21#include <linux/serial_core.h>
22
23#define FIQ_DEBUGGER_NO_CHAR NO_POLL_CHAR
24#define FIQ_DEBUGGER_BREAK 0x00ff0100
25
26#define FIQ_DEBUGGER_FIQ_IRQ_NAME "fiq"
27#define FIQ_DEBUGGER_SIGNAL_IRQ_NAME "signal"
28#define FIQ_DEBUGGER_WAKEUP_IRQ_NAME "wakeup"
29
30/**
31 * struct fiq_debugger_pdata - fiq debugger platform data
32 * @uart_resume: used to restore uart state right before enabling
33 * the fiq.
34 * @uart_enable: Do the work necessary to communicate with the uart
35 * hw (enable clocks, etc.). This must be ref-counted.
36 * @uart_disable: Do the work necessary to disable the uart hw
37 * (disable clocks, etc.). This must be ref-counted.
38 * @uart_dev_suspend: called during PM suspend, generally not needed
39 * for real fiq mode debugger.
40 * @uart_dev_resume: called during PM resume, generally not needed
41 * for real fiq mode debugger.
42 */
43struct fiq_debugger_pdata {
44 int (*uart_init)(struct platform_device *pdev);
45 void (*uart_free)(struct platform_device *pdev);
46 int (*uart_resume)(struct platform_device *pdev);
47 int (*uart_getc)(struct platform_device *pdev);
48 void (*uart_putc)(struct platform_device *pdev, unsigned int c);
49 void (*uart_flush)(struct platform_device *pdev);
50 void (*uart_enable)(struct platform_device *pdev);
51 void (*uart_disable)(struct platform_device *pdev);
52
53 int (*uart_dev_suspend)(struct platform_device *pdev);
54 int (*uart_dev_resume)(struct platform_device *pdev);
55
56 void (*fiq_enable)(struct platform_device *pdev, unsigned int fiq,
57 bool enable);
58 void (*fiq_ack)(struct platform_device *pdev, unsigned int fiq);
59
60 void (*force_irq)(struct platform_device *pdev, unsigned int irq);
61 void (*force_irq_ack)(struct platform_device *pdev, unsigned int irq);
62};
63
64#endif
diff --git a/arch/arm/include/asm/fiq_glue.h b/arch/arm/include/asm/fiq_glue.h
new file mode 100644
index 00000000000..d54c29db97a
--- /dev/null
+++ b/arch/arm/include/asm/fiq_glue.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2010 Google, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __ASM_FIQ_GLUE_H
15#define __ASM_FIQ_GLUE_H
16
17struct fiq_glue_handler {
18 void (*fiq)(struct fiq_glue_handler *h, void *regs, void *svc_sp);
19 void (*resume)(struct fiq_glue_handler *h);
20};
21
22int fiq_glue_register_handler(struct fiq_glue_handler *handler);
23
24#ifdef CONFIG_FIQ_GLUE
25void fiq_glue_resume(void);
26#else
27static inline void fiq_glue_resume(void) {}
28#endif
29
30#endif
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 8c73900da9e..253cc86318b 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -25,17 +25,17 @@
25 25
26#ifdef CONFIG_SMP 26#ifdef CONFIG_SMP
27 27
28#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 28#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
29 smp_mb(); \ 29 smp_mb(); \
30 __asm__ __volatile__( \ 30 __asm__ __volatile__( \
31 "1: ldrex %1, [%2]\n" \ 31 "1: ldrex %1, [%3]\n" \
32 " " insn "\n" \ 32 " " insn "\n" \
33 "2: strex %1, %0, [%2]\n" \ 33 "2: strex %2, %0, [%3]\n" \
34 " teq %1, #0\n" \ 34 " teq %2, #0\n" \
35 " bne 1b\n" \ 35 " bne 1b\n" \
36 " mov %0, #0\n" \ 36 " mov %0, #0\n" \
37 __futex_atomic_ex_table("%4") \ 37 __futex_atomic_ex_table("%5") \
38 : "=&r" (ret), "=&r" (oldval) \ 38 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
39 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ 39 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
40 : "cc", "memory") 40 : "cc", "memory")
41 41
@@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
73#include <linux/preempt.h> 73#include <linux/preempt.h>
74#include <asm/domain.h> 74#include <asm/domain.h>
75 75
76#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 76#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
77 __asm__ __volatile__( \ 77 __asm__ __volatile__( \
78 "1: " T(ldr) " %1, [%2]\n" \ 78 "1: " T(ldr) " %1, [%3]\n" \
79 " " insn "\n" \ 79 " " insn "\n" \
80 "2: " T(str) " %0, [%2]\n" \ 80 "2: " T(str) " %0, [%3]\n" \
81 " mov %0, #0\n" \ 81 " mov %0, #0\n" \
82 __futex_atomic_ex_table("%4") \ 82 __futex_atomic_ex_table("%5") \
83 : "=&r" (ret), "=&r" (oldval) \ 83 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
84 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ 84 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
85 : "cc", "memory") 85 : "cc", "memory")
86 86
@@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
117 int cmp = (encoded_op >> 24) & 15; 117 int cmp = (encoded_op >> 24) & 15;
118 int oparg = (encoded_op << 8) >> 20; 118 int oparg = (encoded_op << 8) >> 20;
119 int cmparg = (encoded_op << 20) >> 20; 119 int cmparg = (encoded_op << 20) >> 20;
120 int oldval = 0, ret; 120 int oldval = 0, ret, tmp;
121 121
122 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) 122 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
123 oparg = 1 << oparg; 123 oparg = 1 << oparg;
@@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
129 129
130 switch (op) { 130 switch (op) {
131 case FUTEX_OP_SET: 131 case FUTEX_OP_SET:
132 __futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg); 132 __futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
133 break; 133 break;
134 case FUTEX_OP_ADD: 134 case FUTEX_OP_ADD:
135 __futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg); 135 __futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
136 break; 136 break;
137 case FUTEX_OP_OR: 137 case FUTEX_OP_OR:
138 __futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg); 138 __futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
139 break; 139 break;
140 case FUTEX_OP_ANDN: 140 case FUTEX_OP_ANDN:
141 __futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg); 141 __futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
142 break; 142 break;
143 case FUTEX_OP_XOR: 143 case FUTEX_OP_XOR:
144 __futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg); 144 __futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
145 break; 145 break;
146 default: 146 default:
147 ret = -ENOSYS; 147 ret = -ENOSYS;
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 166a7a3e284..7f95555319a 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -1,6 +1,10 @@
1#ifndef _ARCH_ARM_GPIO_H 1#ifndef _ARCH_ARM_GPIO_H
2#define _ARCH_ARM_GPIO_H 2#define _ARCH_ARM_GPIO_H
3 3
4#if CONFIG_ARCH_NR_GPIO > 0
5#define ARCH_NR_GPIO CONFIG_ARCH_NR_GPIO
6#endif
7
4/* not all ARM platforms necessarily support this API ... */ 8/* not all ARM platforms necessarily support this API ... */
5#include <mach/gpio.h> 9#include <mach/gpio.h>
6 10
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index 89ad1805e57..2635c8b5bf5 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -5,7 +5,7 @@
5#include <linux/threads.h> 5#include <linux/threads.h>
6#include <asm/irq.h> 6#include <asm/irq.h>
7 7
8#define NR_IPI 5 8#define NR_IPI 6
9 9
10typedef struct { 10typedef struct {
11 unsigned int __softirq_pending; 11 unsigned int __softirq_pending;
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 16bd4803158..fd04f24055f 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -45,8 +45,13 @@
45#define L2X0_CLEAN_INV_LINE_PA 0x7F0 45#define L2X0_CLEAN_INV_LINE_PA 0x7F0
46#define L2X0_CLEAN_INV_LINE_IDX 0x7F8 46#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
47#define L2X0_CLEAN_INV_WAY 0x7FC 47#define L2X0_CLEAN_INV_WAY 0x7FC
48#define L2X0_LOCKDOWN_WAY_D 0x900 48/*
49#define L2X0_LOCKDOWN_WAY_I 0x904 49 * The lockdown registers repeat 8 times for L310, the L210 has only one
50 * D and one I lockdown register at 0x0900 and 0x0904.
51 */
52#define L2X0_LOCKDOWN_WAY_D_BASE 0x900
53#define L2X0_LOCKDOWN_WAY_I_BASE 0x904
54#define L2X0_LOCKDOWN_STRIDE 0x08
50#define L2X0_TEST_OPERATION 0xF00 55#define L2X0_TEST_OPERATION 0xF00
51#define L2X0_LINE_DATA 0xF10 56#define L2X0_LINE_DATA 0xF10
52#define L2X0_LINE_TAG 0xF30 57#define L2X0_LINE_TAG 0xF30
@@ -57,6 +62,7 @@
57#define L2X0_STNDBY_MODE_EN (1 << 0) 62#define L2X0_STNDBY_MODE_EN (1 << 0)
58 63
59/* Registers shifts and masks */ 64/* Registers shifts and masks */
65#define L2X0_CACHE_ID_REV_MASK (0x3f)
60#define L2X0_CACHE_ID_PART_MASK (0xf << 6) 66#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
61#define L2X0_CACHE_ID_PART_L210 (1 << 6) 67#define L2X0_CACHE_ID_PART_L210 (1 << 6)
62#define L2X0_CACHE_ID_PART_L310 (3 << 6) 68#define L2X0_CACHE_ID_PART_L310 (3 << 6)
@@ -64,7 +70,7 @@
64#define L2X0_AUX_CTRL_MASK 0xc0000fff 70#define L2X0_AUX_CTRL_MASK 0xc0000fff
65#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 71#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
66#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 72#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
67#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17) 73#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
68#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 74#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
69#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26 75#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
70#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27 76#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27
@@ -72,8 +78,11 @@
72#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 78#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29
73#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 79#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30
74 80
81#define REV_PL310_R2P0 4
82
75#ifndef __ASSEMBLY__ 83#ifndef __ASSEMBLY__
76extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); 84extern void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
85extern void l2x0_enable(void);
77#endif 86#endif
78 87
79#endif 88#endif
diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h
index 7ecd793b8f5..6643d6c4f35 100644
--- a/arch/arm/include/asm/hardware/coresight.h
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -17,15 +17,17 @@
17#define TRACER_ACCESSED_BIT 0 17#define TRACER_ACCESSED_BIT 0
18#define TRACER_RUNNING_BIT 1 18#define TRACER_RUNNING_BIT 1
19#define TRACER_CYCLE_ACC_BIT 2 19#define TRACER_CYCLE_ACC_BIT 2
20#define TRACER_TRACE_DATA_BIT 3
20#define TRACER_ACCESSED BIT(TRACER_ACCESSED_BIT) 21#define TRACER_ACCESSED BIT(TRACER_ACCESSED_BIT)
21#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT) 22#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT)
22#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT) 23#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT)
24#define TRACER_TRACE_DATA BIT(TRACER_TRACE_DATA_BIT)
23 25
24#define TRACER_TIMEOUT 10000 26#define TRACER_TIMEOUT 10000
25 27
26#define etm_writel(t, v, x) \ 28#define etm_writel(t, id, v, x) \
27 (__raw_writel((v), (t)->etm_regs + (x))) 29 (__raw_writel((v), (t)->etm_regs[(id)] + (x)))
28#define etm_readl(t, x) (__raw_readl((t)->etm_regs + (x))) 30#define etm_readl(t, id, x) (__raw_readl((t)->etm_regs[(id)] + (x)))
29 31
30/* CoreSight Management Registers */ 32/* CoreSight Management Registers */
31#define CSMR_LOCKACCESS 0xfb0 33#define CSMR_LOCKACCESS 0xfb0
@@ -113,11 +115,19 @@
113#define ETMR_TRACEENCTRL 0x24 115#define ETMR_TRACEENCTRL 0x24
114#define ETMTE_INCLEXCL BIT(24) 116#define ETMTE_INCLEXCL BIT(24)
115#define ETMR_TRACEENEVT 0x20 117#define ETMR_TRACEENEVT 0x20
118
119#define ETMR_VIEWDATAEVT 0x30
120#define ETMR_VIEWDATACTRL1 0x34
121#define ETMR_VIEWDATACTRL2 0x38
122#define ETMR_VIEWDATACTRL3 0x3c
123#define ETMVDC3_EXCLONLY BIT(16)
124
116#define ETMCTRL_OPTS (ETMCTRL_DO_CPRT | \ 125#define ETMCTRL_OPTS (ETMCTRL_DO_CPRT | \
117 ETMCTRL_DATA_DO_ADDR | \
118 ETMCTRL_BRANCH_OUTPUT | \ 126 ETMCTRL_BRANCH_OUTPUT | \
119 ETMCTRL_DO_CONTEXTID) 127 ETMCTRL_DO_CONTEXTID)
120 128
129#define ETMR_TRACEIDR 0x200
130
121/* ETM management registers, "ETM Architecture", 3.5.24 */ 131/* ETM management registers, "ETM Architecture", 3.5.24 */
122#define ETMMR_OSLAR 0x300 132#define ETMMR_OSLAR 0x300
123#define ETMMR_OSLSR 0x304 133#define ETMMR_OSLSR 0x304
@@ -140,14 +150,16 @@
140#define ETBFF_TRIGIN BIT(8) 150#define ETBFF_TRIGIN BIT(8)
141#define ETBFF_TRIGEVT BIT(9) 151#define ETBFF_TRIGEVT BIT(9)
142#define ETBFF_TRIGFL BIT(10) 152#define ETBFF_TRIGFL BIT(10)
153#define ETBFF_STOPFL BIT(12)
143 154
144#define etb_writel(t, v, x) \ 155#define etb_writel(t, v, x) \
145 (__raw_writel((v), (t)->etb_regs + (x))) 156 (__raw_writel((v), (t)->etb_regs + (x)))
146#define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x))) 157#define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x)))
147 158
148#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0) 159#define etm_lock(t, id) \
149#define etm_unlock(t) \ 160 do { etm_writel((t), (id), 0, CSMR_LOCKACCESS); } while (0)
150 do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0) 161#define etm_unlock(t, id) \
162 do { etm_writel((t), (id), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
151 163
152#define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0) 164#define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)
153#define etb_unlock(t) \ 165#define etb_unlock(t) \
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 0691f9dcc50..67d28c76365 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -41,6 +41,21 @@ void gic_secondary_init(unsigned int);
41void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); 41void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
42void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); 42void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
43void gic_enable_ppi(unsigned int); 43void gic_enable_ppi(unsigned int);
44
45struct gic_chip_data {
46 unsigned int irq_offset;
47 void __iomem *dist_base;
48 void __iomem *cpu_base;
49 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
50 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
51 u32 saved_spi_pri[DIV_ROUND_UP(1020, 4)];
52 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
53 u32 __percpu *saved_ppi_enable;
54 u32 __percpu *saved_ppi_conf;
55 u32 __percpu *saved_ppi_pri;
56
57 unsigned int gic_irqs;
58};
44#endif 59#endif
45 60
46#endif 61#endif
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h
index b2f95c72287..b3fea38d55c 100644
--- a/arch/arm/include/asm/hardware/it8152.h
+++ b/arch/arm/include/asm/hardware/it8152.h
@@ -105,7 +105,7 @@ struct pci_sys_data;
105 105
106extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc); 106extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
107extern void it8152_init_irq(void); 107extern void it8152_init_irq(void);
108extern int it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); 108extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
109extern int it8152_pci_setup(int nr, struct pci_sys_data *sys); 109extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
110extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys); 110extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
111 111
diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h
index ebb3ceaa8fa..58cdf5d8412 100644
--- a/arch/arm/include/asm/hardware/scoop.h
+++ b/arch/arm/include/asm/hardware/scoop.h
@@ -61,7 +61,6 @@ struct scoop_pcmcia_dev {
61struct scoop_pcmcia_config { 61struct scoop_pcmcia_config {
62 struct scoop_pcmcia_dev *devs; 62 struct scoop_pcmcia_dev *devs;
63 int num_devs; 63 int num_devs;
64 void (*pcmcia_init)(void);
65 void (*power_ctrl)(struct device *scoop, unsigned short cpr, int nr); 64 void (*power_ctrl)(struct device *scoop, unsigned short cpr, int nr);
66}; 65};
67 66
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index c1062c31710..c93a22a8b92 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -4,22 +4,26 @@
4/* 4/*
5 * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP 5 * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
6 */ 6 */
7#define HWCAP_SWP 1 7#define HWCAP_SWP (1 << 0)
8#define HWCAP_HALF 2 8#define HWCAP_HALF (1 << 1)
9#define HWCAP_THUMB 4 9#define HWCAP_THUMB (1 << 2)
10#define HWCAP_26BIT 8 /* Play it safe */ 10#define HWCAP_26BIT (1 << 3) /* Play it safe */
11#define HWCAP_FAST_MULT 16 11#define HWCAP_FAST_MULT (1 << 4)
12#define HWCAP_FPA 32 12#define HWCAP_FPA (1 << 5)
13#define HWCAP_VFP 64 13#define HWCAP_VFP (1 << 6)
14#define HWCAP_EDSP 128 14#define HWCAP_EDSP (1 << 7)
15#define HWCAP_JAVA 256 15#define HWCAP_JAVA (1 << 8)
16#define HWCAP_IWMMXT 512 16#define HWCAP_IWMMXT (1 << 9)
17#define HWCAP_CRUNCH 1024 17#define HWCAP_CRUNCH (1 << 10)
18#define HWCAP_THUMBEE 2048 18#define HWCAP_THUMBEE (1 << 11)
19#define HWCAP_NEON 4096 19#define HWCAP_NEON (1 << 12)
20#define HWCAP_VFPv3 8192 20#define HWCAP_VFPv3 (1 << 13)
21#define HWCAP_VFPv3D16 16384 21#define HWCAP_VFPv3D16 (1 << 14)
22#define HWCAP_TLS 32768 22#define HWCAP_TLS (1 << 15)
23#define HWCAP_VFPv4 (1 << 16)
24#define HWCAP_IDIVA (1 << 17)
25#define HWCAP_IDIVT (1 << 18)
26#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
23 27
24#if defined(__KERNEL__) && !defined(__ASSEMBLY__) 28#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
25/* 29/*
diff --git a/arch/arm/include/asm/i8253.h b/arch/arm/include/asm/i8253.h
deleted file mode 100644
index 70656b69d5c..00000000000
--- a/arch/arm/include/asm/i8253.h
+++ /dev/null
@@ -1,15 +0,0 @@
1#ifndef __ASMARM_I8253_H
2#define __ASMARM_I8253_H
3
4/* i8253A PIT registers */
5#define PIT_MODE 0x43
6#define PIT_CH0 0x40
7
8#define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ)
9
10extern raw_spinlock_t i8253_lock;
11
12#define outb_pit outb_p
13#define inb_pit inb_p
14
15#endif
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 2721a5814cb..a5656333d57 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -23,8 +23,12 @@ struct pt_regs;
23extern void migrate_irqs(void); 23extern void migrate_irqs(void);
24 24
25extern void asm_do_IRQ(unsigned int, struct pt_regs *); 25extern void asm_do_IRQ(unsigned int, struct pt_regs *);
26void handle_IRQ(unsigned int, struct pt_regs *);
26void init_IRQ(void); 27void init_IRQ(void);
27 28
29void arch_trigger_all_cpu_backtrace(void);
30#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
31
28#endif 32#endif
29 33
30#endif 34#endif
diff --git a/arch/arm/include/asm/kprobes.h b/arch/arm/include/asm/kprobes.h
index e46bdd0097e..feec86768f9 100644
--- a/arch/arm/include/asm/kprobes.h
+++ b/arch/arm/include/asm/kprobes.h
@@ -24,12 +24,6 @@
24#define MAX_INSN_SIZE 2 24#define MAX_INSN_SIZE 2
25#define MAX_STACK_SIZE 64 /* 32 would probably be OK */ 25#define MAX_STACK_SIZE 64 /* 32 would probably be OK */
26 26
27/*
28 * This undefined instruction must be unique and
29 * reserved solely for kprobes' use.
30 */
31#define KPROBE_BREAKPOINT_INSTRUCTION 0xe7f001f8
32
33#define regs_return_value(regs) ((regs)->ARM_r0) 27#define regs_return_value(regs) ((regs)->ARM_r0)
34#define flush_insn_slot(p) do { } while (0) 28#define flush_insn_slot(p) do { } while (0)
35#define kretprobe_blacklist_size 0 29#define kretprobe_blacklist_size 0
@@ -38,14 +32,17 @@ typedef u32 kprobe_opcode_t;
38 32
39struct kprobe; 33struct kprobe;
40typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *); 34typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *);
41
42typedef unsigned long (kprobe_check_cc)(unsigned long); 35typedef unsigned long (kprobe_check_cc)(unsigned long);
36typedef void (kprobe_insn_singlestep_t)(struct kprobe *, struct pt_regs *);
37typedef void (kprobe_insn_fn_t)(void);
43 38
44/* Architecture specific copy of original instruction. */ 39/* Architecture specific copy of original instruction. */
45struct arch_specific_insn { 40struct arch_specific_insn {
46 kprobe_opcode_t *insn; 41 kprobe_opcode_t *insn;
47 kprobe_insn_handler_t *insn_handler; 42 kprobe_insn_handler_t *insn_handler;
48 kprobe_check_cc *insn_check_cc; 43 kprobe_check_cc *insn_check_cc;
44 kprobe_insn_singlestep_t *insn_singlestep;
45 kprobe_insn_fn_t *insn_fn;
49}; 46};
50 47
51struct prev_kprobe { 48struct prev_kprobe {
@@ -62,20 +59,9 @@ struct kprobe_ctlblk {
62}; 59};
63 60
64void arch_remove_kprobe(struct kprobe *); 61void arch_remove_kprobe(struct kprobe *);
65void kretprobe_trampoline(void);
66
67int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr); 62int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr);
68int kprobe_exceptions_notify(struct notifier_block *self, 63int kprobe_exceptions_notify(struct notifier_block *self,
69 unsigned long val, void *data); 64 unsigned long val, void *data);
70 65
71enum kprobe_insn {
72 INSN_REJECTED,
73 INSN_GOOD,
74 INSN_GOOD_NO_SLOT
75};
76
77enum kprobe_insn arm_kprobe_decode_insn(kprobe_opcode_t,
78 struct arch_specific_insn *);
79void __init arm_kprobe_decode_init(void);
80 66
81#endif /* _ARM_KPROBES_H */ 67#endif /* _ARM_KPROBES_H */
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index 080d74f8128..ff66638ff54 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -10,6 +10,8 @@
10#ifndef __ASM_ARM_LOCALTIMER_H 10#ifndef __ASM_ARM_LOCALTIMER_H
11#define __ASM_ARM_LOCALTIMER_H 11#define __ASM_ARM_LOCALTIMER_H
12 12
13#include <linux/errno.h>
14
13struct clock_event_device; 15struct clock_event_device;
14 16
15/* 17/*
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 946f4d778f7..217aa1911dd 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -23,6 +23,10 @@ struct machine_desc {
23 23
24 unsigned int nr_irqs; /* number of IRQs */ 24 unsigned int nr_irqs; /* number of IRQs */
25 25
26#ifdef CONFIG_ZONE_DMA
27 unsigned long dma_zone_size; /* size of DMA-able area */
28#endif
29
26 unsigned int video_start; /* start of video RAM */ 30 unsigned int video_start; /* start of video RAM */
27 unsigned int video_end; /* end of video RAM */ 31 unsigned int video_end; /* end of video RAM */
28 32
@@ -70,4 +74,11 @@ static const struct machine_desc __mach_desc_##_type \
70#define MACHINE_END \ 74#define MACHINE_END \
71}; 75};
72 76
77#define DT_MACHINE_START(_name, _namestr) \
78static const struct machine_desc __mach_desc_##_name \
79 __used \
80 __attribute__((__section__(".arch.info.init"))) = { \
81 .nr = ~0, \
82 .name = _namestr,
83
73#endif 84#endif
diff --git a/arch/arm/include/asm/mach/mmc.h b/arch/arm/include/asm/mach/mmc.h
new file mode 100644
index 00000000000..bca864ac945
--- /dev/null
+++ b/arch/arm/include/asm/mach/mmc.h
@@ -0,0 +1,28 @@
1/*
2 * arch/arm/include/asm/mach/mmc.h
3 */
4#ifndef ASMARM_MACH_MMC_H
5#define ASMARM_MACH_MMC_H
6
7#include <linux/mmc/host.h>
8#include <linux/mmc/card.h>
9#include <linux/mmc/sdio_func.h>
10
11struct embedded_sdio_data {
12 struct sdio_cis cis;
13 struct sdio_cccr cccr;
14 struct sdio_embedded_func *funcs;
15 int num_funcs;
16};
17
18struct mmc_platform_data {
19 unsigned int ocr_mask; /* available voltages */
20 int built_in; /* built-in device flag */
21 int card_present; /* card detect state */
22 u32 (*translate_vdd)(struct device *, unsigned int);
23 unsigned int (*status)(struct device *);
24 struct embedded_sdio_data *embedded_sdio;
25 int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
26};
27
28#endif
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 16330bd0657..186efd4e05c 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -25,7 +25,7 @@ struct hw_pci {
25 void (*preinit)(void); 25 void (*preinit)(void);
26 void (*postinit)(void); 26 void (*postinit)(void);
27 u8 (*swizzle)(struct pci_dev *dev, u8 *pin); 27 u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
28 int (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin); 28 int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
29}; 29};
30 30
31/* 31/*
@@ -44,7 +44,7 @@ struct pci_sys_data {
44 /* Bridge swizzling */ 44 /* Bridge swizzling */
45 u8 (*swizzle)(struct pci_dev *, u8 *); 45 u8 (*swizzle)(struct pci_dev *, u8 *);
46 /* IRQ mapping */ 46 /* IRQ mapping */
47 int (*map_irq)(struct pci_dev *, u8, u8); 47 int (*map_irq)(const struct pci_dev *, u8, u8);
48 struct hw_pci *hw; 48 struct hw_pci *hw;
49 void *private_data; /* platform controller private data */ 49 void *private_data; /* platform controller private data */
50}; 50};
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index af44a8fb348..25669795d80 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -33,7 +33,7 @@
33 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area 33 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
34 */ 34 */
35#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET) 35#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
36#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(0x01000000)) 36#define TASK_SIZE UL(CONFIG_TASK_SIZE)
37#define TASK_UNMAPPED_BASE (UL(CONFIG_PAGE_OFFSET) / 3) 37#define TASK_UNMAPPED_BASE (UL(CONFIG_PAGE_OFFSET) / 3)
38 38
39/* 39/*
@@ -46,7 +46,7 @@
46 * and PAGE_OFFSET - it must be within 32MB of the kernel text. 46 * and PAGE_OFFSET - it must be within 32MB of the kernel text.
47 */ 47 */
48#ifndef CONFIG_THUMB2_KERNEL 48#ifndef CONFIG_THUMB2_KERNEL
49#define MODULES_VADDR (PAGE_OFFSET - 16*1024*1024) 49#define MODULES_VADDR UL(CONFIG_TASK_SIZE)
50#else 50#else
51/* smaller range for Thumb-2 symbols relocation (2^24)*/ 51/* smaller range for Thumb-2 symbols relocation (2^24)*/
52#define MODULES_VADDR (PAGE_OFFSET - 8*1024*1024) 52#define MODULES_VADDR (PAGE_OFFSET - 8*1024*1024)
@@ -204,18 +204,6 @@ static inline unsigned long __phys_to_virt(unsigned long x)
204#endif 204#endif
205 205
206/* 206/*
207 * The DMA mask corresponding to the maximum bus address allocatable
208 * using GFP_DMA. The default here places no restriction on DMA
209 * allocations. This must be the smallest DMA mask in the system,
210 * so a successful GFP_DMA allocation will always satisfy this.
211 */
212#ifndef ARM_DMA_ZONE_SIZE
213#define ISA_DMA_THRESHOLD (0xffffffffULL)
214#else
215#define ISA_DMA_THRESHOLD (PHYS_OFFSET + ARM_DMA_ZONE_SIZE - 1)
216#endif
217
218/*
219 * PFNs are used to describe any physical page; this means 207 * PFNs are used to describe any physical page; this means
220 * PFN 0 == physical address 0. 208 * PFN 0 == physical address 0.
221 * 209 *
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index ac75d084888..c906a2534c8 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -201,6 +201,8 @@ typedef struct page *pgtable_t;
201extern int pfn_valid(unsigned long); 201extern int pfn_valid(unsigned long);
202#endif 202#endif
203 203
204extern phys_addr_t lowmem_limit;
205
204#include <asm/memory.h> 206#include <asm/memory.h>
205 207
206#endif /* !__ASSEMBLY__ */ 208#endif /* !__ASSEMBLY__ */
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 92e2a833693..2b1f245db0c 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -3,9 +3,19 @@
3 3
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5#include <asm-generic/pci-dma-compat.h> 5#include <asm-generic/pci-dma-compat.h>
6#include <asm-generic/pci-bridge.h>
6 7
7#include <asm/mach/pci.h> /* for pci_sys_data */ 8#include <asm/mach/pci.h> /* for pci_sys_data */
8#include <mach/hardware.h> /* for PCIBIOS_MIN_* */ 9
10extern unsigned long pcibios_min_io;
11#define PCIBIOS_MIN_IO pcibios_min_io
12extern unsigned long pcibios_min_mem;
13#define PCIBIOS_MIN_MEM pcibios_min_mem
14
15static inline int pcibios_assign_all_busses(void)
16{
17 return pci_has_flag(PCI_REASSIGN_ALL_RSRC);
18}
9 19
10#ifdef CONFIG_PCI_DOMAINS 20#ifdef CONFIG_PCI_DOMAINS
11static inline int pci_domain_nr(struct pci_bus *bus) 21static inline int pci_domain_nr(struct pci_bus *bus)
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index c4aa4e8c6af..0f8e3827a89 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -24,6 +24,8 @@ enum arm_perf_pmu_ids {
24 ARM_PERF_PMU_ID_V6MP, 24 ARM_PERF_PMU_ID_V6MP,
25 ARM_PERF_PMU_ID_CA8, 25 ARM_PERF_PMU_ID_CA8,
26 ARM_PERF_PMU_ID_CA9, 26 ARM_PERF_PMU_ID_CA9,
27 ARM_PERF_PMU_ID_CA5,
28 ARM_PERF_PMU_ID_CA15,
27 ARM_NUM_PMU_IDS, 29 ARM_NUM_PMU_IDS,
28}; 30};
29 31
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h
index 22de005f159..9a8099ed3ad 100644
--- a/arch/arm/include/asm/pgalloc.h
+++ b/arch/arm/include/asm/pgalloc.h
@@ -64,8 +64,10 @@ pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
64 pte_t *pte; 64 pte_t *pte;
65 65
66 pte = (pte_t *)__get_free_page(PGALLOC_GFP); 66 pte = (pte_t *)__get_free_page(PGALLOC_GFP);
67#if !defined(CONFIG_CPU_CACHE_V7) || !defined(CONFIG_SMP)
67 if (pte) 68 if (pte)
68 clean_pte_table(pte); 69 clean_pte_table(pte);
70#endif
69 71
70 return pte; 72 return pte;
71} 73}
@@ -81,8 +83,10 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr)
81 pte = alloc_pages(PGALLOC_GFP, 0); 83 pte = alloc_pages(PGALLOC_GFP, 0);
82#endif 84#endif
83 if (pte) { 85 if (pte) {
86#if !defined(CONFIG_CPU_CACHE_V7) || !defined(CONFIG_SMP)
84 if (!PageHighMem(pte)) 87 if (!PageHighMem(pte))
85 clean_pte_table(page_address(pte)); 88 clean_pte_table(page_address(pte));
89#endif
86 pgtable_page_ctor(pte); 90 pgtable_page_ctor(pte);
87 } 91 }
88 92
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 5750704e027..e6d609c2cb9 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -189,6 +189,7 @@ extern void __pgd_error(const char *file, int line, pgd_t);
189#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ 189#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
190#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ 190#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
191#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) 191#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
192#define L_PTE_MT_INNER_WB (_AT(pteval_t, 0x05) << 2) /* 0101 (armv6, armv7) */
192 193
193#ifndef __ASSEMBLY__ 194#ifndef __ASSEMBLY__
194 195
@@ -244,6 +245,9 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
244 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN) 245 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
245#endif 246#endif
246 247
248#define pgprot_inner_writeback(prot) \
249 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_INNER_WB)
250
247#endif /* __ASSEMBLY__ */ 251#endif /* __ASSEMBLY__ */
248 252
249/* 253/*
@@ -325,6 +329,24 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
325 clean_pmd_entry(pmdp); \ 329 clean_pmd_entry(pmdp); \
326 } while (0) 330 } while (0)
327 331
332extern spinlock_t pgd_lock;
333extern struct list_head pgd_list;
334
335pte_t *lookup_address(unsigned long address, unsigned int *level);
336enum {
337 PG_LEVEL_NONE,
338 PG_LEVEL_4K,
339 PG_LEVEL_2M,
340 PG_LEVEL_NUM
341};
342
343#ifdef CONFIG_PROC_FS
344extern void update_page_count(int level, unsigned long pages);
345#else
346static inline void update_page_count(int level, unsigned long pages) { }
347#endif
348
349
328static inline pte_t *pmd_page_vaddr(pmd_t pmd) 350static inline pte_t *pmd_page_vaddr(pmd_t pmd)
329{ 351{
330 return __va(pmd_val(pmd) & PAGE_MASK); 352 return __va(pmd_val(pmd) & PAGE_MASK);
@@ -354,6 +376,9 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
354#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) 376#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
355#define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot)) 377#define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot))
356 378
379#define pmd_pfn(pmd) ((pmd_val(pmd) & SECTION_MASK) >> PAGE_SHIFT)
380#define pte_pgprot(pte) ((pgprot_t)(pte_val(pte) & ~PAGE_MASK))
381
357#define pte_page(pte) pfn_to_page(pte_pfn(pte)) 382#define pte_page(pte) pfn_to_page(pte_pfn(pte))
358#define mk_pte(page,prot) pfn_pte(page_to_pfn(page), prot) 383#define mk_pte(page,prot) pfn_pte(page_to_pfn(page), prot)
359 384
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 7544ce6b481..b7e82c4aced 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -41,7 +41,7 @@ struct arm_pmu_platdata {
41 * encoded error on failure. 41 * encoded error on failure.
42 */ 42 */
43extern struct platform_device * 43extern struct platform_device *
44reserve_pmu(enum arm_pmu_type device); 44reserve_pmu(enum arm_pmu_type type);
45 45
46/** 46/**
47 * release_pmu() - Relinquish control of the performance counters 47 * release_pmu() - Relinquish control of the performance counters
@@ -52,7 +52,7 @@ reserve_pmu(enum arm_pmu_type device);
52 * a cookie. 52 * a cookie.
53 */ 53 */
54extern int 54extern int
55release_pmu(struct platform_device *pdev); 55release_pmu(enum arm_pmu_type type);
56 56
57/** 57/**
58 * init_pmu() - Initialise the PMU. 58 * init_pmu() - Initialise the PMU.
@@ -62,26 +62,26 @@ release_pmu(struct platform_device *pdev);
62 * the actual hardware initialisation. 62 * the actual hardware initialisation.
63 */ 63 */
64extern int 64extern int
65init_pmu(enum arm_pmu_type device); 65init_pmu(enum arm_pmu_type type);
66 66
67#else /* CONFIG_CPU_HAS_PMU */ 67#else /* CONFIG_CPU_HAS_PMU */
68 68
69#include <linux/err.h> 69#include <linux/err.h>
70 70
71static inline struct platform_device * 71static inline struct platform_device *
72reserve_pmu(enum arm_pmu_type device) 72reserve_pmu(enum arm_pmu_type type)
73{ 73{
74 return ERR_PTR(-ENODEV); 74 return ERR_PTR(-ENODEV);
75} 75}
76 76
77static inline int 77static inline int
78release_pmu(struct platform_device *pdev) 78release_pmu(enum arm_pmu_type type)
79{ 79{
80 return -ENODEV; 80 return -ENODEV;
81} 81}
82 82
83static inline int 83static inline int
84init_pmu(enum arm_pmu_type device) 84init_pmu(enum arm_pmu_type type)
85{ 85{
86 return -ENODEV; 86 return -ENODEV;
87} 87}
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 8ec535e11fd..633d1cb84d8 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -82,13 +82,13 @@ extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
82extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext); 82extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext);
83extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); 83extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
84#else 84#else
85#define cpu_proc_init() processor._proc_init() 85#define cpu_proc_init processor._proc_init
86#define cpu_proc_fin() processor._proc_fin() 86#define cpu_proc_fin processor._proc_fin
87#define cpu_reset(addr) processor.reset(addr) 87#define cpu_reset processor.reset
88#define cpu_do_idle() processor._do_idle() 88#define cpu_do_idle processor._do_idle
89#define cpu_dcache_clean_area(addr,sz) processor.dcache_clean_area(addr,sz) 89#define cpu_dcache_clean_area processor.dcache_clean_area
90#define cpu_set_pte_ext(ptep,pte,ext) processor.set_pte_ext(ptep,pte,ext) 90#define cpu_set_pte_ext processor.set_pte_ext
91#define cpu_do_switch_mm(pgd,mm) processor.switch_mm(pgd,mm) 91#define cpu_do_switch_mm processor.switch_mm
92#endif 92#endif
93 93
94extern void cpu_resume(void); 94extern void cpu_resume(void);
diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h
index 11b8708fc4d..6f65ca86a5e 100644
--- a/arch/arm/include/asm/prom.h
+++ b/arch/arm/include/asm/prom.h
@@ -16,11 +16,6 @@
16#include <asm/setup.h> 16#include <asm/setup.h>
17#include <asm/irq.h> 17#include <asm/irq.h>
18 18
19static inline void irq_dispose_mapping(unsigned int virq)
20{
21 return;
22}
23
24extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys); 19extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys);
25extern void arm_dt_memblock_reserve(void); 20extern void arm_dt_memblock_reserve(void);
26 21
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 312d10877bd..96187ff58c2 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -69,8 +69,9 @@
69#define PSR_c 0x000000ff /* Control */ 69#define PSR_c 0x000000ff /* Control */
70 70
71/* 71/*
72 * ARMv7 groups of APSR bits 72 * ARMv7 groups of PSR bits
73 */ 73 */
74#define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */
74#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */ 75#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */
75#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 76#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
76#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */ 77#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */
@@ -200,6 +201,14 @@ extern unsigned long profile_pc(struct pt_regs *regs);
200#define PREDICATE_ALWAYS 0xe0000000 201#define PREDICATE_ALWAYS 0xe0000000
201 202
202/* 203/*
204 * True if instr is a 32-bit thumb instruction. This works if instr
205 * is the first or only half-word of a thumb instruction. It also works
206 * when instr holds all 32-bits of a wide thumb instruction if stored
207 * in the form (first_half<<16)|(second_half)
208 */
209#define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800)
210
211/*
203 * kprobe-based event tracer support 212 * kprobe-based event tracer support
204 */ 213 */
205#include <linux/stddef.h> 214#include <linux/stddef.h>
diff --git a/arch/arm/include/asm/scatterlist.h b/arch/arm/include/asm/scatterlist.h
index 2f87870d934..cefdb8f898a 100644
--- a/arch/arm/include/asm/scatterlist.h
+++ b/arch/arm/include/asm/scatterlist.h
@@ -1,6 +1,10 @@
1#ifndef _ASMARM_SCATTERLIST_H 1#ifndef _ASMARM_SCATTERLIST_H
2#define _ASMARM_SCATTERLIST_H 2#define _ASMARM_SCATTERLIST_H
3 3
4#ifdef CONFIG_ARM_HAS_SG_CHAIN
5#define ARCH_HAS_SG_CHAIN
6#endif
7
4#include <asm/memory.h> 8#include <asm/memory.h>
5#include <asm/types.h> 9#include <asm/types.h>
6#include <asm-generic/scatterlist.h> 10#include <asm-generic/scatterlist.h>
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index ee2ad8ae07a..915696dd9c7 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -187,12 +187,16 @@ struct tagtable {
187 187
188#define __tag __used __attribute__((__section__(".taglist.init"))) 188#define __tag __used __attribute__((__section__(".taglist.init")))
189#define __tagtable(tag, fn) \ 189#define __tagtable(tag, fn) \
190static struct tagtable __tagtable_##fn __tag = { tag, fn } 190static const struct tagtable __tagtable_##fn __tag = { tag, fn }
191 191
192/* 192/*
193 * Memory map description 193 * Memory map description
194 */ 194 */
195#define NR_BANKS 8 195#ifdef CONFIG_ARCH_EP93XX
196# define NR_BANKS 16
197#else
198# define NR_BANKS 8
199#endif
196 200
197struct membank { 201struct membank {
198 phys_addr_t start; 202 phys_addr_t start;
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index 154b89b81d3..d208fc07421 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -18,4 +18,5 @@
18 */ 18 */
19#include <asm-generic/sizes.h> 19#include <asm-generic/sizes.h>
20 20
21#define SZ_48M (SZ_32M + SZ_16M) 21#define SZ_48M (SZ_32M + SZ_16M)
22#define SZ_160M (SZ_128M | SZ_32M)
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index e42d96a45d3..74f288f4802 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -93,4 +93,6 @@ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
93 */ 93 */
94extern void show_local_irqs(struct seq_file *, int); 94extern void show_local_irqs(struct seq_file *, int);
95 95
96extern void smp_send_all_cpu_backtrace(void);
97
96#endif /* ifndef __ASM_ARM_SMP_H */ 98#endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
new file mode 100644
index 00000000000..b0e4e1a0231
--- /dev/null
+++ b/arch/arm/include/asm/suspend.h
@@ -0,0 +1,22 @@
1#ifndef __ASM_ARM_SUSPEND_H
2#define __ASM_ARM_SUSPEND_H
3
4#include <asm/memory.h>
5#include <asm/tlbflush.h>
6
7extern void cpu_resume(void);
8
9/*
10 * Hide the first two arguments to __cpu_suspend - these are an implementation
11 * detail which platform code shouldn't have to know about.
12 */
13static inline int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
14{
15 extern int __cpu_suspend(int, long, unsigned long,
16 int (*)(unsigned long));
17 int ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
18 flush_tlb_all();
19 return ret;
20}
21
22#endif
diff --git a/arch/arm/include/asm/tcm.h b/arch/arm/include/asm/tcm.h
index 5929ef5d927..8578d726ad7 100644
--- a/arch/arm/include/asm/tcm.h
+++ b/arch/arm/include/asm/tcm.h
@@ -27,5 +27,7 @@
27 27
28void *tcm_alloc(size_t len); 28void *tcm_alloc(size_t len);
29void tcm_free(void *addr, size_t len); 29void tcm_free(void *addr, size_t len);
30bool tcm_dtcm_present(void);
31bool tcm_itcm_present(void);
30 32
31#endif 33#endif
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index d2005de383b..8077145698f 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -34,16 +34,12 @@
34#define TLB_V6_D_ASID (1 << 17) 34#define TLB_V6_D_ASID (1 << 17)
35#define TLB_V6_I_ASID (1 << 18) 35#define TLB_V6_I_ASID (1 << 18)
36 36
37#define TLB_BTB (1 << 28)
38
39/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */ 37/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
40#define TLB_V7_UIS_PAGE (1 << 19) 38#define TLB_V7_UIS_PAGE (1 << 19)
41#define TLB_V7_UIS_FULL (1 << 20) 39#define TLB_V7_UIS_FULL (1 << 20)
42#define TLB_V7_UIS_ASID (1 << 21) 40#define TLB_V7_UIS_ASID (1 << 21)
43 41
44/* Inner Shareable BTB operation (ARMv7 MP extensions) */ 42#define TLB_BARRIER (1 << 28)
45#define TLB_V7_IS_BTB (1 << 22)
46
47#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ 43#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
48#define TLB_DCLEAN (1 << 30) 44#define TLB_DCLEAN (1 << 30)
49#define TLB_WB (1 << 31) 45#define TLB_WB (1 << 31)
@@ -58,7 +54,7 @@
58 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction 54 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction
59 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction 55 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
60 * fr - Feroceon (v4wbi with non-outer-cacheable page table walks) 56 * fr - Feroceon (v4wbi with non-outer-cacheable page table walks)
61 * fa - Faraday (v4 with write buffer with UTLB and branch target buffer (BTB)) 57 * fa - Faraday (v4 with write buffer with UTLB)
62 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction 58 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
63 * v7wbi - identical to v6wbi 59 * v7wbi - identical to v6wbi
64 */ 60 */
@@ -99,7 +95,7 @@
99# define v4_always_flags (-1UL) 95# define v4_always_flags (-1UL)
100#endif 96#endif
101 97
102#define fa_tlb_flags (TLB_WB | TLB_BTB | TLB_DCLEAN | \ 98#define fa_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
103 TLB_V4_U_FULL | TLB_V4_U_PAGE) 99 TLB_V4_U_FULL | TLB_V4_U_PAGE)
104 100
105#ifdef CONFIG_CPU_TLB_FA 101#ifdef CONFIG_CPU_TLB_FA
@@ -166,7 +162,7 @@
166# define v4wb_always_flags (-1UL) 162# define v4wb_always_flags (-1UL)
167#endif 163#endif
168 164
169#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \ 165#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
170 TLB_V6_I_FULL | TLB_V6_D_FULL | \ 166 TLB_V6_I_FULL | TLB_V6_D_FULL | \
171 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ 167 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
172 TLB_V6_I_ASID | TLB_V6_D_ASID) 168 TLB_V6_I_ASID | TLB_V6_D_ASID)
@@ -184,9 +180,9 @@
184# define v6wbi_always_flags (-1UL) 180# define v6wbi_always_flags (-1UL)
185#endif 181#endif
186 182
187#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \ 183#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
188 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID) 184 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
189#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BTB | \ 185#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
190 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID) 186 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
191 187
192#ifdef CONFIG_CPU_TLB_V7 188#ifdef CONFIG_CPU_TLB_V7
@@ -341,15 +337,7 @@ static inline void local_flush_tlb_all(void)
341 if (tlb_flag(TLB_V7_UIS_FULL)) 337 if (tlb_flag(TLB_V7_UIS_FULL))
342 asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc"); 338 asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
343 339
344 if (tlb_flag(TLB_BTB)) { 340 if (tlb_flag(TLB_BARRIER)) {
345 /* flush the branch target cache */
346 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
347 dsb();
348 isb();
349 }
350 if (tlb_flag(TLB_V7_IS_BTB)) {
351 /* flush the branch target cache */
352 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
353 dsb(); 341 dsb();
354 isb(); 342 isb();
355 } 343 }
@@ -389,17 +377,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
389 asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc"); 377 asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
390#endif 378#endif
391 379
392 if (tlb_flag(TLB_BTB)) { 380 if (tlb_flag(TLB_BARRIER))
393 /* flush the branch target cache */
394 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
395 dsb();
396 }
397 if (tlb_flag(TLB_V7_IS_BTB)) {
398 /* flush the branch target cache */
399 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
400 dsb(); 381 dsb();
401 isb();
402 }
403} 382}
404 383
405static inline void 384static inline void
@@ -439,17 +418,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
439 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc"); 418 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
440#endif 419#endif
441 420
442 if (tlb_flag(TLB_BTB)) { 421 if (tlb_flag(TLB_BARRIER))
443 /* flush the branch target cache */
444 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
445 dsb();
446 }
447 if (tlb_flag(TLB_V7_IS_BTB)) {
448 /* flush the branch target cache */
449 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
450 dsb(); 422 dsb();
451 isb();
452 }
453} 423}
454 424
455static inline void local_flush_tlb_kernel_page(unsigned long kaddr) 425static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
@@ -482,15 +452,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
482 if (tlb_flag(TLB_V7_UIS_PAGE)) 452 if (tlb_flag(TLB_V7_UIS_PAGE))
483 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc"); 453 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
484 454
485 if (tlb_flag(TLB_BTB)) { 455 if (tlb_flag(TLB_BARRIER)) {
486 /* flush the branch target cache */
487 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
488 dsb();
489 isb();
490 }
491 if (tlb_flag(TLB_V7_IS_BTB)) {
492 /* flush the branch target cache */
493 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
494 dsb(); 456 dsb();
495 isb(); 457 isb();
496 } 458 }
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h
index f90756dc16d..5b29a667362 100644
--- a/arch/arm/include/asm/traps.h
+++ b/arch/arm/include/asm/traps.h
@@ -3,6 +3,9 @@
3 3
4#include <linux/list.h> 4#include <linux/list.h>
5 5
6struct pt_regs;
7struct task_struct;
8
6struct undef_hook { 9struct undef_hook {
7 struct list_head node; 10 struct list_head node;
8 u32 instr_mask; 11 u32 instr_mask;
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 0196edf6ee5..23ae09ffc49 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -481,8 +481,8 @@
481/* 481/*
482 * Unimplemented (or alternatively implemented) syscalls 482 * Unimplemented (or alternatively implemented) syscalls
483 */ 483 */
484#define __IGNORE_fadvise64_64 1 484#define __IGNORE_fadvise64_64
485#define __IGNORE_migrate_pages 1 485#define __IGNORE_migrate_pages
486 486
487#endif /* __KERNEL__ */ 487#endif /* __KERNEL__ */
488#endif /* __ASM_ARM_UNISTD_H */ 488#endif /* __ASM_ARM_UNISTD_H */
diff --git a/arch/arm/include/asm/vga.h b/arch/arm/include/asm/vga.h
index 250a4dd0063..91f40217bfa 100644
--- a/arch/arm/include/asm/vga.h
+++ b/arch/arm/include/asm/vga.h
@@ -2,9 +2,10 @@
2#define ASMARM_VGA_H 2#define ASMARM_VGA_H
3 3
4#include <linux/io.h> 4#include <linux/io.h>
5#include <mach/hardware.h>
6 5
7#define VGA_MAP_MEM(x,s) (PCIMEM_BASE + (x)) 6extern unsigned long vga_base;
7
8#define VGA_MAP_MEM(x,s) (vga_base + (x))
8 9
9#define vga_readb(x) (*((volatile unsigned char *)x)) 10#define vga_readb(x) (*((volatile unsigned char *)x))
10#define vga_writeb(x,y) (*((volatile unsigned char *)y) = (x)) 11#define vga_writeb(x,y) (*((volatile unsigned char *)y) = (x))
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-07 04:23:52 -0400