1 files changed, 207 insertions, 11 deletions

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 4ddd0a6ac7f..05cd423c575 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -29,6 +29,7 @@
 #include <linux/cpumask.h>
 #include <linux/io.h>
 
+#include <asm/cpu_pm.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
@@ -38,12 +39,6 @@ static DEFINE_SPINLOCK(irq_controller_lock);
 /* Address of GIC 0 CPU interface */
 void __iomem *gic_cpu_base_addr __read_mostly;
 
-struct gic_chip_data {
-        unsigned int irq_offset;
-        void __iomem *dist_base;
-        void __iomem *cpu_base;
-};
-
 /*
  * Supported arch specific GIC irq extension.
  * Default make them NULL.
@@ -179,22 +174,32 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 {
         void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
         unsigned int shift = (d->irq % 4) * 8;
-        unsigned int cpu = cpumask_first(mask_val);
+        unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
         u32 val, mask, bit;
+#ifdef CONFIG_GIC_SET_MULTIPLE_CPUS
+        struct irq_desc *desc = irq_to_desc(d->irq);
+#endif
 
-        if (cpu >= 8)
+        if (cpu >= 8 || cpu >= nr_cpu_ids)
                 return -EINVAL;
 
         mask = 0xff << shift;
         bit = 1 << (cpu + shift);
 
         spin_lock(&irq_controller_lock);
-        d->node = cpu;
         val = readl_relaxed(reg) & ~mask;
-        writel_relaxed(val | bit, reg);
+        val |= bit;
+#ifdef CONFIG_GIC_SET_MULTIPLE_CPUS
+        if (desc && desc->affinity_hint) {
+                struct cpumask mask_hint;
+                if (cpumask_and(&mask_hint, desc->affinity_hint, mask_val))
+                        val |= (*cpumask_bits(&mask_hint) << shift) & mask;
+        }
+#endif
+        writel_relaxed(val, reg);
         spin_unlock(&irq_controller_lock);
 
-        return 0;
+        return IRQ_SET_MASK_OK;
 }
 #endif
 
@@ -283,6 +288,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
         if (gic_irqs > 1020)
                 gic_irqs = 1020;
 
+        gic->gic_irqs = gic_irqs;
+
         /*
          * Set all global interrupts to be level triggered, active low.
          */
@@ -350,6 +357,180 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
         writel_relaxed(1, base + GIC_CPU_CTRL);
 }
 
+/*
+ * Saves the GIC distributor registers during suspend or idle.  Must be called
+ * with interrupts disabled but before powering down the GIC.  After calling
+ * this function, no interrupts will be delivered by the GIC, and another
+ * platform-specific wakeup source must be enabled.
+ */
+static void gic_dist_save(unsigned int gic_nr)
+{
+        unsigned int gic_irqs;
+        void __iomem *dist_base;
+        int i;
+
+        if (gic_nr >= MAX_GIC_NR)
+                BUG();
+
+        gic_irqs = gic_data[gic_nr].gic_irqs;
+        dist_base = gic_data[gic_nr].dist_base;
+
+        if (!dist_base)
+                return;
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
+                gic_data[gic_nr].saved_spi_conf[i] =
+                        readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+                gic_data[gic_nr].saved_spi_pri[i] =
+                        readl_relaxed(dist_base + GIC_DIST_PRI + i * 4);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+                gic_data[gic_nr].saved_spi_target[i] =
+                        readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
+                gic_data[gic_nr].saved_spi_enable[i] =
+                        readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
+
+        writel_relaxed(0, dist_base + GIC_DIST_CTRL);
+}
+
+/*
+ * Restores the GIC distributor registers during resume or when coming out of
+ * idle.  Must be called before enabling interrupts.  If a level interrupt
+ * that occured while the GIC was suspended is still present, it will be
+ * handled normally, but any edge interrupts that occured will not be seen by
+ * the GIC and need to be handled by the platform-specific wakeup source.
+ */
+static void gic_dist_restore(unsigned int gic_nr)
+{
+        unsigned int gic_irqs;
+        unsigned int i;
+        void __iomem *dist_base;
+
+        if (gic_nr >= MAX_GIC_NR)
+                BUG();
+
+        gic_irqs = gic_data[gic_nr].gic_irqs;
+        dist_base = gic_data[gic_nr].dist_base;
+
+        if (!dist_base)
+                return;
+
+        writel_relaxed(0, dist_base + GIC_DIST_CTRL);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
+                writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
+                        dist_base + GIC_DIST_CONFIG + i * 4);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+                writel_relaxed(gic_data[gic_nr].saved_spi_pri[i],
+                        dist_base + GIC_DIST_PRI + i * 4);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+                writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
+                        dist_base + GIC_DIST_TARGET + i * 4);
+
+        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
+                writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
+                        dist_base + GIC_DIST_ENABLE_SET + i * 4);
+
+        writel_relaxed(1, dist_base + GIC_DIST_CTRL);
+}
+
+static void gic_cpu_save(unsigned int gic_nr)
+{
+        int i;
+        u32 *ptr;
+        void __iomem *dist_base;
+        void __iomem *cpu_base;
+
+        if (gic_nr >= MAX_GIC_NR)
+                BUG();
+
+        dist_base = gic_data[gic_nr].dist_base;
+        cpu_base = gic_data[gic_nr].cpu_base;
+
+        if (!dist_base || !cpu_base)
+                return;
+
+        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
+        for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
+                ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
+
+        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
+        for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
+                ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
+
+        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_pri);
+        for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
+                ptr[i] = readl_relaxed(dist_base + GIC_DIST_PRI + i * 4);
+}
+
+static void gic_cpu_restore(unsigned int gic_nr)
+{
+        int i;
+        u32 *ptr;
+        void __iomem *dist_base;
+        void __iomem *cpu_base;
+
+        if (gic_nr >= MAX_GIC_NR)
+                BUG();
+
+        dist_base = gic_data[gic_nr].dist_base;
+        cpu_base = gic_data[gic_nr].cpu_base;
+
+        if (!dist_base || !cpu_base)
+                return;
+
+        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
+        for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
+                writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
+
+        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
+        for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
+                writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
+
+        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_pri);
+        for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
+                writel_relaxed(ptr[i], dist_base + GIC_DIST_PRI + i * 4);
+
+        writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
+        writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
+}
+
+static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
+{
+        int i;
+
+        for (i = 0; i < MAX_GIC_NR; i++) {
+                switch (cmd) {
+                case CPU_PM_ENTER:
+                        gic_cpu_save(i);
+                        break;
+                case CPU_PM_ENTER_FAILED:
+                case CPU_PM_EXIT:
+                        gic_cpu_restore(i);
+                        break;
+                case CPU_COMPLEX_PM_ENTER:
+                        gic_dist_save(i);
+                        break;
+                case CPU_COMPLEX_PM_ENTER_FAILED:
+                case CPU_COMPLEX_PM_EXIT:
+                        gic_dist_restore(i);
+                        break;
+                }
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block gic_notifier_block = {
+        .notifier_call = gic_notifier,
+};
+
 void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
         void __iomem *dist_base, void __iomem *cpu_base)
 {
@@ -365,8 +546,23 @@ void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
         if (gic_nr == 0)
                 gic_cpu_base_addr = cpu_base;
 
+        gic_chip.flags |= gic_arch_extn.flags;
         gic_dist_init(gic, irq_start);
         gic_cpu_init(gic);
+
+        gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
+                sizeof(u32));
+        BUG_ON(!gic->saved_ppi_enable);
+
+        gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
+                sizeof(u32));
+        BUG_ON(!gic->saved_ppi_conf);
+
+        gic->saved_ppi_pri = __alloc_percpu(DIV_ROUND_UP(32, 4) * 4,
+                sizeof(u32));
+        BUG_ON(!gic->saved_ppi_pri);
+
+        cpu_pm_register_notifier(&gic_notifier_block);
 }
 
 void __cpuinit gic_secondary_init(unsigned int gic_nr)