1 files changed, 59 insertions, 0 deletions

diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 4b71766fb21..23b2a6a98c2 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -39,3 +39,62 @@ config SHARP_PARAM
 
 config SHARP_SCOOP
         bool
+
+config FIQ_GLUE
+        bool
+        select FIQ
+
+config FIQ_DEBUGGER
+        bool "FIQ Mode Serial Debugger"
+        select FIQ
+        select FIQ_GLUE
+        default n
+        help
+          The FIQ serial debugger can accept commands even when the
+          kernel is unresponsive due to being stuck with interrupts
+          disabled.
+
+
+config FIQ_DEBUGGER_NO_SLEEP
+        bool "Keep serial debugger active"
+        depends on FIQ_DEBUGGER
+        default n
+        help
+          Enables the serial debugger at boot. Passing
+          fiq_debugger.no_sleep on the kernel commandline will
+          override this config option.
+
+config FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON
+        bool "Don't disable wakeup IRQ when debugger is active"
+        depends on FIQ_DEBUGGER
+        default n
+        help
+          Don't disable the wakeup irq when enabling the uart clock.  This will
+          cause extra interrupts, but it makes the serial debugger usable with
+          on some MSM radio builds that ignore the uart clock request in power
+          collapse.
+
+config FIQ_DEBUGGER_CONSOLE
+        bool "Console on FIQ Serial Debugger port"
+        depends on FIQ_DEBUGGER
+        default n
+        help
+          Enables a console so that printk messages are displayed on
+          the debugger serial port as the occur.
+
+config FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE
+        bool "Put the FIQ debugger into console mode by default"
+        depends on FIQ_DEBUGGER_CONSOLE
+        default n
+        help
+          If enabled, this puts the fiq debugger into console mode by default.
+          Otherwise, the fiq debugger will start out in debug mode.
+
+config GIC_SET_MULTIPLE_CPUS
+        bool "Use affinity hint to allow multiple CPUs for IRQ"
+        depends on ARM_GIC && SMP
+        default n
+        help
+          IRQ affinity is always set by gic to the 1st cpu in the requested
+          mask. If this option is enabled, affinity is also set to all cpus
+          present in affinity_hint and requested masks.