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-rw-r--r--arch/arm/boot/compressed/head.S14
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi2
5 files changed, 19 insertions, 7 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 90275f036cd..49ca86e37b8 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -652,6 +652,15 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
652 mov pc, lr 652 mov pc, lr
653ENDPROC(__setup_mmu) 653ENDPROC(__setup_mmu)
654 654
655@ Enable unaligned access on v6, to allow better code generation
656@ for the decompressor C code:
657__armv6_mmu_cache_on:
658 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
659 bic r0, r0, #2 @ A (no unaligned access fault)
660 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
661 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
662 b __armv4_mmu_cache_on
663
655__arm926ejs_mmu_cache_on: 664__arm926ejs_mmu_cache_on:
656#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 665#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
657 mov r0, #4 @ put dcache in WT mode 666 mov r0, #4 @ put dcache in WT mode
@@ -694,6 +703,9 @@ __armv7_mmu_cache_on:
694 bic r0, r0, #1 << 28 @ clear SCTLR.TRE 703 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
695 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 704 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
696 orr r0, r0, #0x003c @ write buffer 705 orr r0, r0, #0x003c @ write buffer
706 bic r0, r0, #2 @ A (no unaligned access fault)
707 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
708 @ (needed for ARM1176)
697#ifdef CONFIG_MMU 709#ifdef CONFIG_MMU
698#ifdef CONFIG_CPU_ENDIAN_BE8 710#ifdef CONFIG_CPU_ENDIAN_BE8
699 orr r0, r0, #1 << 25 @ big-endian page tables 711 orr r0, r0, #1 << 25 @ big-endian page tables
@@ -914,7 +926,7 @@ proc_types:
914 926
915 .word 0x0007b000 @ ARMv6 927 .word 0x0007b000 @ ARMv6
916 .word 0x000ff000 928 .word 0x000ff000
917 W(b) __armv4_mmu_cache_on 929 W(b) __armv6_mmu_cache_on
918 W(b) __armv4_mmu_cache_off 930 W(b) __armv4_mmu_cache_off
919 W(b) __armv6_mmu_cache_flush 931 W(b) __armv6_mmu_cache_flush
920 932
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index aaa42d8d4f8..03c56cbd050 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -217,7 +217,7 @@
217 compatible = "atmel,at91rm9200-ssc"; 217 compatible = "atmel,at91rm9200-ssc";
218 reg = <0xfffbc000 0x4000>; 218 reg = <0xfffbc000 0x4000>;
219 interrupts = <14 4 5>; 219 interrupts = <14 4 5>;
220 status = "disable"; 220 status = "disabled";
221 }; 221 };
222 222
223 adc0: adc@fffe0000 { 223 adc0: adc@fffe0000 {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 3b721ee59b1..15f12dd803e 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -179,14 +179,14 @@
179 compatible = "atmel,at91rm9200-ssc"; 179 compatible = "atmel,at91rm9200-ssc";
180 reg = <0xfff98000 0x4000>; 180 reg = <0xfff98000 0x4000>;
181 interrupts = <16 4 5>; 181 interrupts = <16 4 5>;
182 status = "disable"; 182 status = "disabled";
183 }; 183 };
184 184
185 ssc1: ssc@fff9c000 { 185 ssc1: ssc@fff9c000 {
186 compatible = "atmel,at91rm9200-ssc"; 186 compatible = "atmel,at91rm9200-ssc";
187 reg = <0xfff9c000 0x4000>; 187 reg = <0xfff9c000 0x4000>;
188 interrupts = <17 4 5>; 188 interrupts = <17 4 5>;
189 status = "disable"; 189 status = "disabled";
190 }; 190 };
191 191
192 macb0: ethernet@fffbc000 { 192 macb0: ethernet@fffbc000 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index acfa207162f..44a38d0fe59 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -232,14 +232,14 @@
232 compatible = "atmel,at91sam9g45-ssc"; 232 compatible = "atmel,at91sam9g45-ssc";
233 reg = <0xfff9c000 0x4000>; 233 reg = <0xfff9c000 0x4000>;
234 interrupts = <16 4 5>; 234 interrupts = <16 4 5>;
235 status = "disable"; 235 status = "disabled";
236 }; 236 };
237 237
238 ssc1: ssc@fffa0000 { 238 ssc1: ssc@fffa0000 {
239 compatible = "atmel,at91sam9g45-ssc"; 239 compatible = "atmel,at91sam9g45-ssc";
240 reg = <0xfffa0000 0x4000>; 240 reg = <0xfffa0000 0x4000>;
241 interrupts = <17 4 5>; 241 interrupts = <17 4 5>;
242 status = "disable"; 242 status = "disabled";
243 }; 243 };
244 244
245 adc0: adc@fffb0000 { 245 adc0: adc@fffb0000 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 69667d0ac34..0beff720caf 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -92,7 +92,7 @@
92 compatible = "atmel,at91sam9g45-ssc"; 92 compatible = "atmel,at91sam9g45-ssc";
93 reg = <0xf0010000 0x4000>; 93 reg = <0xf0010000 0x4000>;
94 interrupts = <28 4 5>; 94 interrupts = <28 4 5>;
95 status = "disable"; 95 status = "disabled";
96 }; 96 };
97 97
98 tcb0: timer@f8008000 { 98 tcb0: timer@f8008000 {