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-rw-r--r--arch/arm/boot/.gitignore1
-rw-r--r--arch/arm/boot/Makefile6
-rw-r--r--arch/arm/boot/compressed/.gitignore12
-rw-r--r--arch/arm/boot/compressed/Makefile10
-rw-r--r--arch/arm/boot/compressed/head-shmobile.S12
-rw-r--r--arch/arm/boot/compressed/head.S6
-rw-r--r--arch/arm/boot/compressed/mmcif-sh7372.c4
-rw-r--r--arch/arm/boot/compressed/sdhi-sh7372.c95
-rw-r--r--arch/arm/boot/compressed/sdhi-shmobile.c449
-rw-r--r--arch/arm/boot/compressed/sdhi-shmobile.h11
-rw-r--r--arch/arm/boot/compressed/vmlinux.lds.in12
-rw-r--r--arch/arm/boot/dts/prima2-cb.dts416
-rw-r--r--arch/arm/boot/dts/skeleton.dtsi13
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts70
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts28
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi139
-rw-r--r--arch/arm/boot/dts/versatile-ab.dts192
-rw-r--r--arch/arm/boot/dts/versatile-pb.dts48
-rw-r--r--arch/arm/boot/dts/zynq-ep107.dts52
19 files changed, 1561 insertions, 15 deletions
diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore
index ce1c5ff746e..3c79f85975a 100644
--- a/arch/arm/boot/.gitignore
+++ b/arch/arm/boot/.gitignore
@@ -3,3 +3,4 @@ zImage
3xipImage 3xipImage
4bootpImage 4bootpImage
5uImage 5uImage
6*.dtb
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 9128fddf110..a1edfd5a129 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -59,6 +59,12 @@ $(obj)/zImage: $(obj)/compressed/vmlinux FORCE
59 59
60endif 60endif
61 61
62# Rule to build device tree blobs
63$(obj)/%.dtb: $(src)/dts/%.dts
64 $(call cmd,dtc)
65
66$(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
67
62quiet_cmd_uimage = UIMAGE $@ 68quiet_cmd_uimage = UIMAGE $@
63 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \ 69 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
64 -C none -a $(LOADADDR) -e $(STARTADDR) \ 70 -C none -a $(LOADADDR) -e $(STARTADDR) \
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index c6028967d33..f79a08efe00 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -1,7 +1,19 @@
1ashldi3.S
1font.c 2font.c
2lib1funcs.S 3lib1funcs.S
4hyp-stub.S
3piggy.gzip 5piggy.gzip
4piggy.lzo 6piggy.lzo
5piggy.lzma 7piggy.lzma
8piggy.xzkern
6vmlinux 9vmlinux
7vmlinux.lds 10vmlinux.lds
11
12# borrowed libfdt files
13fdt.c
14fdt.h
15fdt_ro.c
16fdt_rw.c
17fdt_wip.c
18libfdt.h
19libfdt_internal.h
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 23aad072230..0c74a6fab95 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -6,13 +6,19 @@
6 6
7OBJS = 7OBJS =
8 8
9# Ensure that mmcif loader code appears early in the image 9# Ensure that MMCIF loader code appears early in the image
10# to minimise that number of bocks that have to be read in 10# to minimise that number of bocks that have to be read in
11# order to load it. 11# order to load it.
12ifeq ($(CONFIG_ZBOOT_ROM_MMCIF),y) 12ifeq ($(CONFIG_ZBOOT_ROM_MMCIF),y)
13ifeq ($(CONFIG_ARCH_SH7372),y)
14OBJS += mmcif-sh7372.o 13OBJS += mmcif-sh7372.o
15endif 14endif
15
16# Ensure that SDHI loader code appears early in the image
17# to minimise that number of bocks that have to be read in
18# order to load it.
19ifeq ($(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI),y)
20OBJS += sdhi-shmobile.o
21OBJS += sdhi-sh7372.o
16endif 22endif
17 23
18AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) 24AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
index c943d2e7da9..fe3719b516f 100644
--- a/arch/arm/boot/compressed/head-shmobile.S
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -25,14 +25,14 @@
25 /* load board-specific initialization code */ 25 /* load board-specific initialization code */
26#include <mach/zboot.h> 26#include <mach/zboot.h>
27 27
28#ifdef CONFIG_ZBOOT_ROM_MMCIF 28#if defined(CONFIG_ZBOOT_ROM_MMCIF) || defined(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI)
29 /* Load image from MMC */ 29 /* Load image from MMC/SD */
30 adr sp, __tmp_stack + 128 30 adr sp, __tmp_stack + 256
31 ldr r0, __image_start 31 ldr r0, __image_start
32 ldr r1, __image_end 32 ldr r1, __image_end
33 subs r1, r1, r0 33 subs r1, r1, r0
34 ldr r0, __load_base 34 ldr r0, __load_base
35 bl mmcif_loader 35 bl mmc_loader
36 36
37 /* Jump to loaded code */ 37 /* Jump to loaded code */
38 ldr r0, __loaded 38 ldr r0, __loaded
@@ -51,9 +51,9 @@ __loaded:
51 .long __continue 51 .long __continue
52 .align 52 .align
53__tmp_stack: 53__tmp_stack:
54 .space 128 54 .space 256
55__continue: 55__continue:
56#endif /* CONFIG_ZBOOT_ROM_MMCIF */ 56#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */
57 57
58 b 1f 58 b 1f
59__atags:@ tag #1 59__atags:@ tag #1
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 940b2017810..24701d6f72b 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -353,7 +353,8 @@ not_relocated: mov r0, #0
353 mov r0, #0 @ must be zero 353 mov r0, #0 @ must be zero
354 mov r1, r7 @ restore architecture number 354 mov r1, r7 @ restore architecture number
355 mov r2, r8 @ restore atags pointer 355 mov r2, r8 @ restore atags pointer
356 mov pc, r4 @ call kernel 356 ARM( mov pc, r4 ) @ call kernel
357 THUMB( bx r4 ) @ entry point is always ARM
357 358
358 .align 2 359 .align 2
359 .type LC0, #object 360 .type LC0, #object
@@ -656,6 +657,8 @@ proc_types:
656@ b __arm6_mmu_cache_off 657@ b __arm6_mmu_cache_off
657@ b __armv3_mmu_cache_flush 658@ b __armv3_mmu_cache_flush
658 659
660#if !defined(CONFIG_CPU_V7)
661 /* This collides with some V7 IDs, preventing correct detection */
659 .word 0x00000000 @ old ARM ID 662 .word 0x00000000 @ old ARM ID
660 .word 0x0000f000 663 .word 0x0000f000
661 mov pc, lr 664 mov pc, lr
@@ -664,6 +667,7 @@ proc_types:
664 THUMB( nop ) 667 THUMB( nop )
665 mov pc, lr 668 mov pc, lr
666 THUMB( nop ) 669 THUMB( nop )
670#endif
667 671
668 .word 0x41007000 @ ARM7/710 672 .word 0x41007000 @ ARM7/710
669 .word 0xfff8fe00 673 .word 0xfff8fe00
diff --git a/arch/arm/boot/compressed/mmcif-sh7372.c b/arch/arm/boot/compressed/mmcif-sh7372.c
index 7453c8337b8..672ae95db5c 100644
--- a/arch/arm/boot/compressed/mmcif-sh7372.c
+++ b/arch/arm/boot/compressed/mmcif-sh7372.c
@@ -40,7 +40,7 @@
40 * to an MMC card 40 * to an MMC card
41 * # dd if=vrl4.out of=/dev/sdx bs=512 seek=1 41 * # dd if=vrl4.out of=/dev/sdx bs=512 seek=1
42 */ 42 */
43asmlinkage void mmcif_loader(unsigned char *buf, unsigned long len) 43asmlinkage void mmc_loader(unsigned char *buf, unsigned long len)
44{ 44{
45 mmc_init_progress(); 45 mmc_init_progress();
46 mmc_update_progress(MMC_PROGRESS_ENTER); 46 mmc_update_progress(MMC_PROGRESS_ENTER);
@@ -82,7 +82,7 @@ asmlinkage void mmcif_loader(unsigned char *buf, unsigned long len)
82 82
83 83
84 /* Disable clock to MMC hardware block */ 84 /* Disable clock to MMC hardware block */
85 __raw_writel(__raw_readl(SMSTPCR3) & (1 << 12), SMSTPCR3); 85 __raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3);
86 86
87 mmc_update_progress(MMC_PROGRESS_DONE); 87 mmc_update_progress(MMC_PROGRESS_DONE);
88} 88}
diff --git a/arch/arm/boot/compressed/sdhi-sh7372.c b/arch/arm/boot/compressed/sdhi-sh7372.c
new file mode 100644
index 00000000000..d279294f238
--- /dev/null
+++ b/arch/arm/boot/compressed/sdhi-sh7372.c
@@ -0,0 +1,95 @@
1/*
2 * SuperH Mobile SDHI
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2010 Kuninori Morimoto
6 * Copyright (C) 2010 Simon Horman
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 *
12 * Parts inspired by u-boot
13 */
14
15#include <linux/io.h>
16#include <mach/mmc.h>
17#include <linux/mmc/boot.h>
18#include <linux/mmc/tmio.h>
19
20#include "sdhi-shmobile.h"
21
22#define PORT179CR 0xe60520b3
23#define PORT180CR 0xe60520b4
24#define PORT181CR 0xe60520b5
25#define PORT182CR 0xe60520b6
26#define PORT183CR 0xe60520b7
27#define PORT184CR 0xe60520b8
28
29#define SMSTPCR3 0xe615013c
30
31#define CR_INPUT_ENABLE 0x10
32#define CR_FUNCTION1 0x01
33
34#define SDHI1_BASE (void __iomem *)0xe6860000
35#define SDHI_BASE SDHI1_BASE
36
37/* SuperH Mobile SDHI loader
38 *
39 * loads the zImage from an SD card starting from block 0
40 * on physical partition 1
41 *
42 * The image must be start with a vrl4 header and
43 * the zImage must start at offset 512 of the image. That is,
44 * at block 1 (=byte 512) of physical partition 1
45 *
46 * Use the following line to write the vrl4 formated zImage
47 * to an SD card
48 * # dd if=vrl4.out of=/dev/sdx bs=512
49 */
50asmlinkage void mmc_loader(unsigned short *buf, unsigned long len)
51{
52 int high_capacity;
53
54 mmc_init_progress();
55
56 mmc_update_progress(MMC_PROGRESS_ENTER);
57 /* Initialise SDHI1 */
58 /* PORT184CR: GPIO_FN_SDHICMD1 Control */
59 __raw_writeb(CR_FUNCTION1, PORT184CR);
60 /* PORT179CR: GPIO_FN_SDHICLK1 Control */
61 __raw_writeb(CR_INPUT_ENABLE|CR_FUNCTION1, PORT179CR);
62 /* PORT181CR: GPIO_FN_SDHID1_3 Control */
63 __raw_writeb(CR_FUNCTION1, PORT183CR);
64 /* PORT182CR: GPIO_FN_SDHID1_2 Control */
65 __raw_writeb(CR_FUNCTION1, PORT182CR);
66 /* PORT183CR: GPIO_FN_SDHID1_1 Control */
67 __raw_writeb(CR_FUNCTION1, PORT181CR);
68 /* PORT180CR: GPIO_FN_SDHID1_0 Control */
69 __raw_writeb(CR_FUNCTION1, PORT180CR);
70
71 /* Enable clock to SDHI1 hardware block */
72 __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 13), SMSTPCR3);
73
74 /* setup SDHI hardware */
75 mmc_update_progress(MMC_PROGRESS_INIT);
76 high_capacity = sdhi_boot_init(SDHI_BASE);
77 if (high_capacity < 0)
78 goto err;
79
80 mmc_update_progress(MMC_PROGRESS_LOAD);
81 /* load kernel */
82 if (sdhi_boot_do_read(SDHI_BASE, high_capacity,
83 0, /* Kernel is at block 1 */
84 (len + TMIO_BBS - 1) / TMIO_BBS, buf))
85 goto err;
86
87 /* Disable clock to SDHI1 hardware block */
88 __raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3);
89
90 mmc_update_progress(MMC_PROGRESS_DONE);
91
92 return;
93err:
94 for(;;);
95}
diff --git a/arch/arm/boot/compressed/sdhi-shmobile.c b/arch/arm/boot/compressed/sdhi-shmobile.c
new file mode 100644
index 00000000000..bd3d4698095
--- /dev/null
+++ b/arch/arm/boot/compressed/sdhi-shmobile.c
@@ -0,0 +1,449 @@
1/*
2 * SuperH Mobile SDHI
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2010 Kuninori Morimoto
6 * Copyright (C) 2010 Simon Horman
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 *
12 * Parts inspired by u-boot
13 */
14
15#include <linux/io.h>
16#include <linux/mmc/host.h>
17#include <linux/mmc/core.h>
18#include <linux/mmc/mmc.h>
19#include <linux/mmc/sd.h>
20#include <linux/mmc/tmio.h>
21#include <mach/sdhi.h>
22
23#define OCR_FASTBOOT (1<<29)
24#define OCR_HCS (1<<30)
25#define OCR_BUSY (1<<31)
26
27#define RESP_CMD12 0x00000030
28
29static inline u16 sd_ctrl_read16(void __iomem *base, int addr)
30{
31 return __raw_readw(base + addr);
32}
33
34static inline u32 sd_ctrl_read32(void __iomem *base, int addr)
35{
36 return __raw_readw(base + addr) |
37 __raw_readw(base + addr + 2) << 16;
38}
39
40static inline void sd_ctrl_write16(void __iomem *base, int addr, u16 val)
41{
42 __raw_writew(val, base + addr);
43}
44
45static inline void sd_ctrl_write32(void __iomem *base, int addr, u32 val)
46{
47 __raw_writew(val, base + addr);
48 __raw_writew(val >> 16, base + addr + 2);
49}
50
51#define ALL_ERROR (TMIO_STAT_CMD_IDX_ERR | TMIO_STAT_CRCFAIL | \
52 TMIO_STAT_STOPBIT_ERR | TMIO_STAT_DATATIMEOUT | \
53 TMIO_STAT_RXOVERFLOW | TMIO_STAT_TXUNDERRUN | \
54 TMIO_STAT_CMDTIMEOUT | TMIO_STAT_ILL_ACCESS | \
55 TMIO_STAT_ILL_FUNC)
56
57static int sdhi_intr(void __iomem *base)
58{
59 unsigned long state = sd_ctrl_read32(base, CTL_STATUS);
60
61 if (state & ALL_ERROR) {
62 sd_ctrl_write32(base, CTL_STATUS, ~ALL_ERROR);
63 sd_ctrl_write32(base, CTL_IRQ_MASK,
64 ALL_ERROR |
65 sd_ctrl_read32(base, CTL_IRQ_MASK));
66 return -EINVAL;
67 }
68 if (state & TMIO_STAT_CMDRESPEND) {
69 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND);
70 sd_ctrl_write32(base, CTL_IRQ_MASK,
71 TMIO_STAT_CMDRESPEND |
72 sd_ctrl_read32(base, CTL_IRQ_MASK));
73 return 0;
74 }
75 if (state & TMIO_STAT_RXRDY) {
76 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_RXRDY);
77 sd_ctrl_write32(base, CTL_IRQ_MASK,
78 TMIO_STAT_RXRDY | TMIO_STAT_TXUNDERRUN |
79 sd_ctrl_read32(base, CTL_IRQ_MASK));
80 return 0;
81 }
82 if (state & TMIO_STAT_DATAEND) {
83 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_DATAEND);
84 sd_ctrl_write32(base, CTL_IRQ_MASK,
85 TMIO_STAT_DATAEND |
86 sd_ctrl_read32(base, CTL_IRQ_MASK));
87 return 0;
88 }
89
90 return -EAGAIN;
91}
92
93static int sdhi_boot_wait_resp_end(void __iomem *base)
94{
95 int err = -EAGAIN, timeout = 10000000;
96
97 while (timeout--) {
98 err = sdhi_intr(base);
99 if (err != -EAGAIN)
100 break;
101 udelay(1);
102 }
103
104 return err;
105}
106
107/* SDHI_CLK_CTRL */
108#define CLK_MMC_ENABLE (1 << 8)
109#define CLK_MMC_INIT (1 << 6) /* clk / 256 */
110
111static void sdhi_boot_mmc_clk_stop(void __iomem *base)
112{
113 sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, 0x0000);
114 msleep(10);
115 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, ~CLK_MMC_ENABLE &
116 sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL));
117 msleep(10);
118}
119
120static void sdhi_boot_mmc_clk_start(void __iomem *base)
121{
122 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, CLK_MMC_ENABLE |
123 sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL));
124 msleep(10);
125 sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, CLK_MMC_ENABLE);
126 msleep(10);
127}
128
129static void sdhi_boot_reset(void __iomem *base)
130{
131 sd_ctrl_write16(base, CTL_RESET_SD, 0x0000);
132 msleep(10);
133 sd_ctrl_write16(base, CTL_RESET_SD, 0x0001);
134 msleep(10);
135}
136
137/* Set MMC clock / power.
138 * Note: This controller uses a simple divider scheme therefore it cannot
139 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
140 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
141 * slowest setting.
142 */
143static int sdhi_boot_mmc_set_ios(void __iomem *base, struct mmc_ios *ios)
144{
145 if (sd_ctrl_read32(base, CTL_STATUS) & TMIO_STAT_CMD_BUSY)
146 return -EBUSY;
147
148 if (ios->clock)
149 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL,
150 ios->clock | CLK_MMC_ENABLE);
151
152 /* Power sequence - OFF -> ON -> UP */
153 switch (ios->power_mode) {
154 case MMC_POWER_OFF: /* power down SD bus */
155 sdhi_boot_mmc_clk_stop(base);
156 break;
157 case MMC_POWER_ON: /* power up SD bus */
158 break;
159 case MMC_POWER_UP: /* start bus clock */
160 sdhi_boot_mmc_clk_start(base);
161 break;
162 }
163
164 switch (ios->bus_width) {
165 case MMC_BUS_WIDTH_1:
166 sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x80e0);
167 break;
168 case MMC_BUS_WIDTH_4:
169 sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x00e0);
170 break;
171 }
172
173 /* Let things settle. delay taken from winCE driver */
174 udelay(140);
175
176 return 0;
177}
178
179/* These are the bitmasks the tmio chip requires to implement the MMC response
180 * types. Note that R1 and R6 are the same in this scheme. */
181#define RESP_NONE 0x0300
182#define RESP_R1 0x0400
183#define RESP_R1B 0x0500
184#define RESP_R2 0x0600
185#define RESP_R3 0x0700
186#define DATA_PRESENT 0x0800
187#define TRANSFER_READ 0x1000
188
189static int sdhi_boot_request(void __iomem *base, struct mmc_command *cmd)
190{
191 int err, c = cmd->opcode;
192
193 switch (mmc_resp_type(cmd)) {
194 case MMC_RSP_NONE: c |= RESP_NONE; break;
195 case MMC_RSP_R1: c |= RESP_R1; break;
196 case MMC_RSP_R1B: c |= RESP_R1B; break;
197 case MMC_RSP_R2: c |= RESP_R2; break;
198 case MMC_RSP_R3: c |= RESP_R3; break;
199 default:
200 return -EINVAL;
201 }
202
203 /* No interrupts so this may not be cleared */
204 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND);
205
206 sd_ctrl_write32(base, CTL_IRQ_MASK, TMIO_STAT_CMDRESPEND |
207 sd_ctrl_read32(base, CTL_IRQ_MASK));
208 sd_ctrl_write32(base, CTL_ARG_REG, cmd->arg);
209 sd_ctrl_write16(base, CTL_SD_CMD, c);
210
211
212 sd_ctrl_write32(base, CTL_IRQ_MASK,
213 ~(TMIO_STAT_CMDRESPEND | ALL_ERROR) &
214 sd_ctrl_read32(base, CTL_IRQ_MASK));
215
216 err = sdhi_boot_wait_resp_end(base);
217 if (err)
218 return err;
219
220 cmd->resp[0] = sd_ctrl_read32(base, CTL_RESPONSE);
221
222 return 0;
223}
224
225static int sdhi_boot_do_read_single(void __iomem *base, int high_capacity,
226 unsigned long block, unsigned short *buf)
227{
228 int err, i;
229
230 /* CMD17 - Read */
231 {
232 struct mmc_command cmd;
233
234 cmd.opcode = MMC_READ_SINGLE_BLOCK | \
235 TRANSFER_READ | DATA_PRESENT;
236 if (high_capacity)
237 cmd.arg = block;
238 else
239 cmd.arg = block * TMIO_BBS;
240 cmd.flags = MMC_RSP_R1;
241 err = sdhi_boot_request(base, &cmd);
242 if (err)
243 return err;
244 }
245
246 sd_ctrl_write32(base, CTL_IRQ_MASK,
247 ~(TMIO_STAT_DATAEND | TMIO_STAT_RXRDY |
248 TMIO_STAT_TXUNDERRUN) &
249 sd_ctrl_read32(base, CTL_IRQ_MASK));
250 err = sdhi_boot_wait_resp_end(base);
251 if (err)
252 return err;
253
254 sd_ctrl_write16(base, CTL_SD_XFER_LEN, TMIO_BBS);
255 for (i = 0; i < TMIO_BBS / sizeof(*buf); i++)
256 *buf++ = sd_ctrl_read16(base, RESP_CMD12);
257
258 err = sdhi_boot_wait_resp_end(base);
259 if (err)
260 return err;
261
262 return 0;
263}
264
265int sdhi_boot_do_read(void __iomem *base, int high_capacity,
266 unsigned long offset, unsigned short count,
267 unsigned short *buf)
268{
269 unsigned long i;
270 int err = 0;
271
272 for (i = 0; i < count; i++) {
273 err = sdhi_boot_do_read_single(base, high_capacity, offset + i,
274 buf + (i * TMIO_BBS /
275 sizeof(*buf)));
276 if (err)
277 return err;
278 }
279
280 return 0;
281}
282
283#define VOLTAGES (MMC_VDD_32_33 | MMC_VDD_33_34)
284
285int sdhi_boot_init(void __iomem *base)
286{
287 bool sd_v2 = false, sd_v1_0 = false;
288 unsigned short cid;
289 int err, high_capacity = 0;
290
291 sdhi_boot_mmc_clk_stop(base);
292 sdhi_boot_reset(base);
293
294 /* mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 0 timing 0 */
295 {
296 struct mmc_ios ios;
297 ios.power_mode = MMC_POWER_ON;
298 ios.bus_width = MMC_BUS_WIDTH_1;
299 ios.clock = CLK_MMC_INIT;
300 err = sdhi_boot_mmc_set_ios(base, &ios);
301 if (err)
302 return err;
303 }
304
305 /* CMD0 */
306 {
307 struct mmc_command cmd;
308 msleep(1);
309 cmd.opcode = MMC_GO_IDLE_STATE;
310 cmd.arg = 0;
311 cmd.flags = MMC_RSP_NONE;
312 err = sdhi_boot_request(base, &cmd);
313 if (err)
314 return err;
315 msleep(2);
316 }
317
318 /* CMD8 - Test for SD version 2 */
319 {
320 struct mmc_command cmd;
321 cmd.opcode = SD_SEND_IF_COND;
322 cmd.arg = (VOLTAGES != 0) << 8 | 0xaa;
323 cmd.flags = MMC_RSP_R1;
324 err = sdhi_boot_request(base, &cmd); /* Ignore error */
325 if ((cmd.resp[0] & 0xff) == 0xaa)
326 sd_v2 = true;
327 }
328
329 /* CMD55 - Get OCR (SD) */
330 {
331 int timeout = 1000;
332 struct mmc_command cmd;
333
334 cmd.arg = 0;
335
336 do {
337 cmd.opcode = MMC_APP_CMD;
338 cmd.flags = MMC_RSP_R1;
339 cmd.arg = 0;
340 err = sdhi_boot_request(base, &cmd);
341 if (err)
342 break;
343
344 cmd.opcode = SD_APP_OP_COND;
345 cmd.flags = MMC_RSP_R3;
346 cmd.arg = (VOLTAGES & 0xff8000);
347 if (sd_v2)
348 cmd.arg |= OCR_HCS;
349 cmd.arg |= OCR_FASTBOOT;
350 err = sdhi_boot_request(base, &cmd);
351 if (err)
352 break;
353
354 msleep(1);
355 } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout);
356
357 if (!err && timeout) {
358 if (!sd_v2)
359 sd_v1_0 = true;
360 high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS;
361 }
362 }
363
364 /* CMD1 - Get OCR (MMC) */
365 if (!sd_v2 && !sd_v1_0) {
366 int timeout = 1000;
367 struct mmc_command cmd;
368
369 do {
370 cmd.opcode = MMC_SEND_OP_COND;
371 cmd.arg = VOLTAGES | OCR_HCS;
372 cmd.flags = MMC_RSP_R3;
373 err = sdhi_boot_request(base, &cmd);
374 if (err)
375 return err;
376
377 msleep(1);
378 } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout);
379
380 if (!timeout)
381 return -EAGAIN;
382
383 high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS;
384 }
385
386 /* CMD2 - Get CID */
387 {
388 struct mmc_command cmd;
389 cmd.opcode = MMC_ALL_SEND_CID;
390 cmd.arg = 0;
391 cmd.flags = MMC_RSP_R2;
392 err = sdhi_boot_request(base, &cmd);
393 if (err)
394 return err;
395 }
396
397 /* CMD3
398 * MMC: Set the relative address
399 * SD: Get the relative address
400 * Also puts the card into the standby state
401 */
402 {
403 struct mmc_command cmd;
404 cmd.opcode = MMC_SET_RELATIVE_ADDR;
405 cmd.arg = 0;
406 cmd.flags = MMC_RSP_R1;
407 err = sdhi_boot_request(base, &cmd);
408 if (err)
409 return err;
410 cid = cmd.resp[0] >> 16;
411 }
412
413 /* CMD9 - Get CSD */
414 {
415 struct mmc_command cmd;
416 cmd.opcode = MMC_SEND_CSD;
417 cmd.arg = cid << 16;
418 cmd.flags = MMC_RSP_R2;
419 err = sdhi_boot_request(base, &cmd);
420 if (err)
421 return err;
422 }
423
424 /* CMD7 - Select the card */
425 {
426 struct mmc_command cmd;
427 cmd.opcode = MMC_SELECT_CARD;
428 //cmd.arg = rca << 16;
429 cmd.arg = cid << 16;
430 //cmd.flags = MMC_RSP_R1B;
431 cmd.flags = MMC_RSP_R1;
432 err = sdhi_boot_request(base, &cmd);
433 if (err)
434 return err;
435 }
436
437 /* CMD16 - Set the block size */
438 {
439 struct mmc_command cmd;
440 cmd.opcode = MMC_SET_BLOCKLEN;
441 cmd.arg = TMIO_BBS;
442 cmd.flags = MMC_RSP_R1;
443 err = sdhi_boot_request(base, &cmd);
444 if (err)
445 return err;
446 }
447
448 return high_capacity;
449}
diff --git a/arch/arm/boot/compressed/sdhi-shmobile.h b/arch/arm/boot/compressed/sdhi-shmobile.h
new file mode 100644
index 00000000000..92eaa09f985
--- /dev/null
+++ b/arch/arm/boot/compressed/sdhi-shmobile.h
@@ -0,0 +1,11 @@
1#ifndef SDHI_MOBILE_H
2#define SDHI_MOBILE_H
3
4#include <linux/compiler.h>
5
6int sdhi_boot_do_read(void __iomem *base, int high_capacity,
7 unsigned long offset, unsigned short count,
8 unsigned short *buf);
9int sdhi_boot_init(void __iomem *base);
10
11#endif
diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in
index ea80abe7884..4e728834a1b 100644
--- a/arch/arm/boot/compressed/vmlinux.lds.in
+++ b/arch/arm/boot/compressed/vmlinux.lds.in
@@ -33,20 +33,24 @@ SECTIONS
33 *(.text.*) 33 *(.text.*)
34 *(.fixup) 34 *(.fixup)
35 *(.gnu.warning) 35 *(.gnu.warning)
36 *(.glue_7t)
37 *(.glue_7)
38 }
39 .rodata : {
36 *(.rodata) 40 *(.rodata)
37 *(.rodata.*) 41 *(.rodata.*)
38 *(.glue_7) 42 }
39 *(.glue_7t) 43 .piggydata : {
40 *(.piggydata) 44 *(.piggydata)
41 . = ALIGN(4);
42 } 45 }
43 46
47 . = ALIGN(4);
44 _etext = .; 48 _etext = .;
45 49
50 .got.plt : { *(.got.plt) }
46 _got_start = .; 51 _got_start = .;
47 .got : { *(.got) } 52 .got : { *(.got) }
48 _got_end = .; 53 _got_end = .;
49 .got.plt : { *(.got.plt) }
50 _edata = .; 54 _edata = .;
51 55
52 . = BSS_START; 56 . = BSS_START;
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
new file mode 100644
index 00000000000..6fecc88065b
--- /dev/null
+++ b/arch/arm/boot/dts/prima2-cb.dts
@@ -0,0 +1,416 @@
1/dts-v1/;
2/ {
3 model = "SiRF Prima2 eVB";
4 compatible = "sirf,prima2-cb", "sirf,prima2";
5 #address-cells = <1>;
6 #size-cells = <1>;
7 interrupt-parent = <&intc>;
8
9 memory {
10 reg = <0x00000000 0x20000000>;
11 };
12
13 chosen {
14 bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
15 linux,stdout-path = &uart1;
16 };
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu@0 {
23 reg = <0x0>;
24 d-cache-line-size = <32>;
25 i-cache-line-size = <32>;
26 d-cache-size = <32768>;
27 i-cache-size = <32768>;
28 /* from bootloader */
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
32 };
33 };
34
35 axi {
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges = <0x40000000 0x40000000 0x80000000>;
40
41 l2-cache-controller@80040000 {
42 compatible = "arm,pl310-cache";
43 reg = <0x80040000 0x1000>;
44 interrupts = <59>;
45 };
46
47 intc: interrupt-controller@80020000 {
48 #interrupt-cells = <1>;
49 interrupt-controller;
50 compatible = "sirf,prima2-intc";
51 reg = <0x80020000 0x1000>;
52 };
53
54 sys-iobg {
55 compatible = "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
58 ranges = <0x88000000 0x88000000 0x40000>;
59
60 clock-controller@88000000 {
61 compatible = "sirf,prima2-clkc";
62 reg = <0x88000000 0x1000>;
63 interrupts = <3>;
64 };
65
66 reset-controller@88010000 {
67 compatible = "sirf,prima2-rstc";
68 reg = <0x88010000 0x1000>;
69 };
70 };
71
72 mem-iobg {
73 compatible = "simple-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges = <0x90000000 0x90000000 0x10000>;
77
78 memory-controller@90000000 {
79 compatible = "sirf,prima2-memc";
80 reg = <0x90000000 0x10000>;
81 interrupts = <27>;
82 };
83 };
84
85 disp-iobg {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges = <0x90010000 0x90010000 0x30000>;
90
91 display@90010000 {
92 compatible = "sirf,prima2-lcd";
93 reg = <0x90010000 0x20000>;
94 interrupts = <30>;
95 };
96
97 vpp@90020000 {
98 compatible = "sirf,prima2-vpp";
99 reg = <0x90020000 0x10000>;
100 interrupts = <31>;
101 };
102 };
103
104 graphics-iobg {
105 compatible = "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges = <0x98000000 0x98000000 0x8000000>;
109
110 graphics@98000000 {
111 compatible = "powervr,sgx531";
112 reg = <0x98000000 0x8000000>;
113 interrupts = <6>;
114 };
115 };
116
117 multimedia-iobg {
118 compatible = "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <1>;
121 ranges = <0xa0000000 0xa0000000 0x8000000>;
122
123 multimedia@a0000000 {
124 compatible = "sirf,prima2-video-codec";
125 reg = <0xa0000000 0x8000000>;
126 interrupts = <5>;
127 };
128 };
129
130 dsp-iobg {
131 compatible = "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 ranges = <0xa8000000 0xa8000000 0x2000000>;
135
136 dspif@a8000000 {
137 compatible = "sirf,prima2-dspif";
138 reg = <0xa8000000 0x10000>;
139 interrupts = <9>;
140 };
141
142 gps@a8010000 {
143 compatible = "sirf,prima2-gps";
144 reg = <0xa8010000 0x10000>;
145 interrupts = <7>;
146 };
147
148 dsp@a9000000 {
149 compatible = "sirf,prima2-dsp";
150 reg = <0xa9000000 0x1000000>;
151 interrupts = <8>;
152 };
153 };
154
155 peri-iobg {
156 compatible = "simple-bus";
157 #address-cells = <1>;
158 #size-cells = <1>;
159 ranges = <0xb0000000 0xb0000000 0x180000>;
160
161 timer@b0020000 {
162 compatible = "sirf,prima2-tick";
163 reg = <0xb0020000 0x1000>;
164 interrupts = <0>;
165 };
166
167 nand@b0030000 {
168 compatible = "sirf,prima2-nand";
169 reg = <0xb0030000 0x10000>;
170 interrupts = <41>;
171 };
172
173 audio@b0040000 {
174 compatible = "sirf,prima2-audio";
175 reg = <0xb0040000 0x10000>;
176 interrupts = <35>;
177 };
178
179 uart0: uart@b0050000 {
180 cell-index = <0>;
181 compatible = "sirf,prima2-uart";
182 reg = <0xb0050000 0x10000>;
183 interrupts = <17>;
184 };
185
186 uart1: uart@b0060000 {
187 cell-index = <1>;
188 compatible = "sirf,prima2-uart";
189 reg = <0xb0060000 0x10000>;
190 interrupts = <18>;
191 };
192
193 uart2: uart@b0070000 {
194 cell-index = <2>;
195 compatible = "sirf,prima2-uart";
196 reg = <0xb0070000 0x10000>;
197 interrupts = <19>;
198 };
199
200 usp0: usp@b0080000 {
201 cell-index = <0>;
202 compatible = "sirf,prima2-usp";
203 reg = <0xb0080000 0x10000>;
204 interrupts = <20>;
205 };
206
207 usp1: usp@b0090000 {
208 cell-index = <1>;
209 compatible = "sirf,prima2-usp";
210 reg = <0xb0090000 0x10000>;
211 interrupts = <21>;
212 };
213
214 usp2: usp@b00a0000 {
215 cell-index = <2>;
216 compatible = "sirf,prima2-usp";
217 reg = <0xb00a0000 0x10000>;
218 interrupts = <22>;
219 };
220
221 dmac0: dma-controller@b00b0000 {
222 cell-index = <0>;
223 compatible = "sirf,prima2-dmac";
224 reg = <0xb00b0000 0x10000>;
225 interrupts = <12>;
226 };
227
228 dmac1: dma-controller@b0160000 {
229 cell-index = <1>;
230 compatible = "sirf,prima2-dmac";
231 reg = <0xb0160000 0x10000>;
232 interrupts = <13>;
233 };
234
235 vip@b00C0000 {
236 compatible = "sirf,prima2-vip";
237 reg = <0xb00C0000 0x10000>;
238 };
239
240 spi0: spi@b00d0000 {
241 cell-index = <0>;
242 compatible = "sirf,prima2-spi";
243 reg = <0xb00d0000 0x10000>;
244 interrupts = <15>;
245 };
246
247 spi1: spi@b0170000 {
248 cell-index = <1>;
249 compatible = "sirf,prima2-spi";
250 reg = <0xb0170000 0x10000>;
251 interrupts = <16>;
252 };
253
254 i2c0: i2c@b00e0000 {
255 cell-index = <0>;
256 compatible = "sirf,prima2-i2c";
257 reg = <0xb00e0000 0x10000>;
258 interrupts = <24>;
259 };
260
261 i2c1: i2c@b00f0000 {
262 cell-index = <1>;
263 compatible = "sirf,prima2-i2c";
264 reg = <0xb00f0000 0x10000>;
265 interrupts = <25>;
266 };
267
268 tsc@b0110000 {
269 compatible = "sirf,prima2-tsc";
270 reg = <0xb0110000 0x10000>;
271 interrupts = <33>;
272 };
273
274 gpio: gpio-controller@b0120000 {
275 #gpio-cells = <2>;
276 #interrupt-cells = <2>;
277 compatible = "sirf,prima2-gpio";
278 reg = <0xb0120000 0x10000>;
279 gpio-controller;
280 interrupt-controller;
281 };
282
283 pwm@b0130000 {
284 compatible = "sirf,prima2-pwm";
285 reg = <0xb0130000 0x10000>;
286 };
287
288 efusesys@b0140000 {
289 compatible = "sirf,prima2-efuse";
290 reg = <0xb0140000 0x10000>;
291 };
292
293 pulsec@b0150000 {
294 compatible = "sirf,prima2-pulsec";
295 reg = <0xb0150000 0x10000>;
296 interrupts = <48>;
297 };
298
299 pci-iobg {
300 compatible = "sirf,prima2-pciiobg", "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
303 ranges = <0x56000000 0x56000000 0x1b00000>;
304
305 sd0: sdhci@56000000 {
306 cell-index = <0>;
307 compatible = "sirf,prima2-sdhc";
308 reg = <0x56000000 0x100000>;
309 interrupts = <38>;
310 };
311
312 sd1: sdhci@56100000 {
313 cell-index = <1>;
314 compatible = "sirf,prima2-sdhc";
315 reg = <0x56100000 0x100000>;
316 interrupts = <38>;
317 };
318
319 sd2: sdhci@56200000 {
320 cell-index = <2>;
321 compatible = "sirf,prima2-sdhc";
322 reg = <0x56200000 0x100000>;
323 interrupts = <23>;
324 };
325
326 sd3: sdhci@56300000 {
327 cell-index = <3>;
328 compatible = "sirf,prima2-sdhc";
329 reg = <0x56300000 0x100000>;
330 interrupts = <23>;
331 };
332
333 sd4: sdhci@56400000 {
334 cell-index = <4>;
335 compatible = "sirf,prima2-sdhc";
336 reg = <0x56400000 0x100000>;
337 interrupts = <39>;
338 };
339
340 sd5: sdhci@56500000 {
341 cell-index = <5>;
342 compatible = "sirf,prima2-sdhc";
343 reg = <0x56500000 0x100000>;
344 interrupts = <39>;
345 };
346
347 pci-copy@57900000 {
348 compatible = "sirf,prima2-pcicp";
349 reg = <0x57900000 0x100000>;
350 interrupts = <40>;
351 };
352
353 rom-interface@57a00000 {
354 compatible = "sirf,prima2-romif";
355 reg = <0x57a00000 0x100000>;
356 };
357 };
358 };
359
360 rtc-iobg {
361 compatible = "sirf,prima2-rtciobg", "simple-bus";
362 #address-cells = <1>;
363 #size-cells = <1>;
364 reg = <0x80030000 0x10000>;
365
366 gpsrtc@1000 {
367 compatible = "sirf,prima2-gpsrtc";
368 reg = <0x1000 0x1000>;
369 interrupts = <55 56 57>;
370 };
371
372 sysrtc@2000 {
373 compatible = "sirf,prima2-sysrtc";
374 reg = <0x2000 0x1000>;
375 interrupts = <52 53 54>;
376 };
377
378 pwrc@3000 {
379 compatible = "sirf,prima2-pwrc";
380 reg = <0x3000 0x1000>;
381 interrupts = <32>;
382 };
383 };
384
385 uus-iobg {
386 compatible = "simple-bus";
387 #address-cells = <1>;
388 #size-cells = <1>;
389 ranges = <0xb8000000 0xb8000000 0x40000>;
390
391 usb0: usb@b00e0000 {
392 compatible = "chipidea,ci13611a-prima2";
393 reg = <0xb8000000 0x10000>;
394 interrupts = <10>;
395 };
396
397 usb1: usb@b00f0000 {
398 compatible = "chipidea,ci13611a-prima2";
399 reg = <0xb8010000 0x10000>;
400 interrupts = <11>;
401 };
402
403 sata@b00f0000 {
404 compatible = "synopsys,dwc-ahsata";
405 reg = <0xb8020000 0x10000>;
406 interrupts = <37>;
407 };
408
409 security@b00f0000 {
410 compatible = "sirf,prima2-security";
411 reg = <0xb8030000 0x10000>;
412 interrupts = <42>;
413 };
414 };
415 };
416};
diff --git a/arch/arm/boot/dts/skeleton.dtsi b/arch/arm/boot/dts/skeleton.dtsi
new file mode 100644
index 00000000000..b41d241de2c
--- /dev/null
+++ b/arch/arm/boot/dts/skeleton.dtsi
@@ -0,0 +1,13 @@
1/*
2 * Skeleton device tree; the bare minimum needed to boot; just include and
3 * add a compatible value. The bootloader will typically populate the memory
4 * node.
5 */
6
7/ {
8 #address-cells = <1>;
9 #size-cells = <1>;
10 chosen { };
11 aliases { };
12 memory { device_type = "memory"; reg = <0 0>; };
13};
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
new file mode 100644
index 00000000000..e5818668d09
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -0,0 +1,70 @@
1/dts-v1/;
2
3/memreserve/ 0x1c000000 0x04000000;
4/include/ "tegra20.dtsi"
5
6/ {
7 model = "NVIDIA Tegra2 Harmony evaluation board";
8 compatible = "nvidia,harmony", "nvidia,tegra20";
9
10 chosen {
11 bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait";
12 };
13
14 memory@0 {
15 reg = < 0x00000000 0x40000000 >;
16 };
17
18 i2c@7000c000 {
19 clock-frequency = <400000>;
20
21 codec: wm8903@1a {
22 compatible = "wlf,wm8903";
23 reg = <0x1a>;
24 interrupts = < 347 >;
25
26 gpio-controller;
27 #gpio-cells = <2>;
28
29 /* 0x8000 = Not configured */
30 gpio-cfg = < 0x8000 0x8000 0 0x8000 0x8000 >;
31 };
32 };
33
34 i2c@7000c400 {
35 clock-frequency = <400000>;
36 };
37
38 i2c@7000c500 {
39 clock-frequency = <400000>;
40 };
41
42 i2c@7000d000 {
43 clock-frequency = <400000>;
44 };
45
46 sound {
47 compatible = "nvidia,harmony-sound", "nvidia,tegra-wm8903";
48
49 spkr-en-gpios = <&codec 2 0>;
50 hp-det-gpios = <&gpio 178 0>;
51 int-mic-en-gpios = <&gpio 184 0>;
52 ext-mic-en-gpios = <&gpio 185 0>;
53 };
54
55 serial@70006300 {
56 clock-frequency = < 216000000 >;
57 };
58
59 sdhci@c8000200 {
60 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
61 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
62 power-gpios = <&gpio 155 0>; /* gpio PT3 */
63 };
64
65 sdhci@c8000600 {
66 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
67 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
68 power-gpios = <&gpio 70 0>; /* gpio PI6 */
69 };
70};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
new file mode 100644
index 00000000000..64cedca6fc7
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -0,0 +1,28 @@
1/dts-v1/;
2
3/memreserve/ 0x1c000000 0x04000000;
4/include/ "tegra20.dtsi"
5
6/ {
7 model = "NVIDIA Seaboard";
8 compatible = "nvidia,seaboard", "nvidia,tegra20";
9
10 chosen {
11 bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
12 };
13
14 memory {
15 device_type = "memory";
16 reg = < 0x00000000 0x40000000 >;
17 };
18
19 serial@70006300 {
20 clock-frequency = < 216000000 >;
21 };
22
23 sdhci@c8000400 {
24 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
25 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
26 power-gpios = <&gpio 70 0>; /* gpio PI6 */
27 };
28};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
new file mode 100644
index 00000000000..5727595cde6
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -0,0 +1,139 @@
1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
7 intc: interrupt-controller@50041000 {
8 compatible = "nvidia,tegra20-gic";
9 interrupt-controller;
10 #interrupt-cells = <1>;
11 reg = < 0x50041000 0x1000 >,
12 < 0x50040100 0x0100 >;
13 };
14
15 i2c@7000c000 {
16 #address-cells = <1>;
17 #size-cells = <0>;
18 compatible = "nvidia,tegra20-i2c";
19 reg = <0x7000C000 0x100>;
20 interrupts = < 70 >;
21 };
22
23 i2c@7000c400 {
24 #address-cells = <1>;
25 #size-cells = <0>;
26 compatible = "nvidia,tegra20-i2c";
27 reg = <0x7000C400 0x100>;
28 interrupts = < 116 >;
29 };
30
31 i2c@7000c500 {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 compatible = "nvidia,tegra20-i2c";
35 reg = <0x7000C500 0x100>;
36 interrupts = < 124 >;
37 };
38
39 i2c@7000d000 {
40 #address-cells = <1>;
41 #size-cells = <0>;
42 compatible = "nvidia,tegra20-i2c";
43 reg = <0x7000D000 0x200>;
44 interrupts = < 85 >;
45 };
46
47 i2s@70002800 {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 compatible = "nvidia,tegra20-i2s";
51 reg = <0x70002800 0x200>;
52 interrupts = < 45 >;
53 dma-channel = < 2 >;
54 };
55
56 i2s@70002a00 {
57 #address-cells = <1>;
58 #size-cells = <0>;
59 compatible = "nvidia,tegra20-i2s";
60 reg = <0x70002a00 0x200>;
61 interrupts = < 35 >;
62 dma-channel = < 1 >;
63 };
64
65 das@70000c00 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 compatible = "nvidia,tegra20-das";
69 reg = <0x70000c00 0x80>;
70 };
71
72 gpio: gpio@6000d000 {
73 compatible = "nvidia,tegra20-gpio";
74 reg = < 0x6000d000 0x1000 >;
75 interrupts = < 64 65 66 67 87 119 121 >;
76 #gpio-cells = <2>;
77 gpio-controller;
78 };
79
80 serial@70006000 {
81 compatible = "nvidia,tegra20-uart";
82 reg = <0x70006000 0x40>;
83 reg-shift = <2>;
84 interrupts = < 68 >;
85 };
86
87 serial@70006040 {
88 compatible = "nvidia,tegra20-uart";
89 reg = <0x70006040 0x40>;
90 reg-shift = <2>;
91 interrupts = < 69 >;
92 };
93
94 serial@70006200 {
95 compatible = "nvidia,tegra20-uart";
96 reg = <0x70006200 0x100>;
97 reg-shift = <2>;
98 interrupts = < 78 >;
99 };
100
101 serial@70006300 {
102 compatible = "nvidia,tegra20-uart";
103 reg = <0x70006300 0x100>;
104 reg-shift = <2>;
105 interrupts = < 122 >;
106 };
107
108 serial@70006400 {
109 compatible = "nvidia,tegra20-uart";
110 reg = <0x70006400 0x100>;
111 reg-shift = <2>;
112 interrupts = < 123 >;
113 };
114
115 sdhci@c8000000 {
116 compatible = "nvidia,tegra20-sdhci";
117 reg = <0xc8000000 0x200>;
118 interrupts = < 46 >;
119 };
120
121 sdhci@c8000200 {
122 compatible = "nvidia,tegra20-sdhci";
123 reg = <0xc8000200 0x200>;
124 interrupts = < 47 >;
125 };
126
127 sdhci@c8000400 {
128 compatible = "nvidia,tegra20-sdhci";
129 reg = <0xc8000400 0x200>;
130 interrupts = < 51 >;
131 };
132
133 sdhci@c8000600 {
134 compatible = "nvidia,tegra20-sdhci";
135 reg = <0xc8000600 0x200>;
136 interrupts = < 63 >;
137 };
138};
139
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
new file mode 100644
index 00000000000..0b32925f214
--- /dev/null
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -0,0 +1,192 @@
1/dts-v1/;
2/include/ "skeleton.dtsi"
3
4/ {
5 model = "ARM Versatile AB";
6 compatible = "arm,versatile-ab";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
10
11 aliases {
12 serial0 = &uart0;
13 serial1 = &uart1;
14 serial2 = &uart2;
15 i2c0 = &i2c0;
16 };
17
18 memory {
19 reg = <0x0 0x08000000>;
20 };
21
22 flash@34000000 {
23 compatible = "arm,versatile-flash";
24 reg = <0x34000000 0x4000000>;
25 bank-width = <4>;
26 };
27
28 i2c0: i2c@10002000 {
29 #address-cells = <1>;
30 #size-cells = <0>;
31 compatible = "arm,versatile-i2c";
32 reg = <0x10002000 0x1000>;
33
34 rtc@68 {
35 compatible = "dallas,ds1338";
36 reg = <0x68>;
37 };
38 };
39
40 net@10010000 {
41 compatible = "smsc,lan91c111";
42 reg = <0x10010000 0x10000>;
43 interrupts = <25>;
44 };
45
46 lcd@10008000 {
47 compatible = "arm,versatile-lcd";
48 reg = <0x10008000 0x1000>;
49 };
50
51 amba {
52 compatible = "arm,amba-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 vic: intc@10140000 {
58 compatible = "arm,versatile-vic";
59 interrupt-controller;
60 #interrupt-cells = <1>;
61 reg = <0x10140000 0x1000>;
62 };
63
64 sic: intc@10003000 {
65 compatible = "arm,versatile-sic";
66 interrupt-controller;
67 #interrupt-cells = <1>;
68 reg = <0x10003000 0x1000>;
69 interrupt-parent = <&vic>;
70 interrupts = <31>; /* Cascaded to vic */
71 };
72
73 dma@10130000 {
74 compatible = "arm,pl081", "arm,primecell";
75 reg = <0x10130000 0x1000>;
76 interrupts = <17>;
77 };
78
79 uart0: uart@101f1000 {
80 compatible = "arm,pl011", "arm,primecell";
81 reg = <0x101f1000 0x1000>;
82 interrupts = <12>;
83 };
84
85 uart1: uart@101f2000 {
86 compatible = "arm,pl011", "arm,primecell";
87 reg = <0x101f2000 0x1000>;
88 interrupts = <13>;
89 };
90
91 uart2: uart@101f3000 {
92 compatible = "arm,pl011", "arm,primecell";
93 reg = <0x101f3000 0x1000>;
94 interrupts = <14>;
95 };
96
97 smc@10100000 {
98 compatible = "arm,primecell";
99 reg = <0x10100000 0x1000>;
100 };
101
102 mpmc@10110000 {
103 compatible = "arm,primecell";
104 reg = <0x10110000 0x1000>;
105 };
106
107 display@10120000 {
108 compatible = "arm,pl110", "arm,primecell";
109 reg = <0x10120000 0x1000>;
110 interrupts = <16>;
111 };
112
113 sctl@101e0000 {
114 compatible = "arm,primecell";
115 reg = <0x101e0000 0x1000>;
116 };
117
118 watchdog@101e1000 {
119 compatible = "arm,primecell";
120 reg = <0x101e1000 0x1000>;
121 interrupts = <0>;
122 };
123
124 gpio0: gpio@101e4000 {
125 compatible = "arm,pl061", "arm,primecell";
126 reg = <0x101e4000 0x1000>;
127 gpio-controller;
128 interrupts = <6>;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 };
133
134 gpio1: gpio@101e5000 {
135 compatible = "arm,pl061", "arm,primecell";
136 reg = <0x101e5000 0x1000>;
137 interrupts = <7>;
138 gpio-controller;
139 #gpio-cells = <2>;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 };
143
144 rtc@101e8000 {
145 compatible = "arm,pl030", "arm,primecell";
146 reg = <0x101e8000 0x1000>;
147 interrupts = <10>;
148 };
149
150 sci@101f0000 {
151 compatible = "arm,primecell";
152 reg = <0x101f0000 0x1000>;
153 interrupts = <15>;
154 };
155
156 ssp@101f4000 {
157 compatible = "arm,pl022", "arm,primecell";
158 reg = <0x101f4000 0x1000>;
159 interrupts = <11>;
160 };
161
162 fpga {
163 compatible = "arm,versatile-fpga", "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 ranges = <0 0x10000000 0x10000>;
167
168 aaci@4000 {
169 compatible = "arm,primecell";
170 reg = <0x4000 0x1000>;
171 interrupts = <24>;
172 };
173 mmc@5000 {
174 compatible = "arm,primecell";
175 reg = < 0x5000 0x1000>;
176 interrupts = <22>;
177 };
178 kmi@6000 {
179 compatible = "arm,pl050", "arm,primecell";
180 reg = <0x6000 0x1000>;
181 interrupt-parent = <&sic>;
182 interrupts = <3>;
183 };
184 kmi@7000 {
185 compatible = "arm,pl050", "arm,primecell";
186 reg = <0x7000 0x1000>;
187 interrupt-parent = <&sic>;
188 interrupts = <4>;
189 };
190 };
191 };
192};
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
new file mode 100644
index 00000000000..8a614e39800
--- /dev/null
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -0,0 +1,48 @@
1/include/ "versatile-ab.dts"
2
3/ {
4 model = "ARM Versatile PB";
5 compatible = "arm,versatile-pb";
6
7 amba {
8 gpio2: gpio@101e6000 {
9 compatible = "arm,pl061", "arm,primecell";
10 reg = <0x101e6000 0x1000>;
11 interrupts = <8>;
12 gpio-controller;
13 #gpio-cells = <2>;
14 interrupt-controller;
15 #interrupt-cells = <2>;
16 };
17
18 gpio3: gpio@101e7000 {
19 compatible = "arm,pl061", "arm,primecell";
20 reg = <0x101e7000 0x1000>;
21 interrupts = <9>;
22 gpio-controller;
23 #gpio-cells = <2>;
24 interrupt-controller;
25 #interrupt-cells = <2>;
26 };
27
28 fpga {
29 uart@9000 {
30 compatible = "arm,pl011", "arm,primecell";
31 reg = <0x9000 0x1000>;
32 interrupt-parent = <&sic>;
33 interrupts = <6>;
34 };
35 sci@a000 {
36 compatible = "arm,primecell";
37 reg = <0xa000 0x1000>;
38 interrupt-parent = <&sic>;
39 interrupts = <5>;
40 };
41 mmc@b000 {
42 compatible = "arm,primecell";
43 reg = <0xb000 0x1000>;
44 interrupts = <23>;
45 };
46 };
47 };
48};
diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts
new file mode 100644
index 00000000000..37ca192fb19
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-ep107.dts
@@ -0,0 +1,52 @@
1/*
2 * Copyright (C) 2011 Xilinx
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15/ {
16 model = "Xilinx Zynq EP107";
17 compatible = "xlnx,zynq-ep107";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&intc>;
21
22 memory {
23 device_type = "memory";
24 reg = <0x0 0x10000000>;
25 };
26
27 chosen {
28 bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk";
29 linux,stdout-path = &uart0;
30 };
31
32 amba {
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges;
37
38 intc: interrupt-controller@f8f01000 {
39 interrupt-controller;
40 compatible = "arm,gic";
41 reg = <0xF8F01000 0x1000>;
42 #interrupt-cells = <2>;
43 };
44
45 uart0: uart@e0000000 {
46 compatible = "xlnx,xuartps";
47 reg = <0xE0000000 0x1000>;
48 interrupts = <59 0>;
49 clock = <50000000>;
50 };
51 };
52};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-10 15:33:51 -0400