3 files changed, 115 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
new file mode 100644
index 00000000000..939a26d541f
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
@@ -0,0 +1,76 @@
+Integrated Flash Controller
+
+Properties:
+- name : Should be ifc
+- compatible : should contain "fsl,ifc". The version of the integrated
+               flash controller can be found in the IFC_REV register at
+               offset zero.
+
+- #address-cells : Should be either two or three.  The first cell is the
+                   chipselect number, and the remaining cells are the
+                   offset into the chipselect.
+- #size-cells : Either one or two, depending on how large each chipselect
+                can be.
+- reg : Offset and length of the register set for the device
+- interrupts : IFC has two interrupts. The first one is the "common"
+               interrupt(CM_EVTER_STAT), and second is the NAND interrupt
+               (NAND_EVTER_STAT).
+
+- ranges : Each range corresponds to a single chipselect, and covers
+           the entire access window as configured.
+
+Child device nodes describe the devices connected to IFC such as NOR (e.g.
+cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
+like FPGAs, CPLDs, etc.
+
+Example:
+
+        ifc@ffe1e000 {
+                compatible = "fsl,ifc", "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                reg = <0x0 0xffe1e000 0 0x2000>;
+                interrupts = <16 2 19 2>;
+
+                /* NOR, NAND Flashes and CPLD on board */
+                ranges = <0x0 0x0 0x0 0xee000000 0x02000000
+                          0x1 0x0 0x0 0xffa00000 0x00010000
+                          0x3 0x0 0x0 0xffb00000 0x00020000>;
+
+                flash@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x2000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        partition@0 {
+                                /* 32MB for user data */
+                                reg = <0x0 0x02000000>;
+                                label = "NOR Data";
+                        };
+                };
+
+                flash@1,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,ifc-nand";
+                        reg = <0x1 0x0 0x10000>;
+
+                        partition@0 {
+                                /* This location must not be altered  */
+                                /* 1MB for u-boot Bootloader Image */
+                                reg = <0x0 0x00100000>;
+                                label = "NAND U-Boot Image";
+                                read-only;
+                        };
+                };
+
+                cpld@3,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,p1010rdb-cpld";
+                        reg = <0x3 0x0 0x000001f>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
new file mode 100644
index 00000000000..df41958140e
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
@@ -0,0 +1,38 @@
+* Freescale MPIC timers
+
+Required properties:
+- compatible: "fsl,mpic-global-timer"
+
+- reg : Contains two regions.  The first is the main timer register bank
+  (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx).  The second is the timer control
+  register (TCRx) for the group.
+
+- fsl,available-ranges: use <start count> style section to define which
+  timer interrupts can be used.  This property is optional; without this,
+  all timers within the group can be used.
+
+- interrupts: one interrupt per timer in the group, in order, starting
+  with timer zero.  If timer-available-ranges is present, only the
+  interrupts that correspond to available timers shall be present.
+
+Example:
+        /* Note that this requires #interrupt-cells to be 4 */
+        timer0: timer@41100 {
+                compatible = "fsl,mpic-global-timer";
+                reg = <0x41100 0x100 0x41300 4>;
+
+                /* Another AMP partition is using timers 0 and 1 */
+                fsl,available-ranges = <2 2>;
+
+                interrupts = <2 0 3 0
+                              3 0 3 0>;
+        };
+
+        timer1: timer@42100 {
+                compatible = "fsl,mpic-global-timer";
+                reg = <0x42100 0x100 0x42300 4>;
+                interrupts = <4 0 3 0
+                              5 0 3 0
+                              6 0 3 0
+                              7 0 3 0>;
+        };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
index 4f6145859aa..2cf38bd841f 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
@@ -190,7 +190,7 @@ EXAMPLE 4
          */
         timer0: timer@41100 {
                 compatible = "fsl,mpic-global-timer";
-                reg = <0x41100 0x100>;
+                reg = <0x41100 0x100 0x41300 4>;
                 interrupts = <0 0 3 0
                               1 0 3 0
                               2 0 3 0