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Diffstat (limited to 'Documentation/devicetree/bindings/mips/cavium/ciu.txt')
-rw-r--r-- | Documentation/devicetree/bindings/mips/cavium/ciu.txt | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/Documentation/devicetree/bindings/mips/cavium/ciu.txt deleted file mode 100644 index 2c2d0746b43..00000000000 --- a/Documentation/devicetree/bindings/mips/cavium/ciu.txt +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | * Central Interrupt Unit | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-3860-ciu" | ||
5 | |||
6 | Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs. | ||
7 | |||
8 | - interrupt-controller: This is an interrupt controller. | ||
9 | |||
10 | - reg: The base address of the CIU's register bank. | ||
11 | |||
12 | - #interrupt-cells: Must be <2>. The first cell is the bank within | ||
13 | the CIU and may have a value of 0 or 1. The second cell is the bit | ||
14 | within the bank and may have a value between 0 and 63. | ||
15 | |||
16 | Example: | ||
17 | interrupt-controller@1070000000000 { | ||
18 | compatible = "cavium,octeon-3860-ciu"; | ||
19 | interrupt-controller; | ||
20 | /* Interrupts are specified by two parts: | ||
21 | * 1) Controller register (0 or 1) | ||
22 | * 2) Bit within the register (0..63) | ||
23 | */ | ||
24 | #interrupt-cells = <2>; | ||
25 | reg = <0x10700 0x00000000 0x0 0x7000>; | ||
26 | }; | ||