1 files changed, 17 insertions, 17 deletions

diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
index 7564e88bfa4..e7be75b96e4 100644
--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
@@ -183,21 +183,21 @@ Description:	Discover and change clock speed of CPUs
                 to learn how to control the knobs.
 
 
-What:      /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
-Date:      August 2008
+What:           /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1}
+Date:           August 2008
 KernelVersion:  2.6.27
-Contact:        mark.langsdorf@amd.com
-Description:    These files exist in every cpu's cache index directories.
-                There are currently 2 cache_disable_# files in each
-                directory.  Reading from these files on a supported
-                processor will return that cache disable index value
-                for that processor and node.  Writing to one of these
-                files will cause the specificed cache index to be disabled.
-
-                Currently, only AMD Family 10h Processors support cache index
-                disable, and only for their L3 caches.  See the BIOS and
-                Kernel Developer's Guide at
-                http://support.amd.com/us/Embedded_TechDocs/31116-Public-GH-BKDG_3-28_5-28-09.pdf       
-                for formatting information and other details on the
-                cache index disable.
-Users:    joachim.deguara@amd.com
+Contact:        discuss@x86-64.org
+Description:    Disable L3 cache indices
+
+                These files exist in every CPU's cache/index3 directory. Each
+                cache_disable_{0,1} file corresponds to one disable slot which
+                can be used to disable a cache index. Reading from these files
+                on a processor with this functionality will return the currently
+                disabled index for that node. There is one L3 structure per
+                node, or per internal node on MCM machines. Writing a valid
+                index to one of these files will cause the specificed cache
+                index to be disabled.
+
+                All AMD processors with L3 caches provide this functionality.
+                For details, see BKDGs at
+                http://developer.amd.com/documentation/guides/Pages/default.aspx