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-rw-r--r--arch/x86/include/asm/bigsmp/apic.h4
-rw-r--r--arch/x86/include/asm/es7000/apic.h4
-rw-r--r--arch/x86/include/asm/genapic.h4
-rw-r--r--arch/x86/include/asm/mach-default/mach_apic.h8
-rw-r--r--arch/x86/include/asm/mach-generic/mach_apic.h4
-rw-r--r--arch/x86/include/asm/numaq/apic.h4
-rw-r--r--arch/x86/include/asm/summit/apic.h4
-rw-r--r--arch/x86/kernel/genapic_flat_64.c8
-rw-r--r--arch/x86/kernel/genx2apic_cluster.c4
-rw-r--r--arch/x86/kernel/genx2apic_phys.c4
-rw-r--r--arch/x86/kernel/genx2apic_uv_x.c4
-rw-r--r--arch/x86/kernel/io_apic.c30
-rw-r--r--arch/x86/mach-generic/bigsmp.c4
-rw-r--r--arch/x86/mach-generic/default.c4
-rw-r--r--arch/x86/mach-generic/es7000.c8
-rw-r--r--arch/x86/mach-generic/numaq.c4
-rw-r--r--arch/x86/mach-generic/summit.c4
17 files changed, 53 insertions, 53 deletions
diff --git a/arch/x86/include/asm/bigsmp/apic.h b/arch/x86/include/asm/bigsmp/apic.h
index 42c56df3ff3..8ff8bba8833 100644
--- a/arch/x86/include/asm/bigsmp/apic.h
+++ b/arch/x86/include/asm/bigsmp/apic.h
@@ -21,8 +21,8 @@ static inline const cpumask_t *target_cpus(void)
21#undef APIC_DEST_LOGICAL 21#undef APIC_DEST_LOGICAL
22#define APIC_DEST_LOGICAL 0 22#define APIC_DEST_LOGICAL 0
23#define APIC_DFR_VALUE (APIC_DFR_FLAT) 23#define APIC_DFR_VALUE (APIC_DFR_FLAT)
24#define INT_DELIVERY_MODE (dest_Fixed) 24#define IRQ_DELIVERY_MODE (dest_Fixed)
25#define INT_DEST_MODE (0) /* phys delivery to target proc */ 25#define IRQ_DEST_MODE (0) /* phys delivery to target proc */
26#define NO_BALANCE_IRQ (0) 26#define NO_BALANCE_IRQ (0)
27 27
28static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) 28static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
diff --git a/arch/x86/include/asm/es7000/apic.h b/arch/x86/include/asm/es7000/apic.h
index a1819b510de..830e8731cc0 100644
--- a/arch/x86/include/asm/es7000/apic.h
+++ b/arch/x86/include/asm/es7000/apic.h
@@ -27,8 +27,8 @@ static inline const cpumask_t *target_cpus(void)
27#define NO_BALANCE_IRQ_CLUSTER (1) 27#define NO_BALANCE_IRQ_CLUSTER (1)
28 28
29#define APIC_DFR_VALUE (APIC_DFR_FLAT) 29#define APIC_DFR_VALUE (APIC_DFR_FLAT)
30#define INT_DELIVERY_MODE (dest_Fixed) 30#define IRQ_DELIVERY_MODE (dest_Fixed)
31#define INT_DEST_MODE (0) /* phys delivery to target procs */ 31#define IRQ_DEST_MODE (0) /* phys delivery to target procs */
32#define NO_BALANCE_IRQ (0) 32#define NO_BALANCE_IRQ (0)
33#undef APIC_DEST_LOGICAL 33#undef APIC_DEST_LOGICAL
34#define APIC_DEST_LOGICAL 0x0 34#define APIC_DEST_LOGICAL 0x0
diff --git a/arch/x86/include/asm/genapic.h b/arch/x86/include/asm/genapic.h
index 108abdf6953..e998e3df5d2 100644
--- a/arch/x86/include/asm/genapic.h
+++ b/arch/x86/include/asm/genapic.h
@@ -23,8 +23,8 @@ struct genapic {
23 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 23 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
24 int (*apic_id_registered)(void); 24 int (*apic_id_registered)(void);
25 25
26 u32 int_delivery_mode; 26 u32 irq_delivery_mode;
27 u32 int_dest_mode; 27 u32 irq_dest_mode;
28 28
29 const struct cpumask *(*target_cpus)(void); 29 const struct cpumask *(*target_cpus)(void);
30 30
diff --git a/arch/x86/include/asm/mach-default/mach_apic.h b/arch/x86/include/asm/mach-default/mach_apic.h
index 6a454fa0b43..b5364793262 100644
--- a/arch/x86/include/asm/mach-default/mach_apic.h
+++ b/arch/x86/include/asm/mach-default/mach_apic.h
@@ -22,8 +22,8 @@ static inline const struct cpumask *target_cpus(void)
22 22
23#ifdef CONFIG_X86_64 23#ifdef CONFIG_X86_64
24#include <asm/genapic.h> 24#include <asm/genapic.h>
25#define INT_DELIVERY_MODE (apic->int_delivery_mode) 25#define IRQ_DELIVERY_MODE (apic->irq_delivery_mode)
26#define INT_DEST_MODE (apic->int_dest_mode) 26#define IRQ_DEST_MODE (apic->irq_dest_mode)
27#define TARGET_CPUS (apic->target_cpus()) 27#define TARGET_CPUS (apic->target_cpus())
28#define init_apic_ldr (apic->init_apic_ldr) 28#define init_apic_ldr (apic->init_apic_ldr)
29#define cpu_mask_to_apicid (apic->cpu_mask_to_apicid) 29#define cpu_mask_to_apicid (apic->cpu_mask_to_apicid)
@@ -35,8 +35,8 @@ static inline const struct cpumask *target_cpus(void)
35#define wakeup_secondary_cpu (apic->wakeup_cpu) 35#define wakeup_secondary_cpu (apic->wakeup_cpu)
36extern void setup_apic_routing(void); 36extern void setup_apic_routing(void);
37#else 37#else
38#define INT_DELIVERY_MODE dest_LowestPrio 38#define IRQ_DELIVERY_MODE dest_LowestPrio
39#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ 39#define IRQ_DEST_MODE 1 /* logical delivery broadcast to all procs */
40#define TARGET_CPUS (target_cpus()) 40#define TARGET_CPUS (target_cpus())
41#define wakeup_secondary_cpu wakeup_secondary_cpu_via_init 41#define wakeup_secondary_cpu wakeup_secondary_cpu_via_init
42/* 42/*
diff --git a/arch/x86/include/asm/mach-generic/mach_apic.h b/arch/x86/include/asm/mach-generic/mach_apic.h
index cc6e9d70f06..03492f2219e 100644
--- a/arch/x86/include/asm/mach-generic/mach_apic.h
+++ b/arch/x86/include/asm/mach-generic/mach_apic.h
@@ -5,8 +5,8 @@
5 5
6#define esr_disable (apic->ESR_DISABLE) 6#define esr_disable (apic->ESR_DISABLE)
7#define NO_BALANCE_IRQ (apic->no_balance_irq) 7#define NO_BALANCE_IRQ (apic->no_balance_irq)
8#define INT_DELIVERY_MODE (apic->int_delivery_mode) 8#define IRQ_DELIVERY_MODE (apic->irq_delivery_mode)
9#define INT_DEST_MODE (apic->int_dest_mode) 9#define IRQ_DEST_MODE (apic->irq_dest_mode)
10#undef APIC_DEST_LOGICAL 10#undef APIC_DEST_LOGICAL
11#define APIC_DEST_LOGICAL (apic->apic_destination_logical) 11#define APIC_DEST_LOGICAL (apic->apic_destination_logical)
12#define TARGET_CPUS (apic->target_cpus()) 12#define TARGET_CPUS (apic->target_cpus())
diff --git a/arch/x86/include/asm/numaq/apic.h b/arch/x86/include/asm/numaq/apic.h
index 59b62b19d02..d885e35df18 100644
--- a/arch/x86/include/asm/numaq/apic.h
+++ b/arch/x86/include/asm/numaq/apic.h
@@ -15,8 +15,8 @@ static inline const cpumask_t *target_cpus(void)
15#define NO_BALANCE_IRQ (1) 15#define NO_BALANCE_IRQ (1)
16#define esr_disable (1) 16#define esr_disable (1)
17 17
18#define INT_DELIVERY_MODE dest_LowestPrio 18#define IRQ_DELIVERY_MODE dest_LowestPrio
19#define INT_DEST_MODE 0 /* physical delivery on LOCAL quad */ 19#define IRQ_DEST_MODE 0 /* physical delivery on LOCAL quad */
20 20
21static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) 21static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
22{ 22{
diff --git a/arch/x86/include/asm/summit/apic.h b/arch/x86/include/asm/summit/apic.h
index a36ef6e4b1f..0b7d0d14e56 100644
--- a/arch/x86/include/asm/summit/apic.h
+++ b/arch/x86/include/asm/summit/apic.h
@@ -24,8 +24,8 @@ static inline const cpumask_t *target_cpus(void)
24 return &cpumask_of_cpu(0); 24 return &cpumask_of_cpu(0);
25} 25}
26 26
27#define INT_DELIVERY_MODE (dest_LowestPrio) 27#define IRQ_DELIVERY_MODE (dest_LowestPrio)
28#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ 28#define IRQ_DEST_MODE 1 /* logical delivery broadcast to all procs */
29 29
30static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) 30static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
31{ 31{
diff --git a/arch/x86/kernel/genapic_flat_64.c b/arch/x86/kernel/genapic_flat_64.c
index e9233374cef..0a263d6bb5e 100644
--- a/arch/x86/kernel/genapic_flat_64.c
+++ b/arch/x86/kernel/genapic_flat_64.c
@@ -180,8 +180,8 @@ struct genapic apic_flat = {
180 .acpi_madt_oem_check = flat_acpi_madt_oem_check, 180 .acpi_madt_oem_check = flat_acpi_madt_oem_check,
181 .apic_id_registered = flat_apic_id_registered, 181 .apic_id_registered = flat_apic_id_registered,
182 182
183 .int_delivery_mode = dest_LowestPrio, 183 .irq_delivery_mode = dest_LowestPrio,
184 .int_dest_mode = (APIC_DEST_LOGICAL != 0), 184 .irq_dest_mode = (APIC_DEST_LOGICAL != 0),
185 185
186 .target_cpus = flat_target_cpus, 186 .target_cpus = flat_target_cpus,
187 .ESR_DISABLE = 0, 187 .ESR_DISABLE = 0,
@@ -326,8 +326,8 @@ struct genapic apic_physflat = {
326 .acpi_madt_oem_check = physflat_acpi_madt_oem_check, 326 .acpi_madt_oem_check = physflat_acpi_madt_oem_check,
327 .apic_id_registered = flat_apic_id_registered, 327 .apic_id_registered = flat_apic_id_registered,
328 328
329 .int_delivery_mode = dest_Fixed, 329 .irq_delivery_mode = dest_Fixed,
330 .int_dest_mode = (APIC_DEST_PHYSICAL != 0), 330 .irq_dest_mode = (APIC_DEST_PHYSICAL != 0),
331 331
332 .target_cpus = physflat_target_cpus, 332 .target_cpus = physflat_target_cpus,
333 .ESR_DISABLE = 0, 333 .ESR_DISABLE = 0,
diff --git a/arch/x86/kernel/genx2apic_cluster.c b/arch/x86/kernel/genx2apic_cluster.c
index fc855e503ac..e9ff7dc9a0f 100644
--- a/arch/x86/kernel/genx2apic_cluster.c
+++ b/arch/x86/kernel/genx2apic_cluster.c
@@ -182,8 +182,8 @@ struct genapic apic_x2apic_cluster = {
182 .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, 182 .acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
183 .apic_id_registered = x2apic_apic_id_registered, 183 .apic_id_registered = x2apic_apic_id_registered,
184 184
185 .int_delivery_mode = dest_LowestPrio, 185 .irq_delivery_mode = dest_LowestPrio,
186 .int_dest_mode = (APIC_DEST_LOGICAL != 0), 186 .irq_dest_mode = (APIC_DEST_LOGICAL != 0),
187 187
188 .target_cpus = x2apic_target_cpus, 188 .target_cpus = x2apic_target_cpus,
189 .ESR_DISABLE = 0, 189 .ESR_DISABLE = 0,
diff --git a/arch/x86/kernel/genx2apic_phys.c b/arch/x86/kernel/genx2apic_phys.c
index c98361fb7ee..8141b5a88f6 100644
--- a/arch/x86/kernel/genx2apic_phys.c
+++ b/arch/x86/kernel/genx2apic_phys.c
@@ -178,8 +178,8 @@ struct genapic apic_x2apic_phys = {
178 .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, 178 .acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
179 .apic_id_registered = x2apic_apic_id_registered, 179 .apic_id_registered = x2apic_apic_id_registered,
180 180
181 .int_delivery_mode = dest_Fixed, 181 .irq_delivery_mode = dest_Fixed,
182 .int_dest_mode = (APIC_DEST_PHYSICAL != 0), 182 .irq_dest_mode = (APIC_DEST_PHYSICAL != 0),
183 183
184 .target_cpus = x2apic_target_cpus, 184 .target_cpus = x2apic_target_cpus,
185 .ESR_DISABLE = 0, 185 .ESR_DISABLE = 0,
diff --git a/arch/x86/kernel/genx2apic_uv_x.c b/arch/x86/kernel/genx2apic_uv_x.c
index 94f606f204a..6a73cad0d3e 100644
--- a/arch/x86/kernel/genx2apic_uv_x.c
+++ b/arch/x86/kernel/genx2apic_uv_x.c
@@ -243,8 +243,8 @@ struct genapic apic_x2apic_uv_x = {
243 .acpi_madt_oem_check = uv_acpi_madt_oem_check, 243 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
244 .apic_id_registered = uv_apic_id_registered, 244 .apic_id_registered = uv_apic_id_registered,
245 245
246 .int_delivery_mode = dest_Fixed, 246 .irq_delivery_mode = dest_Fixed,
247 .int_dest_mode = (APIC_DEST_PHYSICAL != 0), 247 .irq_dest_mode = (APIC_DEST_PHYSICAL != 0),
248 248
249 .target_cpus = uv_target_cpus, 249 .target_cpus = uv_target_cpus,
250 .ESR_DISABLE = 0, 250 .ESR_DISABLE = 0,
diff --git a/arch/x86/kernel/io_apic.c b/arch/x86/kernel/io_apic.c
index 7283234229f..5f967b9c9af 100644
--- a/arch/x86/kernel/io_apic.c
+++ b/arch/x86/kernel/io_apic.c
@@ -1514,9 +1514,9 @@ static int setup_ioapic_entry(int apic_id, int irq,
1514 memset(&irte, 0, sizeof(irte)); 1514 memset(&irte, 0, sizeof(irte));
1515 1515
1516 irte.present = 1; 1516 irte.present = 1;
1517 irte.dst_mode = INT_DEST_MODE; 1517 irte.dst_mode = IRQ_DEST_MODE;
1518 irte.trigger_mode = trigger; 1518 irte.trigger_mode = trigger;
1519 irte.dlvry_mode = INT_DELIVERY_MODE; 1519 irte.dlvry_mode = IRQ_DELIVERY_MODE;
1520 irte.vector = vector; 1520 irte.vector = vector;
1521 irte.dest_id = IRTE_DEST(destination); 1521 irte.dest_id = IRTE_DEST(destination);
1522 1522
@@ -1529,8 +1529,8 @@ static int setup_ioapic_entry(int apic_id, int irq,
1529 } else 1529 } else
1530#endif 1530#endif
1531 { 1531 {
1532 entry->delivery_mode = INT_DELIVERY_MODE; 1532 entry->delivery_mode = IRQ_DELIVERY_MODE;
1533 entry->dest_mode = INT_DEST_MODE; 1533 entry->dest_mode = IRQ_DEST_MODE;
1534 entry->dest = destination; 1534 entry->dest = destination;
1535 } 1535 }
1536 1536
@@ -1659,10 +1659,10 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1659 * We use logical delivery to get the timer IRQ 1659 * We use logical delivery to get the timer IRQ
1660 * to the first CPU. 1660 * to the first CPU.
1661 */ 1661 */
1662 entry.dest_mode = INT_DEST_MODE; 1662 entry.dest_mode = IRQ_DEST_MODE;
1663 entry.mask = 1; /* mask IRQ now */ 1663 entry.mask = 1; /* mask IRQ now */
1664 entry.dest = cpu_mask_to_apicid(TARGET_CPUS); 1664 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1665 entry.delivery_mode = INT_DELIVERY_MODE; 1665 entry.delivery_mode = IRQ_DELIVERY_MODE;
1666 entry.polarity = 0; 1666 entry.polarity = 0;
1667 entry.trigger = 0; 1667 entry.trigger = 0;
1668 entry.vector = vector; 1668 entry.vector = vector;
@@ -3279,9 +3279,9 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
3279 memset (&irte, 0, sizeof(irte)); 3279 memset (&irte, 0, sizeof(irte));
3280 3280
3281 irte.present = 1; 3281 irte.present = 1;
3282 irte.dst_mode = INT_DEST_MODE; 3282 irte.dst_mode = IRQ_DEST_MODE;
3283 irte.trigger_mode = 0; /* edge */ 3283 irte.trigger_mode = 0; /* edge */
3284 irte.dlvry_mode = INT_DELIVERY_MODE; 3284 irte.dlvry_mode = IRQ_DELIVERY_MODE;
3285 irte.vector = cfg->vector; 3285 irte.vector = cfg->vector;
3286 irte.dest_id = IRTE_DEST(dest); 3286 irte.dest_id = IRTE_DEST(dest);
3287 3287
@@ -3299,10 +3299,10 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
3299 msg->address_hi = MSI_ADDR_BASE_HI; 3299 msg->address_hi = MSI_ADDR_BASE_HI;
3300 msg->address_lo = 3300 msg->address_lo =
3301 MSI_ADDR_BASE_LO | 3301 MSI_ADDR_BASE_LO |
3302 ((INT_DEST_MODE == 0) ? 3302 ((IRQ_DEST_MODE == 0) ?
3303 MSI_ADDR_DEST_MODE_PHYSICAL: 3303 MSI_ADDR_DEST_MODE_PHYSICAL:
3304 MSI_ADDR_DEST_MODE_LOGICAL) | 3304 MSI_ADDR_DEST_MODE_LOGICAL) |
3305 ((INT_DELIVERY_MODE != dest_LowestPrio) ? 3305 ((IRQ_DELIVERY_MODE != dest_LowestPrio) ?
3306 MSI_ADDR_REDIRECTION_CPU: 3306 MSI_ADDR_REDIRECTION_CPU:
3307 MSI_ADDR_REDIRECTION_LOWPRI) | 3307 MSI_ADDR_REDIRECTION_LOWPRI) |
3308 MSI_ADDR_DEST_ID(dest); 3308 MSI_ADDR_DEST_ID(dest);
@@ -3310,7 +3310,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
3310 msg->data = 3310 msg->data =
3311 MSI_DATA_TRIGGER_EDGE | 3311 MSI_DATA_TRIGGER_EDGE |
3312 MSI_DATA_LEVEL_ASSERT | 3312 MSI_DATA_LEVEL_ASSERT |
3313 ((INT_DELIVERY_MODE != dest_LowestPrio) ? 3313 ((IRQ_DELIVERY_MODE != dest_LowestPrio) ?
3314 MSI_DATA_DELIVERY_FIXED: 3314 MSI_DATA_DELIVERY_FIXED:
3315 MSI_DATA_DELIVERY_LOWPRI) | 3315 MSI_DATA_DELIVERY_LOWPRI) |
3316 MSI_DATA_VECTOR(cfg->vector); 3316 MSI_DATA_VECTOR(cfg->vector);
@@ -3711,11 +3711,11 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3711 HT_IRQ_LOW_BASE | 3711 HT_IRQ_LOW_BASE |
3712 HT_IRQ_LOW_DEST_ID(dest) | 3712 HT_IRQ_LOW_DEST_ID(dest) |
3713 HT_IRQ_LOW_VECTOR(cfg->vector) | 3713 HT_IRQ_LOW_VECTOR(cfg->vector) |
3714 ((INT_DEST_MODE == 0) ? 3714 ((IRQ_DEST_MODE == 0) ?
3715 HT_IRQ_LOW_DM_PHYSICAL : 3715 HT_IRQ_LOW_DM_PHYSICAL :
3716 HT_IRQ_LOW_DM_LOGICAL) | 3716 HT_IRQ_LOW_DM_LOGICAL) |
3717 HT_IRQ_LOW_RQEOI_EDGE | 3717 HT_IRQ_LOW_RQEOI_EDGE |
3718 ((INT_DELIVERY_MODE != dest_LowestPrio) ? 3718 ((IRQ_DELIVERY_MODE != dest_LowestPrio) ?
3719 HT_IRQ_LOW_MT_FIXED : 3719 HT_IRQ_LOW_MT_FIXED :
3720 HT_IRQ_LOW_MT_ARBITRATED) | 3720 HT_IRQ_LOW_MT_ARBITRATED) |
3721 HT_IRQ_LOW_IRQ_MASKED; 3721 HT_IRQ_LOW_IRQ_MASKED;
@@ -3763,8 +3763,8 @@ int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3763 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); 3763 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3764 3764
3765 entry->vector = cfg->vector; 3765 entry->vector = cfg->vector;
3766 entry->delivery_mode = INT_DELIVERY_MODE; 3766 entry->delivery_mode = IRQ_DELIVERY_MODE;
3767 entry->dest_mode = INT_DEST_MODE; 3767 entry->dest_mode = IRQ_DEST_MODE;
3768 entry->polarity = 0; 3768 entry->polarity = 0;
3769 entry->trigger = 0; 3769 entry->trigger = 0;
3770 entry->mask = 0; 3770 entry->mask = 0;
diff --git a/arch/x86/mach-generic/bigsmp.c b/arch/x86/mach-generic/bigsmp.c
index 17abf5c6242..c15c1aa2dc7 100644
--- a/arch/x86/mach-generic/bigsmp.c
+++ b/arch/x86/mach-generic/bigsmp.c
@@ -64,8 +64,8 @@ struct genapic apic_bigsmp = {
64 .acpi_madt_oem_check = NULL, 64 .acpi_madt_oem_check = NULL,
65 .apic_id_registered = bigsmp_apic_id_registered, 65 .apic_id_registered = bigsmp_apic_id_registered,
66 66
67 .int_delivery_mode = INT_DELIVERY_MODE, 67 .irq_delivery_mode = IRQ_DELIVERY_MODE,
68 .int_dest_mode = INT_DEST_MODE, 68 .irq_dest_mode = IRQ_DEST_MODE,
69 69
70 .target_cpus = target_cpus, 70 .target_cpus = target_cpus,
71 .ESR_DISABLE = esr_disable, 71 .ESR_DISABLE = esr_disable,
diff --git a/arch/x86/mach-generic/default.c b/arch/x86/mach-generic/default.c
index 1f30559e9d8..d32b175eff8 100644
--- a/arch/x86/mach-generic/default.c
+++ b/arch/x86/mach-generic/default.c
@@ -31,8 +31,8 @@ struct genapic apic_default = {
31 .acpi_madt_oem_check = NULL, 31 .acpi_madt_oem_check = NULL,
32 .apic_id_registered = default_apic_id_registered, 32 .apic_id_registered = default_apic_id_registered,
33 33
34 .int_delivery_mode = INT_DELIVERY_MODE, 34 .irq_delivery_mode = IRQ_DELIVERY_MODE,
35 .int_dest_mode = INT_DEST_MODE, 35 .irq_dest_mode = IRQ_DEST_MODE,
36 36
37 .target_cpus = target_cpus, 37 .target_cpus = target_cpus,
38 .ESR_DISABLE = esr_disable, 38 .ESR_DISABLE = esr_disable,
diff --git a/arch/x86/mach-generic/es7000.c b/arch/x86/mach-generic/es7000.c
index d68ca0bce67..06653892953 100644
--- a/arch/x86/mach-generic/es7000.c
+++ b/arch/x86/mach-generic/es7000.c
@@ -21,8 +21,8 @@
21void __init es7000_update_genapic_to_cluster(void) 21void __init es7000_update_genapic_to_cluster(void)
22{ 22{
23 apic->target_cpus = target_cpus_cluster; 23 apic->target_cpus = target_cpus_cluster;
24 apic->int_delivery_mode = INT_DELIVERY_MODE_CLUSTER; 24 apic->irq_delivery_mode = INT_DELIVERY_MODE_CLUSTER;
25 apic->int_dest_mode = INT_DEST_MODE_CLUSTER; 25 apic->irq_dest_mode = INT_DEST_MODE_CLUSTER;
26 apic->no_balance_irq = NO_BALANCE_IRQ_CLUSTER; 26 apic->no_balance_irq = NO_BALANCE_IRQ_CLUSTER;
27 27
28 apic->init_apic_ldr = init_apic_ldr_cluster; 28 apic->init_apic_ldr = init_apic_ldr_cluster;
@@ -107,8 +107,8 @@ struct genapic apic_es7000 = {
107 .acpi_madt_oem_check = es7000_acpi_madt_oem_check, 107 .acpi_madt_oem_check = es7000_acpi_madt_oem_check,
108 .apic_id_registered = es7000_apic_id_registered, 108 .apic_id_registered = es7000_apic_id_registered,
109 109
110 .int_delivery_mode = INT_DELIVERY_MODE, 110 .irq_delivery_mode = IRQ_DELIVERY_MODE,
111 .int_dest_mode = INT_DEST_MODE, 111 .irq_dest_mode = IRQ_DEST_MODE,
112 112
113 .target_cpus = target_cpus, 113 .target_cpus = target_cpus,
114 .ESR_DISABLE = esr_disable, 114 .ESR_DISABLE = esr_disable,
diff --git a/arch/x86/mach-generic/numaq.c b/arch/x86/mach-generic/numaq.c
index b22a79b15b1..401957142fd 100644
--- a/arch/x86/mach-generic/numaq.c
+++ b/arch/x86/mach-generic/numaq.c
@@ -51,8 +51,8 @@ struct genapic apic_numaq = {
51 .acpi_madt_oem_check = NULL, 51 .acpi_madt_oem_check = NULL,
52 .apic_id_registered = numaq_apic_id_registered, 52 .apic_id_registered = numaq_apic_id_registered,
53 53
54 .int_delivery_mode = INT_DELIVERY_MODE, 54 .irq_delivery_mode = IRQ_DELIVERY_MODE,
55 .int_dest_mode = INT_DEST_MODE, 55 .irq_dest_mode = IRQ_DEST_MODE,
56 56
57 .target_cpus = target_cpus, 57 .target_cpus = target_cpus,
58 .ESR_DISABLE = esr_disable, 58 .ESR_DISABLE = esr_disable,
diff --git a/arch/x86/mach-generic/summit.c b/arch/x86/mach-generic/summit.c
index 744fa1b86ef..946da7aa762 100644
--- a/arch/x86/mach-generic/summit.c
+++ b/arch/x86/mach-generic/summit.c
@@ -44,8 +44,8 @@ struct genapic apic_summit = {
44 .acpi_madt_oem_check = summit_acpi_madt_oem_check, 44 .acpi_madt_oem_check = summit_acpi_madt_oem_check,
45 .apic_id_registered = summit_apic_id_registered, 45 .apic_id_registered = summit_apic_id_registered,
46 46
47 .int_delivery_mode = INT_DELIVERY_MODE, 47 .irq_delivery_mode = IRQ_DELIVERY_MODE,
48 .int_dest_mode = INT_DEST_MODE, 48 .irq_dest_mode = IRQ_DEST_MODE,
49 49
50 .target_cpus = target_cpus, 50 .target_cpus = target_cpus,
51 .ESR_DISABLE = esr_disable, 51 .ESR_DISABLE = esr_disable,