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-rw-r--r--drivers/gpu/drm/radeon/ObjectID.h48
-rw-r--r--drivers/gpu/drm/radeon/atombios.h997
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c297
-rw-r--r--drivers/gpu/drm/radeon/evergreen_blit_kms.c27
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h8
-rw-r--r--drivers/gpu/drm/radeon/r600.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon.h5
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c50
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c1078
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c79
-rw-r--r--drivers/gpu/drm/radeon/radeon_family.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq_kms.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c4
-rw-r--r--drivers/gpu/drm/radeon/rv770.c97
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h3
-rw-r--r--include/drm/drm_pciids.h4
18 files changed, 2081 insertions, 639 deletions
diff --git a/drivers/gpu/drm/radeon/ObjectID.h b/drivers/gpu/drm/radeon/ObjectID.h
index c714179d1bf..c61c3fe9fb9 100644
--- a/drivers/gpu/drm/radeon/ObjectID.h
+++ b/drivers/gpu/drm/radeon/ObjectID.h
@@ -37,6 +37,8 @@
37#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3 37#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
38#define GRAPH_OBJECT_TYPE_ROUTER 0x4 38#define GRAPH_OBJECT_TYPE_ROUTER 0x4
39/* deleted */ 39/* deleted */
40#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
41#define GRAPH_OBJECT_TYPE_GENERIC 0x7
40 42
41/****************************************************/ 43/****************************************************/
42/* Encoder Object ID Definition */ 44/* Encoder Object ID Definition */
@@ -64,6 +66,9 @@
64#define ENCODER_OBJECT_ID_VT1623 0x10 66#define ENCODER_OBJECT_ID_VT1623 0x10
65#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11 67#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11
66#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12 68#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12
69#define ENCODER_OBJECT_ID_ALMOND 0x22
70#define ENCODER_OBJECT_ID_TRAVIS 0x23
71#define ENCODER_OBJECT_ID_NUTMEG 0x22
67/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */ 72/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */
68#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13 73#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13
69#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14 74#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14
@@ -108,6 +113,7 @@
108#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13 113#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13
109#define CONNECTOR_OBJECT_ID_eDP 0x14 114#define CONNECTOR_OBJECT_ID_eDP 0x14
110#define CONNECTOR_OBJECT_ID_MXM 0x15 115#define CONNECTOR_OBJECT_ID_MXM 0x15
116#define CONNECTOR_OBJECT_ID_LVDS_eDP 0x16
111 117
112/* deleted */ 118/* deleted */
113 119
@@ -124,6 +130,7 @@
124#define GENERIC_OBJECT_ID_GLSYNC 0x01 130#define GENERIC_OBJECT_ID_GLSYNC 0x01
125#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE 0x02 131#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE 0x02
126#define GENERIC_OBJECT_ID_MXM_OPM 0x03 132#define GENERIC_OBJECT_ID_MXM_OPM 0x03
133#define GENERIC_OBJECT_ID_STEREO_PIN 0x04 //This object could show up from Misc Object table, it follows ATOM_OBJECT format, and contains one ATOM_OBJECT_GPIO_CNTL_RECORD for the stereo pin
127 134
128/****************************************************/ 135/****************************************************/
129/* Graphics Object ENUM ID Definition */ 136/* Graphics Object ENUM ID Definition */
@@ -360,6 +367,26 @@
360 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 367 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
361 ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT) 368 ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
362 369
370#define ENCODER_ALMOND_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
371 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
372 ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT)
373
374#define ENCODER_ALMOND_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
375 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
376 ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT)
377
378#define ENCODER_TRAVIS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
379 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
380 ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT)
381
382#define ENCODER_TRAVIS_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
383 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
384 ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT)
385
386#define ENCODER_NUTMEG_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
387 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
388 ENCODER_OBJECT_ID_NUTMEG << OBJECT_ID_SHIFT)
389
363/****************************************************/ 390/****************************************************/
364/* Connector Object ID definition - Shared with BIOS */ 391/* Connector Object ID definition - Shared with BIOS */
365/****************************************************/ 392/****************************************************/
@@ -421,6 +448,14 @@
421 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 448 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
422 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) 449 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
423 450
451#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
452 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
453 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
454
455#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
456 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
457 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
458
424#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 459#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
425 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 460 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
426 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) 461 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
@@ -512,6 +547,7 @@
512#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 547#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
513 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 548 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
514 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) 549 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
550
515#define CONNECTOR_7PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 551#define CONNECTOR_7PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
516 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 552 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
517 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) 553 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
@@ -593,6 +629,14 @@
593 GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\ 629 GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\
594 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DAC 630 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DAC
595 631
632#define CONNECTOR_LVDS_eDP_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
633 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
634 CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT)
635
636#define CONNECTOR_LVDS_eDP_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
637 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
638 CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT)
639
596/****************************************************/ 640/****************************************************/
597/* Router Object ID definition - Shared with BIOS */ 641/* Router Object ID definition - Shared with BIOS */
598/****************************************************/ 642/****************************************************/
@@ -621,6 +665,10 @@
621 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 665 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
622 GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT) 666 GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT)
623 667
668#define GENERICOBJECT_STEREO_PIN_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
669 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
670 GENERIC_OBJECT_ID_STEREO_PIN << OBJECT_ID_SHIFT)
671
624/****************************************************/ 672/****************************************************/
625/* Object Cap definition - Shared with BIOS */ 673/* Object Cap definition - Shared with BIOS */
626/****************************************************/ 674/****************************************************/
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index fe359a239df..58a0cd02c0a 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -73,8 +73,18 @@
73#define ATOM_PPLL1 0 73#define ATOM_PPLL1 0
74#define ATOM_PPLL2 1 74#define ATOM_PPLL2 1
75#define ATOM_DCPLL 2 75#define ATOM_DCPLL 2
76#define ATOM_PPLL0 2
77#define ATOM_EXT_PLL1 8
78#define ATOM_EXT_PLL2 9
79#define ATOM_EXT_CLOCK 10
76#define ATOM_PPLL_INVALID 0xFF 80#define ATOM_PPLL_INVALID 0xFF
77 81
82#define ENCODER_REFCLK_SRC_P1PLL 0
83#define ENCODER_REFCLK_SRC_P2PLL 1
84#define ENCODER_REFCLK_SRC_DCPLL 2
85#define ENCODER_REFCLK_SRC_EXTCLK 3
86#define ENCODER_REFCLK_SRC_INVALID 0xFF
87
78#define ATOM_SCALER1 0 88#define ATOM_SCALER1 0
79#define ATOM_SCALER2 1 89#define ATOM_SCALER2 1
80 90
@@ -192,6 +202,9 @@ typedef struct _ATOM_COMMON_TABLE_HEADER
192 /*Image can't be updated, while Driver needs to carry the new table! */ 202 /*Image can't be updated, while Driver needs to carry the new table! */
193}ATOM_COMMON_TABLE_HEADER; 203}ATOM_COMMON_TABLE_HEADER;
194 204
205/****************************************************************************/
206// Structure stores the ROM header.
207/****************************************************************************/
195typedef struct _ATOM_ROM_HEADER 208typedef struct _ATOM_ROM_HEADER
196{ 209{
197 ATOM_COMMON_TABLE_HEADER sHeader; 210 ATOM_COMMON_TABLE_HEADER sHeader;
@@ -221,6 +234,9 @@ typedef struct _ATOM_ROM_HEADER
221 #define USHORT void* 234 #define USHORT void*
222#endif 235#endif
223 236
237/****************************************************************************/
238// Structures used in Command.mtb
239/****************************************************************************/
224typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 240typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
225 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 241 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
226 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 242 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
@@ -312,6 +328,7 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
312#define SetUniphyInstance ASIC_StaticPwrMgtStatusChange 328#define SetUniphyInstance ASIC_StaticPwrMgtStatusChange
313#define HPDInterruptService ReadHWAssistedI2CStatus 329#define HPDInterruptService ReadHWAssistedI2CStatus
314#define EnableVGA_Access GetSCLKOverMCLKRatio 330#define EnableVGA_Access GetSCLKOverMCLKRatio
331#define GetDispObjectInfo EnableYUV
315 332
316typedef struct _ATOM_MASTER_COMMAND_TABLE 333typedef struct _ATOM_MASTER_COMMAND_TABLE
317{ 334{
@@ -357,6 +374,24 @@ typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
357/****************************************************************************/ 374/****************************************************************************/
358#define COMPUTE_MEMORY_PLL_PARAM 1 375#define COMPUTE_MEMORY_PLL_PARAM 1
359#define COMPUTE_ENGINE_PLL_PARAM 2 376#define COMPUTE_ENGINE_PLL_PARAM 2
377#define ADJUST_MC_SETTING_PARAM 3
378
379/****************************************************************************/
380// Structures used by AdjustMemoryControllerTable
381/****************************************************************************/
382typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
383{
384#if ATOM_BIG_ENDIAN
385 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
386 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
387 ULONG ulClockFreq:24;
388#else
389 ULONG ulClockFreq:24;
390 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
391 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
392#endif
393}ATOM_ADJUST_MEMORY_CLOCK_FREQ;
394#define POINTER_RETURN_FLAG 0x80
360 395
361typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 396typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
362{ 397{
@@ -440,6 +475,26 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
440#endif 475#endif
441}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 476}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
442 477
478typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
479{
480 union
481 {
482 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
483 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
484 };
485 UCHAR ucRefDiv; //Output Parameter
486 UCHAR ucPostDiv; //Output Parameter
487 union
488 {
489 UCHAR ucCntlFlag; //Output Flags
490 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
491 };
492 UCHAR ucReserved;
493}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
494
495// ucInputFlag
496#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
497
443typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 498typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
444{ 499{
445 ATOM_COMPUTE_CLOCK_FREQ ulClock; 500 ATOM_COMPUTE_CLOCK_FREQ ulClock;
@@ -583,6 +638,7 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
583#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 638#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01
584#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 639#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00
585#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 640#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01
641#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02
586#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 642#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
587#define ATOM_ENCODER_CONFIG_LINKA 0x00 643#define ATOM_ENCODER_CONFIG_LINKA 0x00
588#define ATOM_ENCODER_CONFIG_LINKB 0x04 644#define ATOM_ENCODER_CONFIG_LINKB 0x04
@@ -608,6 +664,9 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
608#define ATOM_ENCODER_MODE_TV 13 664#define ATOM_ENCODER_MODE_TV 13
609#define ATOM_ENCODER_MODE_CV 14 665#define ATOM_ENCODER_MODE_CV 14
610#define ATOM_ENCODER_MODE_CRT 15 666#define ATOM_ENCODER_MODE_CRT 15
667#define ATOM_ENCODER_MODE_DVO 16
668#define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2
669#define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2
611 670
612typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 671typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
613{ 672{
@@ -661,6 +720,7 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
661#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 720#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08
662#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 721#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09
663#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 722#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a
723#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13
664#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 724#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b
665#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 725#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c
666#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 726#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
@@ -671,24 +731,34 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
671#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 731#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
672#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 732#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00
673 733
734//ucTableFormatRevision=1
735//ucTableContentRevision=3
674// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 736// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
675typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 737typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
676{ 738{
677#if ATOM_BIG_ENDIAN 739#if ATOM_BIG_ENDIAN
678 UCHAR ucReserved1:1; 740 UCHAR ucReserved1:1;
679 UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F 741 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F)
680 UCHAR ucReserved:3; 742 UCHAR ucReserved:3;
681 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 743 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
682#else 744#else
683 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 745 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
684 UCHAR ucReserved:3; 746 UCHAR ucReserved:3;
685 UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F 747 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F)
686 UCHAR ucReserved1:1; 748 UCHAR ucReserved1:1;
687#endif 749#endif
688}ATOM_DIG_ENCODER_CONFIG_V3; 750}ATOM_DIG_ENCODER_CONFIG_V3;
689 751
752#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
753#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
754#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
690#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 755#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70
691 756#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00
757#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10
758#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20
759#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30
760#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40
761#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50
692 762
693typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 763typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
694{ 764{
@@ -707,6 +777,56 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
707 UCHAR ucReserved; 777 UCHAR ucReserved;
708}DIG_ENCODER_CONTROL_PARAMETERS_V3; 778}DIG_ENCODER_CONTROL_PARAMETERS_V3;
709 779
780//ucTableFormatRevision=1
781//ucTableContentRevision=4
782// start from NI
783// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
784typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
785{
786#if ATOM_BIG_ENDIAN
787 UCHAR ucReserved1:1;
788 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F)
789 UCHAR ucReserved:2;
790 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
791#else
792 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
793 UCHAR ucReserved:2;
794 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F)
795 UCHAR ucReserved1:1;
796#endif
797}ATOM_DIG_ENCODER_CONFIG_V4;
798
799#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03
800#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00
801#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01
802#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02
803#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70
804#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00
805#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10
806#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20
807#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30
808#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40
809#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50
810
811typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
812{
813 USHORT usPixelClock; // in 10KHz; for bios convenient
814 union{
815 ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
816 UCHAR ucConfig;
817 };
818 UCHAR ucAction;
819 UCHAR ucEncoderMode;
820 // =0: DP encoder
821 // =1: LVDS encoder
822 // =2: DVI encoder
823 // =3: HDMI encoder
824 // =4: SDVO encoder
825 // =5: DP audio
826 UCHAR ucLaneNum; // how many lanes to enable
827 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
828 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
829}DIG_ENCODER_CONTROL_PARAMETERS_V4;
710 830
711// define ucBitPerColor: 831// define ucBitPerColor:
712#define PANEL_BPC_UNDEFINE 0x00 832#define PANEL_BPC_UNDEFINE 0x00
@@ -893,6 +1013,7 @@ typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
893#endif 1013#endif
894}ATOM_DIG_TRANSMITTER_CONFIG_V3; 1014}ATOM_DIG_TRANSMITTER_CONFIG_V3;
895 1015
1016
896typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1017typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
897{ 1018{
898 union 1019 union
@@ -936,6 +1057,149 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
936#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1057#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD
937#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1058#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF
938 1059
1060
1061/****************************************************************************/
1062// Structures used by UNIPHYTransmitterControlTable V1.4
1063// ASIC Families: NI
1064// ucTableFormatRevision=1
1065// ucTableContentRevision=4
1066/****************************************************************************/
1067typedef struct _ATOM_DP_VS_MODE_V4
1068{
1069 UCHAR ucLaneSel;
1070 union
1071 {
1072 UCHAR ucLaneSet;
1073 struct {
1074#if ATOM_BIG_ENDIAN
1075 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1076 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1077 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1078#else
1079 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1080 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1081 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1082#endif
1083 };
1084 };
1085}ATOM_DP_VS_MODE_V4;
1086
1087typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
1088{
1089#if ATOM_BIG_ENDIAN
1090 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1091 // =1 Dig Transmitter 2 ( Uniphy CD )
1092 // =2 Dig Transmitter 3 ( Uniphy EF )
1093 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1094 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1095 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1096 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1097 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1098 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1099#else
1100 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1101 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1102 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1103 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1104 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1105 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1106 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1107 // =1 Dig Transmitter 2 ( Uniphy CD )
1108 // =2 Dig Transmitter 3 ( Uniphy EF )
1109#endif
1110}ATOM_DIG_TRANSMITTER_CONFIG_V4;
1111
1112typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
1113{
1114 union
1115 {
1116 USHORT usPixelClock; // in 10KHz; for bios convenient
1117 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1118 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
1119 };
1120 union
1121 {
1122 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
1123 UCHAR ucConfig;
1124 };
1125 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1126 UCHAR ucLaneNum;
1127 UCHAR ucReserved[3];
1128}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
1129
1130//ucConfig
1131//Bit0
1132#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01
1133//Bit1
1134#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02
1135//Bit2
1136#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04
1137#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00
1138#define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04
1139// Bit3
1140#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08
1141#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00
1142#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08
1143// Bit5:4
1144#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30
1145#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00
1146#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10
1147#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4
1148#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3
1149// Bit7:6
1150#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0
1151#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB
1152#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD
1153#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF
1154
1155
1156/****************************************************************************/
1157// Structures used by ExternalEncoderControlTable V1.3
1158// ASIC Families: Evergreen, Llano, NI
1159// ucTableFormatRevision=1
1160// ucTableContentRevision=3
1161/****************************************************************************/
1162
1163typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
1164{
1165 union{
1166 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1167 USHORT usConnectorId; // connector id, valid when ucAction = INIT
1168 };
1169 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1170 UCHAR ucAction; //
1171 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1172 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1173 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1174 UCHAR ucReserved;
1175}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
1176
1177// ucAction
1178#define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00
1179#define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01
1180#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07
1181#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f
1182#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10
1183#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11
1184#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12
1185
1186// ucConfig
1187#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
1188#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
1189#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
1190#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02
1191#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70
1192#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00
1193#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10
1194#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20
1195
1196typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
1197{
1198 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
1199 ULONG ulReserved[2];
1200}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
1201
1202
939/****************************************************************************/ 1203/****************************************************************************/
940// Structures used by DAC1OuputControlTable 1204// Structures used by DAC1OuputControlTable
941// DAC2OuputControlTable 1205// DAC2OuputControlTable
@@ -1142,6 +1406,7 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V2
1142#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1406#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10
1143#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1407#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20
1144 1408
1409
1145typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1410typedef struct _PIXEL_CLOCK_PARAMETERS_V3
1146{ 1411{
1147 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1412 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
@@ -1202,6 +1467,55 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V5
1202#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1467#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08
1203#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1468#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10
1204 1469
1470typedef struct _CRTC_PIXEL_CLOCK_FREQ
1471{
1472#if ATOM_BIG_ENDIAN
1473 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1474 // drive the pixel clock. not used for DCPLL case.
1475 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1476 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1477#else
1478 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1479 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1480 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1481 // drive the pixel clock. not used for DCPLL case.
1482#endif
1483}CRTC_PIXEL_CLOCK_FREQ;
1484
1485typedef struct _PIXEL_CLOCK_PARAMETERS_V6
1486{
1487 union{
1488 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency
1489 ULONG ulDispEngClkFreq; // dispclk frequency
1490 };
1491 USHORT usFbDiv; // feedback divider integer part.
1492 UCHAR ucPostDiv; // post divider.
1493 UCHAR ucRefDiv; // Reference divider
1494 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1495 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1496 // indicate which graphic encoder will be used.
1497 UCHAR ucEncoderMode; // Encoder mode:
1498 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1499 // bit[1]= when VGA timing is used.
1500 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1501 // bit[4]= RefClock source for PPLL.
1502 // =0: XTLAIN( default mode )
1503 // =1: other external clock source, which is pre-defined
1504 // by VBIOS depend on the feature required.
1505 // bit[7:5]: reserved.
1506 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1507
1508}PIXEL_CLOCK_PARAMETERS_V6;
1509
1510#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01
1511#define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02
1512#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
1513#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
1514#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
1515#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
1516#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
1517#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
1518
1205typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1519typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
1206{ 1520{
1207 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 1521 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
@@ -1241,10 +1555,11 @@ typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
1241typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 1555typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
1242{ 1556{
1243 USHORT usPixelClock; // target pixel clock 1557 USHORT usPixelClock; // target pixel clock
1244 UCHAR ucTransmitterID; // transmitter id defined in objectid.h 1558 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
1245 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 1559 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1246 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 1560 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
1247 UCHAR ucReserved[3]; 1561 UCHAR ucExtTransmitterID; // external encoder id.
1562 UCHAR ucReserved[2];
1248}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 1563}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
1249 1564
1250// usDispPllConfig v1.2 for RoadRunner 1565// usDispPllConfig v1.2 for RoadRunner
@@ -1358,6 +1673,7 @@ typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
1358/**************************************************************************/ 1673/**************************************************************************/
1359#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1674#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1360 1675
1676
1361/****************************************************************************/ 1677/****************************************************************************/
1362// Structures used by PowerConnectorDetectionTable 1678// Structures used by PowerConnectorDetectionTable
1363/****************************************************************************/ 1679/****************************************************************************/
@@ -1438,6 +1754,31 @@ typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
1438#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 1754#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00
1439#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 1755#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
1440 1756
1757// Used by DCE5.0
1758 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
1759{
1760 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0
1761 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1762 // Bit[1]: 1-Ext. 0-Int.
1763 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1764 // Bits[7:4] reserved
1765 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1766 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1767 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
1768}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
1769
1770#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00
1771#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01
1772#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02
1773#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c
1774#define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00
1775#define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04
1776#define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08
1777#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF
1778#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0
1779#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00
1780#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8
1781
1441#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 1782#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
1442 1783
1443/**************************************************************************/ 1784/**************************************************************************/
@@ -1706,7 +2047,7 @@ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
1706 USHORT StandardVESA_Timing; // Only used by Bios 2047 USHORT StandardVESA_Timing; // Only used by Bios
1707 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2048 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
1708 USHORT DAC_Info; // Will be obsolete from R600 2049 USHORT DAC_Info; // Will be obsolete from R600
1709 USHORT LVDS_Info; // Shared by various SW components,latest version 1.1 2050 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
1710 USHORT TMDS_Info; // Will be obsolete from R600 2051 USHORT TMDS_Info; // Will be obsolete from R600
1711 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 2052 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
1712 USHORT SupportedDevicesInfo; // Will be obsolete from R600 2053 USHORT SupportedDevicesInfo; // Will be obsolete from R600
@@ -1736,12 +2077,16 @@ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
1736 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2077 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
1737}ATOM_MASTER_LIST_OF_DATA_TABLES; 2078}ATOM_MASTER_LIST_OF_DATA_TABLES;
1738 2079
2080// For backward compatible
2081#define LVDS_Info LCD_Info
2082
1739typedef struct _ATOM_MASTER_DATA_TABLE 2083typedef struct _ATOM_MASTER_DATA_TABLE
1740{ 2084{
1741 ATOM_COMMON_TABLE_HEADER sHeader; 2085 ATOM_COMMON_TABLE_HEADER sHeader;
1742 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2086 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
1743}ATOM_MASTER_DATA_TABLE; 2087}ATOM_MASTER_DATA_TABLE;
1744 2088
2089
1745/****************************************************************************/ 2090/****************************************************************************/
1746// Structure used in MultimediaCapabilityInfoTable 2091// Structure used in MultimediaCapabilityInfoTable
1747/****************************************************************************/ 2092/****************************************************************************/
@@ -1776,6 +2121,7 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
1776 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2121 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
1777}ATOM_MULTIMEDIA_CONFIG_INFO; 2122}ATOM_MULTIMEDIA_CONFIG_INFO;
1778 2123
2124
1779/****************************************************************************/ 2125/****************************************************************************/
1780// Structures used in FirmwareInfoTable 2126// Structures used in FirmwareInfoTable
1781/****************************************************************************/ 2127/****************************************************************************/
@@ -2031,8 +2377,47 @@ typedef struct _ATOM_FIRMWARE_INFO_V2_1
2031 UCHAR ucReserved4[3]; 2377 UCHAR ucReserved4[3];
2032}ATOM_FIRMWARE_INFO_V2_1; 2378}ATOM_FIRMWARE_INFO_V2_1;
2033 2379
2380//the structure below to be used from NI
2381//ucTableFormatRevision=2
2382//ucTableContentRevision=2
2383typedef struct _ATOM_FIRMWARE_INFO_V2_2
2384{
2385 ATOM_COMMON_TABLE_HEADER sHeader;
2386 ULONG ulFirmwareRevision;
2387 ULONG ulDefaultEngineClock; //In 10Khz unit
2388 ULONG ulDefaultMemoryClock; //In 10Khz unit
2389 ULONG ulReserved[2];
2390 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2391 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2392 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2393 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
2394 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
2395 UCHAR ucReserved3; //Was ucASICMaxTemperature;
2396 UCHAR ucMinAllowedBL_Level;
2397 USHORT usBootUpVDDCVoltage; //In MV unit
2398 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
2399 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
2400 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2401 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2402 ULONG ulReserved5; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
2403 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
2404 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
2405 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC
2406 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2407 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2408 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
2409 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2410 USHORT usCoreReferenceClock; //In 10Khz unit
2411 USHORT usMemoryReferenceClock; //In 10Khz unit
2412 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2413 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2414 UCHAR ucReserved9[3];
2415 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
2416 USHORT usReserved12;
2417 ULONG ulReserved10[3]; // New added comparing to previous version
2418}ATOM_FIRMWARE_INFO_V2_2;
2034 2419
2035#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_1 2420#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2
2036 2421
2037/****************************************************************************/ 2422/****************************************************************************/
2038// Structures used in IntegratedSystemInfoTable 2423// Structures used in IntegratedSystemInfoTable
@@ -2212,7 +2597,7 @@ ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pi
2212ucDockingPinBit: which bit in this register to read the pin status; 2597ucDockingPinBit: which bit in this register to read the pin status;
2213ucDockingPinPolarity:Polarity of the pin when docked; 2598ucDockingPinPolarity:Polarity of the pin when docked;
2214 2599
2215ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0 2600ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
2216 2601
2217usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 2602usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
2218 2603
@@ -2250,6 +2635,14 @@ usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to rep
2250usMinDownStreamHTLinkWidth: same as above. 2635usMinDownStreamHTLinkWidth: same as above.
2251*/ 2636*/
2252 2637
2638// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
2639#define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0
2640#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1
2641#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2
2642#define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3
2643#define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4
2644
2645#define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH // this deff reflects max defined CPU code
2253 2646
2254#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 2647#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001
2255#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 2648#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002
@@ -2778,8 +3171,88 @@ typedef struct _ATOM_LVDS_INFO_V12
2778#define PANEL_RANDOM_DITHER 0x80 3171#define PANEL_RANDOM_DITHER 0x80
2779#define PANEL_RANDOM_DITHER_MASK 0x80 3172#define PANEL_RANDOM_DITHER_MASK 0x80
2780 3173
3174#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this
3175
3176/****************************************************************************/
3177// Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12
3178// ASIC Families: NI
3179// ucTableFormatRevision=1
3180// ucTableContentRevision=3
3181/****************************************************************************/
3182typedef struct _ATOM_LCD_INFO_V13
3183{
3184 ATOM_COMMON_TABLE_HEADER sHeader;
3185 ATOM_DTD_FORMAT sLCDTiming;
3186 USHORT usExtInfoTableOffset;
3187 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3188 ULONG ulReserved0;
3189 UCHAR ucLCD_Misc; // Reorganized in V13
3190 // Bit0: {=0:single, =1:dual},
3191 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB},
3192 // Bit3:2: {Grey level}
3193 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
3194 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it?
3195 UCHAR ucPanelDefaultRefreshRate;
3196 UCHAR ucPanelIdentification;
3197 UCHAR ucSS_Id;
3198 USHORT usLCDVenderID;
3199 USHORT usLCDProductID;
3200 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
3201 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
3202 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
3203 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
3204 // Bit7-3: Reserved
3205 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3206 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
3207
3208 UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
3209 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
3210 UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
3211 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
3212
3213 UCHAR ucOffDelay_in4Ms;
3214 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
3215 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
3216 UCHAR ucReserved1;
3217
3218 ULONG ulReserved[4];
3219}ATOM_LCD_INFO_V13;
3220
3221#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13
3222
3223//Definitions for ucLCD_Misc
3224#define ATOM_PANEL_MISC_V13_DUAL 0x00000001
3225#define ATOM_PANEL_MISC_V13_FPDI 0x00000002
3226#define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C
3227#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2
3228#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70
3229#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10
3230#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20
3231
3232//Color Bit Depth definition in EDID V1.4 @BYTE 14h
3233//Bit 6 5 4
3234 // 0 0 0 - Color bit depth is undefined
3235 // 0 0 1 - 6 Bits per Primary Color
3236 // 0 1 0 - 8 Bits per Primary Color
3237 // 0 1 1 - 10 Bits per Primary Color
3238 // 1 0 0 - 12 Bits per Primary Color
3239 // 1 0 1 - 14 Bits per Primary Color
3240 // 1 1 0 - 16 Bits per Primary Color
3241 // 1 1 1 - Reserved
3242
3243//Definitions for ucLCDPanel_SpecialHandlingCap:
3244
3245//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3246//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3247#define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
3248
3249//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3250//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3251//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3252#define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
2781 3253
2782#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 3254//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3255#define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version
2783 3256
2784typedef struct _ATOM_PATCH_RECORD_MODE 3257typedef struct _ATOM_PATCH_RECORD_MODE
2785{ 3258{
@@ -2944,9 +3417,9 @@ typedef struct _ATOM_DPCD_INFO
2944#define MAX_DTD_MODE_IN_VRAM 6 3417#define MAX_DTD_MODE_IN_VRAM 6
2945#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 3418#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT)
2946#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 3419#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
2947#define DFP_ENCODER_TYPE_OFFSET 0x80 3420//20 bytes for Encoder Type and DPCD in STD EDID area
2948#define DP_ENCODER_LANE_NUM_OFFSET 0x84 3421#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
2949#define DP_ENCODER_LINK_RATE_OFFSET 0x88 3422#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 )
2950 3423
2951#define ATOM_HWICON1_SURFACE_ADDR 0 3424#define ATOM_HWICON1_SURFACE_ADDR 0
2952#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3425#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
@@ -2997,14 +3470,16 @@ typedef struct _ATOM_DPCD_INFO
2997#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3470#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
2998#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3471#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
2999 3472
3000#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3473#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3001 3474
3002#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256) 3475#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024)
3003#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512 3476#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512
3004 3477
3005//The size below is in Kb! 3478//The size below is in Kb!
3006#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 3479#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
3007 3480
3481#define ATOM_VRAM_RESERVE_V2_SIZE 32
3482
3008#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 3483#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L
3009#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 3484#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
3010#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 3485#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
@@ -3206,6 +3681,15 @@ typedef struct _ATOM_DISPLAY_OBJECT_PATH
3206 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 3681 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
3207}ATOM_DISPLAY_OBJECT_PATH; 3682}ATOM_DISPLAY_OBJECT_PATH;
3208 3683
3684typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
3685{
3686 USHORT usDeviceTag; //supported device
3687 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
3688 USHORT usConnObjectId; //Connector Object ID
3689 USHORT usGPUObjectId; //GPU ID
3690 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
3691}ATOM_DISPLAY_EXTERNAL_OBJECT_PATH;
3692
3209typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 3693typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
3210{ 3694{
3211 UCHAR ucNumOfDispPath; 3695 UCHAR ucNumOfDispPath;
@@ -3261,6 +3745,47 @@ typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset
3261#define EXT_AUXDDC_LUTINDEX_7 7 3745#define EXT_AUXDDC_LUTINDEX_7 7
3262#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 3746#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1)
3263 3747
3748//ucChannelMapping are defined as following
3749//for DP connector, eDP, DP to VGA/LVDS
3750//Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
3751//Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
3752//Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
3753//Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
3754typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING
3755{
3756#if ATOM_BIG_ENDIAN
3757 UCHAR ucDP_Lane3_Source:2;
3758 UCHAR ucDP_Lane2_Source:2;
3759 UCHAR ucDP_Lane1_Source:2;
3760 UCHAR ucDP_Lane0_Source:2;
3761#else
3762 UCHAR ucDP_Lane0_Source:2;
3763 UCHAR ucDP_Lane1_Source:2;
3764 UCHAR ucDP_Lane2_Source:2;
3765 UCHAR ucDP_Lane3_Source:2;
3766#endif
3767}ATOM_DP_CONN_CHANNEL_MAPPING;
3768
3769//for DVI/HDMI, in dual link case, both links have to have same mapping.
3770//Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
3771//Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
3772//Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
3773//Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
3774typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING
3775{
3776#if ATOM_BIG_ENDIAN
3777 UCHAR ucDVI_CLK_Source:2;
3778 UCHAR ucDVI_DATA0_Source:2;
3779 UCHAR ucDVI_DATA1_Source:2;
3780 UCHAR ucDVI_DATA2_Source:2;
3781#else
3782 UCHAR ucDVI_DATA2_Source:2;
3783 UCHAR ucDVI_DATA1_Source:2;
3784 UCHAR ucDVI_DATA0_Source:2;
3785 UCHAR ucDVI_CLK_Source:2;
3786#endif
3787}ATOM_DVI_CONN_CHANNEL_MAPPING;
3788
3264typedef struct _EXT_DISPLAY_PATH 3789typedef struct _EXT_DISPLAY_PATH
3265{ 3790{
3266 USHORT usDeviceTag; //A bit vector to show what devices are supported 3791 USHORT usDeviceTag; //A bit vector to show what devices are supported
@@ -3269,7 +3794,13 @@ typedef struct _EXT_DISPLAY_PATH
3269 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 3794 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
3270 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 3795 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
3271 USHORT usExtEncoderObjId; //external encoder object id 3796 USHORT usExtEncoderObjId; //external encoder object id
3272 USHORT usReserved[3]; 3797 union{
3798 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping
3799 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;
3800 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;
3801 };
3802 UCHAR ucReserved;
3803 USHORT usReserved[2];
3273}EXT_DISPLAY_PATH; 3804}EXT_DISPLAY_PATH;
3274 3805
3275#define NUMBER_OF_UCHAR_FOR_GUID 16 3806#define NUMBER_OF_UCHAR_FOR_GUID 16
@@ -3281,7 +3812,8 @@ typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
3281 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 3812 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
3282 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 3813 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
3283 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 3814 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.
3284 UCHAR Reserved [7]; // for potential expansion 3815 UCHAR uc3DStereoPinId; // use for eDP panel
3816 UCHAR Reserved [6]; // for potential expansion
3285}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 3817}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
3286 3818
3287//Related definitions, all records are differnt but they have a commond header 3819//Related definitions, all records are differnt but they have a commond header
@@ -3311,10 +3843,11 @@ typedef struct _ATOM_COMMON_RECORD_HEADER
3311#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 3843#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table
3312#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 3844#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
3313#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 3845#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19
3846#define ATOM_ENCODER_CAP_RECORD_TYPE 20
3314 3847
3315 3848
3316//Must be updated when new record type is added,equal to that record definition! 3849//Must be updated when new record type is added,equal to that record definition!
3317#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 3850#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE
3318 3851
3319typedef struct _ATOM_I2C_RECORD 3852typedef struct _ATOM_I2C_RECORD
3320{ 3853{
@@ -3441,6 +3974,26 @@ typedef struct _ATOM_ENCODER_DVO_CF_RECORD
3441 UCHAR ucPadding[2]; 3974 UCHAR ucPadding[2];
3442}ATOM_ENCODER_DVO_CF_RECORD; 3975}ATOM_ENCODER_DVO_CF_RECORD;
3443 3976
3977// Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap
3978#define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by this path
3979
3980typedef struct _ATOM_ENCODER_CAP_RECORD
3981{
3982 ATOM_COMMON_RECORD_HEADER sheader;
3983 union {
3984 USHORT usEncoderCap;
3985 struct {
3986#if ATOM_BIG_ENDIAN
3987 USHORT usReserved:15; // Bit1-15 may be defined for other capability in future
3988 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
3989#else
3990 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
3991 USHORT usReserved:15; // Bit1-15 may be defined for other capability in future
3992#endif
3993 };
3994 };
3995}ATOM_ENCODER_CAP_RECORD;
3996
3444// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 3997// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
3445#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 3998#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1
3446#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 3999#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
@@ -3580,6 +4133,11 @@ typedef struct _ATOM_VOLTAGE_CONTROL
3580#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 4133#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
3581#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 4134#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage
3582#define VOLTAGE_CONTROL_ID_DS4402 0x04 4135#define VOLTAGE_CONTROL_ID_DS4402 0x04
4136#define VOLTAGE_CONTROL_ID_UP6266 0x05
4137#define VOLTAGE_CONTROL_ID_SCORPIO 0x06
4138#define VOLTAGE_CONTROL_ID_VT1556M 0x07
4139#define VOLTAGE_CONTROL_ID_CHL822x 0x08
4140#define VOLTAGE_CONTROL_ID_VT1586M 0x09
3583 4141
3584typedef struct _ATOM_VOLTAGE_OBJECT 4142typedef struct _ATOM_VOLTAGE_OBJECT
3585{ 4143{
@@ -3670,66 +4228,157 @@ typedef struct _ATOM_POWER_SOURCE_INFO
3670#define POWER_SENSOR_GPIO 0x01 4228#define POWER_SENSOR_GPIO 0x01
3671#define POWER_SENSOR_I2C 0x02 4229#define POWER_SENSOR_I2C 0x02
3672 4230
4231typedef struct _ATOM_CLK_VOLT_CAPABILITY
4232{
4233 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
4234 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4235}ATOM_CLK_VOLT_CAPABILITY;
4236
4237typedef struct _ATOM_AVAILABLE_SCLK_LIST
4238{
4239 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4240 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK
4241 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK
4242}ATOM_AVAILABLE_SCLK_LIST;
4243
4244// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition
4245#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0]
4246
4247// this IntegrateSystemInfoTable is used for Liano/Ontario APU
3673typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 4248typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
3674{ 4249{
3675 ATOM_COMMON_TABLE_HEADER sHeader; 4250 ATOM_COMMON_TABLE_HEADER sHeader;
3676 ULONG ulBootUpEngineClock; 4251 ULONG ulBootUpEngineClock;
3677 ULONG ulDentistVCOFreq; 4252 ULONG ulDentistVCOFreq;
3678 ULONG ulBootUpUMAClock; 4253 ULONG ulBootUpUMAClock;
3679 ULONG ulReserved1[8]; 4254 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
3680 ULONG ulBootUpReqDisplayVector; 4255 ULONG ulBootUpReqDisplayVector;
3681 ULONG ulOtherDisplayMisc; 4256 ULONG ulOtherDisplayMisc;
3682 ULONG ulGPUCapInfo; 4257 ULONG ulGPUCapInfo;
3683 ULONG ulReserved2[3]; 4258 ULONG ulSB_MMIO_Base_Addr;
4259 USHORT usRequestedPWMFreqInHz;
4260 UCHAR ucHtcTmpLmt;
4261 UCHAR ucHtcHystLmt;
4262 ULONG ulMinEngineClock;
3684 ULONG ulSystemConfig; 4263 ULONG ulSystemConfig;
3685 ULONG ulCPUCapInfo; 4264 ULONG ulCPUCapInfo;
3686 USHORT usMaxNBVoltage; 4265 USHORT usNBP0Voltage;
3687 USHORT usMinNBVoltage; 4266 USHORT usNBP1Voltage;
3688 USHORT usBootUpNBVoltage; 4267 USHORT usBootUpNBVoltage;
3689 USHORT usExtDispConnInfoOffset; 4268 USHORT usExtDispConnInfoOffset;
3690 UCHAR ucHtcTmpLmt; 4269 USHORT usPanelRefreshRateRange;
3691 UCHAR ucTjOffset;
3692 UCHAR ucMemoryType; 4270 UCHAR ucMemoryType;
3693 UCHAR ucUMAChannelNumber; 4271 UCHAR ucUMAChannelNumber;
3694 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 4272 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
3695 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 4273 ULONG ulCSR_M3_ARB_CNTL_UVD[10];
3696 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 4274 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
3697 ULONG ulReserved3[42]; 4275 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
4276 ULONG ulGMCRestoreResetTime;
4277 ULONG ulMinimumNClk;
4278 ULONG ulIdleNClk;
4279 ULONG ulDDR_DLL_PowerUpTime;
4280 ULONG ulDDR_PLL_PowerUpTime;
4281 USHORT usPCIEClkSSPercentage;
4282 USHORT usPCIEClkSSType;
4283 USHORT usLvdsSSPercentage;
4284 USHORT usLvdsSSpreadRateIn10Hz;
4285 USHORT usHDMISSPercentage;
4286 USHORT usHDMISSpreadRateIn10Hz;
4287 USHORT usDVISSPercentage;
4288 USHORT usDVISSpreadRateIn10Hz;
4289 ULONG ulReserved3[21];
3698 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 4290 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
3699}ATOM_INTEGRATED_SYSTEM_INFO_V6; 4291}ATOM_INTEGRATED_SYSTEM_INFO_V6;
3700 4292
4293// ulGPUCapInfo
4294#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01
4295#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08
4296
4297// ulOtherDisplayMisc
4298#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01
4299
4300
3701/********************************************************************************************************************** 4301/**********************************************************************************************************************
3702// ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 4302 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
3703//ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. 4303ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
3704//ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 4304ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
3705//ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 4305ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
3706//ulReserved1[8] Reserved by now, must be 0x0. 4306sDISPCLK_Voltage: Report Display clock voltage requirement.
3707//ulBootUpReqDisplayVector VBIOS boot up display IDs 4307
3708// ATOM_DEVICE_CRT1_SUPPORT 0x0001 4308ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:
3709// ATOM_DEVICE_CRT2_SUPPORT 0x0010 4309 ATOM_DEVICE_CRT1_SUPPORT 0x0001
3710// ATOM_DEVICE_DFP1_SUPPORT 0x0008 4310 ATOM_DEVICE_CRT2_SUPPORT 0x0010
3711// ATOM_DEVICE_DFP6_SUPPORT 0x0040 4311 ATOM_DEVICE_DFP1_SUPPORT 0x0008
3712// ATOM_DEVICE_DFP2_SUPPORT 0x0080 4312 ATOM_DEVICE_DFP6_SUPPORT 0x0040
3713// ATOM_DEVICE_DFP3_SUPPORT 0x0200 4313 ATOM_DEVICE_DFP2_SUPPORT 0x0080
3714// ATOM_DEVICE_DFP4_SUPPORT 0x0400 4314 ATOM_DEVICE_DFP3_SUPPORT 0x0200
3715// ATOM_DEVICE_DFP5_SUPPORT 0x0800 4315 ATOM_DEVICE_DFP4_SUPPORT 0x0400
3716// ATOM_DEVICE_LCD1_SUPPORT 0x0002 4316 ATOM_DEVICE_DFP5_SUPPORT 0x0800
3717//ulOtherDisplayMisc Other display related flags, not defined yet. 4317 ATOM_DEVICE_LCD1_SUPPORT 0x0002
3718//ulGPUCapInfo TBD 4318ulOtherDisplayMisc: Other display related flags, not defined yet.
3719//ulReserved2[3] must be 0x0 for the reserved. 4319ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
3720//ulSystemConfig TBD 4320 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
3721//ulCPUCapInfo TBD 4321 bit[3]=0: Enable HW AUX mode detection logic
3722//usMaxNBVoltage High NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. 4322 =1: Disable HW AUX mode dettion logic
3723//usMinNBVoltage Low NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. 4323ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
3724//usBootUpNBVoltage Boot up NB voltage in unit of mv. 4324
3725//ucHtcTmpLmt Bit [22:16] of D24F3x64 Thermal Control (HTC) Register. 4325usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
3726//ucTjOffset Bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed. 4326 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
3727//ucMemoryType [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 4327
3728//ucUMAChannelNumber System memory channel numbers. 4328 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
3729//usExtDispConnectionInfoOffset ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO offset relative to beginning of this table. 4329 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
3730//ulCSR_M3_ARB_CNTL_DEFAULT[10] Arrays with values for CSR M3 arbiter for default 4330 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
3731//ulCSR_M3_ARB_CNTL_UVD[10] Arrays with values for CSR M3 arbiter for UVD playback. 4331 Changing BL using VBIOS function is functional in both driver and non-driver present environment;
3732//ulCSR_M3_ARB_CNTL_FS3D[10] Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 4332 and enabling VariBri under the driver environment from PP table is optional.
4333
4334 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
4335 that BL control from GPU is expected.
4336 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
4337 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
4338 it's per platform
4339 and enabling VariBri under the driver environment from PP table is optional.
4340
4341ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
4342 Threshold on value to enter HTC_active state.
4343ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
4344 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
4345ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
4346ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
4347 =1: PCIE Power Gating Enabled
4348 Bit[1]=0: DDR-DLL shut-down feature disabled.
4349 1: DDR-DLL shut-down feature enabled.
4350 Bit[2]=0: DDR-PLL Power down feature disabled.
4351 1: DDR-PLL Power down feature enabled.
4352ulCPUCapInfo: TBD
4353usNBP0Voltage: VID for voltage on NB P0 State
4354usNBP1Voltage: VID for voltage on NB P1 State
4355usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
4356usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
4357usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
4358 to indicate a range.
4359 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
4360 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
4361 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
4362 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
4363ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
4364ucUMAChannelNumber: System memory channel numbers.
4365ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
4366ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
4367ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
4368sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
4369ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
4370ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
4371ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4372ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
4373ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
4374usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.
4375usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread.
4376usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
4377usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4378usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
4379usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4380usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
4381usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
3733**********************************************************************************************************************/ 4382**********************************************************************************************************************/
3734 4383
3735/**************************************************************************/ 4384/**************************************************************************/
@@ -3790,6 +4439,7 @@ typedef struct _ATOM_ASIC_SS_ASSIGNMENT
3790#define ASIC_INTERNAL_SS_ON_LVDS 6 4439#define ASIC_INTERNAL_SS_ON_LVDS 6
3791#define ASIC_INTERNAL_SS_ON_DP 7 4440#define ASIC_INTERNAL_SS_ON_DP 7
3792#define ASIC_INTERNAL_SS_ON_DCPLL 8 4441#define ASIC_INTERNAL_SS_ON_DCPLL 8
4442#define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9
3793 4443
3794typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 4444typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
3795{ 4445{
@@ -3903,6 +4553,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
3903#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 4553#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1
3904#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 4554#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
3905#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 4555#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
4556#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
3906 4557
3907//Byte aligned defintion for BIOS usage 4558//Byte aligned defintion for BIOS usage
3908#define ATOM_S0_CRT1_MONOb0 0x01 4559#define ATOM_S0_CRT1_MONOb0 0x01
@@ -4529,7 +5180,8 @@ typedef struct _ATOM_INIT_REG_BLOCK{
4529#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 5180#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1)
4530#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 5181#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1)
4531#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 5182#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1)
4532 5183//#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code
5184#define ACCESS_PLACEHOLDER 0x80
4533 5185
4534typedef struct _ATOM_MC_INIT_PARAM_TABLE 5186typedef struct _ATOM_MC_INIT_PARAM_TABLE
4535{ 5187{
@@ -4554,6 +5206,10 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE
4554#define _32Mx32 0x33 5206#define _32Mx32 0x33
4555#define _64Mx8 0x41 5207#define _64Mx8 0x41
4556#define _64Mx16 0x42 5208#define _64Mx16 0x42
5209#define _64Mx32 0x43
5210#define _128Mx8 0x51
5211#define _128Mx16 0x52
5212#define _256Mx8 0x61
4557 5213
4558#define SAMSUNG 0x1 5214#define SAMSUNG 0x1
4559#define INFINEON 0x2 5215#define INFINEON 0x2
@@ -4569,10 +5225,11 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE
4569#define QIMONDA INFINEON 5225#define QIMONDA INFINEON
4570#define PROMOS MOSEL 5226#define PROMOS MOSEL
4571#define KRETON INFINEON 5227#define KRETON INFINEON
5228#define ELIXIR NANYA
4572 5229
4573/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 5230/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
4574 5231
4575#define UCODE_ROM_START_ADDRESS 0x1c000 5232#define UCODE_ROM_START_ADDRESS 0x1b800
4576#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 5233#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
4577 5234
4578//uCode block header for reference 5235//uCode block header for reference
@@ -4903,7 +5560,34 @@ typedef struct _ATOM_VRAM_MODULE_V6
4903 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 5560 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
4904}ATOM_VRAM_MODULE_V6; 5561}ATOM_VRAM_MODULE_V6;
4905 5562
4906 5563typedef struct _ATOM_VRAM_MODULE_V7
5564{
5565// Design Specific Values
5566 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
5567 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
5568 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
5569 USHORT usReserved;
5570 UCHAR ucExtMemoryID; // Current memory module ID
5571 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
5572 UCHAR ucChannelNum; // Number of mem. channels supported in this module
5573 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
5574 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
5575 UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now.
5576 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
5577 UCHAR ucVREFI; // Not used.
5578 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
5579 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
5580 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
5581 UCHAR ucReserved[3];
5582// Memory Module specific values
5583 USHORT usEMRS2Value; // EMRS2/MR2 Value.
5584 USHORT usEMRS3Value; // EMRS3/MR3 Value.
5585 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
5586 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
5587 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
5588 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
5589 char strMemPNString[20]; // part number end with '0'.
5590}ATOM_VRAM_MODULE_V7;
4907 5591
4908typedef struct _ATOM_VRAM_INFO_V2 5592typedef struct _ATOM_VRAM_INFO_V2
4909{ 5593{
@@ -4942,6 +5626,20 @@ typedef struct _ATOM_VRAM_INFO_V4
4942 // ATOM_INIT_REG_BLOCK aMemAdjust; 5626 // ATOM_INIT_REG_BLOCK aMemAdjust;
4943}ATOM_VRAM_INFO_V4; 5627}ATOM_VRAM_INFO_V4;
4944 5628
5629typedef struct _ATOM_VRAM_INFO_HEADER_V2_1
5630{
5631 ATOM_COMMON_TABLE_HEADER sHeader;
5632 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
5633 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
5634 USHORT usReserved[4];
5635 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
5636 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
5637 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
5638 UCHAR ucReserved;
5639 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
5640}ATOM_VRAM_INFO_HEADER_V2_1;
5641
5642
4945typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 5643typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
4946{ 5644{
4947 ATOM_COMMON_TABLE_HEADER sHeader; 5645 ATOM_COMMON_TABLE_HEADER sHeader;
@@ -5182,6 +5880,16 @@ typedef struct _ASIC_TRANSMITTER_INFO
5182 UCHAR ucReserved; 5880 UCHAR ucReserved;
5183}ASIC_TRANSMITTER_INFO; 5881}ASIC_TRANSMITTER_INFO;
5184 5882
5883#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01
5884#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02
5885#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4
5886#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00
5887#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04
5888#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40
5889#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44
5890#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80
5891#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84
5892
5185typedef struct _ASIC_ENCODER_INFO 5893typedef struct _ASIC_ENCODER_INFO
5186{ 5894{
5187 UCHAR ucEncoderID; 5895 UCHAR ucEncoderID;
@@ -5284,6 +5992,28 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS
5284/* /obselete */ 5992/* /obselete */
5285#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 5993#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
5286 5994
5995
5996typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2
5997{
5998 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
5999 UCHAR ucAuxId;
6000 UCHAR ucAction;
6001 UCHAR ucSinkType; // Iput and Output parameters.
6002 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
6003 UCHAR ucReserved[2];
6004}DP_ENCODER_SERVICE_PARAMETERS_V2;
6005
6006typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2
6007{
6008 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam;
6009 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam;
6010}DP_ENCODER_SERVICE_PS_ALLOCATION_V2;
6011
6012// ucAction
6013#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01
6014#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02
6015
6016
5287// DP_TRAINING_TABLE 6017// DP_TRAINING_TABLE
5288#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 6018#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR
5289#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 6019#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )
@@ -5339,6 +6069,7 @@ typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
5339#define SELECT_DCIO_IMPCAL 4 6069#define SELECT_DCIO_IMPCAL 4
5340#define SELECT_DCIO_DIG 6 6070#define SELECT_DCIO_DIG 6
5341#define SELECT_CRTC_PIXEL_RATE 7 6071#define SELECT_CRTC_PIXEL_RATE 7
6072#define SELECT_VGA_BLK 8
5342 6073
5343/****************************************************************************/ 6074/****************************************************************************/
5344//Portion VI: Definitinos for vbios MC scratch registers that driver used 6075//Portion VI: Definitinos for vbios MC scratch registers that driver used
@@ -5744,7 +6475,17 @@ typedef struct _ATOM_PPLIB_THERMALCONTROLLER
5744#define ATOM_PP_THERMALCONTROLLER_ADT7473 9 6475#define ATOM_PP_THERMALCONTROLLER_ADT7473 9
5745#define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 6476#define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11
5746#define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 6477#define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12
6478#define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen.
6479#define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally
6480#define ATOM_PP_THERMALCONTROLLER_NISLANDS 15
6481
6482// Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal.
6483// We probably should reserve the bit 0x80 for this use.
6484// To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here).
6485// The driver can pick the correct internal controller based on the ASIC.
6486
5747#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller 6487#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller
6488#define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller
5748 6489
5749typedef struct _ATOM_PPLIB_STATE 6490typedef struct _ATOM_PPLIB_STATE
5750{ 6491{
@@ -5841,6 +6582,29 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
5841 USHORT usExtendendedHeaderOffset; 6582 USHORT usExtendendedHeaderOffset;
5842} ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; 6583} ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3;
5843 6584
6585typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
6586{
6587 ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
6588 ULONG ulGoldenPPID; // PPGen use only
6589 ULONG ulGoldenRevision; // PPGen use only
6590 USHORT usVddcDependencyOnSCLKOffset;
6591 USHORT usVddciDependencyOnMCLKOffset;
6592 USHORT usVddcDependencyOnMCLKOffset;
6593 USHORT usMaxClockVoltageOnDCOffset;
6594 USHORT usReserved[2];
6595} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
6596
6597typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
6598{
6599 ATOM_PPLIB_POWERPLAYTABLE4 basicTable4;
6600 ULONG ulTDPLimit;
6601 ULONG ulNearTDPLimit;
6602 ULONG ulSQRampingThreshold;
6603 USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table
6604 ULONG ulCACLeakage; // TBD, this parameter is still under discussion. Change to ulReserved if not needed.
6605 ULONG ulReserved;
6606} ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5;
6607
5844//// ATOM_PPLIB_NONCLOCK_INFO::usClassification 6608//// ATOM_PPLIB_NONCLOCK_INFO::usClassification
5845#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 6609#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007
5846#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 6610#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0
@@ -5864,6 +6628,10 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
5864#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 6628#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000
5865#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 6629#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000
5866 6630
6631//// ATOM_PPLIB_NONCLOCK_INFO::usClassification2
6632#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001
6633#define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002
6634
5867//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings 6635//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
5868#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 6636#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001
5869#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 6637#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002
@@ -5896,9 +6664,21 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
5896#define ATOM_PPLIB_M3ARB_MASK 0x00060000 6664#define ATOM_PPLIB_M3ARB_MASK 0x00060000
5897#define ATOM_PPLIB_M3ARB_SHIFT 17 6665#define ATOM_PPLIB_M3ARB_SHIFT 17
5898 6666
6667#define ATOM_PPLIB_ENABLE_DRR 0x00080000
6668
6669// remaining 16 bits are reserved
6670typedef struct _ATOM_PPLIB_THERMAL_STATE
6671{
6672 UCHAR ucMinTemperature;
6673 UCHAR ucMaxTemperature;
6674 UCHAR ucThermalAction;
6675}ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE;
6676
5899// Contained in an array starting at the offset 6677// Contained in an array starting at the offset
5900// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. 6678// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
5901// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex 6679// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex
6680#define ATOM_PPLIB_NONCLOCKINFO_VER1 12
6681#define ATOM_PPLIB_NONCLOCKINFO_VER2 24
5902typedef struct _ATOM_PPLIB_NONCLOCK_INFO 6682typedef struct _ATOM_PPLIB_NONCLOCK_INFO
5903{ 6683{
5904 USHORT usClassification; 6684 USHORT usClassification;
@@ -5906,15 +6686,15 @@ typedef struct _ATOM_PPLIB_NONCLOCK_INFO
5906 UCHAR ucMaxTemperature; 6686 UCHAR ucMaxTemperature;
5907 ULONG ulCapsAndSettings; 6687 ULONG ulCapsAndSettings;
5908 UCHAR ucRequiredPower; 6688 UCHAR ucRequiredPower;
5909 UCHAR ucUnused1[3]; 6689 USHORT usClassification2;
6690 ULONG ulVCLK;
6691 ULONG ulDCLK;
6692 UCHAR ucUnused[5];
5910} ATOM_PPLIB_NONCLOCK_INFO; 6693} ATOM_PPLIB_NONCLOCK_INFO;
5911 6694
5912// Contained in an array starting at the offset 6695// Contained in an array starting at the offset
5913// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. 6696// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
5914// referenced from ATOM_PPLIB_STATE::ucClockStateIndices 6697// referenced from ATOM_PPLIB_STATE::ucClockStateIndices
5915#define ATOM_PPLIB_NONCLOCKINFO_VER1 12
5916#define ATOM_PPLIB_NONCLOCKINFO_VER2 24
5917
5918typedef struct _ATOM_PPLIB_R600_CLOCK_INFO 6698typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
5919{ 6699{
5920 USHORT usEngineClockLow; 6700 USHORT usEngineClockLow;
@@ -5985,6 +6765,93 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
5985#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 6765#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
5986#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 6766#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
5987 6767
6768typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
6769 USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
6770 UCHAR ucEngineClockHigh; //clockfrequency >> 16.
6771 UCHAR vddcIndex; //2-bit vddc index;
6772 UCHAR leakage; //please use 8-bit absolute value, not the 6-bit % value
6773 //please initalize to 0
6774 UCHAR rsv;
6775 //please initalize to 0
6776 USHORT rsv1;
6777 //please initialize to 0s
6778 ULONG rsv2[2];
6779}ATOM_PPLIB_SUMO_CLOCK_INFO;
6780
6781
6782
6783typedef struct _ATOM_PPLIB_STATE_V2
6784{
6785 //number of valid dpm levels in this state; Driver uses it to calculate the whole
6786 //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
6787 UCHAR ucNumDPMLevels;
6788
6789 //a index to the array of nonClockInfos
6790 UCHAR nonClockInfoIndex;
6791 /**
6792 * Driver will read the first ucNumDPMLevels in this array
6793 */
6794 UCHAR clockInfoIndex[1];
6795} ATOM_PPLIB_STATE_V2;
6796
6797typedef struct StateArray{
6798 //how many states we have
6799 UCHAR ucNumEntries;
6800
6801 ATOM_PPLIB_STATE_V2 states[1];
6802}StateArray;
6803
6804
6805typedef struct ClockInfoArray{
6806 //how many clock levels we have
6807 UCHAR ucNumEntries;
6808
6809 //sizeof(ATOM_PPLIB_SUMO_CLOCK_INFO)
6810 UCHAR ucEntrySize;
6811
6812 //this is for Sumo
6813 ATOM_PPLIB_SUMO_CLOCK_INFO clockInfo[1];
6814}ClockInfoArray;
6815
6816typedef struct NonClockInfoArray{
6817
6818 //how many non-clock levels we have. normally should be same as number of states
6819 UCHAR ucNumEntries;
6820 //sizeof(ATOM_PPLIB_NONCLOCK_INFO)
6821 UCHAR ucEntrySize;
6822
6823 ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
6824}NonClockInfoArray;
6825
6826typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
6827{
6828 USHORT usClockLow;
6829 UCHAR ucClockHigh;
6830 USHORT usVoltage;
6831}ATOM_PPLIB_Clock_Voltage_Dependency_Record;
6832
6833typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table
6834{
6835 UCHAR ucNumEntries; // Number of entries.
6836 ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries.
6837}ATOM_PPLIB_Clock_Voltage_Dependency_Table;
6838
6839typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
6840{
6841 USHORT usSclkLow;
6842 UCHAR ucSclkHigh;
6843 USHORT usMclkLow;
6844 UCHAR ucMclkHigh;
6845 USHORT usVddc;
6846 USHORT usVddci;
6847}ATOM_PPLIB_Clock_Voltage_Limit_Record;
6848
6849typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
6850{
6851 UCHAR ucNumEntries; // Number of entries.
6852 ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries.
6853}ATOM_PPLIB_Clock_Voltage_Limit_Table;
6854
5988/**************************************************************************/ 6855/**************************************************************************/
5989 6856
5990 6857
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 25e84379e7c..522d29b3700 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -112,6 +112,14 @@ u32 evergreen_get_temp(struct radeon_device *rdev)
112 return actual_temp * 1000; 112 return actual_temp * 1000;
113} 113}
114 114
115u32 sumo_get_temp(struct radeon_device *rdev)
116{
117 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
118 u32 actual_temp = (temp >> 1) & 0xff;
119
120 return actual_temp * 1000;
121}
122
115void evergreen_pm_misc(struct radeon_device *rdev) 123void evergreen_pm_misc(struct radeon_device *rdev)
116{ 124{
117 int req_ps_idx = rdev->pm.requested_power_state_index; 125 int req_ps_idx = rdev->pm.requested_power_state_index;
@@ -943,31 +951,39 @@ static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_sa
943 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 951 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
944 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 952 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
945 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 953 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
946 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 954 if (!(rdev->flags & RADEON_IS_IGP)) {
947 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 955 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
948 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 956 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
949 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 957 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
958 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
959 }
950 960
951 /* Stop all video */ 961 /* Stop all video */
952 WREG32(VGA_RENDER_CONTROL, 0); 962 WREG32(VGA_RENDER_CONTROL, 0);
953 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 963 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
954 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 964 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
955 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 965 if (!(rdev->flags & RADEON_IS_IGP)) {
956 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 966 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
957 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 967 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
958 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 968 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
969 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
970 }
959 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 971 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
960 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 972 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
961 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 973 if (!(rdev->flags & RADEON_IS_IGP)) {
962 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 974 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
963 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 975 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
964 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 976 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
977 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
978 }
965 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 979 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
966 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 980 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
967 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 981 if (!(rdev->flags & RADEON_IS_IGP)) {
968 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 982 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
969 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 983 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
970 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 984 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
985 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
986 }
971 987
972 WREG32(D1VGA_CONTROL, 0); 988 WREG32(D1VGA_CONTROL, 0);
973 WREG32(D2VGA_CONTROL, 0); 989 WREG32(D2VGA_CONTROL, 0);
@@ -997,41 +1013,43 @@ static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_
997 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1013 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
998 (u32)rdev->mc.vram_start); 1014 (u32)rdev->mc.vram_start);
999 1015
1000 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1016 if (!(rdev->flags & RADEON_IS_IGP)) {
1001 upper_32_bits(rdev->mc.vram_start)); 1017 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1002 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1018 upper_32_bits(rdev->mc.vram_start));
1003 upper_32_bits(rdev->mc.vram_start)); 1019 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1004 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, 1020 upper_32_bits(rdev->mc.vram_start));
1005 (u32)rdev->mc.vram_start); 1021 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1006 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, 1022 (u32)rdev->mc.vram_start);
1007 (u32)rdev->mc.vram_start); 1023 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1008 1024 (u32)rdev->mc.vram_start);
1009 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, 1025
1010 upper_32_bits(rdev->mc.vram_start)); 1026 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1011 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, 1027 upper_32_bits(rdev->mc.vram_start));
1012 upper_32_bits(rdev->mc.vram_start)); 1028 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1013 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1029 upper_32_bits(rdev->mc.vram_start));
1014 (u32)rdev->mc.vram_start); 1030 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1015 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1031 (u32)rdev->mc.vram_start);
1016 (u32)rdev->mc.vram_start); 1032 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1017 1033 (u32)rdev->mc.vram_start);
1018 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1034
1019 upper_32_bits(rdev->mc.vram_start)); 1035 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1020 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1036 upper_32_bits(rdev->mc.vram_start));
1021 upper_32_bits(rdev->mc.vram_start)); 1037 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1022 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, 1038 upper_32_bits(rdev->mc.vram_start));
1023 (u32)rdev->mc.vram_start); 1039 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1024 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, 1040 (u32)rdev->mc.vram_start);
1025 (u32)rdev->mc.vram_start); 1041 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1026 1042 (u32)rdev->mc.vram_start);
1027 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, 1043
1028 upper_32_bits(rdev->mc.vram_start)); 1044 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1029 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, 1045 upper_32_bits(rdev->mc.vram_start));
1030 upper_32_bits(rdev->mc.vram_start)); 1046 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1031 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, 1047 upper_32_bits(rdev->mc.vram_start));
1032 (u32)rdev->mc.vram_start); 1048 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1033 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, 1049 (u32)rdev->mc.vram_start);
1034 (u32)rdev->mc.vram_start); 1050 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1051 (u32)rdev->mc.vram_start);
1052 }
1035 1053
1036 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); 1054 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1037 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 1055 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
@@ -1047,22 +1065,28 @@ static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_
1047 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); 1065 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1048 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1066 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1049 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1067 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1050 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1068 if (!(rdev->flags & RADEON_IS_IGP)) {
1051 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1069 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1052 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1070 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1053 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1071 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1072 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1073 }
1054 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); 1074 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1055 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); 1075 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1056 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); 1076 if (!(rdev->flags & RADEON_IS_IGP)) {
1057 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); 1077 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1058 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); 1078 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1059 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); 1079 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1080 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1081 }
1060 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1082 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1061 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1083 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1062 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1084 if (!(rdev->flags & RADEON_IS_IGP)) {
1063 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1085 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1064 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1086 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1065 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1087 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1088 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1089 }
1066 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 1090 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1067} 1091}
1068 1092
@@ -1338,6 +1362,7 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1338 switch (rdev->family) { 1362 switch (rdev->family) {
1339 case CHIP_CEDAR: 1363 case CHIP_CEDAR:
1340 case CHIP_REDWOOD: 1364 case CHIP_REDWOOD:
1365 case CHIP_PALM:
1341 force_no_swizzle = false; 1366 force_no_swizzle = false;
1342 break; 1367 break;
1343 case CHIP_CYPRESS: 1368 case CHIP_CYPRESS:
@@ -1437,6 +1462,43 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1437 return backend_map; 1462 return backend_map;
1438} 1463}
1439 1464
1465static void evergreen_program_channel_remap(struct radeon_device *rdev)
1466{
1467 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1468
1469 tmp = RREG32(MC_SHARED_CHMAP);
1470 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1471 case 0:
1472 case 1:
1473 case 2:
1474 case 3:
1475 default:
1476 /* default mapping */
1477 mc_shared_chremap = 0x00fac688;
1478 break;
1479 }
1480
1481 switch (rdev->family) {
1482 case CHIP_HEMLOCK:
1483 case CHIP_CYPRESS:
1484 tcp_chan_steer_lo = 0x54763210;
1485 tcp_chan_steer_hi = 0x0000ba98;
1486 break;
1487 case CHIP_JUNIPER:
1488 case CHIP_REDWOOD:
1489 case CHIP_CEDAR:
1490 case CHIP_PALM:
1491 default:
1492 tcp_chan_steer_lo = 0x76543210;
1493 tcp_chan_steer_hi = 0x0000ba98;
1494 break;
1495 }
1496
1497 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1498 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1499 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1500}
1501
1440static void evergreen_gpu_init(struct radeon_device *rdev) 1502static void evergreen_gpu_init(struct radeon_device *rdev)
1441{ 1503{
1442 u32 cc_rb_backend_disable = 0; 1504 u32 cc_rb_backend_disable = 0;
@@ -1548,6 +1610,27 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1548 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1610 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1549 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1611 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1550 break; 1612 break;
1613 case CHIP_PALM:
1614 rdev->config.evergreen.num_ses = 1;
1615 rdev->config.evergreen.max_pipes = 2;
1616 rdev->config.evergreen.max_tile_pipes = 2;
1617 rdev->config.evergreen.max_simds = 2;
1618 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1619 rdev->config.evergreen.max_gprs = 256;
1620 rdev->config.evergreen.max_threads = 192;
1621 rdev->config.evergreen.max_gs_threads = 16;
1622 rdev->config.evergreen.max_stack_entries = 256;
1623 rdev->config.evergreen.sx_num_of_sets = 4;
1624 rdev->config.evergreen.sx_max_export_size = 128;
1625 rdev->config.evergreen.sx_max_export_pos_size = 32;
1626 rdev->config.evergreen.sx_max_export_smx_size = 96;
1627 rdev->config.evergreen.max_hw_contexts = 4;
1628 rdev->config.evergreen.sq_num_cf_insts = 1;
1629
1630 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1631 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1632 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1633 break;
1551 } 1634 }
1552 1635
1553 /* Initialize HDP */ 1636 /* Initialize HDP */
@@ -1740,6 +1823,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1740 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1823 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1741 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1824 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1742 1825
1826 evergreen_program_channel_remap(rdev);
1827
1743 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; 1828 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1744 grbm_gfx_index = INSTANCE_BROADCAST_WRITES; 1829 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1745 1830
@@ -1822,9 +1907,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1822 GS_PRIO(2) | 1907 GS_PRIO(2) |
1823 ES_PRIO(3)); 1908 ES_PRIO(3));
1824 1909
1825 if (rdev->family == CHIP_CEDAR) 1910 switch (rdev->family) {
1911 case CHIP_CEDAR:
1912 case CHIP_PALM:
1826 /* no vertex cache */ 1913 /* no vertex cache */
1827 sq_config &= ~VC_ENABLE; 1914 sq_config &= ~VC_ENABLE;
1915 break;
1916 default:
1917 break;
1918 }
1828 1919
1829 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); 1920 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1830 1921
@@ -1836,10 +1927,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1836 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); 1927 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1837 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); 1928 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1838 1929
1839 if (rdev->family == CHIP_CEDAR) 1930 switch (rdev->family) {
1931 case CHIP_CEDAR:
1932 case CHIP_PALM:
1840 ps_thread_count = 96; 1933 ps_thread_count = 96;
1841 else 1934 break;
1935 default:
1842 ps_thread_count = 128; 1936 ps_thread_count = 128;
1937 break;
1938 }
1843 1939
1844 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count); 1940 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1845 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 1941 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
@@ -1870,10 +1966,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1870 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1966 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1871 FORCE_EOV_MAX_REZ_CNT(255))); 1967 FORCE_EOV_MAX_REZ_CNT(255)));
1872 1968
1873 if (rdev->family == CHIP_CEDAR) 1969 switch (rdev->family) {
1970 case CHIP_CEDAR:
1971 case CHIP_PALM:
1874 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY); 1972 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1875 else 1973 break;
1974 default:
1876 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC); 1975 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1976 break;
1977 }
1877 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO); 1978 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1878 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); 1979 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1879 1980
@@ -1957,12 +2058,18 @@ int evergreen_mc_init(struct radeon_device *rdev)
1957 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2058 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1958 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2059 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1959 /* Setup GPU memory space */ 2060 /* Setup GPU memory space */
1960 /* size in MB on evergreen */ 2061 if (rdev->flags & RADEON_IS_IGP) {
1961 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2062 /* size in bytes on fusion */
1962 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2063 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2064 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2065 } else {
2066 /* size in MB on evergreen */
2067 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2068 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2069 }
1963 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2070 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1964 rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 2071 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1965 r600_vram_gtt_location(rdev, &rdev->mc); 2072 r700_vram_gtt_location(rdev, &rdev->mc);
1966 radeon_update_bandwidth_info(rdev); 2073 radeon_update_bandwidth_info(rdev);
1967 2074
1968 return 0; 2075 return 0;
@@ -2079,17 +2186,21 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2079 WREG32(GRBM_INT_CNTL, 0); 2186 WREG32(GRBM_INT_CNTL, 0);
2080 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2187 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2081 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2188 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2082 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2189 if (!(rdev->flags & RADEON_IS_IGP)) {
2083 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2190 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2084 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2191 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2085 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2192 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2193 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2194 }
2086 2195
2087 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2196 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2088 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2197 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2089 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2198 if (!(rdev->flags & RADEON_IS_IGP)) {
2090 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2199 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2091 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2200 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2092 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2201 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2202 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2203 }
2093 2204
2094 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 2205 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2095 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 2206 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
@@ -2205,10 +2316,12 @@ int evergreen_irq_set(struct radeon_device *rdev)
2205 2316
2206 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 2317 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2207 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 2318 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2208 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 2319 if (!(rdev->flags & RADEON_IS_IGP)) {
2209 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 2320 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2210 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 2321 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2211 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 2322 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2323 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2324 }
2212 2325
2213 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 2326 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2214 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 2327 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
@@ -2765,12 +2878,16 @@ static bool evergreen_card_posted(struct radeon_device *rdev)
2765 u32 reg; 2878 u32 reg;
2766 2879
2767 /* first check CRTCs */ 2880 /* first check CRTCs */
2768 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 2881 if (rdev->flags & RADEON_IS_IGP)
2769 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | 2882 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2770 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 2883 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2771 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | 2884 else
2772 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 2885 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2773 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 2886 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2887 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2888 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2889 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2890 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2774 if (reg & EVERGREEN_CRTC_MASTER_EN) 2891 if (reg & EVERGREEN_CRTC_MASTER_EN)
2775 return true; 2892 return true;
2776 2893
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index e0e590110dd..2ccd1f0545f 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -147,7 +147,8 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
147 radeon_ring_write(rdev, 0); 147 radeon_ring_write(rdev, 0);
148 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); 148 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
149 149
150 if (rdev->family == CHIP_CEDAR) 150 if ((rdev->family == CHIP_CEDAR) ||
151 (rdev->family == CHIP_PALM))
151 cp_set_surface_sync(rdev, 152 cp_set_surface_sync(rdev,
152 PACKET3_TC_ACTION_ENA, 48, gpu_addr); 153 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
153 else 154 else
@@ -331,9 +332,31 @@ set_default_state(struct radeon_device *rdev)
331 num_hs_stack_entries = 85; 332 num_hs_stack_entries = 85;
332 num_ls_stack_entries = 85; 333 num_ls_stack_entries = 85;
333 break; 334 break;
335 case CHIP_PALM:
336 num_ps_gprs = 93;
337 num_vs_gprs = 46;
338 num_temp_gprs = 4;
339 num_gs_gprs = 31;
340 num_es_gprs = 31;
341 num_hs_gprs = 23;
342 num_ls_gprs = 23;
343 num_ps_threads = 96;
344 num_vs_threads = 16;
345 num_gs_threads = 16;
346 num_es_threads = 16;
347 num_hs_threads = 16;
348 num_ls_threads = 16;
349 num_ps_stack_entries = 42;
350 num_vs_stack_entries = 42;
351 num_gs_stack_entries = 42;
352 num_es_stack_entries = 42;
353 num_hs_stack_entries = 42;
354 num_ls_stack_entries = 42;
355 break;
334 } 356 }
335 357
336 if (rdev->family == CHIP_CEDAR) 358 if ((rdev->family == CHIP_CEDAR) ||
359 (rdev->family == CHIP_PALM))
337 sq_config = 0; 360 sq_config = 0;
338 else 361 else
339 sq_config = VC_ENABLE; 362 sq_config = VC_ENABLE;
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 113c70cc8b3..87fcaba7669 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -164,11 +164,13 @@
164#define SE_SC_BUSY (1 << 29) 164#define SE_SC_BUSY (1 << 29)
165#define SE_DB_BUSY (1 << 30) 165#define SE_DB_BUSY (1 << 30)
166#define SE_CB_BUSY (1 << 31) 166#define SE_CB_BUSY (1 << 31)
167 167/* evergreen */
168#define CG_MULT_THERMAL_STATUS 0x740 168#define CG_MULT_THERMAL_STATUS 0x740
169#define ASIC_T(x) ((x) << 16) 169#define ASIC_T(x) ((x) << 16)
170#define ASIC_T_MASK 0x7FF0000 170#define ASIC_T_MASK 0x7FF0000
171#define ASIC_T_SHIFT 16 171#define ASIC_T_SHIFT 16
172/* APU */
173#define CG_THERMAL_STATUS 0x678
172 174
173#define HDP_HOST_PATH_CNTL 0x2C00 175#define HDP_HOST_PATH_CNTL 0x2C00
174#define HDP_NONSURFACE_BASE 0x2C04 176#define HDP_NONSURFACE_BASE 0x2C04
@@ -180,6 +182,7 @@
180#define MC_SHARED_CHMAP 0x2004 182#define MC_SHARED_CHMAP 0x2004
181#define NOOFCHAN_SHIFT 12 183#define NOOFCHAN_SHIFT 12
182#define NOOFCHAN_MASK 0x00003000 184#define NOOFCHAN_MASK 0x00003000
185#define MC_SHARED_CHREMAP 0x2008
183 186
184#define MC_ARB_RAMCFG 0x2760 187#define MC_ARB_RAMCFG 0x2760
185#define NOOFBANK_SHIFT 0 188#define NOOFBANK_SHIFT 0
@@ -348,6 +351,9 @@
348#define SYNC_WALKER (1 << 25) 351#define SYNC_WALKER (1 << 25)
349#define SYNC_ALIGNER (1 << 26) 352#define SYNC_ALIGNER (1 << 26)
350 353
354#define TCP_CHAN_STEER_LO 0x960c
355#define TCP_CHAN_STEER_HI 0x9610
356
351#define VGT_CACHE_INVALIDATION 0x88C4 357#define VGT_CACHE_INVALIDATION 0x88C4
352#define CACHE_INVALIDATION(x) ((x) << 0) 358#define CACHE_INVALIDATION(x) ((x) << 0)
353#define VC_ONLY 0 359#define VC_ONLY 0
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 7057b392e00..53bfe3afb0f 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -83,6 +83,9 @@ MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
83MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 83MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
84MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 84MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
85MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 85MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
86MODULE_FIRMWARE("radeon/PALM_pfp.bin");
87MODULE_FIRMWARE("radeon/PALM_me.bin");
88MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
86 89
87int r600_debugfs_mc_info_init(struct radeon_device *rdev); 90int r600_debugfs_mc_info_init(struct radeon_device *rdev);
88 91
@@ -1161,7 +1164,7 @@ static void r600_mc_program(struct radeon_device *rdev)
1161 * Note: GTT start, end, size should be initialized before calling this 1164 * Note: GTT start, end, size should be initialized before calling this
1162 * function on AGP platform. 1165 * function on AGP platform.
1163 */ 1166 */
1164void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1167static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1165{ 1168{
1166 u64 size_bf, size_af; 1169 u64 size_bf, size_af;
1167 1170
@@ -1998,6 +2001,10 @@ int r600_init_microcode(struct radeon_device *rdev)
1998 chip_name = "CYPRESS"; 2001 chip_name = "CYPRESS";
1999 rlc_chip_name = "CYPRESS"; 2002 rlc_chip_name = "CYPRESS";
2000 break; 2003 break;
2004 case CHIP_PALM:
2005 chip_name = "PALM";
2006 rlc_chip_name = "SUMO";
2007 break;
2001 default: BUG(); 2008 default: BUG();
2002 } 2009 }
2003 2010
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5827a71e409..431d4186ddf 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -181,6 +181,7 @@ void rs690_pm_info(struct radeon_device *rdev);
181extern u32 rv6xx_get_temp(struct radeon_device *rdev); 181extern u32 rv6xx_get_temp(struct radeon_device *rdev);
182extern u32 rv770_get_temp(struct radeon_device *rdev); 182extern u32 rv770_get_temp(struct radeon_device *rdev);
183extern u32 evergreen_get_temp(struct radeon_device *rdev); 183extern u32 evergreen_get_temp(struct radeon_device *rdev);
184extern u32 sumo_get_temp(struct radeon_device *rdev);
184 185
185/* 186/*
186 * Fences. 187 * Fences.
@@ -737,6 +738,7 @@ enum radeon_int_thermal_type {
737 THERMAL_TYPE_RV6XX, 738 THERMAL_TYPE_RV6XX,
738 THERMAL_TYPE_RV770, 739 THERMAL_TYPE_RV770,
739 THERMAL_TYPE_EVERGREEN, 740 THERMAL_TYPE_EVERGREEN,
741 THERMAL_TYPE_SUMO,
740}; 742};
741 743
742struct radeon_voltage { 744struct radeon_voltage {
@@ -1323,6 +1325,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
1323#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1325#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1324#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1326#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1325#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1327#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1328#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM))
1326 1329
1327/* 1330/*
1328 * BIOS helpers. 1331 * BIOS helpers.
@@ -1489,7 +1492,6 @@ extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1489 struct drm_display_mode *mode2); 1492 struct drm_display_mode *mode2);
1490 1493
1491/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ 1494/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1492extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1493extern bool r600_card_posted(struct radeon_device *rdev); 1495extern bool r600_card_posted(struct radeon_device *rdev);
1494extern void r600_cp_stop(struct radeon_device *rdev); 1496extern void r600_cp_stop(struct radeon_device *rdev);
1495extern int r600_cp_start(struct radeon_device *rdev); 1497extern int r600_cp_start(struct radeon_device *rdev);
@@ -1535,6 +1537,7 @@ extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mo
1535extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 1537extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1536extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 1538extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1537 1539
1540extern void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1538extern void r700_cp_stop(struct radeon_device *rdev); 1541extern void r700_cp_stop(struct radeon_device *rdev);
1539extern void r700_cp_fini(struct radeon_device *rdev); 1542extern void r700_cp_fini(struct radeon_device *rdev);
1540extern void evergreen_disable_interrupt_state(struct radeon_device *rdev); 1543extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 6b126b3f5fa..3d73fe484f4 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -793,6 +793,49 @@ static struct radeon_asic evergreen_asic = {
793 .post_page_flip = &evergreen_post_page_flip, 793 .post_page_flip = &evergreen_post_page_flip,
794}; 794};
795 795
796static struct radeon_asic sumo_asic = {
797 .init = &evergreen_init,
798 .fini = &evergreen_fini,
799 .suspend = &evergreen_suspend,
800 .resume = &evergreen_resume,
801 .cp_commit = &r600_cp_commit,
802 .gpu_is_lockup = &evergreen_gpu_is_lockup,
803 .asic_reset = &evergreen_asic_reset,
804 .vga_set_state = &r600_vga_set_state,
805 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
806 .gart_set_page = &rs600_gart_set_page,
807 .ring_test = &r600_ring_test,
808 .ring_ib_execute = &r600_ring_ib_execute,
809 .irq_set = &evergreen_irq_set,
810 .irq_process = &evergreen_irq_process,
811 .get_vblank_counter = &evergreen_get_vblank_counter,
812 .fence_ring_emit = &r600_fence_ring_emit,
813 .cs_parse = &evergreen_cs_parse,
814 .copy_blit = &evergreen_copy_blit,
815 .copy_dma = &evergreen_copy_blit,
816 .copy = &evergreen_copy_blit,
817 .get_engine_clock = &radeon_atom_get_engine_clock,
818 .set_engine_clock = &radeon_atom_set_engine_clock,
819 .get_memory_clock = NULL,
820 .set_memory_clock = NULL,
821 .get_pcie_lanes = NULL,
822 .set_pcie_lanes = NULL,
823 .set_clock_gating = NULL,
824 .set_surface_reg = r600_set_surface_reg,
825 .clear_surface_reg = r600_clear_surface_reg,
826 .bandwidth_update = &evergreen_bandwidth_update,
827 .hpd_init = &evergreen_hpd_init,
828 .hpd_fini = &evergreen_hpd_fini,
829 .hpd_sense = &evergreen_hpd_sense,
830 .hpd_set_polarity = &evergreen_hpd_set_polarity,
831 .gui_idle = &r600_gui_idle,
832 .pm_misc = &evergreen_pm_misc,
833 .pm_prepare = &evergreen_pm_prepare,
834 .pm_finish = &evergreen_pm_finish,
835 .pm_init_profile = &rs780_pm_init_profile,
836 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
837};
838
796int radeon_asic_init(struct radeon_device *rdev) 839int radeon_asic_init(struct radeon_device *rdev)
797{ 840{
798 radeon_register_accessor_init(rdev); 841 radeon_register_accessor_init(rdev);
@@ -877,6 +920,9 @@ int radeon_asic_init(struct radeon_device *rdev)
877 case CHIP_HEMLOCK: 920 case CHIP_HEMLOCK:
878 rdev->asic = &evergreen_asic; 921 rdev->asic = &evergreen_asic;
879 break; 922 break;
923 case CHIP_PALM:
924 rdev->asic = &sumo_asic;
925 break;
880 default: 926 default:
881 /* FIXME: not supported yet */ 927 /* FIXME: not supported yet */
882 return -EINVAL; 928 return -EINVAL;
@@ -891,7 +937,9 @@ int radeon_asic_init(struct radeon_device *rdev)
891 if (rdev->flags & RADEON_SINGLE_CRTC) 937 if (rdev->flags & RADEON_SINGLE_CRTC)
892 rdev->num_crtc = 1; 938 rdev->num_crtc = 1;
893 else { 939 else {
894 if (ASIC_IS_DCE4(rdev)) 940 if (ASIC_IS_DCE41(rdev))
941 rdev->num_crtc = 2;
942 else if (ASIC_IS_DCE4(rdev))
895 rdev->num_crtc = 6; 943 rdev->num_crtc = 6;
896 else 944 else
897 rdev->num_crtc = 2; 945 rdev->num_crtc = 2;
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 87ead090c7d..ac882639b3e 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1321,6 +1321,43 @@ bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1321 return false; 1321 return false;
1322} 1322}
1323 1323
1324static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1325 struct radeon_atom_ss *ss,
1326 int id)
1327{
1328 struct radeon_mode_info *mode_info = &rdev->mode_info;
1329 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1330 u16 data_offset, size;
1331 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1332 u8 frev, crev;
1333 u16 percentage = 0, rate = 0;
1334
1335 /* get any igp specific overrides */
1336 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1337 &frev, &crev, &data_offset)) {
1338 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1339 (mode_info->atom_context->bios + data_offset);
1340 switch (id) {
1341 case ASIC_INTERNAL_SS_ON_TMDS:
1342 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1343 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1344 break;
1345 case ASIC_INTERNAL_SS_ON_HDMI:
1346 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1347 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1348 break;
1349 case ASIC_INTERNAL_SS_ON_LVDS:
1350 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1351 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1352 break;
1353 }
1354 if (percentage)
1355 ss->percentage = percentage;
1356 if (rate)
1357 ss->rate = rate;
1358 }
1359}
1360
1324union asic_ss_info { 1361union asic_ss_info {
1325 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 1362 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1326 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 1363 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
@@ -1385,6 +1422,8 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1385 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1422 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1386 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode; 1423 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1387 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz); 1424 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1425 if (rdev->flags & RADEON_IS_IGP)
1426 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1388 return true; 1427 return true;
1389 } 1428 }
1390 } 1429 }
@@ -1724,495 +1763,600 @@ static const char *pp_lib_thermal_controller_names[] = {
1724 "RV6xx", 1763 "RV6xx",
1725 "RV770", 1764 "RV770",
1726 "adt7473", 1765 "adt7473",
1766 "NONE",
1727 "External GPIO", 1767 "External GPIO",
1728 "Evergreen", 1768 "Evergreen",
1729 "adt7473 with internal", 1769 "emc2103",
1730 1770 "Sumo",
1731}; 1771};
1732 1772
1733union power_info { 1773union power_info {
1734 struct _ATOM_POWERPLAY_INFO info; 1774 struct _ATOM_POWERPLAY_INFO info;
1735 struct _ATOM_POWERPLAY_INFO_V2 info_2; 1775 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1736 struct _ATOM_POWERPLAY_INFO_V3 info_3; 1776 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1737 struct _ATOM_PPLIB_POWERPLAYTABLE info_4; 1777 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1778 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1779 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1738}; 1780};
1739 1781
1740void radeon_atombios_get_power_modes(struct radeon_device *rdev) 1782union pplib_clock_info {
1783 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1784 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1785 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1786 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1787};
1788
1789union pplib_power_state {
1790 struct _ATOM_PPLIB_STATE v1;
1791 struct _ATOM_PPLIB_STATE_V2 v2;
1792};
1793
1794static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1795 int state_index,
1796 u32 misc, u32 misc2)
1797{
1798 rdev->pm.power_state[state_index].misc = misc;
1799 rdev->pm.power_state[state_index].misc2 = misc2;
1800 /* order matters! */
1801 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1802 rdev->pm.power_state[state_index].type =
1803 POWER_STATE_TYPE_POWERSAVE;
1804 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1805 rdev->pm.power_state[state_index].type =
1806 POWER_STATE_TYPE_BATTERY;
1807 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1808 rdev->pm.power_state[state_index].type =
1809 POWER_STATE_TYPE_BATTERY;
1810 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1811 rdev->pm.power_state[state_index].type =
1812 POWER_STATE_TYPE_BALANCED;
1813 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1814 rdev->pm.power_state[state_index].type =
1815 POWER_STATE_TYPE_PERFORMANCE;
1816 rdev->pm.power_state[state_index].flags &=
1817 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1818 }
1819 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1820 rdev->pm.power_state[state_index].type =
1821 POWER_STATE_TYPE_BALANCED;
1822 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1823 rdev->pm.power_state[state_index].type =
1824 POWER_STATE_TYPE_DEFAULT;
1825 rdev->pm.default_power_state_index = state_index;
1826 rdev->pm.power_state[state_index].default_clock_mode =
1827 &rdev->pm.power_state[state_index].clock_info[0];
1828 } else if (state_index == 0) {
1829 rdev->pm.power_state[state_index].clock_info[0].flags |=
1830 RADEON_PM_MODE_NO_DISPLAY;
1831 }
1832}
1833
1834static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1741{ 1835{
1742 struct radeon_mode_info *mode_info = &rdev->mode_info; 1836 struct radeon_mode_info *mode_info = &rdev->mode_info;
1837 u32 misc, misc2 = 0;
1838 int num_modes = 0, i;
1839 int state_index = 0;
1840 struct radeon_i2c_bus_rec i2c_bus;
1841 union power_info *power_info;
1743 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 1842 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1744 u16 data_offset; 1843 u16 data_offset;
1745 u8 frev, crev; 1844 u8 frev, crev;
1746 u32 misc, misc2 = 0, sclk, mclk;
1747 union power_info *power_info;
1748 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1749 struct _ATOM_PPLIB_STATE *power_state;
1750 int num_modes = 0, i, j;
1751 int state_index = 0, mode_index = 0;
1752 struct radeon_i2c_bus_rec i2c_bus;
1753
1754 rdev->pm.default_power_state_index = -1;
1755 1845
1756 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1846 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1757 &frev, &crev, &data_offset)) { 1847 &frev, &crev, &data_offset))
1758 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 1848 return state_index;
1759 if (frev < 4) { 1849 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1760 /* add the i2c bus for thermal/fan chip */ 1850
1761 if (power_info->info.ucOverdriveThermalController > 0) { 1851 /* add the i2c bus for thermal/fan chip */
1762 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 1852 if (power_info->info.ucOverdriveThermalController > 0) {
1763 thermal_controller_names[power_info->info.ucOverdriveThermalController], 1853 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1764 power_info->info.ucOverdriveControllerAddress >> 1); 1854 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1765 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 1855 power_info->info.ucOverdriveControllerAddress >> 1);
1766 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1856 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1767 if (rdev->pm.i2c_bus) { 1857 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1768 struct i2c_board_info info = { }; 1858 if (rdev->pm.i2c_bus) {
1769 const char *name = thermal_controller_names[power_info->info. 1859 struct i2c_board_info info = { };
1770 ucOverdriveThermalController]; 1860 const char *name = thermal_controller_names[power_info->info.
1771 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 1861 ucOverdriveThermalController];
1772 strlcpy(info.type, name, sizeof(info.type)); 1862 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1773 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 1863 strlcpy(info.type, name, sizeof(info.type));
1774 } 1864 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1865 }
1866 }
1867 num_modes = power_info->info.ucNumOfPowerModeEntries;
1868 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1869 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1870 /* last mode is usually default, array is low to high */
1871 for (i = 0; i < num_modes; i++) {
1872 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1873 switch (frev) {
1874 case 1:
1875 rdev->pm.power_state[state_index].num_clock_modes = 1;
1876 rdev->pm.power_state[state_index].clock_info[0].mclk =
1877 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1878 rdev->pm.power_state[state_index].clock_info[0].sclk =
1879 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1880 /* skip invalid modes */
1881 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1882 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1883 continue;
1884 rdev->pm.power_state[state_index].pcie_lanes =
1885 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1886 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1887 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1888 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1889 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1890 VOLTAGE_GPIO;
1891 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1892 radeon_lookup_gpio(rdev,
1893 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1894 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1895 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1896 true;
1897 else
1898 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1899 false;
1900 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1901 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1902 VOLTAGE_VDDC;
1903 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1904 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1775 } 1905 }
1776 num_modes = power_info->info.ucNumOfPowerModeEntries; 1906 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1777 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 1907 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
1778 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 1908 state_index++;
1779 /* last mode is usually default, array is low to high */ 1909 break;
1780 for (i = 0; i < num_modes; i++) { 1910 case 2:
1781 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 1911 rdev->pm.power_state[state_index].num_clock_modes = 1;
1782 switch (frev) { 1912 rdev->pm.power_state[state_index].clock_info[0].mclk =
1783 case 1: 1913 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1784 rdev->pm.power_state[state_index].num_clock_modes = 1; 1914 rdev->pm.power_state[state_index].clock_info[0].sclk =
1785 rdev->pm.power_state[state_index].clock_info[0].mclk = 1915 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1786 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 1916 /* skip invalid modes */
1787 rdev->pm.power_state[state_index].clock_info[0].sclk = 1917 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1788 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); 1918 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1789 /* skip invalid modes */ 1919 continue;
1790 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 1920 rdev->pm.power_state[state_index].pcie_lanes =
1791 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 1921 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1792 continue; 1922 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1793 rdev->pm.power_state[state_index].pcie_lanes = 1923 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1794 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 1924 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1795 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 1925 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1796 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 1926 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1797 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 1927 VOLTAGE_GPIO;
1798 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 1928 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1799 VOLTAGE_GPIO; 1929 radeon_lookup_gpio(rdev,
1800 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 1930 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1801 radeon_lookup_gpio(rdev, 1931 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1802 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); 1932 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1803 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 1933 true;
1804 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 1934 else
1805 true; 1935 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1806 else 1936 false;
1807 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 1937 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1808 false; 1938 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1809 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 1939 VOLTAGE_VDDC;
1810 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 1940 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1811 VOLTAGE_VDDC; 1941 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1812 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1813 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1814 }
1815 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1816 rdev->pm.power_state[state_index].misc = misc;
1817 /* order matters! */
1818 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1819 rdev->pm.power_state[state_index].type =
1820 POWER_STATE_TYPE_POWERSAVE;
1821 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1822 rdev->pm.power_state[state_index].type =
1823 POWER_STATE_TYPE_BATTERY;
1824 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1825 rdev->pm.power_state[state_index].type =
1826 POWER_STATE_TYPE_BATTERY;
1827 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1828 rdev->pm.power_state[state_index].type =
1829 POWER_STATE_TYPE_BALANCED;
1830 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1831 rdev->pm.power_state[state_index].type =
1832 POWER_STATE_TYPE_PERFORMANCE;
1833 rdev->pm.power_state[state_index].flags &=
1834 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1835 }
1836 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1837 rdev->pm.power_state[state_index].type =
1838 POWER_STATE_TYPE_DEFAULT;
1839 rdev->pm.default_power_state_index = state_index;
1840 rdev->pm.power_state[state_index].default_clock_mode =
1841 &rdev->pm.power_state[state_index].clock_info[0];
1842 rdev->pm.power_state[state_index].flags &=
1843 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1844 } else if (state_index == 0) {
1845 rdev->pm.power_state[state_index].clock_info[0].flags |=
1846 RADEON_PM_MODE_NO_DISPLAY;
1847 }
1848 state_index++;
1849 break;
1850 case 2:
1851 rdev->pm.power_state[state_index].num_clock_modes = 1;
1852 rdev->pm.power_state[state_index].clock_info[0].mclk =
1853 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1854 rdev->pm.power_state[state_index].clock_info[0].sclk =
1855 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1856 /* skip invalid modes */
1857 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1858 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1859 continue;
1860 rdev->pm.power_state[state_index].pcie_lanes =
1861 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1862 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1863 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1864 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1865 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1866 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1867 VOLTAGE_GPIO;
1868 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1869 radeon_lookup_gpio(rdev,
1870 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1871 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1872 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1873 true;
1874 else
1875 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1876 false;
1877 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1878 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1879 VOLTAGE_VDDC;
1880 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1881 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1882 }
1883 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1884 rdev->pm.power_state[state_index].misc = misc;
1885 rdev->pm.power_state[state_index].misc2 = misc2;
1886 /* order matters! */
1887 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1888 rdev->pm.power_state[state_index].type =
1889 POWER_STATE_TYPE_POWERSAVE;
1890 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1891 rdev->pm.power_state[state_index].type =
1892 POWER_STATE_TYPE_BATTERY;
1893 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1894 rdev->pm.power_state[state_index].type =
1895 POWER_STATE_TYPE_BATTERY;
1896 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1897 rdev->pm.power_state[state_index].type =
1898 POWER_STATE_TYPE_BALANCED;
1899 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1900 rdev->pm.power_state[state_index].type =
1901 POWER_STATE_TYPE_PERFORMANCE;
1902 rdev->pm.power_state[state_index].flags &=
1903 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1904 }
1905 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1906 rdev->pm.power_state[state_index].type =
1907 POWER_STATE_TYPE_BALANCED;
1908 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1909 rdev->pm.power_state[state_index].flags &=
1910 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1911 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1912 rdev->pm.power_state[state_index].type =
1913 POWER_STATE_TYPE_DEFAULT;
1914 rdev->pm.default_power_state_index = state_index;
1915 rdev->pm.power_state[state_index].default_clock_mode =
1916 &rdev->pm.power_state[state_index].clock_info[0];
1917 rdev->pm.power_state[state_index].flags &=
1918 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1919 } else if (state_index == 0) {
1920 rdev->pm.power_state[state_index].clock_info[0].flags |=
1921 RADEON_PM_MODE_NO_DISPLAY;
1922 }
1923 state_index++;
1924 break;
1925 case 3:
1926 rdev->pm.power_state[state_index].num_clock_modes = 1;
1927 rdev->pm.power_state[state_index].clock_info[0].mclk =
1928 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1929 rdev->pm.power_state[state_index].clock_info[0].sclk =
1930 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1931 /* skip invalid modes */
1932 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1933 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1934 continue;
1935 rdev->pm.power_state[state_index].pcie_lanes =
1936 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1937 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1938 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1939 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1940 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1941 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1942 VOLTAGE_GPIO;
1943 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1944 radeon_lookup_gpio(rdev,
1945 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1946 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1947 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1948 true;
1949 else
1950 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1951 false;
1952 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1953 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1954 VOLTAGE_VDDC;
1955 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1956 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1957 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1958 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1959 true;
1960 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1961 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1962 }
1963 }
1964 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1965 rdev->pm.power_state[state_index].misc = misc;
1966 rdev->pm.power_state[state_index].misc2 = misc2;
1967 /* order matters! */
1968 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1969 rdev->pm.power_state[state_index].type =
1970 POWER_STATE_TYPE_POWERSAVE;
1971 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1972 rdev->pm.power_state[state_index].type =
1973 POWER_STATE_TYPE_BATTERY;
1974 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1975 rdev->pm.power_state[state_index].type =
1976 POWER_STATE_TYPE_BATTERY;
1977 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1978 rdev->pm.power_state[state_index].type =
1979 POWER_STATE_TYPE_BALANCED;
1980 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1981 rdev->pm.power_state[state_index].type =
1982 POWER_STATE_TYPE_PERFORMANCE;
1983 rdev->pm.power_state[state_index].flags &=
1984 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1985 }
1986 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1987 rdev->pm.power_state[state_index].type =
1988 POWER_STATE_TYPE_BALANCED;
1989 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1990 rdev->pm.power_state[state_index].type =
1991 POWER_STATE_TYPE_DEFAULT;
1992 rdev->pm.default_power_state_index = state_index;
1993 rdev->pm.power_state[state_index].default_clock_mode =
1994 &rdev->pm.power_state[state_index].clock_info[0];
1995 } else if (state_index == 0) {
1996 rdev->pm.power_state[state_index].clock_info[0].flags |=
1997 RADEON_PM_MODE_NO_DISPLAY;
1998 }
1999 state_index++;
2000 break;
2001 }
2002 } 1942 }
2003 /* last mode is usually default */ 1943 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2004 if (rdev->pm.default_power_state_index == -1) { 1944 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2005 rdev->pm.power_state[state_index - 1].type = 1945 state_index++;
2006 POWER_STATE_TYPE_DEFAULT; 1946 break;
2007 rdev->pm.default_power_state_index = state_index - 1; 1947 case 3:
2008 rdev->pm.power_state[state_index - 1].default_clock_mode = 1948 rdev->pm.power_state[state_index].num_clock_modes = 1;
2009 &rdev->pm.power_state[state_index - 1].clock_info[0]; 1949 rdev->pm.power_state[state_index].clock_info[0].mclk =
2010 rdev->pm.power_state[state_index].flags &= 1950 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2011 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 1951 rdev->pm.power_state[state_index].clock_info[0].sclk =
2012 rdev->pm.power_state[state_index].misc = 0; 1952 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2013 rdev->pm.power_state[state_index].misc2 = 0; 1953 /* skip invalid modes */
1954 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1955 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1956 continue;
1957 rdev->pm.power_state[state_index].pcie_lanes =
1958 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1959 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1960 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1961 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1962 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1963 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1964 VOLTAGE_GPIO;
1965 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1966 radeon_lookup_gpio(rdev,
1967 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1968 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1969 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1970 true;
1971 else
1972 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1973 false;
1974 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1975 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1976 VOLTAGE_VDDC;
1977 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1978 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1979 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1980 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1981 true;
1982 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1983 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1984 }
2014 } 1985 }
1986 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1987 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
1988 state_index++;
1989 break;
1990 }
1991 }
1992 /* last mode is usually default */
1993 if (rdev->pm.default_power_state_index == -1) {
1994 rdev->pm.power_state[state_index - 1].type =
1995 POWER_STATE_TYPE_DEFAULT;
1996 rdev->pm.default_power_state_index = state_index - 1;
1997 rdev->pm.power_state[state_index - 1].default_clock_mode =
1998 &rdev->pm.power_state[state_index - 1].clock_info[0];
1999 rdev->pm.power_state[state_index].flags &=
2000 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2001 rdev->pm.power_state[state_index].misc = 0;
2002 rdev->pm.power_state[state_index].misc2 = 0;
2003 }
2004 return state_index;
2005}
2006
2007static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2008 ATOM_PPLIB_THERMALCONTROLLER *controller)
2009{
2010 struct radeon_i2c_bus_rec i2c_bus;
2011
2012 /* add the i2c bus for thermal/fan chip */
2013 if (controller->ucType > 0) {
2014 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2015 DRM_INFO("Internal thermal controller %s fan control\n",
2016 (controller->ucFanParameters &
2017 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2018 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2019 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2020 DRM_INFO("Internal thermal controller %s fan control\n",
2021 (controller->ucFanParameters &
2022 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2023 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2024 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2025 DRM_INFO("Internal thermal controller %s fan control\n",
2026 (controller->ucFanParameters &
2027 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2028 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2029 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2030 DRM_INFO("Internal thermal controller %s fan control\n",
2031 (controller->ucFanParameters &
2032 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2033 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2034 } else if ((controller->ucType ==
2035 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2036 (controller->ucType ==
2037 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2038 (controller->ucType ==
2039 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2040 DRM_INFO("Special thermal controller config\n");
2015 } else { 2041 } else {
2016 int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2042 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2017 uint8_t fw_frev, fw_crev; 2043 pp_lib_thermal_controller_names[controller->ucType],
2018 uint16_t fw_data_offset, vddc = 0; 2044 controller->ucI2cAddress >> 1,
2019 union firmware_info *firmware_info; 2045 (controller->ucFanParameters &
2020 ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController; 2046 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2021 2047 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2022 if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL, 2048 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2023 &fw_frev, &fw_crev, &fw_data_offset)) { 2049 if (rdev->pm.i2c_bus) {
2024 firmware_info = 2050 struct i2c_board_info info = { };
2025 (union firmware_info *)(mode_info->atom_context->bios + 2051 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2026 fw_data_offset); 2052 info.addr = controller->ucI2cAddress >> 1;
2027 vddc = firmware_info->info_14.usBootUpVDDCVoltage; 2053 strlcpy(info.type, name, sizeof(info.type));
2054 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2028 } 2055 }
2056 }
2057 }
2058}
2029 2059
2030 /* add the i2c bus for thermal/fan chip */ 2060static u16 radeon_atombios_get_default_vddc(struct radeon_device *rdev)
2031 if (controller->ucType > 0) { 2061{
2032 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { 2062 struct radeon_mode_info *mode_info = &rdev->mode_info;
2033 DRM_INFO("Internal thermal controller %s fan control\n", 2063 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2034 (controller->ucFanParameters & 2064 u8 frev, crev;
2035 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2065 u16 data_offset;
2036 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; 2066 union firmware_info *firmware_info;
2037 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { 2067 u16 vddc = 0;
2038 DRM_INFO("Internal thermal controller %s fan control\n",
2039 (controller->ucFanParameters &
2040 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2041 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2042 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2043 DRM_INFO("Internal thermal controller %s fan control\n",
2044 (controller->ucFanParameters &
2045 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2046 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2047 } else if ((controller->ucType ==
2048 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2049 (controller->ucType ==
2050 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
2051 DRM_INFO("Special thermal controller config\n");
2052 } else {
2053 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2054 pp_lib_thermal_controller_names[controller->ucType],
2055 controller->ucI2cAddress >> 1,
2056 (controller->ucFanParameters &
2057 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2058 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2059 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2060 if (rdev->pm.i2c_bus) {
2061 struct i2c_board_info info = { };
2062 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2063 info.addr = controller->ucI2cAddress >> 1;
2064 strlcpy(info.type, name, sizeof(info.type));
2065 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2066 }
2067 2068
2068 } 2069 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2069 } 2070 &frev, &crev, &data_offset)) {
2070 /* first mode is usually default, followed by low to high */ 2071 firmware_info =
2071 for (i = 0; i < power_info->info_4.ucNumStates; i++) { 2072 (union firmware_info *)(mode_info->atom_context->bios +
2072 mode_index = 0; 2073 data_offset);
2073 power_state = (struct _ATOM_PPLIB_STATE *) 2074 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2074 (mode_info->atom_context->bios + 2075 }
2075 data_offset + 2076
2076 le16_to_cpu(power_info->info_4.usStateArrayOffset) + 2077 return vddc;
2077 i * power_info->info_4.ucStateEntrySize); 2078}
2078 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2079
2079 (mode_info->atom_context->bios + 2080static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2080 data_offset + 2081 int state_index, int mode_index,
2081 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) + 2082 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2082 (power_state->ucNonClockStateIndex * 2083{
2083 power_info->info_4.ucNonClockSize)); 2084 int j;
2084 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) { 2085 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2085 if (rdev->flags & RADEON_IS_IGP) { 2086 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2086 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info = 2087 u16 vddc = radeon_atombios_get_default_vddc(rdev);
2087 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *) 2088
2088 (mode_info->atom_context->bios + 2089 rdev->pm.power_state[state_index].misc = misc;
2089 data_offset + 2090 rdev->pm.power_state[state_index].misc2 = misc2;
2090 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) + 2091 rdev->pm.power_state[state_index].pcie_lanes =
2091 (power_state->ucClockStateIndices[j] * 2092 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2092 power_info->info_4.ucClockInfoSize)); 2093 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2093 sclk = le16_to_cpu(clock_info->usLowEngineClockLow); 2094 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2094 sclk |= clock_info->ucLowEngineClockHigh << 16; 2095 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2095 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2096 rdev->pm.power_state[state_index].type =
2096 /* skip invalid modes */ 2097 POWER_STATE_TYPE_BATTERY;
2097 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2098 break;
2098 continue; 2099 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2099 /* voltage works differently on IGPs */ 2100 rdev->pm.power_state[state_index].type =
2100 mode_index++; 2101 POWER_STATE_TYPE_BALANCED;
2101 } else if (ASIC_IS_DCE4(rdev)) { 2102 break;
2102 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info = 2103 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2103 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *) 2104 rdev->pm.power_state[state_index].type =
2104 (mode_info->atom_context->bios + 2105 POWER_STATE_TYPE_PERFORMANCE;
2105 data_offset + 2106 break;
2106 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) + 2107 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2107 (power_state->ucClockStateIndices[j] * 2108 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2108 power_info->info_4.ucClockInfoSize)); 2109 rdev->pm.power_state[state_index].type =
2109 sclk = le16_to_cpu(clock_info->usEngineClockLow); 2110 POWER_STATE_TYPE_PERFORMANCE;
2110 sclk |= clock_info->ucEngineClockHigh << 16; 2111 break;
2111 mclk = le16_to_cpu(clock_info->usMemoryClockLow); 2112 }
2112 mclk |= clock_info->ucMemoryClockHigh << 16; 2113 rdev->pm.power_state[state_index].flags = 0;
2113 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2114 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2114 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2115 rdev->pm.power_state[state_index].flags |=
2115 /* skip invalid modes */ 2116 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2116 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2117 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2117 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2118 rdev->pm.power_state[state_index].type =
2118 continue; 2119 POWER_STATE_TYPE_DEFAULT;
2119 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2120 rdev->pm.default_power_state_index = state_index;
2120 VOLTAGE_SW; 2121 rdev->pm.power_state[state_index].default_clock_mode =
2121 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2122 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2122 clock_info->usVDDC; 2123 /* patch the table values with the default slck/mclk from firmware info */
2123 /* XXX usVDDCI */ 2124 for (j = 0; j < mode_index; j++) {
2124 mode_index++; 2125 rdev->pm.power_state[state_index].clock_info[j].mclk =
2125 } else { 2126 rdev->clock.default_mclk;
2126 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info = 2127 rdev->pm.power_state[state_index].clock_info[j].sclk =
2127 (struct _ATOM_PPLIB_R600_CLOCK_INFO *) 2128 rdev->clock.default_sclk;
2128 (mode_info->atom_context->bios + 2129 if (vddc)
2129 data_offset + 2130 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2130 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) + 2131 vddc;
2131 (power_state->ucClockStateIndices[j] * 2132 }
2132 power_info->info_4.ucClockInfoSize)); 2133 }
2133 sclk = le16_to_cpu(clock_info->usEngineClockLow); 2134}
2134 sclk |= clock_info->ucEngineClockHigh << 16; 2135
2135 mclk = le16_to_cpu(clock_info->usMemoryClockLow); 2136static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2136 mclk |= clock_info->ucMemoryClockHigh << 16; 2137 int state_index, int mode_index,
2137 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2138 union pplib_clock_info *clock_info)
2138 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2139{
2139 /* skip invalid modes */ 2140 u32 sclk, mclk;
2140 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2141
2141 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2142 if (rdev->flags & RADEON_IS_IGP) {
2142 continue; 2143 if (rdev->family >= CHIP_PALM) {
2143 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2144 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2144 VOLTAGE_SW; 2145 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2145 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2146 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2146 clock_info->usVDDC; 2147 } else {
2147 mode_index++; 2148 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2148 } 2149 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2149 } 2150 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2150 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2151 }
2151 if (mode_index) { 2152 } else if (ASIC_IS_DCE4(rdev)) {
2152 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2153 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2153 misc2 = le16_to_cpu(non_clock_info->usClassification); 2154 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2154 rdev->pm.power_state[state_index].misc = misc; 2155 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2155 rdev->pm.power_state[state_index].misc2 = misc2; 2156 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2156 rdev->pm.power_state[state_index].pcie_lanes = 2157 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2157 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 2158 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2158 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 2159 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2159 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 2160 VOLTAGE_SW;
2160 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 2161 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2161 rdev->pm.power_state[state_index].type = 2162 clock_info->evergreen.usVDDC;
2162 POWER_STATE_TYPE_BATTERY; 2163 } else {
2163 break; 2164 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2164 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 2165 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2165 rdev->pm.power_state[state_index].type = 2166 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2166 POWER_STATE_TYPE_BALANCED; 2167 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2167 break; 2168 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2168 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 2169 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2169 rdev->pm.power_state[state_index].type = 2170 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2170 POWER_STATE_TYPE_PERFORMANCE; 2171 VOLTAGE_SW;
2171 break; 2172 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2172 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 2173 clock_info->r600.usVDDC;
2173 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 2174 }
2174 rdev->pm.power_state[state_index].type = 2175
2175 POWER_STATE_TYPE_PERFORMANCE; 2176 if (rdev->flags & RADEON_IS_IGP) {
2176 break; 2177 /* skip invalid modes */
2177 } 2178 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2178 rdev->pm.power_state[state_index].flags = 0; 2179 return false;
2179 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2180 } else {
2180 rdev->pm.power_state[state_index].flags |= 2181 /* skip invalid modes */
2181 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2182 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2182 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2183 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2183 rdev->pm.power_state[state_index].type = 2184 return false;
2184 POWER_STATE_TYPE_DEFAULT; 2185 }
2185 rdev->pm.default_power_state_index = state_index; 2186 return true;
2186 rdev->pm.power_state[state_index].default_clock_mode = 2187}
2187 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2188
2188 /* patch the table values with the default slck/mclk from firmware info */ 2189static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2189 for (j = 0; j < mode_index; j++) { 2190{
2190 rdev->pm.power_state[state_index].clock_info[j].mclk = 2191 struct radeon_mode_info *mode_info = &rdev->mode_info;
2191 rdev->clock.default_mclk; 2192 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2192 rdev->pm.power_state[state_index].clock_info[j].sclk = 2193 union pplib_power_state *power_state;
2193 rdev->clock.default_sclk; 2194 int i, j;
2194 if (vddc) 2195 int state_index = 0, mode_index = 0;
2195 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2196 union pplib_clock_info *clock_info;
2196 vddc; 2197 bool valid;
2197 } 2198 union power_info *power_info;
2198 } 2199 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2199 state_index++; 2200 u16 data_offset;
2200 } 2201 u8 frev, crev;
2201 } 2202
2202 /* if multiple clock modes, mark the lowest as no display */ 2203 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2203 for (i = 0; i < state_index; i++) { 2204 &frev, &crev, &data_offset))
2204 if (rdev->pm.power_state[i].num_clock_modes > 1) 2205 return state_index;
2205 rdev->pm.power_state[i].clock_info[0].flags |= 2206 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2206 RADEON_PM_MODE_NO_DISPLAY; 2207
2207 } 2208 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2208 /* first mode is usually default */ 2209 /* first mode is usually default, followed by low to high */
2209 if (rdev->pm.default_power_state_index == -1) { 2210 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2210 rdev->pm.power_state[0].type = 2211 mode_index = 0;
2211 POWER_STATE_TYPE_DEFAULT; 2212 power_state = (union pplib_power_state *)
2212 rdev->pm.default_power_state_index = 0; 2213 (mode_info->atom_context->bios + data_offset +
2213 rdev->pm.power_state[0].default_clock_mode = 2214 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2214 &rdev->pm.power_state[0].clock_info[0]; 2215 i * power_info->pplib.ucStateEntrySize);
2215 } 2216 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2217 (mode_info->atom_context->bios + data_offset +
2218 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2219 (power_state->v1.ucNonClockStateIndex *
2220 power_info->pplib.ucNonClockSize));
2221 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2222 clock_info = (union pplib_clock_info *)
2223 (mode_info->atom_context->bios + data_offset +
2224 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2225 (power_state->v1.ucClockStateIndices[j] *
2226 power_info->pplib.ucClockInfoSize));
2227 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2228 state_index, mode_index,
2229 clock_info);
2230 if (valid)
2231 mode_index++;
2232 }
2233 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2234 if (mode_index) {
2235 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2236 non_clock_info);
2237 state_index++;
2238 }
2239 }
2240 /* if multiple clock modes, mark the lowest as no display */
2241 for (i = 0; i < state_index; i++) {
2242 if (rdev->pm.power_state[i].num_clock_modes > 1)
2243 rdev->pm.power_state[i].clock_info[0].flags |=
2244 RADEON_PM_MODE_NO_DISPLAY;
2245 }
2246 /* first mode is usually default */
2247 if (rdev->pm.default_power_state_index == -1) {
2248 rdev->pm.power_state[0].type =
2249 POWER_STATE_TYPE_DEFAULT;
2250 rdev->pm.default_power_state_index = 0;
2251 rdev->pm.power_state[0].default_clock_mode =
2252 &rdev->pm.power_state[0].clock_info[0];
2253 }
2254 return state_index;
2255}
2256
2257static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2258{
2259 struct radeon_mode_info *mode_info = &rdev->mode_info;
2260 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2261 union pplib_power_state *power_state;
2262 int i, j, non_clock_array_index, clock_array_index;
2263 int state_index = 0, mode_index = 0;
2264 union pplib_clock_info *clock_info;
2265 struct StateArray *state_array;
2266 struct ClockInfoArray *clock_info_array;
2267 struct NonClockInfoArray *non_clock_info_array;
2268 bool valid;
2269 union power_info *power_info;
2270 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2271 u16 data_offset;
2272 u8 frev, crev;
2273
2274 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2275 &frev, &crev, &data_offset))
2276 return state_index;
2277 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2278
2279 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2280 state_array = (struct StateArray *)
2281 (mode_info->atom_context->bios + data_offset +
2282 power_info->pplib.usStateArrayOffset);
2283 clock_info_array = (struct ClockInfoArray *)
2284 (mode_info->atom_context->bios + data_offset +
2285 power_info->pplib.usClockInfoArrayOffset);
2286 non_clock_info_array = (struct NonClockInfoArray *)
2287 (mode_info->atom_context->bios + data_offset +
2288 power_info->pplib.usNonClockInfoArrayOffset);
2289 for (i = 0; i < state_array->ucNumEntries; i++) {
2290 mode_index = 0;
2291 power_state = (union pplib_power_state *)&state_array->states[i];
2292 /* XXX this might be an inagua bug... */
2293 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2294 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2295 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2296 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2297 clock_array_index = power_state->v2.clockInfoIndex[j];
2298 /* XXX this might be an inagua bug... */
2299 if (clock_array_index >= clock_info_array->ucNumEntries)
2300 continue;
2301 clock_info = (union pplib_clock_info *)
2302 &clock_info_array->clockInfo[clock_array_index];
2303 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2304 state_index, mode_index,
2305 clock_info);
2306 if (valid)
2307 mode_index++;
2308 }
2309 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2310 if (mode_index) {
2311 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2312 non_clock_info);
2313 state_index++;
2314 }
2315 }
2316 /* if multiple clock modes, mark the lowest as no display */
2317 for (i = 0; i < state_index; i++) {
2318 if (rdev->pm.power_state[i].num_clock_modes > 1)
2319 rdev->pm.power_state[i].clock_info[0].flags |=
2320 RADEON_PM_MODE_NO_DISPLAY;
2321 }
2322 /* first mode is usually default */
2323 if (rdev->pm.default_power_state_index == -1) {
2324 rdev->pm.power_state[0].type =
2325 POWER_STATE_TYPE_DEFAULT;
2326 rdev->pm.default_power_state_index = 0;
2327 rdev->pm.power_state[0].default_clock_mode =
2328 &rdev->pm.power_state[0].clock_info[0];
2329 }
2330 return state_index;
2331}
2332
2333void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2334{
2335 struct radeon_mode_info *mode_info = &rdev->mode_info;
2336 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2337 u16 data_offset;
2338 u8 frev, crev;
2339 int state_index = 0;
2340
2341 rdev->pm.default_power_state_index = -1;
2342
2343 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2344 &frev, &crev, &data_offset)) {
2345 switch (frev) {
2346 case 1:
2347 case 2:
2348 case 3:
2349 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2350 break;
2351 case 4:
2352 case 5:
2353 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2354 break;
2355 case 6:
2356 state_index = radeon_atombios_parse_power_table_6(rdev);
2357 break;
2358 default:
2359 break;
2216 } 2360 }
2217 } else { 2361 } else {
2218 /* add the default mode */ 2362 /* add the default mode */
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index d8ac1849180..dd93c9c9414 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -335,7 +335,12 @@ bool radeon_card_posted(struct radeon_device *rdev)
335 uint32_t reg; 335 uint32_t reg;
336 336
337 /* first check CRTCs */ 337 /* first check CRTCs */
338 if (ASIC_IS_DCE4(rdev)) { 338 if (ASIC_IS_DCE41(rdev)) {
339 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
340 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
341 if (reg & EVERGREEN_CRTC_MASTER_EN)
342 return true;
343 } else if (ASIC_IS_DCE4(rdev)) {
339 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 344 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
340 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | 345 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
341 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 346 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 15f24f2ee04..7b17e639ab3 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -485,7 +485,7 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
485 radeon_legacy_init_crtc(dev, radeon_crtc); 485 radeon_legacy_init_crtc(dev, radeon_crtc);
486} 486}
487 487
488static const char *encoder_names[34] = { 488static const char *encoder_names[36] = {
489 "NONE", 489 "NONE",
490 "INTERNAL_LVDS", 490 "INTERNAL_LVDS",
491 "INTERNAL_TMDS1", 491 "INTERNAL_TMDS1",
@@ -520,6 +520,8 @@ static const char *encoder_names[34] = {
520 "INTERNAL_KLDSCP_LVTMA", 520 "INTERNAL_KLDSCP_LVTMA",
521 "INTERNAL_UNIPHY1", 521 "INTERNAL_UNIPHY1",
522 "INTERNAL_UNIPHY2", 522 "INTERNAL_UNIPHY2",
523 "NUTMEG",
524 "TRAVIS",
523}; 525};
524 526
525static const char *connector_names[15] = { 527static const char *connector_names[15] = {
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 041943df966..e4e64a80b58 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -713,7 +713,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
713 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 713 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
714 * 714 *
715 * DCE 4.0 715 * DCE 4.0
716 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B). 716 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
717 * Supports up to 6 digital outputs 717 * Supports up to 6 digital outputs
718 * - 6 DIG encoder blocks. 718 * - 6 DIG encoder blocks.
719 * - DIG to PHY mapping is hardcoded 719 * - DIG to PHY mapping is hardcoded
@@ -724,6 +724,12 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
724 * DIG5 drives UNIPHY2 link A, A+B 724 * DIG5 drives UNIPHY2 link A, A+B
725 * DIG6 drives UNIPHY2 link B 725 * DIG6 drives UNIPHY2 link B
726 * 726 *
727 * DCE 4.1
728 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
729 * Supports up to 6 digital outputs
730 * - 2 DIG encoder blocks.
731 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
732 *
727 * Routing 733 * Routing
728 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 734 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
729 * Examples: 735 * Examples:
@@ -904,9 +910,15 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
904 else 910 else
905 args.v3.ucLaneNum = 4; 911 args.v3.ucLaneNum = 4;
906 912
907 if (dig->linkb) { 913 if (ASIC_IS_DCE41(rdev)) {
908 args.v3.acConfig.ucLinkSel = 1; 914 args.v3.acConfig.ucEncoderSel = dig->dig_encoder;
909 args.v3.acConfig.ucEncoderSel = 1; 915 if (dig->linkb)
916 args.v3.acConfig.ucLinkSel = 1;
917 } else {
918 if (dig->linkb) {
919 args.v3.acConfig.ucLinkSel = 1;
920 args.v3.acConfig.ucEncoderSel = 1;
921 }
910 } 922 }
911 923
912 /* Select the PLL for the PHY 924 /* Select the PLL for the PHY
@@ -1044,6 +1056,7 @@ atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1044 1056
1045union external_encoder_control { 1057union external_encoder_control {
1046 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1058 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1059 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1047}; 1060};
1048 1061
1049static void 1062static void
@@ -1054,6 +1067,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
1054 struct drm_device *dev = encoder->dev; 1067 struct drm_device *dev = encoder->dev;
1055 struct radeon_device *rdev = dev->dev_private; 1068 struct radeon_device *rdev = dev->dev_private;
1056 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1069 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1070 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1057 union external_encoder_control args; 1071 union external_encoder_control args;
1058 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1072 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1059 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1073 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
@@ -1061,6 +1075,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
1061 int dp_clock = 0; 1075 int dp_clock = 0;
1062 int dp_lane_count = 0; 1076 int dp_lane_count = 0;
1063 int connector_object_id = 0; 1077 int connector_object_id = 0;
1078 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1064 1079
1065 if (connector) { 1080 if (connector) {
1066 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1081 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -1099,6 +1114,37 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
1099 else 1114 else
1100 args.v1.sDigEncoder.ucLaneNum = 4; 1115 args.v1.sDigEncoder.ucLaneNum = 4;
1101 break; 1116 break;
1117 case 3:
1118 args.v3.sExtEncoder.ucAction = action;
1119 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1120 args.v3.sExtEncoder.usConnectorId = connector_object_id;
1121 else
1122 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1123 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1124
1125 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1126 if (dp_clock == 270000)
1127 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1128 else if (dp_clock == 540000)
1129 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1130 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1131 } else if (radeon_encoder->pixel_clock > 165000)
1132 args.v3.sExtEncoder.ucLaneNum = 8;
1133 else
1134 args.v3.sExtEncoder.ucLaneNum = 4;
1135 switch (ext_enum) {
1136 case GRAPH_OBJECT_ENUM_ID1:
1137 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1138 break;
1139 case GRAPH_OBJECT_ENUM_ID2:
1140 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1141 break;
1142 case GRAPH_OBJECT_ENUM_ID3:
1143 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1144 break;
1145 }
1146 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1147 break;
1102 default: 1148 default:
1103 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1149 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1104 return; 1150 return;
@@ -1289,12 +1335,18 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1289 switch (mode) { 1335 switch (mode) {
1290 case DRM_MODE_DPMS_ON: 1336 case DRM_MODE_DPMS_ON:
1291 default: 1337 default:
1292 action = ATOM_ENABLE; 1338 if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP))
1339 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
1340 else
1341 action = ATOM_ENABLE;
1293 break; 1342 break;
1294 case DRM_MODE_DPMS_STANDBY: 1343 case DRM_MODE_DPMS_STANDBY:
1295 case DRM_MODE_DPMS_SUSPEND: 1344 case DRM_MODE_DPMS_SUSPEND:
1296 case DRM_MODE_DPMS_OFF: 1345 case DRM_MODE_DPMS_OFF:
1297 action = ATOM_DISABLE; 1346 if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP))
1347 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
1348 else
1349 action = ATOM_DISABLE;
1298 break; 1350 break;
1299 } 1351 }
1300 atombios_external_encoder_setup(encoder, ext_encoder, action); 1352 atombios_external_encoder_setup(encoder, ext_encoder, action);
@@ -1483,6 +1535,11 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1483 struct radeon_encoder_atom_dig *dig; 1535 struct radeon_encoder_atom_dig *dig;
1484 uint32_t dig_enc_in_use = 0; 1536 uint32_t dig_enc_in_use = 0;
1485 1537
1538 /* on DCE41 and encoder can driver any phy so just crtc id */
1539 if (ASIC_IS_DCE41(rdev)) {
1540 return radeon_crtc->crtc_id;
1541 }
1542
1486 if (ASIC_IS_DCE4(rdev)) { 1543 if (ASIC_IS_DCE4(rdev)) {
1487 dig = radeon_encoder->enc_priv; 1544 dig = radeon_encoder->enc_priv;
1488 switch (radeon_encoder->encoder_id) { 1545 switch (radeon_encoder->encoder_id) {
@@ -1610,7 +1667,13 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1610 } 1667 }
1611 1668
1612 if (ext_encoder) { 1669 if (ext_encoder) {
1613 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1670 if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP)) {
1671 atombios_external_encoder_setup(encoder, ext_encoder,
1672 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1673 atombios_external_encoder_setup(encoder, ext_encoder,
1674 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1675 } else
1676 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1614 } 1677 }
1615 1678
1616 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1679 atombios_apply_encoder_quirks(encoder, adjusted_mode);
@@ -2029,6 +2092,8 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t
2029 case ENCODER_OBJECT_ID_TITFP513: 2092 case ENCODER_OBJECT_ID_TITFP513:
2030 case ENCODER_OBJECT_ID_VT1623: 2093 case ENCODER_OBJECT_ID_VT1623:
2031 case ENCODER_OBJECT_ID_HDMI_SI1930: 2094 case ENCODER_OBJECT_ID_HDMI_SI1930:
2095 case ENCODER_OBJECT_ID_TRAVIS:
2096 case ENCODER_OBJECT_ID_NUTMEG:
2032 /* these are handled by the primary encoders */ 2097 /* these are handled by the primary encoders */
2033 radeon_encoder->is_ext_encoder = true; 2098 radeon_encoder->is_ext_encoder = true;
2034 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2099 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h
index e329066dcab..4c222d5437d 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -80,6 +80,7 @@ enum radeon_family {
80 CHIP_JUNIPER, 80 CHIP_JUNIPER,
81 CHIP_CYPRESS, 81 CHIP_CYPRESS,
82 CHIP_HEMLOCK, 82 CHIP_HEMLOCK,
83 CHIP_PALM,
83 CHIP_LAST, 84 CHIP_LAST,
84}; 85};
85 86
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index e0d1c6d1b9c..c6861bb751a 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -125,7 +125,7 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
125 * chips. Disable MSI on them for now. 125 * chips. Disable MSI on them for now.
126 */ 126 */
127 if ((rdev->family >= CHIP_RV380) && 127 if ((rdev->family >= CHIP_RV380) &&
128 (!(rdev->flags & RADEON_IS_IGP)) && 128 ((!(rdev->flags & RADEON_IS_IGP)) || (rdev->family >= CHIP_PALM)) &&
129 (!(rdev->flags & RADEON_IS_AGP))) { 129 (!(rdev->flags & RADEON_IS_AGP))) {
130 int ret = pci_enable_msi(rdev->pdev); 130 int ret = pci_enable_msi(rdev->pdev);
131 if (!ret) { 131 if (!ret) {
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 5eda5e47198..4de7776bd1c 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -449,6 +449,9 @@ static ssize_t radeon_hwmon_show_temp(struct device *dev,
449 case THERMAL_TYPE_EVERGREEN: 449 case THERMAL_TYPE_EVERGREEN:
450 temp = evergreen_get_temp(rdev); 450 temp = evergreen_get_temp(rdev);
451 break; 451 break;
452 case THERMAL_TYPE_SUMO:
453 temp = sumo_get_temp(rdev);
454 break;
452 default: 455 default:
453 temp = 0; 456 temp = 0;
454 break; 457 break;
@@ -487,6 +490,7 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
487 case THERMAL_TYPE_RV6XX: 490 case THERMAL_TYPE_RV6XX:
488 case THERMAL_TYPE_RV770: 491 case THERMAL_TYPE_RV770:
489 case THERMAL_TYPE_EVERGREEN: 492 case THERMAL_TYPE_EVERGREEN:
493 case THERMAL_TYPE_SUMO:
490 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev); 494 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
491 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 495 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
492 err = PTR_ERR(rdev->pm.int_hwmon_dev); 496 err = PTR_ERR(rdev->pm.int_hwmon_dev);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 42ff07893f3..7c2e0b19a55 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -271,6 +271,12 @@ static void rv770_mc_program(struct radeon_device *rdev)
271 rdev->mc.vram_end >> 12); 271 rdev->mc.vram_end >> 12);
272 } 272 }
273 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 273 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
274 if (rdev->flags & RADEON_IS_IGP) {
275 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
276 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
277 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
278 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
279 }
274 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 280 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
275 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 281 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
276 WREG32(MC_VM_FB_LOCATION, tmp); 282 WREG32(MC_VM_FB_LOCATION, tmp);
@@ -523,6 +529,49 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
523 return backend_map; 529 return backend_map;
524} 530}
525 531
532static void rv770_program_channel_remap(struct radeon_device *rdev)
533{
534 u32 tcp_chan_steer, mc_shared_chremap, tmp;
535 bool force_no_swizzle;
536
537 switch (rdev->family) {
538 case CHIP_RV770:
539 case CHIP_RV730:
540 force_no_swizzle = false;
541 break;
542 case CHIP_RV710:
543 case CHIP_RV740:
544 default:
545 force_no_swizzle = true;
546 break;
547 }
548
549 tmp = RREG32(MC_SHARED_CHMAP);
550 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
551 case 0:
552 case 1:
553 default:
554 /* default mapping */
555 mc_shared_chremap = 0x00fac688;
556 break;
557 case 2:
558 case 3:
559 if (force_no_swizzle)
560 mc_shared_chremap = 0x00fac688;
561 else
562 mc_shared_chremap = 0x00bbc298;
563 break;
564 }
565
566 if (rdev->family == CHIP_RV740)
567 tcp_chan_steer = 0x00ef2a60;
568 else
569 tcp_chan_steer = 0x00fac688;
570
571 WREG32(TCP_CHAN_STEER, tcp_chan_steer);
572 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
573}
574
526static void rv770_gpu_init(struct radeon_device *rdev) 575static void rv770_gpu_init(struct radeon_device *rdev)
527{ 576{
528 int i, j, num_qd_pipes; 577 int i, j, num_qd_pipes;
@@ -722,6 +771,8 @@ static void rv770_gpu_init(struct radeon_device *rdev)
722 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 771 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
723 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 772 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
724 773
774 rv770_program_channel_remap(rdev);
775
725 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 776 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
726 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 777 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
727 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 778 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
@@ -990,6 +1041,50 @@ static void rv770_vram_scratch_fini(struct radeon_device *rdev)
990 radeon_bo_unref(&rdev->vram_scratch.robj); 1041 radeon_bo_unref(&rdev->vram_scratch.robj);
991} 1042}
992 1043
1044void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1045{
1046 u64 size_bf, size_af;
1047
1048 if (mc->mc_vram_size > 0xE0000000) {
1049 /* leave room for at least 512M GTT */
1050 dev_warn(rdev->dev, "limiting VRAM\n");
1051 mc->real_vram_size = 0xE0000000;
1052 mc->mc_vram_size = 0xE0000000;
1053 }
1054 if (rdev->flags & RADEON_IS_AGP) {
1055 size_bf = mc->gtt_start;
1056 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1057 if (size_bf > size_af) {
1058 if (mc->mc_vram_size > size_bf) {
1059 dev_warn(rdev->dev, "limiting VRAM\n");
1060 mc->real_vram_size = size_bf;
1061 mc->mc_vram_size = size_bf;
1062 }
1063 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1064 } else {
1065 if (mc->mc_vram_size > size_af) {
1066 dev_warn(rdev->dev, "limiting VRAM\n");
1067 mc->real_vram_size = size_af;
1068 mc->mc_vram_size = size_af;
1069 }
1070 mc->vram_start = mc->gtt_end;
1071 }
1072 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1073 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1074 mc->mc_vram_size >> 20, mc->vram_start,
1075 mc->vram_end, mc->real_vram_size >> 20);
1076 } else {
1077 u64 base = 0;
1078 if (rdev->flags & RADEON_IS_IGP) {
1079 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1080 base |= RREG32(MC_FUS_VM_FB_OFFSET) & 0x00F00000;
1081 }
1082 radeon_vram_location(rdev, &rdev->mc, base);
1083 rdev->mc.gtt_base_align = 0;
1084 radeon_gtt_location(rdev, mc);
1085 }
1086}
1087
993int rv770_mc_init(struct radeon_device *rdev) 1088int rv770_mc_init(struct radeon_device *rdev)
994{ 1089{
995 u32 tmp; 1090 u32 tmp;
@@ -1030,7 +1125,7 @@ int rv770_mc_init(struct radeon_device *rdev)
1030 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1125 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1031 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1126 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1032 rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1127 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1033 r600_vram_gtt_location(rdev, &rdev->mc); 1128 r700_vram_gtt_location(rdev, &rdev->mc);
1034 radeon_update_bandwidth_info(rdev); 1129 radeon_update_bandwidth_info(rdev);
1035 1130
1036 return 0; 1131 return 0;
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 11955c685ad..98f9ad256d3 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -138,6 +138,7 @@
138#define MC_SHARED_CHMAP 0x2004 138#define MC_SHARED_CHMAP 0x2004
139#define NOOFCHAN_SHIFT 12 139#define NOOFCHAN_SHIFT 12
140#define NOOFCHAN_MASK 0x00003000 140#define NOOFCHAN_MASK 0x00003000
141#define MC_SHARED_CHREMAP 0x2008
141 142
142#define MC_ARB_RAMCFG 0x2760 143#define MC_ARB_RAMCFG 0x2760
143#define NOOFBANK_SHIFT 0 144#define NOOFBANK_SHIFT 0
@@ -157,6 +158,7 @@
157#define MC_VM_AGP_BOT 0x202C 158#define MC_VM_AGP_BOT 0x202C
158#define MC_VM_AGP_BASE 0x2030 159#define MC_VM_AGP_BASE 0x2030
159#define MC_VM_FB_LOCATION 0x2024 160#define MC_VM_FB_LOCATION 0x2024
161#define MC_FUS_VM_FB_OFFSET 0x2898
160#define MC_VM_MB_L1_TLB0_CNTL 0x2234 162#define MC_VM_MB_L1_TLB0_CNTL 0x2234
161#define MC_VM_MB_L1_TLB1_CNTL 0x2238 163#define MC_VM_MB_L1_TLB1_CNTL 0x2238
162#define MC_VM_MB_L1_TLB2_CNTL 0x223C 164#define MC_VM_MB_L1_TLB2_CNTL 0x223C
@@ -303,6 +305,7 @@
303#define BILINEAR_PRECISION_8_BIT (1 << 31) 305#define BILINEAR_PRECISION_8_BIT (1 << 31)
304 306
305#define TCP_CNTL 0x9610 307#define TCP_CNTL 0x9610
308#define TCP_CHAN_STEER 0x9614
306 309
307#define VGT_CACHE_INVALIDATION 0x88C4 310#define VGT_CACHE_INVALIDATION 0x88C4
308#define CACHE_INVALIDATION(x) ((x)<<0) 311#define CACHE_INVALIDATION(x) ((x)<<0)
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 883c1d43989..e6b28a39942 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -419,6 +419,10 @@
419 {0x1002, 0x9713, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 419 {0x1002, 0x9713, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
420 {0x1002, 0x9714, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 420 {0x1002, 0x9714, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
421 {0x1002, 0x9715, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 421 {0x1002, 0x9715, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
422 {0x1002, 0x9802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
423 {0x1002, 0x9803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
424 {0x1002, 0x9804, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
425 {0x1002, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
422 {0, 0, 0} 426 {0, 0, 0}
423 427
424#define r128_PCI_IDS \ 428#define r128_PCI_IDS \
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 07:27:19 -0400