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-rw-r--r--drivers/staging/poch/poch.c16
1 files changed, 13 insertions, 3 deletions
diff --git a/drivers/staging/poch/poch.c b/drivers/staging/poch/poch.c
index 1637c281ea3..babd881809a 100644
--- a/drivers/staging/poch/poch.c
+++ b/drivers/staging/poch/poch.c
@@ -252,6 +252,11 @@ module_param(synth_rx, bool, 0600);
252MODULE_PARM_DESC(synth_rx, 252MODULE_PARM_DESC(synth_rx,
253 "Synthesize received values using a counter. Default: No"); 253 "Synthesize received values using a counter. Default: No");
254 254
255static int loopback;
256module_param(loopback, bool, 0600);
257MODULE_PARM_DESC(loopback,
258 "Enable hardware loopback of trasnmitted data. Default: No");
259
255static dev_t poch_first_dev; 260static dev_t poch_first_dev;
256static struct class *poch_cls; 261static struct class *poch_cls;
257static DEFINE_IDR(poch_ids); 262static DEFINE_IDR(poch_ids);
@@ -830,9 +835,14 @@ static int poch_open(struct inode *inode, struct file *filp)
830 835
831 if (channel->dir == CHANNEL_DIR_TX) { 836 if (channel->dir == CHANNEL_DIR_TX) {
832 /* Flush TX FIFO and output data from cardbus. */ 837 /* Flush TX FIFO and output data from cardbus. */
833 iowrite32(FPGA_TX_CTL_FIFO_FLUSH 838 u32 ctl_val = 0;
834 | FPGA_TX_CTL_OUTPUT_CARDBUS, 839
835 fpga + FPGA_TX_CTL_REG); 840 ctl_val |= FPGA_TX_CTL_FIFO_FLUSH;
841 ctl_val |= FPGA_TX_CTL_OUTPUT_CARDBUS;
842 if (loopback)
843 ctl_val |= FPGA_TX_CTL_LOOPBACK;
844
845 iowrite32(ctl_val, fpga + FPGA_TX_CTL_REG);
836 } else { 846 } else {
837 /* Flush RX FIFO and output data to cardbus. */ 847 /* Flush RX FIFO and output data to cardbus. */
838 u32 ctl_val = FPGA_RX_CTL_CONT_CAP | FPGA_RX_CTL_FIFO_FLUSH; 848 u32 ctl_val = FPGA_RX_CTL_CONT_CAP | FPGA_RX_CTL_FIFO_FLUSH;