diff options
-rw-r--r-- | arch/arm/mach-pxa/include/mach/pxa-regs.h | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h index b6b80f63b4d..f842fd3d39a 100644 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h | |||
@@ -92,7 +92,13 @@ | |||
92 | #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ | 92 | #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ |
93 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ | 93 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ |
94 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ | 94 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ |
95 | #ifdef CONFIG_PXA27x | 95 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ |
96 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ | ||
97 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ | ||
98 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ | ||
99 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ | ||
100 | |||
101 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
96 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ | 102 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ |
97 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ | 103 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ |
98 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ | 104 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ |
@@ -101,11 +107,6 @@ | |||
101 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ | 107 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ |
102 | #define DCSR_EORINTR (1 << 9) /* The end of Receive */ | 108 | #define DCSR_EORINTR (1 << 9) /* The end of Receive */ |
103 | #endif | 109 | #endif |
104 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ | ||
105 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ | ||
106 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ | ||
107 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ | ||
108 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ | ||
109 | 110 | ||
110 | #define DALGN __REG(0x400000a0) /* DMA Alignment Register */ | 111 | #define DALGN __REG(0x400000a0) /* DMA Alignment Register */ |
111 | #define DINT __REG(0x400000f0) /* DMA Interrupt Register */ | 112 | #define DINT __REG(0x400000f0) /* DMA Interrupt Register */ |