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-rw-r--r--arch/mips/Kconfig7
-rw-r--r--arch/mips/Kconfig.debug22
-rw-r--r--arch/mips/au1000/Kconfig1
-rw-r--r--arch/mips/au1000/common/Makefile1
-rw-r--r--arch/mips/au1000/common/dbg_io.c109
-rw-r--r--arch/mips/au1000/db1x00/init.c2
-rw-r--r--arch/mips/au1000/mtx-1/init.c2
-rw-r--r--arch/mips/au1000/pb1000/init.c2
-rw-r--r--arch/mips/au1000/pb1100/init.c2
-rw-r--r--arch/mips/au1000/pb1200/init.c2
-rw-r--r--arch/mips/au1000/pb1500/init.c2
-rw-r--r--arch/mips/au1000/pb1550/init.c2
-rw-r--r--arch/mips/au1000/xxs1500/init.c2
-rw-r--r--arch/mips/basler/excite/Makefile1
-rw-r--r--arch/mips/basler/excite/excite_dbg_io.c121
-rw-r--r--arch/mips/basler/excite/excite_irq.c7
-rw-r--r--arch/mips/basler/excite/excite_setup.c4
-rw-r--r--arch/mips/configs/cobalt_defconfig378
-rw-r--r--arch/mips/configs/db1000_defconfig1
-rw-r--r--arch/mips/configs/db1100_defconfig1
-rw-r--r--arch/mips/configs/db1200_defconfig1
-rw-r--r--arch/mips/configs/db1500_defconfig1
-rw-r--r--arch/mips/configs/db1550_defconfig1
-rw-r--r--arch/mips/configs/excite_defconfig1
-rw-r--r--arch/mips/configs/ip27_defconfig1
-rw-r--r--arch/mips/configs/msp71xx_defconfig2
-rw-r--r--arch/mips/configs/mtx1_defconfig1
-rw-r--r--arch/mips/configs/pb1100_defconfig1
-rw-r--r--arch/mips/configs/pb1500_defconfig1
-rw-r--r--arch/mips/configs/pb1550_defconfig1
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig4
-rw-r--r--arch/mips/configs/pnx8550-stb810_defconfig4
-rw-r--r--arch/mips/configs/rbtx49xx_defconfig1
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig1
-rw-r--r--arch/mips/configs/yosemite_defconfig2
-rw-r--r--arch/mips/emma2rh/markeins/platform.c1
-rw-r--r--arch/mips/emma2rh/markeins/setup.c1
-rw-r--r--arch/mips/kernel/Makefile2
-rw-r--r--arch/mips/kernel/gdb-low.S394
-rw-r--r--arch/mips/kernel/gdb-stub.c1155
-rw-r--r--arch/mips/kernel/irq.c30
-rw-r--r--arch/mips/kernel/kgdb.c281
-rw-r--r--arch/mips/kernel/traps.c21
-rw-r--r--arch/mips/mm/tlb-r3k.c4
-rw-r--r--arch/mips/mti-malta/Makefile1
-rw-r--r--arch/mips/mti-malta/malta-init.c54
-rw-r--r--arch/mips/mti-malta/malta-kgdb.c133
-rw-r--r--arch/mips/mti-malta/malta-setup.c4
-rw-r--r--arch/mips/nxp/pnx8550/common/Makefile1
-rw-r--r--arch/mips/nxp/pnx8550/common/gdb_hook.c109
-rw-r--r--arch/mips/nxp/pnx8550/common/int.c1
-rw-r--r--arch/mips/nxp/pnx8550/common/proc.c1
-rw-r--r--arch/mips/nxp/pnx8550/common/setup.c12
-rw-r--r--arch/mips/pci/ops-tx3927.c80
-rw-r--r--arch/mips/pci/ops-tx4927.c118
-rw-r--r--arch/mips/pci/pci-tx4927.c10
-rw-r--r--arch/mips/pci/pci-tx4938.c10
-rw-r--r--arch/mips/pci/pci.c6
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_serial.c73
-rw-r--r--arch/mips/pmc-sierra/yosemite/Makefile1
-rw-r--r--arch/mips/pmc-sierra/yosemite/dbg_io.c180
-rw-r--r--arch/mips/pmc-sierra/yosemite/irq.c9
-rw-r--r--arch/mips/rb532/gpio.c5
-rw-r--r--arch/mips/rb532/time.c4
-rw-r--r--arch/mips/sgi-ip22/ip22-setup.c25
-rw-r--r--arch/mips/sgi-ip27/Makefile1
-rw-r--r--arch/mips/sgi-ip27/ip27-dbgio.c60
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c80
-rw-r--r--arch/mips/sibyte/cfe/setup.c14
-rw-r--r--arch/mips/sibyte/sb1250/irq.c60
-rw-r--r--arch/mips/sibyte/swarm/Makefile1
-rw-r--r--arch/mips/sibyte/swarm/dbg_io.c76
-rw-r--r--arch/mips/txx9/Kconfig59
-rw-r--r--arch/mips/txx9/generic/Makefile2
-rw-r--r--arch/mips/txx9/generic/dbgio.c48
-rw-r--r--arch/mips/txx9/generic/irq_tx3927.c25
-rw-r--r--arch/mips/txx9/generic/pci.c36
-rw-r--r--arch/mips/txx9/generic/setup.c124
-rw-r--r--arch/mips/txx9/generic/setup_tx3927.c130
-rw-r--r--arch/mips/txx9/generic/setup_tx4927.c30
-rw-r--r--arch/mips/txx9/generic/setup_tx4938.c41
-rw-r--r--arch/mips/txx9/generic/smsc_fdc37m81x.c20
-rw-r--r--arch/mips/txx9/jmr3927/Makefile1
-rw-r--r--arch/mips/txx9/jmr3927/irq.c65
-rw-r--r--arch/mips/txx9/jmr3927/kgdb_io.c105
-rw-r--r--arch/mips/txx9/jmr3927/prom.c29
-rw-r--r--arch/mips/txx9/jmr3927/setup.c204
-rw-r--r--arch/mips/txx9/rbtx4927/irq.c161
-rw-r--r--arch/mips/txx9/rbtx4927/prom.c1
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c97
-rw-r--r--arch/mips/txx9/rbtx4938/irq.c107
-rw-r--r--arch/mips/txx9/rbtx4938/prom.c1
-rw-r--r--arch/mips/txx9/rbtx4938/setup.c124
-rw-r--r--include/asm-mips/gdb-stub.h215
-rw-r--r--include/asm-mips/kdebug.h14
-rw-r--r--include/asm-mips/kgdb.h44
-rw-r--r--include/asm-mips/pci.h2
-rw-r--r--include/asm-mips/txx9/generic.h14
-rw-r--r--include/asm-mips/txx9/jmr3927.h2
-rw-r--r--include/asm-mips/txx9/pci.h3
-rw-r--r--include/asm-mips/txx9/smsc_fdc37m81x.h2
-rw-r--r--include/asm-mips/txx9/tx3927.h25
-rw-r--r--include/asm-mips/txx9/tx4927.h5
-rw-r--r--include/asm-mips/txx9/tx4927pcic.h8
-rw-r--r--include/asm-mips/txx9/tx4938.h7
-rw-r--r--include/asm-mips/txx9/txx927.h121
-rw-r--r--include/asm-mips/txx9irq.h4
107 files changed, 1509 insertions, 4077 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b4c4eaa5dd2..4da736e2533 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -3,6 +3,7 @@ config MIPS
3 default y 3 default y
4 select HAVE_IDE 4 select HAVE_IDE
5 select HAVE_OPROFILE 5 select HAVE_OPROFILE
6 select HAVE_ARCH_KGDB
6 # Horrible source of confusion. Die, die, die ... 7 # Horrible source of confusion. Die, die, die ...
7 select EMBEDDED 8 select EMBEDDED
8 select RTC_LIB 9 select RTC_LIB
@@ -34,7 +35,6 @@ config BASLER_EXCITE
34 select SYS_HAS_CPU_RM9000 35 select SYS_HAS_CPU_RM9000
35 select SYS_SUPPORTS_32BIT_KERNEL 36 select SYS_SUPPORTS_32BIT_KERNEL
36 select SYS_SUPPORTS_BIG_ENDIAN 37 select SYS_SUPPORTS_BIG_ENDIAN
37 select SYS_SUPPORTS_KGDB
38 help 38 help
39 The eXcite is a smart camera platform manufactured by 39 The eXcite is a smart camera platform manufactured by
40 Basler Vision Technologies AG. 40 Basler Vision Technologies AG.
@@ -280,7 +280,6 @@ config PMC_MSP
280 select SYS_HAS_CPU_MIPS32_R2 280 select SYS_HAS_CPU_MIPS32_R2
281 select SYS_SUPPORTS_32BIT_KERNEL 281 select SYS_SUPPORTS_32BIT_KERNEL
282 select SYS_SUPPORTS_BIG_ENDIAN 282 select SYS_SUPPORTS_BIG_ENDIAN
283 select SYS_SUPPORTS_KGDB
284 select IRQ_CPU 283 select IRQ_CPU
285 select SERIAL_8250 284 select SERIAL_8250
286 select SERIAL_8250_CONSOLE 285 select SERIAL_8250_CONSOLE
@@ -306,7 +305,6 @@ config PMC_YOSEMITE
306 select SYS_SUPPORTS_64BIT_KERNEL 305 select SYS_SUPPORTS_64BIT_KERNEL
307 select SYS_SUPPORTS_BIG_ENDIAN 306 select SYS_SUPPORTS_BIG_ENDIAN
308 select SYS_SUPPORTS_HIGHMEM 307 select SYS_SUPPORTS_HIGHMEM
309 select SYS_SUPPORTS_KGDB
310 select SYS_SUPPORTS_SMP 308 select SYS_SUPPORTS_SMP
311 help 309 help
312 Yosemite is an evaluation board for the RM9000x2 processor 310 Yosemite is an evaluation board for the RM9000x2 processor
@@ -359,7 +357,6 @@ config SGI_IP27
359 select SYS_HAS_CPU_R10000 357 select SYS_HAS_CPU_R10000
360 select SYS_SUPPORTS_64BIT_KERNEL 358 select SYS_SUPPORTS_64BIT_KERNEL
361 select SYS_SUPPORTS_BIG_ENDIAN 359 select SYS_SUPPORTS_BIG_ENDIAN
362 select SYS_SUPPORTS_KGDB
363 select SYS_SUPPORTS_NUMA 360 select SYS_SUPPORTS_NUMA
364 select SYS_SUPPORTS_SMP 361 select SYS_SUPPORTS_SMP
365 select GENERIC_HARDIRQS_NO__DO_IRQ 362 select GENERIC_HARDIRQS_NO__DO_IRQ
@@ -475,7 +472,6 @@ config SIBYTE_SWARM
475 select SYS_HAS_CPU_SB1 472 select SYS_HAS_CPU_SB1
476 select SYS_SUPPORTS_BIG_ENDIAN 473 select SYS_SUPPORTS_BIG_ENDIAN
477 select SYS_SUPPORTS_HIGHMEM 474 select SYS_SUPPORTS_HIGHMEM
478 select SYS_SUPPORTS_KGDB
479 select SYS_SUPPORTS_LITTLE_ENDIAN 475 select SYS_SUPPORTS_LITTLE_ENDIAN
480 select ZONE_DMA32 if 64BIT 476 select ZONE_DMA32 if 64BIT
481 477
@@ -868,7 +864,6 @@ config SOC_PNX8550
868 select SYS_HAS_EARLY_PRINTK 864 select SYS_HAS_EARLY_PRINTK
869 select SYS_SUPPORTS_32BIT_KERNEL 865 select SYS_SUPPORTS_32BIT_KERNEL
870 select GENERIC_HARDIRQS_NO__DO_IRQ 866 select GENERIC_HARDIRQS_NO__DO_IRQ
871 select SYS_SUPPORTS_KGDB
872 select GENERIC_GPIO 867 select GENERIC_GPIO
873 868
874config SWAP_IO_SPACE 869config SWAP_IO_SPACE
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index f18cf92650e..765c8e287d2 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -34,28 +34,6 @@ config SMTC_IDLE_HOOK_DEBUG
34 arch/mips/kernel/smtc.c. This debugging option result in significant 34 arch/mips/kernel/smtc.c. This debugging option result in significant
35 overhead so should be disabled in production kernels. 35 overhead so should be disabled in production kernels.
36 36
37config KGDB
38 bool "Remote GDB kernel debugging"
39 depends on DEBUG_KERNEL && SYS_SUPPORTS_KGDB
40 select DEBUG_INFO
41 help
42 If you say Y here, it will be possible to remotely debug the MIPS
43 kernel using gdb. This enlarges your kernel image disk size by
44 several megabytes and requires a machine with more than 16 MB,
45 better 32 MB RAM to avoid excessive linking time. This is only
46 useful for kernel hackers. If unsure, say N.
47
48config SYS_SUPPORTS_KGDB
49 bool
50
51config GDB_CONSOLE
52 bool "Console output to GDB"
53 depends on KGDB
54 help
55 If you are using GDB for remote debugging over a serial port and
56 would like kernel messages to be formatted into GDB $O packets so
57 that GDB prints them as program output, say 'Y'.
58
59config SB1XXX_CORELIS 37config SB1XXX_CORELIS
60 bool "Corelis Debugger" 38 bool "Corelis Debugger"
61 depends on SIBYTE_SB1xxx_SOC 39 depends on SIBYTE_SB1xxx_SOC
diff --git a/arch/mips/au1000/Kconfig b/arch/mips/au1000/Kconfig
index 1fe97cccead..e4a057d80ab 100644
--- a/arch/mips/au1000/Kconfig
+++ b/arch/mips/au1000/Kconfig
@@ -134,4 +134,3 @@ config SOC_AU1X00
134 select SYS_HAS_CPU_MIPS32_R1 134 select SYS_HAS_CPU_MIPS32_R1
135 select SYS_SUPPORTS_32BIT_KERNEL 135 select SYS_SUPPORTS_32BIT_KERNEL
136 select SYS_SUPPORTS_APM_EMULATION 136 select SYS_SUPPORTS_APM_EMULATION
137 select SYS_SUPPORTS_KGDB
diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/au1000/common/Makefile
index dd0e19dacfc..df48fd65bbf 100644
--- a/arch/mips/au1000/common/Makefile
+++ b/arch/mips/au1000/common/Makefile
@@ -9,7 +9,6 @@ obj-y += prom.o irq.o puts.o time.o reset.o \
9 au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ 9 au1xxx_irqmap.o clocks.o platform.o power.o setup.o \
10 sleeper.o cputable.o dma.o dbdma.o gpio.o 10 sleeper.o cputable.o dma.o dbdma.o gpio.o
11 11
12obj-$(CONFIG_KGDB) += dbg_io.o
13obj-$(CONFIG_PCI) += pci.o 12obj-$(CONFIG_PCI) += pci.o
14 13
15EXTRA_CFLAGS += -Werror 14EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/au1000/common/dbg_io.c b/arch/mips/au1000/common/dbg_io.c
deleted file mode 100644
index af5be7df2f2..00000000000
--- a/arch/mips/au1000/common/dbg_io.c
+++ /dev/null
@@ -1,109 +0,0 @@
1#include <linux/types.h>
2
3#include <asm/mach-au1x00/au1000.h>
4
5#ifdef CONFIG_KGDB
6
7/*
8 * FIXME the user should be able to select the
9 * uart to be used for debugging.
10 */
11#define DEBUG_BASE UART_DEBUG_BASE
12
13#define UART16550_BAUD_2400 2400
14#define UART16550_BAUD_4800 4800
15#define UART16550_BAUD_9600 9600
16#define UART16550_BAUD_19200 19200
17#define UART16550_BAUD_38400 38400
18#define UART16550_BAUD_57600 57600
19#define UART16550_BAUD_115200 115200
20
21#define UART16550_PARITY_NONE 0
22#define UART16550_PARITY_ODD 0x08
23#define UART16550_PARITY_EVEN 0x18
24#define UART16550_PARITY_MARK 0x28
25#define UART16550_PARITY_SPACE 0x38
26
27#define UART16550_DATA_5BIT 0x0
28#define UART16550_DATA_6BIT 0x1
29#define UART16550_DATA_7BIT 0x2
30#define UART16550_DATA_8BIT 0x3
31
32#define UART16550_STOP_1BIT 0x0
33#define UART16550_STOP_2BIT 0x4
34
35
36#define UART_RX 0 /* Receive buffer */
37#define UART_TX 4 /* Transmit buffer */
38#define UART_IER 8 /* Interrupt Enable Register */
39#define UART_IIR 0xC /* Interrupt ID Register */
40#define UART_FCR 0x10 /* FIFO Control Register */
41#define UART_LCR 0x14 /* Line Control Register */
42#define UART_MCR 0x18 /* Modem Control Register */
43#define UART_LSR 0x1C /* Line Status Register */
44#define UART_MSR 0x20 /* Modem Status Register */
45#define UART_CLK 0x28 /* Baud Rat4e Clock Divider */
46#define UART_MOD_CNTRL 0x100 /* Module Control */
47
48/* memory-mapped read/write of the port */
49#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
50#define UART16550_WRITE(y, z) (au_writel(z & 0xff, DEBUG_BASE + y))
51
52extern unsigned long calc_clock(void);
53
54void debugInit(u32 baud, u8 data, u8 parity, u8 stop)
55{
56 if (UART16550_READ(UART_MOD_CNTRL) != 0x3)
57 UART16550_WRITE(UART_MOD_CNTRL, 3);
58 calc_clock();
59
60 /* disable interrupts */
61 UART16550_WRITE(UART_IER, 0);
62
63 /* set up baud rate */
64 {
65 u32 divisor;
66
67 /* set divisor */
68 divisor = get_au1x00_uart_baud_base() / baud;
69 UART16550_WRITE(UART_CLK, divisor & 0xffff);
70 }
71
72 /* set data format */
73 UART16550_WRITE(UART_LCR, (data | parity | stop));
74}
75
76static int remoteDebugInitialized;
77
78u8 getDebugChar(void)
79{
80 if (!remoteDebugInitialized) {
81 remoteDebugInitialized = 1;
82 debugInit(UART16550_BAUD_115200,
83 UART16550_DATA_8BIT,
84 UART16550_PARITY_NONE,
85 UART16550_STOP_1BIT);
86 }
87
88 while ((UART16550_READ(UART_LSR) & 0x1) == 0);
89 return UART16550_READ(UART_RX);
90}
91
92
93int putDebugChar(u8 byte)
94{
95 if (!remoteDebugInitialized) {
96 remoteDebugInitialized = 1;
97 debugInit(UART16550_BAUD_115200,
98 UART16550_DATA_8BIT,
99 UART16550_PARITY_NONE,
100 UART16550_STOP_1BIT);
101 }
102
103 while ((UART16550_READ(UART_LSR) & 0x40) == 0);
104 UART16550_WRITE(UART_TX, byte);
105
106 return 1;
107}
108
109#endif
diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c
index 5ebe0de5e45..84741351496 100644
--- a/arch/mips/au1000/db1x00/init.c
+++ b/arch/mips/au1000/db1x00/init.c
@@ -57,6 +57,6 @@ void __init prom_init(void)
57 if (!memsize_str) 57 if (!memsize_str)
58 memsize = 0x04000000; 58 memsize = 0x04000000;
59 else 59 else
60 memsize = strict_strtol(memsize_str, 0, NULL); 60 strict_strtol(memsize_str, 0, &memsize);
61 add_memory_region(0, memsize, BOOT_MEM_RAM); 61 add_memory_region(0, memsize, BOOT_MEM_RAM);
62} 62}
diff --git a/arch/mips/au1000/mtx-1/init.c b/arch/mips/au1000/mtx-1/init.c
index 33a4aebe0cb..3bae13c2895 100644
--- a/arch/mips/au1000/mtx-1/init.c
+++ b/arch/mips/au1000/mtx-1/init.c
@@ -55,6 +55,6 @@ void __init prom_init(void)
55 if (!memsize_str) 55 if (!memsize_str)
56 memsize = 0x04000000; 56 memsize = 0x04000000;
57 else 57 else
58 memsize = strict_strtol(memsize_str, 0, NULL); 58 strict_strtol(memsize_str, 0, &memsize);
59 add_memory_region(0, memsize, BOOT_MEM_RAM); 59 add_memory_region(0, memsize, BOOT_MEM_RAM);
60} 60}
diff --git a/arch/mips/au1000/pb1000/init.c b/arch/mips/au1000/pb1000/init.c
index 3837365d613..8a9c7d57208 100644
--- a/arch/mips/au1000/pb1000/init.c
+++ b/arch/mips/au1000/pb1000/init.c
@@ -52,6 +52,6 @@ void __init prom_init(void)
52 if (!memsize_str) 52 if (!memsize_str)
53 memsize = 0x04000000; 53 memsize = 0x04000000;
54 else 54 else
55 memsize = strict_strtol(memsize_str, 0, NULL); 55 strict_strtol(memsize_str, 0, &memsize);
56 add_memory_region(0, memsize, BOOT_MEM_RAM); 56 add_memory_region(0, memsize, BOOT_MEM_RAM);
57} 57}
diff --git a/arch/mips/au1000/pb1100/init.c b/arch/mips/au1000/pb1100/init.c
index 8355483f3de..7c6792308bc 100644
--- a/arch/mips/au1000/pb1100/init.c
+++ b/arch/mips/au1000/pb1100/init.c
@@ -54,7 +54,7 @@ void __init prom_init(void)
54 if (!memsize_str) 54 if (!memsize_str)
55 memsize = 0x04000000; 55 memsize = 0x04000000;
56 else 56 else
57 memsize = strict_strtol(memsize_str, 0, NULL); 57 strict_strtol(memsize_str, 0, &memsize);
58 58
59 add_memory_region(0, memsize, BOOT_MEM_RAM); 59 add_memory_region(0, memsize, BOOT_MEM_RAM);
60} 60}
diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/au1000/pb1200/init.c
index 09fd63b8606..e9b2a0fd48a 100644
--- a/arch/mips/au1000/pb1200/init.c
+++ b/arch/mips/au1000/pb1200/init.c
@@ -53,6 +53,6 @@ void __init prom_init(void)
53 if (!memsize_str) 53 if (!memsize_str)
54 memsize = 0x08000000; 54 memsize = 0x08000000;
55 else 55 else
56 memsize = strict_strtol(memsize_str, 0, NULL); 56 strict_strtol(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM); 57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58} 58}
diff --git a/arch/mips/au1000/pb1500/init.c b/arch/mips/au1000/pb1500/init.c
index 49f51e16586..3b6e395cf95 100644
--- a/arch/mips/au1000/pb1500/init.c
+++ b/arch/mips/au1000/pb1500/init.c
@@ -53,6 +53,6 @@ void __init prom_init(void)
53 if (!memsize_str) 53 if (!memsize_str)
54 memsize = 0x04000000; 54 memsize = 0x04000000;
55 else 55 else
56 memsize = strict_strtol(memsize_str, 0, NULL); 56 strict_strtol(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM); 57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58} 58}
diff --git a/arch/mips/au1000/pb1550/init.c b/arch/mips/au1000/pb1550/init.c
index 1b5f58434bb..e1055a13a1a 100644
--- a/arch/mips/au1000/pb1550/init.c
+++ b/arch/mips/au1000/pb1550/init.c
@@ -53,6 +53,6 @@ void __init prom_init(void)
53 if (!memsize_str) 53 if (!memsize_str)
54 memsize = 0x08000000; 54 memsize = 0x08000000;
55 else 55 else
56 memsize = strict_strtol(memsize_str, 0, NULL); 56 strict_strtol(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM); 57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58} 58}
diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/au1000/xxs1500/init.c
index b849bf501c0..7516434760a 100644
--- a/arch/mips/au1000/xxs1500/init.c
+++ b/arch/mips/au1000/xxs1500/init.c
@@ -53,6 +53,6 @@ void __init prom_init(void)
53 if (!memsize_str) 53 if (!memsize_str)
54 memsize = 0x04000000; 54 memsize = 0x04000000;
55 else 55 else
56 memsize = strict_strtol(memsize_str, 0, NULL); 56 strict_strtol(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM); 57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58} 58}
diff --git a/arch/mips/basler/excite/Makefile b/arch/mips/basler/excite/Makefile
index 519142c2e4e..cff29cf46d0 100644
--- a/arch/mips/basler/excite/Makefile
+++ b/arch/mips/basler/excite/Makefile
@@ -5,5 +5,4 @@
5obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \ 5obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \
6 excite_device.o excite_procfs.o 6 excite_device.o excite_procfs.o
7 7
8obj-$(CONFIG_KGDB) += excite_dbg_io.o
9obj-m += excite_iodev.o 8obj-m += excite_iodev.o
diff --git a/arch/mips/basler/excite/excite_dbg_io.c b/arch/mips/basler/excite/excite_dbg_io.c
deleted file mode 100644
index d289e3a868c..00000000000
--- a/arch/mips/basler/excite/excite_dbg_io.c
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/linkage.h>
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <asm/gdb-stub.h>
24#include <asm/rm9k-ocd.h>
25#include <excite.h>
26
27#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1
28#error Debug port used by serial driver
29#endif
30
31#define UART_CLK 25000000
32#define BASE_BAUD (UART_CLK / 16)
33#define REGISTER_BASE_0 0x0208UL
34#define REGISTER_BASE_1 0x0238UL
35
36#define REGISTER_BASE_DBG REGISTER_BASE_1
37
38#define CPRR 0x0004
39#define UACFG 0x0200
40#define UAINTS 0x0204
41#define UARBR (REGISTER_BASE_DBG + 0x0000)
42#define UATHR (REGISTER_BASE_DBG + 0x0004)
43#define UADLL (REGISTER_BASE_DBG + 0x0008)
44#define UAIER (REGISTER_BASE_DBG + 0x000c)
45#define UADLH (REGISTER_BASE_DBG + 0x0010)
46#define UAIIR (REGISTER_BASE_DBG + 0x0014)
47#define UAFCR (REGISTER_BASE_DBG + 0x0018)
48#define UALCR (REGISTER_BASE_DBG + 0x001c)
49#define UAMCR (REGISTER_BASE_DBG + 0x0020)
50#define UALSR (REGISTER_BASE_DBG + 0x0024)
51#define UAMSR (REGISTER_BASE_DBG + 0x0028)
52#define UASCR (REGISTER_BASE_DBG + 0x002c)
53
54#define PARITY_NONE 0
55#define PARITY_ODD 0x08
56#define PARITY_EVEN 0x18
57#define PARITY_MARK 0x28
58#define PARITY_SPACE 0x38
59
60#define DATA_5BIT 0x0
61#define DATA_6BIT 0x1
62#define DATA_7BIT 0x2
63#define DATA_8BIT 0x3
64
65#define STOP_1BIT 0x0
66#define STOP_2BIT 0x4
67
68#define BAUD_DBG 57600
69#define PARITY_DBG PARITY_NONE
70#define DATA_DBG DATA_8BIT
71#define STOP_DBG STOP_1BIT
72
73/* Initialize the serial port for KGDB debugging */
74void __init excite_kgdb_init(void)
75{
76 const u32 divisor = BASE_BAUD / BAUD_DBG;
77
78 /* Take the UART out of reset */
79 titan_writel(0x00ff1cff, CPRR);
80 titan_writel(0x00000000, UACFG);
81 titan_writel(0x00000002, UACFG);
82
83 titan_writel(0x0, UALCR);
84 titan_writel(0x0, UAIER);
85
86 /* Disable FIFOs */
87 titan_writel(0x00, UAFCR);
88
89 titan_writel(0x80, UALCR);
90 titan_writel(divisor & 0xff, UADLL);
91 titan_writel((divisor & 0xff00) >> 8, UADLH);
92 titan_writel(0x0, UALCR);
93
94 titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR);
95
96 /* Enable receiver interrupt */
97 titan_readl(UARBR);
98 titan_writel(0x1, UAIER);
99}
100
101int getDebugChar(void)
102{
103 while (!(titan_readl(UALSR) & 0x1));
104 return titan_readl(UARBR);
105}
106
107int putDebugChar(int data)
108{
109 while (!(titan_readl(UALSR) & 0x20));
110 titan_writel(data, UATHR);
111 return 1;
112}
113
114/* KGDB interrupt handler */
115asmlinkage void excite_kgdb_inthdl(void)
116{
117 if (unlikely(
118 ((titan_readl(UAIIR) & 0x7) == 4)
119 && ((titan_readl(UARBR) & 0xff) == 0x3)))
120 set_async_breakpoint(&regs->cp0_epc);
121}
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
index 4903e067916..934e0a6b101 100644
--- a/arch/mips/basler/excite/excite_irq.c
+++ b/arch/mips/basler/excite/excite_irq.c
@@ -50,10 +50,6 @@ void __init arch_init_irq(void)
50 mips_cpu_irq_init(); 50 mips_cpu_irq_init();
51 rm7k_cpu_irq_init(); 51 rm7k_cpu_irq_init();
52 rm9k_cpu_irq_init(); 52 rm9k_cpu_irq_init();
53
54#ifdef CONFIG_KGDB
55 excite_kgdb_init();
56#endif
57} 53}
58 54
59asmlinkage void plat_irq_dispatch(void) 55asmlinkage void plat_irq_dispatch(void)
@@ -90,9 +86,6 @@ asmlinkage void plat_irq_dispatch(void)
90 msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20)); 86 msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
91 if ((pending & (1 << TITAN_IRQ)) && msgint) { 87 if ((pending & (1 << TITAN_IRQ)) && msgint) {
92 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10)); 88 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
93#if defined(CONFIG_KGDB)
94 excite_kgdb_inthdl();
95#endif
96 do_IRQ(TITAN_IRQ); 89 do_IRQ(TITAN_IRQ);
97 return; 90 return;
98 } 91 }
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
index 6dd8f0d46d0..d66b3b8edf2 100644
--- a/arch/mips/basler/excite/excite_setup.c
+++ b/arch/mips/basler/excite/excite_setup.c
@@ -95,13 +95,13 @@ static int __init excite_init_console(void)
95 /* Take the DUART out of reset */ 95 /* Take the DUART out of reset */
96 titan_writel(0x00ff1cff, CPRR); 96 titan_writel(0x00ff1cff, CPRR);
97 97
98#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1) 98#if (CONFIG_SERIAL_8250_NR_UARTS > 1)
99 /* Enable both ports */ 99 /* Enable both ports */
100 titan_writel(MASK_SER0 | MASK_SER1, UACFG); 100 titan_writel(MASK_SER0 | MASK_SER1, UACFG);
101#else 101#else
102 /* Enable port #0 only */ 102 /* Enable port #0 only */
103 titan_writel(MASK_SER0, UACFG); 103 titan_writel(MASK_SER0, UACFG);
104#endif /* defined(CONFIG_KGDB) */ 104#endif
105 105
106 /* 106 /*
107 * Set up serial port #0. Do not use autodetection; the result is 107 * Set up serial port #0. Do not use autodetection; the result is
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 2678b7ec335..eb44b72254a 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc5 3# Linux kernel version: 2.6.26
4# Thu Sep 6 13:14:29 2007 4# Fri Jul 25 10:25:34 2008
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -10,9 +10,11 @@ CONFIG_MIPS=y
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set 12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set
13CONFIG_MIPS_COBALT=y 14CONFIG_MIPS_COBALT=y
14# CONFIG_MACH_DECSTATION is not set 15# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 16# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set
16# CONFIG_LEMOTE_FULONG is not set 18# CONFIG_LEMOTE_FULONG is not set
17# CONFIG_MIPS_MALTA is not set 19# CONFIG_MIPS_MALTA is not set
18# CONFIG_MIPS_SIM is not set 20# CONFIG_MIPS_SIM is not set
@@ -24,6 +26,7 @@ CONFIG_MIPS_COBALT=y
24# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
25# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
26# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
29# CONFIG_SGI_IP28 is not set
27# CONFIG_SGI_IP32 is not set 30# CONFIG_SGI_IP32 is not set
28# CONFIG_SIBYTE_CRHINE is not set 31# CONFIG_SIBYTE_CRHINE is not set
29# CONFIG_SIBYTE_CARMEL is not set 32# CONFIG_SIBYTE_CARMEL is not set
@@ -34,19 +37,25 @@ CONFIG_MIPS_COBALT=y
34# CONFIG_SIBYTE_SENTOSA is not set 37# CONFIG_SIBYTE_SENTOSA is not set
35# CONFIG_SIBYTE_BIGSUR is not set 38# CONFIG_SIBYTE_BIGSUR is not set
36# CONFIG_SNI_RM is not set 39# CONFIG_SNI_RM is not set
37# CONFIG_TOSHIBA_JMR3927 is not set 40# CONFIG_MACH_TX39XX is not set
38# CONFIG_TOSHIBA_RBTX4927 is not set 41# CONFIG_MACH_TX49XX is not set
39# CONFIG_TOSHIBA_RBTX4938 is not set 42# CONFIG_MIKROTIK_RB532 is not set
40# CONFIG_WR_PPMC is not set 43# CONFIG_WR_PPMC is not set
41CONFIG_RWSEM_GENERIC_SPINLOCK=y 44CONFIG_RWSEM_GENERIC_SPINLOCK=y
42# CONFIG_ARCH_HAS_ILOG2_U32 is not set 45# CONFIG_ARCH_HAS_ILOG2_U32 is not set
43# CONFIG_ARCH_HAS_ILOG2_U64 is not set 46# CONFIG_ARCH_HAS_ILOG2_U64 is not set
47CONFIG_ARCH_SUPPORTS_OPROFILE=y
44CONFIG_GENERIC_FIND_NEXT_BIT=y 48CONFIG_GENERIC_FIND_NEXT_BIT=y
45CONFIG_GENERIC_HWEIGHT=y 49CONFIG_GENERIC_HWEIGHT=y
46CONFIG_GENERIC_CALIBRATE_DELAY=y 50CONFIG_GENERIC_CALIBRATE_DELAY=y
51CONFIG_GENERIC_CLOCKEVENTS=y
47CONFIG_GENERIC_TIME=y 52CONFIG_GENERIC_TIME=y
53CONFIG_GENERIC_CMOS_UPDATE=y
48CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 54CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
49CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 55CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
56CONFIG_CEVT_GT641XX=y
57CONFIG_CEVT_R4K=y
58CONFIG_CSRC_R4K=y
50CONFIG_DMA_NONCOHERENT=y 59CONFIG_DMA_NONCOHERENT=y
51CONFIG_DMA_NEED_PCI_MAP_STATE=y 60CONFIG_DMA_NEED_PCI_MAP_STATE=y
52CONFIG_EARLY_PRINTK=y 61CONFIG_EARLY_PRINTK=y
@@ -108,6 +117,7 @@ CONFIG_CPU_HAS_SYNC=y
108CONFIG_GENERIC_HARDIRQS=y 117CONFIG_GENERIC_HARDIRQS=y
109CONFIG_GENERIC_IRQ_PROBE=y 118CONFIG_GENERIC_IRQ_PROBE=y
110CONFIG_ARCH_FLATMEM_ENABLE=y 119CONFIG_ARCH_FLATMEM_ENABLE=y
120CONFIG_ARCH_POPULATES_NODE_MAP=y
111CONFIG_SELECT_MEMORY_MODEL=y 121CONFIG_SELECT_MEMORY_MODEL=y
112CONFIG_FLATMEM_MANUAL=y 122CONFIG_FLATMEM_MANUAL=y
113# CONFIG_DISCONTIGMEM_MANUAL is not set 123# CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -115,10 +125,16 @@ CONFIG_FLATMEM_MANUAL=y
115CONFIG_FLATMEM=y 125CONFIG_FLATMEM=y
116CONFIG_FLAT_NODE_MEM_MAP=y 126CONFIG_FLAT_NODE_MEM_MAP=y
117# CONFIG_SPARSEMEM_STATIC is not set 127# CONFIG_SPARSEMEM_STATIC is not set
128# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
129CONFIG_PAGEFLAGS_EXTENDED=y
118CONFIG_SPLIT_PTLOCK_CPUS=4 130CONFIG_SPLIT_PTLOCK_CPUS=4
119# CONFIG_RESOURCES_64BIT is not set 131# CONFIG_RESOURCES_64BIT is not set
120CONFIG_ZONE_DMA_FLAG=0 132CONFIG_ZONE_DMA_FLAG=0
121CONFIG_VIRT_TO_BUS=y 133CONFIG_VIRT_TO_BUS=y
134# CONFIG_TICK_ONESHOT is not set
135# CONFIG_NO_HZ is not set
136# CONFIG_HIGH_RES_TIMERS is not set
137CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
122# CONFIG_HZ_48 is not set 138# CONFIG_HZ_48 is not set
123# CONFIG_HZ_100 is not set 139# CONFIG_HZ_100 is not set
124# CONFIG_HZ_128 is not set 140# CONFIG_HZ_128 is not set
@@ -151,23 +167,28 @@ CONFIG_SYSVIPC_SYSCTL=y
151# CONFIG_POSIX_MQUEUE is not set 167# CONFIG_POSIX_MQUEUE is not set
152# CONFIG_BSD_PROCESS_ACCT is not set 168# CONFIG_BSD_PROCESS_ACCT is not set
153# CONFIG_TASKSTATS is not set 169# CONFIG_TASKSTATS is not set
154# CONFIG_USER_NS is not set
155# CONFIG_AUDIT is not set 170# CONFIG_AUDIT is not set
156# CONFIG_IKCONFIG is not set 171# CONFIG_IKCONFIG is not set
157CONFIG_LOG_BUF_SHIFT=14 172CONFIG_LOG_BUF_SHIFT=14
158CONFIG_SYSFS_DEPRECATED=y 173# CONFIG_CGROUPS is not set
174# CONFIG_GROUP_SCHED is not set
175# CONFIG_SYSFS_DEPRECATED_V2 is not set
159CONFIG_RELAY=y 176CONFIG_RELAY=y
177# CONFIG_NAMESPACES is not set
160# CONFIG_BLK_DEV_INITRD is not set 178# CONFIG_BLK_DEV_INITRD is not set
161# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 179# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
162CONFIG_SYSCTL=y 180CONFIG_SYSCTL=y
163CONFIG_EMBEDDED=y 181CONFIG_EMBEDDED=y
164CONFIG_SYSCTL_SYSCALL=y 182CONFIG_SYSCTL_SYSCALL=y
183CONFIG_SYSCTL_SYSCALL_CHECK=y
165CONFIG_KALLSYMS=y 184CONFIG_KALLSYMS=y
166# CONFIG_KALLSYMS_EXTRA_PASS is not set 185# CONFIG_KALLSYMS_EXTRA_PASS is not set
167CONFIG_HOTPLUG=y 186CONFIG_HOTPLUG=y
168CONFIG_PRINTK=y 187CONFIG_PRINTK=y
169CONFIG_BUG=y 188CONFIG_BUG=y
170CONFIG_ELF_CORE=y 189CONFIG_ELF_CORE=y
190CONFIG_PCSPKR_PLATFORM=y
191CONFIG_COMPAT_BRK=y
171CONFIG_BASE_FULL=y 192CONFIG_BASE_FULL=y
172CONFIG_FUTEX=y 193CONFIG_FUTEX=y
173CONFIG_ANON_INODES=y 194CONFIG_ANON_INODES=y
@@ -177,23 +198,37 @@ CONFIG_TIMERFD=y
177CONFIG_EVENTFD=y 198CONFIG_EVENTFD=y
178CONFIG_SHMEM=y 199CONFIG_SHMEM=y
179CONFIG_VM_EVENT_COUNTERS=y 200CONFIG_VM_EVENT_COUNTERS=y
180CONFIG_SLAB=y 201CONFIG_SLUB_DEBUG=y
181# CONFIG_SLUB is not set 202# CONFIG_SLAB is not set
203CONFIG_SLUB=y
182# CONFIG_SLOB is not set 204# CONFIG_SLOB is not set
205# CONFIG_PROFILING is not set
206# CONFIG_MARKERS is not set
207CONFIG_HAVE_OPROFILE=y
208# CONFIG_HAVE_IOREMAP_PROT is not set
209# CONFIG_HAVE_KPROBES is not set
210# CONFIG_HAVE_KRETPROBES is not set
211# CONFIG_HAVE_DMA_ATTRS is not set
212# CONFIG_USE_GENERIC_SMP_HELPERS is not set
213# CONFIG_HAVE_CLK is not set
214CONFIG_PROC_PAGE_MONITOR=y
215CONFIG_SLABINFO=y
183CONFIG_RT_MUTEXES=y 216CONFIG_RT_MUTEXES=y
184# CONFIG_TINY_SHMEM is not set 217# CONFIG_TINY_SHMEM is not set
185CONFIG_BASE_SMALL=0 218CONFIG_BASE_SMALL=0
186CONFIG_MODULES=y 219CONFIG_MODULES=y
220# CONFIG_MODULE_FORCE_LOAD is not set
187CONFIG_MODULE_UNLOAD=y 221CONFIG_MODULE_UNLOAD=y
188# CONFIG_MODULE_FORCE_UNLOAD is not set 222# CONFIG_MODULE_FORCE_UNLOAD is not set
189# CONFIG_MODVERSIONS is not set 223# CONFIG_MODVERSIONS is not set
190# CONFIG_MODULE_SRCVERSION_ALL is not set 224# CONFIG_MODULE_SRCVERSION_ALL is not set
191# CONFIG_KMOD is not set 225CONFIG_KMOD=y
192CONFIG_BLOCK=y 226CONFIG_BLOCK=y
193# CONFIG_LBD is not set 227# CONFIG_LBD is not set
194# CONFIG_BLK_DEV_IO_TRACE is not set 228# CONFIG_BLK_DEV_IO_TRACE is not set
195# CONFIG_LSF is not set 229# CONFIG_LSF is not set
196# CONFIG_BLK_DEV_BSG is not set 230# CONFIG_BLK_DEV_BSG is not set
231# CONFIG_BLK_DEV_INTEGRITY is not set
197 232
198# 233#
199# IO Schedulers 234# IO Schedulers
@@ -207,18 +242,18 @@ CONFIG_DEFAULT_AS=y
207# CONFIG_DEFAULT_CFQ is not set 242# CONFIG_DEFAULT_CFQ is not set
208# CONFIG_DEFAULT_NOOP is not set 243# CONFIG_DEFAULT_NOOP is not set
209CONFIG_DEFAULT_IOSCHED="anticipatory" 244CONFIG_DEFAULT_IOSCHED="anticipatory"
245CONFIG_CLASSIC_RCU=y
210 246
211# 247#
212# Bus options (PCI, PCMCIA, EISA, ISA, TC) 248# Bus options (PCI, PCMCIA, EISA, ISA, TC)
213# 249#
214CONFIG_HW_HAS_PCI=y 250CONFIG_HW_HAS_PCI=y
215CONFIG_PCI=y 251CONFIG_PCI=y
252CONFIG_PCI_DOMAINS=y
216# CONFIG_ARCH_SUPPORTS_MSI is not set 253# CONFIG_ARCH_SUPPORTS_MSI is not set
254CONFIG_PCI_LEGACY=y
217CONFIG_MMU=y 255CONFIG_MMU=y
218 256CONFIG_I8253=y
219#
220# PCCARD (PCMCIA/CardBus) support
221#
222# CONFIG_PCCARD is not set 257# CONFIG_PCCARD is not set
223# CONFIG_HOTPLUG_PCI is not set 258# CONFIG_HOTPLUG_PCI is not set
224 259
@@ -232,8 +267,8 @@ CONFIG_TRAD_SIGNALS=y
232# 267#
233# Power management options 268# Power management options
234# 269#
270CONFIG_ARCH_SUSPEND_POSSIBLE=y
235# CONFIG_PM is not set 271# CONFIG_PM is not set
236CONFIG_SUSPEND_UP_POSSIBLE=y
237 272
238# 273#
239# Networking 274# Networking
@@ -250,6 +285,7 @@ CONFIG_XFRM=y
250CONFIG_XFRM_USER=y 285CONFIG_XFRM_USER=y
251# CONFIG_XFRM_SUB_POLICY is not set 286# CONFIG_XFRM_SUB_POLICY is not set
252CONFIG_XFRM_MIGRATE=y 287CONFIG_XFRM_MIGRATE=y
288# CONFIG_XFRM_STATISTICS is not set
253CONFIG_NET_KEY=y 289CONFIG_NET_KEY=y
254CONFIG_NET_KEY_MIGRATE=y 290CONFIG_NET_KEY_MIGRATE=y
255CONFIG_INET=y 291CONFIG_INET=y
@@ -269,6 +305,7 @@ CONFIG_IP_FIB_HASH=y
269CONFIG_INET_XFRM_MODE_TRANSPORT=y 305CONFIG_INET_XFRM_MODE_TRANSPORT=y
270CONFIG_INET_XFRM_MODE_TUNNEL=y 306CONFIG_INET_XFRM_MODE_TUNNEL=y
271CONFIG_INET_XFRM_MODE_BEET=y 307CONFIG_INET_XFRM_MODE_BEET=y
308# CONFIG_INET_LRO is not set
272CONFIG_INET_DIAG=y 309CONFIG_INET_DIAG=y
273CONFIG_INET_TCP_DIAG=y 310CONFIG_INET_TCP_DIAG=y
274# CONFIG_TCP_CONG_ADVANCED is not set 311# CONFIG_TCP_CONG_ADVANCED is not set
@@ -276,8 +313,6 @@ CONFIG_TCP_CONG_CUBIC=y
276CONFIG_DEFAULT_TCP_CONG="cubic" 313CONFIG_DEFAULT_TCP_CONG="cubic"
277# CONFIG_TCP_MD5SIG is not set 314# CONFIG_TCP_MD5SIG is not set
278# CONFIG_IPV6 is not set 315# CONFIG_IPV6 is not set
279# CONFIG_INET6_XFRM_TUNNEL is not set
280# CONFIG_INET6_TUNNEL is not set
281# CONFIG_NETWORK_SECMARK is not set 316# CONFIG_NETWORK_SECMARK is not set
282# CONFIG_NETFILTER is not set 317# CONFIG_NETFILTER is not set
283# CONFIG_IP_DCCP is not set 318# CONFIG_IP_DCCP is not set
@@ -294,10 +329,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
294# CONFIG_LAPB is not set 329# CONFIG_LAPB is not set
295# CONFIG_ECONET is not set 330# CONFIG_ECONET is not set
296# CONFIG_WAN_ROUTER is not set 331# CONFIG_WAN_ROUTER is not set
297
298#
299# QoS and/or fair queueing
300#
301# CONFIG_NET_SCHED is not set 332# CONFIG_NET_SCHED is not set
302 333
303# 334#
@@ -305,6 +336,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
305# 336#
306# CONFIG_NET_PKTGEN is not set 337# CONFIG_NET_PKTGEN is not set
307# CONFIG_HAMRADIO is not set 338# CONFIG_HAMRADIO is not set
339# CONFIG_CAN is not set
308# CONFIG_IRDA is not set 340# CONFIG_IRDA is not set
309# CONFIG_BT is not set 341# CONFIG_BT is not set
310# CONFIG_AF_RXRPC is not set 342# CONFIG_AF_RXRPC is not set
@@ -326,9 +358,12 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
326# 358#
327# Generic Driver Options 359# Generic Driver Options
328# 360#
361CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
329CONFIG_STANDALONE=y 362CONFIG_STANDALONE=y
330CONFIG_PREVENT_FIRMWARE_BUILD=y 363CONFIG_PREVENT_FIRMWARE_BUILD=y
331CONFIG_FW_LOADER=y 364CONFIG_FW_LOADER=y
365CONFIG_FIRMWARE_IN_KERNEL=y
366CONFIG_EXTRA_FIRMWARE=""
332# CONFIG_SYS_HYPERVISOR is not set 367# CONFIG_SYS_HYPERVISOR is not set
333# CONFIG_CONNECTOR is not set 368# CONFIG_CONNECTOR is not set
334CONFIG_MTD=y 369CONFIG_MTD=y
@@ -337,6 +372,7 @@ CONFIG_MTD=y
337CONFIG_MTD_PARTITIONS=y 372CONFIG_MTD_PARTITIONS=y
338# CONFIG_MTD_REDBOOT_PARTS is not set 373# CONFIG_MTD_REDBOOT_PARTS is not set
339# CONFIG_MTD_CMDLINE_PARTS is not set 374# CONFIG_MTD_CMDLINE_PARTS is not set
375# CONFIG_MTD_AR7_PARTS is not set
340 376
341# 377#
342# User Modules And Translation Layers 378# User Modules And Translation Layers
@@ -350,6 +386,7 @@ CONFIG_MTD_BLKDEVS=y
350# CONFIG_INFTL is not set 386# CONFIG_INFTL is not set
351# CONFIG_RFD_FTL is not set 387# CONFIG_RFD_FTL is not set
352# CONFIG_SSFDC is not set 388# CONFIG_SSFDC is not set
389# CONFIG_MTD_OOPS is not set
353 390
354# 391#
355# RAM/ROM/Flash chip drivers 392# RAM/ROM/Flash chip drivers
@@ -384,6 +421,7 @@ CONFIG_MTD_PHYSMAP=y
384CONFIG_MTD_PHYSMAP_START=0x0 421CONFIG_MTD_PHYSMAP_START=0x0
385CONFIG_MTD_PHYSMAP_LEN=0x0 422CONFIG_MTD_PHYSMAP_LEN=0x0
386CONFIG_MTD_PHYSMAP_BANKWIDTH=0 423CONFIG_MTD_PHYSMAP_BANKWIDTH=0
424# CONFIG_MTD_INTEL_VR_NOR is not set
387# CONFIG_MTD_PLATRAM is not set 425# CONFIG_MTD_PLATRAM is not set
388 426
389# 427#
@@ -423,7 +461,9 @@ CONFIG_BLK_DEV_LOOP=y
423# CONFIG_BLK_DEV_RAM is not set 461# CONFIG_BLK_DEV_RAM is not set
424# CONFIG_CDROM_PKTCDVD is not set 462# CONFIG_CDROM_PKTCDVD is not set
425# CONFIG_ATA_OVER_ETH is not set 463# CONFIG_ATA_OVER_ETH is not set
464# CONFIG_BLK_DEV_HD is not set
426# CONFIG_MISC_DEVICES is not set 465# CONFIG_MISC_DEVICES is not set
466CONFIG_HAVE_IDE=y
427# CONFIG_IDE is not set 467# CONFIG_IDE is not set
428 468
429# 469#
@@ -462,10 +502,15 @@ CONFIG_SCSI_WAIT_SCAN=m
462# CONFIG_SCSI_FC_ATTRS is not set 502# CONFIG_SCSI_FC_ATTRS is not set
463# CONFIG_SCSI_ISCSI_ATTRS is not set 503# CONFIG_SCSI_ISCSI_ATTRS is not set
464# CONFIG_SCSI_SAS_LIBSAS is not set 504# CONFIG_SCSI_SAS_LIBSAS is not set
505# CONFIG_SCSI_SRP_ATTRS is not set
465# CONFIG_SCSI_LOWLEVEL is not set 506# CONFIG_SCSI_LOWLEVEL is not set
507# CONFIG_SCSI_DH is not set
466CONFIG_ATA=y 508CONFIG_ATA=y
467# CONFIG_ATA_NONSTANDARD is not set 509# CONFIG_ATA_NONSTANDARD is not set
510CONFIG_SATA_PMP=y
468# CONFIG_SATA_AHCI is not set 511# CONFIG_SATA_AHCI is not set
512# CONFIG_SATA_SIL24 is not set
513CONFIG_ATA_SFF=y
469# CONFIG_SATA_SVW is not set 514# CONFIG_SATA_SVW is not set
470# CONFIG_ATA_PIIX is not set 515# CONFIG_ATA_PIIX is not set
471# CONFIG_SATA_MV is not set 516# CONFIG_SATA_MV is not set
@@ -475,7 +520,6 @@ CONFIG_ATA=y
475# CONFIG_SATA_PROMISE is not set 520# CONFIG_SATA_PROMISE is not set
476# CONFIG_SATA_SX4 is not set 521# CONFIG_SATA_SX4 is not set
477# CONFIG_SATA_SIL is not set 522# CONFIG_SATA_SIL is not set
478# CONFIG_SATA_SIL24 is not set
479# CONFIG_SATA_SIS is not set 523# CONFIG_SATA_SIS is not set
480# CONFIG_SATA_ULI is not set 524# CONFIG_SATA_ULI is not set
481# CONFIG_SATA_VIA is not set 525# CONFIG_SATA_VIA is not set
@@ -504,7 +548,9 @@ CONFIG_ATA=y
504# CONFIG_PATA_MPIIX is not set 548# CONFIG_PATA_MPIIX is not set
505# CONFIG_PATA_OLDPIIX is not set 549# CONFIG_PATA_OLDPIIX is not set
506# CONFIG_PATA_NETCELL is not set 550# CONFIG_PATA_NETCELL is not set
551# CONFIG_PATA_NINJA32 is not set
507# CONFIG_PATA_NS87410 is not set 552# CONFIG_PATA_NS87410 is not set
553# CONFIG_PATA_NS87415 is not set
508# CONFIG_PATA_OPTI is not set 554# CONFIG_PATA_OPTI is not set
509# CONFIG_PATA_OPTIDMA is not set 555# CONFIG_PATA_OPTIDMA is not set
510# CONFIG_PATA_PDC_OLD is not set 556# CONFIG_PATA_PDC_OLD is not set
@@ -518,29 +564,27 @@ CONFIG_ATA=y
518CONFIG_PATA_VIA=y 564CONFIG_PATA_VIA=y
519# CONFIG_PATA_WINBOND is not set 565# CONFIG_PATA_WINBOND is not set
520# CONFIG_PATA_PLATFORM is not set 566# CONFIG_PATA_PLATFORM is not set
567# CONFIG_PATA_SCH is not set
521# CONFIG_MD is not set 568# CONFIG_MD is not set
569# CONFIG_FUSION is not set
522 570
523# 571#
524# Fusion MPT device support 572# IEEE 1394 (FireWire) support
525# 573#
526# CONFIG_FUSION is not set
527# CONFIG_FUSION_SPI is not set
528# CONFIG_FUSION_FC is not set
529# CONFIG_FUSION_SAS is not set
530 574
531# 575#
532# IEEE 1394 (FireWire) support 576# Enable only one of the two stacks, unless you know what you are doing
533# 577#
534# CONFIG_FIREWIRE is not set 578# CONFIG_FIREWIRE is not set
535# CONFIG_IEEE1394 is not set 579# CONFIG_IEEE1394 is not set
536# CONFIG_I2O is not set 580# CONFIG_I2O is not set
537CONFIG_NETDEVICES=y 581CONFIG_NETDEVICES=y
538# CONFIG_NETDEVICES_MULTIQUEUE is not set
539# CONFIG_DUMMY is not set 582# CONFIG_DUMMY is not set
540# CONFIG_BONDING is not set 583# CONFIG_BONDING is not set
541# CONFIG_MACVLAN is not set 584# CONFIG_MACVLAN is not set
542# CONFIG_EQUALIZER is not set 585# CONFIG_EQUALIZER is not set
543# CONFIG_TUN is not set 586# CONFIG_TUN is not set
587# CONFIG_VETH is not set
544# CONFIG_ARCNET is not set 588# CONFIG_ARCNET is not set
545# CONFIG_PHYLIB is not set 589# CONFIG_PHYLIB is not set
546CONFIG_NET_ETHERNET=y 590CONFIG_NET_ETHERNET=y
@@ -562,7 +606,12 @@ CONFIG_TULIP=y
562# CONFIG_DM9102 is not set 606# CONFIG_DM9102 is not set
563# CONFIG_ULI526X is not set 607# CONFIG_ULI526X is not set
564# CONFIG_HP100 is not set 608# CONFIG_HP100 is not set
609# CONFIG_IBM_NEW_EMAC_ZMII is not set
610# CONFIG_IBM_NEW_EMAC_RGMII is not set
611# CONFIG_IBM_NEW_EMAC_TAH is not set
612# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
565# CONFIG_NET_PCI is not set 613# CONFIG_NET_PCI is not set
614# CONFIG_B44 is not set
566# CONFIG_NETDEV_1000 is not set 615# CONFIG_NETDEV_1000 is not set
567# CONFIG_NETDEV_10000 is not set 616# CONFIG_NETDEV_10000 is not set
568# CONFIG_TR is not set 617# CONFIG_TR is not set
@@ -572,6 +621,7 @@ CONFIG_TULIP=y
572# 621#
573# CONFIG_WLAN_PRE80211 is not set 622# CONFIG_WLAN_PRE80211 is not set
574# CONFIG_WLAN_80211 is not set 623# CONFIG_WLAN_80211 is not set
624# CONFIG_IWLWIFI_LEDS is not set
575 625
576# 626#
577# USB Network Adapters 627# USB Network Adapters
@@ -580,7 +630,6 @@ CONFIG_TULIP=y
580# CONFIG_USB_KAWETH is not set 630# CONFIG_USB_KAWETH is not set
581# CONFIG_USB_PEGASUS is not set 631# CONFIG_USB_PEGASUS is not set
582# CONFIG_USB_RTL8150 is not set 632# CONFIG_USB_RTL8150 is not set
583# CONFIG_USB_USBNET_MII is not set
584# CONFIG_USB_USBNET is not set 633# CONFIG_USB_USBNET is not set
585# CONFIG_WAN is not set 634# CONFIG_WAN is not set
586# CONFIG_FDDI is not set 635# CONFIG_FDDI is not set
@@ -588,7 +637,6 @@ CONFIG_TULIP=y
588# CONFIG_PPP is not set 637# CONFIG_PPP is not set
589# CONFIG_SLIP is not set 638# CONFIG_SLIP is not set
590# CONFIG_NET_FC is not set 639# CONFIG_NET_FC is not set
591# CONFIG_SHAPER is not set
592# CONFIG_NETCONSOLE is not set 640# CONFIG_NETCONSOLE is not set
593# CONFIG_NETPOLL is not set 641# CONFIG_NETPOLL is not set
594# CONFIG_NET_POLL_CONTROLLER is not set 642# CONFIG_NET_POLL_CONTROLLER is not set
@@ -607,7 +655,6 @@ CONFIG_INPUT_POLLDEV=y
607# 655#
608# CONFIG_INPUT_MOUSEDEV is not set 656# CONFIG_INPUT_MOUSEDEV is not set
609# CONFIG_INPUT_JOYDEV is not set 657# CONFIG_INPUT_JOYDEV is not set
610# CONFIG_INPUT_TSDEV is not set
611CONFIG_INPUT_EVDEV=y 658CONFIG_INPUT_EVDEV=y
612# CONFIG_INPUT_EVBUG is not set 659# CONFIG_INPUT_EVBUG is not set
613 660
@@ -642,7 +689,9 @@ CONFIG_VT=y
642CONFIG_VT_CONSOLE=y 689CONFIG_VT_CONSOLE=y
643CONFIG_HW_CONSOLE=y 690CONFIG_HW_CONSOLE=y
644CONFIG_VT_HW_CONSOLE_BINDING=y 691CONFIG_VT_HW_CONSOLE_BINDING=y
692CONFIG_DEVKMEM=y
645# CONFIG_SERIAL_NONSTANDARD is not set 693# CONFIG_SERIAL_NONSTANDARD is not set
694# CONFIG_NOZOMI is not set
646 695
647# 696#
648# Serial drivers 697# Serial drivers
@@ -664,65 +713,122 @@ CONFIG_UNIX98_PTYS=y
664CONFIG_LEGACY_PTYS=y 713CONFIG_LEGACY_PTYS=y
665CONFIG_LEGACY_PTY_COUNT=256 714CONFIG_LEGACY_PTY_COUNT=256
666# CONFIG_IPMI_HANDLER is not set 715# CONFIG_IPMI_HANDLER is not set
667# CONFIG_WATCHDOG is not set
668# CONFIG_HW_RANDOM is not set 716# CONFIG_HW_RANDOM is not set
669# CONFIG_RTC is not set
670CONFIG_COBALT_LCD=y
671# CONFIG_R3964 is not set 717# CONFIG_R3964 is not set
672# CONFIG_APPLICOM is not set 718# CONFIG_APPLICOM is not set
673# CONFIG_DRM is not set
674# CONFIG_RAW_DRIVER is not set 719# CONFIG_RAW_DRIVER is not set
675# CONFIG_TCG_TPM is not set 720# CONFIG_TCG_TPM is not set
676CONFIG_DEVPORT=y 721CONFIG_DEVPORT=y
677# CONFIG_I2C is not set 722# CONFIG_I2C is not set
678
679#
680# SPI support
681#
682# CONFIG_SPI is not set 723# CONFIG_SPI is not set
683# CONFIG_SPI_MASTER is not set
684# CONFIG_W1 is not set 724# CONFIG_W1 is not set
685# CONFIG_POWER_SUPPLY is not set 725# CONFIG_POWER_SUPPLY is not set
686# CONFIG_HWMON is not set 726# CONFIG_HWMON is not set
727# CONFIG_THERMAL is not set
728# CONFIG_THERMAL_HWMON is not set
729# CONFIG_WATCHDOG is not set
730
731#
732# Sonics Silicon Backplane
733#
734CONFIG_SSB_POSSIBLE=y
735# CONFIG_SSB is not set
687 736
688# 737#
689# Multifunction device drivers 738# Multifunction device drivers
690# 739#
740# CONFIG_MFD_CORE is not set
691# CONFIG_MFD_SM501 is not set 741# CONFIG_MFD_SM501 is not set
742# CONFIG_HTC_PASIC3 is not set
692 743
693# 744#
694# Multimedia devices 745# Multimedia devices
695# 746#
747
748#
749# Multimedia core support
750#
696# CONFIG_VIDEO_DEV is not set 751# CONFIG_VIDEO_DEV is not set
697# CONFIG_DVB_CORE is not set 752# CONFIG_DVB_CORE is not set
753# CONFIG_VIDEO_MEDIA is not set
754
755#
756# Multimedia drivers
757#
698# CONFIG_DAB is not set 758# CONFIG_DAB is not set
699 759
700# 760#
701# Graphics support 761# Graphics support
702# 762#
763# CONFIG_DRM is not set
764# CONFIG_VGASTATE is not set
765# CONFIG_VIDEO_OUTPUT_CONTROL is not set
766CONFIG_FB=y
767# CONFIG_FIRMWARE_EDID is not set
768# CONFIG_FB_DDC is not set
769# CONFIG_FB_CFB_FILLRECT is not set
770# CONFIG_FB_CFB_COPYAREA is not set
771# CONFIG_FB_CFB_IMAGEBLIT is not set
772# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
773# CONFIG_FB_SYS_FILLRECT is not set
774# CONFIG_FB_SYS_COPYAREA is not set
775# CONFIG_FB_SYS_IMAGEBLIT is not set
776# CONFIG_FB_FOREIGN_ENDIAN is not set
777# CONFIG_FB_SYS_FOPS is not set
778# CONFIG_FB_SVGALIB is not set
779# CONFIG_FB_MACMODES is not set
780# CONFIG_FB_BACKLIGHT is not set
781# CONFIG_FB_MODE_HELPERS is not set
782# CONFIG_FB_TILEBLITTING is not set
783
784#
785# Frame buffer hardware drivers
786#
787# CONFIG_FB_CIRRUS is not set
788# CONFIG_FB_PM2 is not set
789# CONFIG_FB_CYBER2000 is not set
790# CONFIG_FB_ASILIANT is not set
791# CONFIG_FB_IMSTT is not set
792# CONFIG_FB_S1D13XXX is not set
793# CONFIG_FB_NVIDIA is not set
794# CONFIG_FB_RIVA is not set
795# CONFIG_FB_MATROX is not set
796# CONFIG_FB_RADEON is not set
797# CONFIG_FB_ATY128 is not set
798# CONFIG_FB_ATY is not set
799# CONFIG_FB_S3 is not set
800# CONFIG_FB_SAVAGE is not set
801# CONFIG_FB_SIS is not set
802# CONFIG_FB_NEOMAGIC is not set
803# CONFIG_FB_KYRO is not set
804# CONFIG_FB_3DFX is not set
805# CONFIG_FB_VOODOO1 is not set
806# CONFIG_FB_VT8623 is not set
807# CONFIG_FB_TRIDENT is not set
808# CONFIG_FB_ARK is not set
809# CONFIG_FB_PM3 is not set
810# CONFIG_FB_CARMINE is not set
811CONFIG_FB_COBALT=y
812# CONFIG_FB_VIRTUAL is not set
703# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 813# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
704 814
705# 815#
706# Display device support 816# Display device support
707# 817#
708# CONFIG_DISPLAY_SUPPORT is not set 818# CONFIG_DISPLAY_SUPPORT is not set
709# CONFIG_VGASTATE is not set
710# CONFIG_VIDEO_OUTPUT_CONTROL is not set
711# CONFIG_FB is not set
712 819
713# 820#
714# Console display driver support 821# Console display driver support
715# 822#
716# CONFIG_VGA_CONSOLE is not set 823# CONFIG_VGA_CONSOLE is not set
717CONFIG_DUMMY_CONSOLE=y 824CONFIG_DUMMY_CONSOLE=y
718 825# CONFIG_FRAMEBUFFER_CONSOLE is not set
719# 826# CONFIG_LOGO is not set
720# Sound
721#
722# CONFIG_SOUND is not set 827# CONFIG_SOUND is not set
723CONFIG_HID_SUPPORT=y 828CONFIG_HID_SUPPORT=y
724CONFIG_HID=m 829CONFIG_HID=m
725# CONFIG_HID_DEBUG is not set 830# CONFIG_HID_DEBUG is not set
831# CONFIG_HIDRAW is not set
726 832
727# 833#
728# USB Input Devices 834# USB Input Devices
@@ -743,6 +849,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y
743CONFIG_USB_ARCH_HAS_EHCI=y 849CONFIG_USB_ARCH_HAS_EHCI=y
744CONFIG_USB=m 850CONFIG_USB=m
745# CONFIG_USB_DEBUG is not set 851# CONFIG_USB_DEBUG is not set
852# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
746 853
747# 854#
748# Miscellaneous USB options 855# Miscellaneous USB options
@@ -751,15 +858,18 @@ CONFIG_USB=m
751# CONFIG_USB_DEVICE_CLASS is not set 858# CONFIG_USB_DEVICE_CLASS is not set
752# CONFIG_USB_DYNAMIC_MINORS is not set 859# CONFIG_USB_DYNAMIC_MINORS is not set
753# CONFIG_USB_OTG is not set 860# CONFIG_USB_OTG is not set
861# CONFIG_USB_OTG_WHITELIST is not set
862# CONFIG_USB_OTG_BLACKLIST_HUB is not set
754 863
755# 864#
756# USB Host Controller Drivers 865# USB Host Controller Drivers
757# 866#
867# CONFIG_USB_C67X00_HCD is not set
758CONFIG_USB_EHCI_HCD=m 868CONFIG_USB_EHCI_HCD=m
759# CONFIG_USB_EHCI_SPLIT_ISO is not set
760# CONFIG_USB_EHCI_ROOT_HUB_TT is not set 869# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
761# CONFIG_USB_EHCI_TT_NEWSCHED is not set 870# CONFIG_USB_EHCI_TT_NEWSCHED is not set
762# CONFIG_USB_ISP116X_HCD is not set 871# CONFIG_USB_ISP116X_HCD is not set
872# CONFIG_USB_ISP1760_HCD is not set
763CONFIG_USB_OHCI_HCD=m 873CONFIG_USB_OHCI_HCD=m
764# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set 874# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
765# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set 875# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -773,6 +883,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
773# 883#
774# CONFIG_USB_ACM is not set 884# CONFIG_USB_ACM is not set
775# CONFIG_USB_PRINTER is not set 885# CONFIG_USB_PRINTER is not set
886# CONFIG_USB_WDM is not set
776 887
777# 888#
778# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 889# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -785,6 +896,7 @@ CONFIG_USB_STORAGE=m
785# CONFIG_USB_STORAGE_DEBUG is not set 896# CONFIG_USB_STORAGE_DEBUG is not set
786# CONFIG_USB_STORAGE_DATAFAB is not set 897# CONFIG_USB_STORAGE_DATAFAB is not set
787# CONFIG_USB_STORAGE_FREECOM is not set 898# CONFIG_USB_STORAGE_FREECOM is not set
899# CONFIG_USB_STORAGE_ISD200 is not set
788# CONFIG_USB_STORAGE_DPCM is not set 900# CONFIG_USB_STORAGE_DPCM is not set
789# CONFIG_USB_STORAGE_USBAT is not set 901# CONFIG_USB_STORAGE_USBAT is not set
790# CONFIG_USB_STORAGE_SDDR09 is not set 902# CONFIG_USB_STORAGE_SDDR09 is not set
@@ -793,6 +905,7 @@ CONFIG_USB_STORAGE=m
793# CONFIG_USB_STORAGE_ALAUDA is not set 905# CONFIG_USB_STORAGE_ALAUDA is not set
794# CONFIG_USB_STORAGE_ONETOUCH is not set 906# CONFIG_USB_STORAGE_ONETOUCH is not set
795# CONFIG_USB_STORAGE_KARMA is not set 907# CONFIG_USB_STORAGE_KARMA is not set
908# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
796# CONFIG_USB_LIBUSUAL is not set 909# CONFIG_USB_LIBUSUAL is not set
797 910
798# 911#
@@ -800,15 +913,11 @@ CONFIG_USB_STORAGE=m
800# 913#
801# CONFIG_USB_MDC800 is not set 914# CONFIG_USB_MDC800 is not set
802# CONFIG_USB_MICROTEK is not set 915# CONFIG_USB_MICROTEK is not set
803CONFIG_USB_MON=y 916# CONFIG_USB_MON is not set
804 917
805# 918#
806# USB port drivers 919# USB port drivers
807# 920#
808
809#
810# USB Serial Converter support
811#
812# CONFIG_USB_SERIAL is not set 921# CONFIG_USB_SERIAL is not set
813 922
814# 923#
@@ -833,16 +942,10 @@ CONFIG_USB_MON=y
833# CONFIG_USB_LD is not set 942# CONFIG_USB_LD is not set
834# CONFIG_USB_TRANCEVIBRATOR is not set 943# CONFIG_USB_TRANCEVIBRATOR is not set
835# CONFIG_USB_IOWARRIOR is not set 944# CONFIG_USB_IOWARRIOR is not set
836 945# CONFIG_USB_ISIGHTFW is not set
837#
838# USB DSL modem support
839#
840
841#
842# USB Gadget Support
843#
844# CONFIG_USB_GADGET is not set 946# CONFIG_USB_GADGET is not set
845# CONFIG_MMC is not set 947# CONFIG_MMC is not set
948# CONFIG_MEMSTICK is not set
846CONFIG_NEW_LEDS=y 949CONFIG_NEW_LEDS=y
847CONFIG_LEDS_CLASS=y 950CONFIG_LEDS_CLASS=y
848 951
@@ -858,6 +961,8 @@ CONFIG_LEDS_COBALT_RAQ=y
858CONFIG_LEDS_TRIGGERS=y 961CONFIG_LEDS_TRIGGERS=y
859# CONFIG_LEDS_TRIGGER_TIMER is not set 962# CONFIG_LEDS_TRIGGER_TIMER is not set
860# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set 963# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
964# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
965# CONFIG_ACCESSIBILITY is not set
861# CONFIG_INFINIBAND is not set 966# CONFIG_INFINIBAND is not set
862CONFIG_RTC_LIB=y 967CONFIG_RTC_LIB=y
863CONFIG_RTC_CLASS=y 968CONFIG_RTC_CLASS=y
@@ -882,9 +987,10 @@ CONFIG_RTC_INTF_DEV=y
882# Platform RTC drivers 987# Platform RTC drivers
883# 988#
884CONFIG_RTC_DRV_CMOS=y 989CONFIG_RTC_DRV_CMOS=y
990# CONFIG_RTC_DRV_DS1511 is not set
885# CONFIG_RTC_DRV_DS1553 is not set 991# CONFIG_RTC_DRV_DS1553 is not set
886# CONFIG_RTC_DRV_STK17TA8 is not set
887# CONFIG_RTC_DRV_DS1742 is not set 992# CONFIG_RTC_DRV_DS1742 is not set
993# CONFIG_RTC_DRV_STK17TA8 is not set
888# CONFIG_RTC_DRV_M48T86 is not set 994# CONFIG_RTC_DRV_M48T86 is not set
889# CONFIG_RTC_DRV_M48T59 is not set 995# CONFIG_RTC_DRV_M48T59 is not set
890# CONFIG_RTC_DRV_V3020 is not set 996# CONFIG_RTC_DRV_V3020 is not set
@@ -892,23 +998,7 @@ CONFIG_RTC_DRV_CMOS=y
892# 998#
893# on-CPU RTC drivers 999# on-CPU RTC drivers
894# 1000#
895 1001# CONFIG_DMADEVICES is not set
896#
897# DMA Engine support
898#
899# CONFIG_DMA_ENGINE is not set
900
901#
902# DMA Clients
903#
904
905#
906# DMA Devices
907#
908
909#
910# Userspace I/O
911#
912# CONFIG_UIO is not set 1002# CONFIG_UIO is not set
913 1003
914# 1004#
@@ -923,22 +1013,22 @@ CONFIG_EXT3_FS=y
923CONFIG_EXT3_FS_XATTR=y 1013CONFIG_EXT3_FS_XATTR=y
924CONFIG_EXT3_FS_POSIX_ACL=y 1014CONFIG_EXT3_FS_POSIX_ACL=y
925CONFIG_EXT3_FS_SECURITY=y 1015CONFIG_EXT3_FS_SECURITY=y
926# CONFIG_EXT4DEV_FS is not set 1016CONFIG_EXT4DEV_FS=y
1017CONFIG_EXT4DEV_FS_XATTR=y
1018CONFIG_EXT4DEV_FS_POSIX_ACL=y
1019CONFIG_EXT4DEV_FS_SECURITY=y
927CONFIG_JBD=y 1020CONFIG_JBD=y
928# CONFIG_JBD_DEBUG is not set 1021CONFIG_JBD2=y
929CONFIG_FS_MBCACHE=y 1022CONFIG_FS_MBCACHE=y
930# CONFIG_REISERFS_FS is not set 1023# CONFIG_REISERFS_FS is not set
931# CONFIG_JFS_FS is not set 1024# CONFIG_JFS_FS is not set
932CONFIG_FS_POSIX_ACL=y 1025CONFIG_FS_POSIX_ACL=y
933# CONFIG_XFS_FS is not set 1026# CONFIG_XFS_FS is not set
934# CONFIG_GFS2_FS is not set
935# CONFIG_OCFS2_FS is not set 1027# CONFIG_OCFS2_FS is not set
936# CONFIG_MINIX_FS is not set 1028CONFIG_DNOTIFY=y
937# CONFIG_ROMFS_FS is not set
938CONFIG_INOTIFY=y 1029CONFIG_INOTIFY=y
939CONFIG_INOTIFY_USER=y 1030CONFIG_INOTIFY_USER=y
940# CONFIG_QUOTA is not set 1031# CONFIG_QUOTA is not set
941CONFIG_DNOTIFY=y
942# CONFIG_AUTOFS_FS is not set 1032# CONFIG_AUTOFS_FS is not set
943# CONFIG_AUTOFS4_FS is not set 1033# CONFIG_AUTOFS4_FS is not set
944# CONFIG_FUSE_FS is not set 1034# CONFIG_FUSE_FS is not set
@@ -967,7 +1057,6 @@ CONFIG_SYSFS=y
967CONFIG_TMPFS=y 1057CONFIG_TMPFS=y
968CONFIG_TMPFS_POSIX_ACL=y 1058CONFIG_TMPFS_POSIX_ACL=y
969# CONFIG_HUGETLB_PAGE is not set 1059# CONFIG_HUGETLB_PAGE is not set
970CONFIG_RAMFS=y
971CONFIG_CONFIGFS_FS=y 1060CONFIG_CONFIGFS_FS=y
972 1061
973# 1062#
@@ -983,32 +1072,28 @@ CONFIG_CONFIGFS_FS=y
983# CONFIG_JFFS2_FS is not set 1072# CONFIG_JFFS2_FS is not set
984# CONFIG_CRAMFS is not set 1073# CONFIG_CRAMFS is not set
985# CONFIG_VXFS_FS is not set 1074# CONFIG_VXFS_FS is not set
1075# CONFIG_MINIX_FS is not set
986# CONFIG_HPFS_FS is not set 1076# CONFIG_HPFS_FS is not set
987# CONFIG_QNX4FS_FS is not set 1077# CONFIG_QNX4FS_FS is not set
1078# CONFIG_ROMFS_FS is not set
988# CONFIG_SYSV_FS is not set 1079# CONFIG_SYSV_FS is not set
989# CONFIG_UFS_FS is not set 1080# CONFIG_UFS_FS is not set
990 1081CONFIG_NETWORK_FILESYSTEMS=y
991#
992# Network File Systems
993#
994CONFIG_NFS_FS=y 1082CONFIG_NFS_FS=y
995CONFIG_NFS_V3=y 1083CONFIG_NFS_V3=y
996CONFIG_NFS_V3_ACL=y 1084CONFIG_NFS_V3_ACL=y
997# CONFIG_NFS_V4 is not set 1085# CONFIG_NFS_V4 is not set
998# CONFIG_NFS_DIRECTIO is not set
999CONFIG_NFSD=y 1086CONFIG_NFSD=y
1000CONFIG_NFSD_V2_ACL=y 1087CONFIG_NFSD_V2_ACL=y
1001CONFIG_NFSD_V3=y 1088CONFIG_NFSD_V3=y
1002CONFIG_NFSD_V3_ACL=y 1089CONFIG_NFSD_V3_ACL=y
1003# CONFIG_NFSD_V4 is not set 1090# CONFIG_NFSD_V4 is not set
1004CONFIG_NFSD_TCP=y
1005CONFIG_LOCKD=y 1091CONFIG_LOCKD=y
1006CONFIG_LOCKD_V4=y 1092CONFIG_LOCKD_V4=y
1007CONFIG_EXPORTFS=y 1093CONFIG_EXPORTFS=y
1008CONFIG_NFS_ACL_SUPPORT=y 1094CONFIG_NFS_ACL_SUPPORT=y
1009CONFIG_NFS_COMMON=y 1095CONFIG_NFS_COMMON=y
1010CONFIG_SUNRPC=y 1096CONFIG_SUNRPC=y
1011# CONFIG_SUNRPC_BIND34 is not set
1012# CONFIG_RPCSEC_GSS_KRB5 is not set 1097# CONFIG_RPCSEC_GSS_KRB5 is not set
1013# CONFIG_RPCSEC_GSS_SPKM3 is not set 1098# CONFIG_RPCSEC_GSS_SPKM3 is not set
1014# CONFIG_SMB_FS is not set 1099# CONFIG_SMB_FS is not set
@@ -1022,34 +1107,26 @@ CONFIG_SUNRPC=y
1022# 1107#
1023# CONFIG_PARTITION_ADVANCED is not set 1108# CONFIG_PARTITION_ADVANCED is not set
1024CONFIG_MSDOS_PARTITION=y 1109CONFIG_MSDOS_PARTITION=y
1025
1026#
1027# Native Language Support
1028#
1029# CONFIG_NLS is not set 1110# CONFIG_NLS is not set
1030
1031#
1032# Distributed Lock Manager
1033#
1034# CONFIG_DLM is not set 1111# CONFIG_DLM is not set
1035 1112
1036# 1113#
1037# Profiling support
1038#
1039# CONFIG_PROFILING is not set
1040
1041#
1042# Kernel hacking 1114# Kernel hacking
1043# 1115#
1044CONFIG_TRACE_IRQFLAGS_SUPPORT=y 1116CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1045# CONFIG_PRINTK_TIME is not set 1117# CONFIG_PRINTK_TIME is not set
1118CONFIG_ENABLE_WARN_DEPRECATED=y
1046CONFIG_ENABLE_MUST_CHECK=y 1119CONFIG_ENABLE_MUST_CHECK=y
1120CONFIG_FRAME_WARN=1024
1047# CONFIG_MAGIC_SYSRQ is not set 1121# CONFIG_MAGIC_SYSRQ is not set
1048# CONFIG_UNUSED_SYMBOLS is not set 1122# CONFIG_UNUSED_SYMBOLS is not set
1049# CONFIG_DEBUG_FS is not set 1123# CONFIG_DEBUG_FS is not set
1050# CONFIG_HEADERS_CHECK is not set 1124# CONFIG_HEADERS_CHECK is not set
1051# CONFIG_DEBUG_KERNEL is not set 1125# CONFIG_DEBUG_KERNEL is not set
1052CONFIG_CROSSCOMPILE=y 1126# CONFIG_SLUB_DEBUG_ON is not set
1127# CONFIG_SLUB_STATS is not set
1128# CONFIG_DEBUG_MEMORY_INIT is not set
1129# CONFIG_SAMPLES is not set
1053CONFIG_CMDLINE="" 1130CONFIG_CMDLINE=""
1054 1131
1055# 1132#
@@ -1057,14 +1134,95 @@ CONFIG_CMDLINE=""
1057# 1134#
1058# CONFIG_KEYS is not set 1135# CONFIG_KEYS is not set
1059# CONFIG_SECURITY is not set 1136# CONFIG_SECURITY is not set
1060# CONFIG_CRYPTO is not set 1137# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1138CONFIG_CRYPTO=y
1139
1140#
1141# Crypto core or helper
1142#
1143# CONFIG_CRYPTO_MANAGER is not set
1144# CONFIG_CRYPTO_GF128MUL is not set
1145# CONFIG_CRYPTO_NULL is not set
1146# CONFIG_CRYPTO_CRYPTD is not set
1147# CONFIG_CRYPTO_AUTHENC is not set
1148# CONFIG_CRYPTO_TEST is not set
1149
1150#
1151# Authenticated Encryption with Associated Data
1152#
1153# CONFIG_CRYPTO_CCM is not set
1154# CONFIG_CRYPTO_GCM is not set
1155# CONFIG_CRYPTO_SEQIV is not set
1156
1157#
1158# Block modes
1159#
1160# CONFIG_CRYPTO_CBC is not set
1161# CONFIG_CRYPTO_CTR is not set
1162# CONFIG_CRYPTO_CTS is not set
1163# CONFIG_CRYPTO_ECB is not set
1164# CONFIG_CRYPTO_LRW is not set
1165# CONFIG_CRYPTO_PCBC is not set
1166# CONFIG_CRYPTO_XTS is not set
1167
1168#
1169# Hash modes
1170#
1171# CONFIG_CRYPTO_HMAC is not set
1172# CONFIG_CRYPTO_XCBC is not set
1173
1174#
1175# Digest
1176#
1177# CONFIG_CRYPTO_CRC32C is not set
1178# CONFIG_CRYPTO_MD4 is not set
1179# CONFIG_CRYPTO_MD5 is not set
1180# CONFIG_CRYPTO_MICHAEL_MIC is not set
1181# CONFIG_CRYPTO_RMD128 is not set
1182# CONFIG_CRYPTO_RMD160 is not set
1183# CONFIG_CRYPTO_RMD256 is not set
1184# CONFIG_CRYPTO_RMD320 is not set
1185# CONFIG_CRYPTO_SHA1 is not set
1186# CONFIG_CRYPTO_SHA256 is not set
1187# CONFIG_CRYPTO_SHA512 is not set
1188# CONFIG_CRYPTO_TGR192 is not set
1189# CONFIG_CRYPTO_WP512 is not set
1190
1191#
1192# Ciphers
1193#
1194# CONFIG_CRYPTO_AES is not set
1195# CONFIG_CRYPTO_ANUBIS is not set
1196# CONFIG_CRYPTO_ARC4 is not set
1197# CONFIG_CRYPTO_BLOWFISH is not set
1198# CONFIG_CRYPTO_CAMELLIA is not set
1199# CONFIG_CRYPTO_CAST5 is not set
1200# CONFIG_CRYPTO_CAST6 is not set
1201# CONFIG_CRYPTO_DES is not set
1202# CONFIG_CRYPTO_FCRYPT is not set
1203# CONFIG_CRYPTO_KHAZAD is not set
1204# CONFIG_CRYPTO_SALSA20 is not set
1205# CONFIG_CRYPTO_SEED is not set
1206# CONFIG_CRYPTO_SERPENT is not set
1207# CONFIG_CRYPTO_TEA is not set
1208# CONFIG_CRYPTO_TWOFISH is not set
1209
1210#
1211# Compression
1212#
1213# CONFIG_CRYPTO_DEFLATE is not set
1214# CONFIG_CRYPTO_LZO is not set
1215CONFIG_CRYPTO_HW=y
1216# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1061 1217
1062# 1218#
1063# Library routines 1219# Library routines
1064# 1220#
1065CONFIG_BITREVERSE=y 1221CONFIG_BITREVERSE=y
1222# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1066# CONFIG_CRC_CCITT is not set 1223# CONFIG_CRC_CCITT is not set
1067# CONFIG_CRC16 is not set 1224CONFIG_CRC16=y
1225# CONFIG_CRC_T10DIF is not set
1068# CONFIG_CRC_ITU_T is not set 1226# CONFIG_CRC_ITU_T is not set
1069CONFIG_CRC32=y 1227CONFIG_CRC32=y
1070# CONFIG_CRC7 is not set 1228# CONFIG_CRC7 is not set
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index ebb8ad62b3a..a279165e3a7 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -1092,7 +1092,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1092CONFIG_LOG_BUF_SHIFT=14 1092CONFIG_LOG_BUF_SHIFT=14
1093CONFIG_CROSSCOMPILE=y 1093CONFIG_CROSSCOMPILE=y
1094CONFIG_CMDLINE="" 1094CONFIG_CMDLINE=""
1095CONFIG_SYS_SUPPORTS_KGDB=y
1096 1095
1097# 1096#
1098# Security options 1097# Security options
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index ad4e5ef6559..8944d15caf1 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -1092,7 +1092,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1092CONFIG_LOG_BUF_SHIFT=14 1092CONFIG_LOG_BUF_SHIFT=14
1093CONFIG_CROSSCOMPILE=y 1093CONFIG_CROSSCOMPILE=y
1094CONFIG_CMDLINE="" 1094CONFIG_CMDLINE=""
1095CONFIG_SYS_SUPPORTS_KGDB=y
1096 1095
1097# 1096#
1098# Security options 1097# Security options
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index d0dc2e83ad3..ab17973107f 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -1174,7 +1174,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1174CONFIG_LOG_BUF_SHIFT=14 1174CONFIG_LOG_BUF_SHIFT=14
1175CONFIG_CROSSCOMPILE=y 1175CONFIG_CROSSCOMPILE=y
1176CONFIG_CMDLINE="mem=48M" 1176CONFIG_CMDLINE="mem=48M"
1177CONFIG_SYS_SUPPORTS_KGDB=y
1178 1177
1179# 1178#
1180# Security options 1179# Security options
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 9155082313c..b65803f1935 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -1392,7 +1392,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1392CONFIG_LOG_BUF_SHIFT=14 1392CONFIG_LOG_BUF_SHIFT=14
1393CONFIG_CROSSCOMPILE=y 1393CONFIG_CROSSCOMPILE=y
1394CONFIG_CMDLINE="" 1394CONFIG_CMDLINE=""
1395CONFIG_SYS_SUPPORTS_KGDB=y
1396 1395
1397# 1396#
1398# Security options 1397# Security options
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index e4e324422cd..a190ac07740 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -1209,7 +1209,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1209CONFIG_LOG_BUF_SHIFT=14 1209CONFIG_LOG_BUF_SHIFT=14
1210CONFIG_CROSSCOMPILE=y 1210CONFIG_CROSSCOMPILE=y
1211CONFIG_CMDLINE="" 1211CONFIG_CMDLINE=""
1212CONFIG_SYS_SUPPORTS_KGDB=y
1213 1212
1214# 1213#
1215# Security options 1214# Security options
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
index 3572e80356d..4e465e94599 100644
--- a/arch/mips/configs/excite_defconfig
+++ b/arch/mips/configs/excite_defconfig
@@ -1269,7 +1269,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1269CONFIG_LOG_BUF_SHIFT=14 1269CONFIG_LOG_BUF_SHIFT=14
1270CONFIG_CROSSCOMPILE=y 1270CONFIG_CROSSCOMPILE=y
1271CONFIG_CMDLINE="" 1271CONFIG_CMDLINE=""
1272CONFIG_SYS_SUPPORTS_KGDB=y
1273 1272
1274# 1273#
1275# Security options 1274# Security options
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 138c575a015..831d3e5a1ea 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -943,7 +943,6 @@ CONFIG_ENABLE_MUST_CHECK=y
943# CONFIG_DEBUG_KERNEL is not set 943# CONFIG_DEBUG_KERNEL is not set
944CONFIG_CROSSCOMPILE=y 944CONFIG_CROSSCOMPILE=y
945CONFIG_CMDLINE="" 945CONFIG_CMDLINE=""
946CONFIG_SYS_SUPPORTS_KGDB=y
947 946
948# 947#
949# Security options 948# Security options
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig
index 59d19472b16..dd13db4d0fb 100644
--- a/arch/mips/configs/msp71xx_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -1415,8 +1415,6 @@ CONFIG_FORCED_INLINING=y
1415CONFIG_CROSSCOMPILE=y 1415CONFIG_CROSSCOMPILE=y
1416CONFIG_CMDLINE="" 1416CONFIG_CMDLINE=""
1417# CONFIG_DEBUG_STACK_USAGE is not set 1417# CONFIG_DEBUG_STACK_USAGE is not set
1418# CONFIG_KGDB is not set
1419CONFIG_SYS_SUPPORTS_KGDB=y
1420# CONFIG_RUNTIME_DEBUG is not set 1418# CONFIG_RUNTIME_DEBUG is not set
1421# CONFIG_MIPS_UNCACHED is not set 1419# CONFIG_MIPS_UNCACHED is not set
1422 1420
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index bacf0dd0e34..db9272677aa 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -3020,7 +3020,6 @@ CONFIG_MAGIC_SYSRQ=y
3020# CONFIG_DEBUG_KERNEL is not set 3020# CONFIG_DEBUG_KERNEL is not set
3021CONFIG_CROSSCOMPILE=y 3021CONFIG_CROSSCOMPILE=y
3022CONFIG_CMDLINE="" 3022CONFIG_CMDLINE=""
3023CONFIG_SYS_SUPPORTS_KGDB=y
3024 3023
3025# 3024#
3026# Security options 3025# Security options
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 6dfe6f793ce..9e21e333a2f 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -1085,7 +1085,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1085CONFIG_LOG_BUF_SHIFT=14 1085CONFIG_LOG_BUF_SHIFT=14
1086CONFIG_CROSSCOMPILE=y 1086CONFIG_CROSSCOMPILE=y
1087CONFIG_CMDLINE="" 1087CONFIG_CMDLINE=""
1088CONFIG_SYS_SUPPORTS_KGDB=y
1089 1088
1090# 1089#
1091# Security options 1090# Security options
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index c965a87e6a9..af67ed4f71a 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -1202,7 +1202,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1202CONFIG_LOG_BUF_SHIFT=14 1202CONFIG_LOG_BUF_SHIFT=14
1203CONFIG_CROSSCOMPILE=y 1203CONFIG_CROSSCOMPILE=y
1204CONFIG_CMDLINE="" 1204CONFIG_CMDLINE=""
1205CONFIG_SYS_SUPPORTS_KGDB=y
1206 1205
1207# 1206#
1208# Security options 1207# Security options
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 0778996c682..7956f56cbf3 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -1195,7 +1195,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1195CONFIG_LOG_BUF_SHIFT=14 1195CONFIG_LOG_BUF_SHIFT=14
1196CONFIG_CROSSCOMPILE=y 1196CONFIG_CROSSCOMPILE=y
1197CONFIG_CMDLINE="" 1197CONFIG_CMDLINE=""
1198CONFIG_SYS_SUPPORTS_KGDB=y
1199 1198
1200# 1199#
1201# Security options 1200# Security options
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index 37c7b5ffd47..723bd5176a3 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -1216,10 +1216,8 @@ CONFIG_DEBUG_MUTEXES=y
1216CONFIG_FORCED_INLINING=y 1216CONFIG_FORCED_INLINING=y
1217# CONFIG_RCU_TORTURE_TEST is not set 1217# CONFIG_RCU_TORTURE_TEST is not set
1218CONFIG_CROSSCOMPILE=y 1218CONFIG_CROSSCOMPILE=y
1219CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp" 1219CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
1220# CONFIG_DEBUG_STACK_USAGE is not set 1220# CONFIG_DEBUG_STACK_USAGE is not set
1221# CONFIG_KGDB is not set
1222CONFIG_SYS_SUPPORTS_KGDB=y
1223# CONFIG_RUNTIME_DEBUG is not set 1221# CONFIG_RUNTIME_DEBUG is not set
1224 1222
1225# 1223#
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index 893e5c4ab66..b5052fb42e9 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -1206,10 +1206,8 @@ CONFIG_DEBUG_SLAB=y
1206CONFIG_FORCED_INLINING=y 1206CONFIG_FORCED_INLINING=y
1207# CONFIG_RCU_TORTURE_TEST is not set 1207# CONFIG_RCU_TORTURE_TEST is not set
1208CONFIG_CROSSCOMPILE=y 1208CONFIG_CROSSCOMPILE=y
1209CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp" 1209CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
1210# CONFIG_DEBUG_STACK_USAGE is not set 1210# CONFIG_DEBUG_STACK_USAGE is not set
1211# CONFIG_KGDB is not set
1212CONFIG_SYS_SUPPORTS_KGDB=y
1213# CONFIG_RUNTIME_DEBUG is not set 1211# CONFIG_RUNTIME_DEBUG is not set
1214 1212
1215# 1213#
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig
index e42aed5a38b..c7c0864b8ce 100644
--- a/arch/mips/configs/rbtx49xx_defconfig
+++ b/arch/mips/configs/rbtx49xx_defconfig
@@ -742,7 +742,6 @@ CONFIG_DEBUG_FS=y
742# CONFIG_DEBUG_KERNEL is not set 742# CONFIG_DEBUG_KERNEL is not set
743# CONFIG_SAMPLES is not set 743# CONFIG_SAMPLES is not set
744CONFIG_CMDLINE="" 744CONFIG_CMDLINE=""
745CONFIG_SYS_SUPPORTS_KGDB=y
746 745
747# 746#
748# Security options 747# Security options
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 1ea97865f2c..a9acaa2f9da 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -963,7 +963,6 @@ CONFIG_ENABLE_MUST_CHECK=y
963# CONFIG_DEBUG_KERNEL is not set 963# CONFIG_DEBUG_KERNEL is not set
964# CONFIG_SAMPLES is not set 964# CONFIG_SAMPLES is not set
965CONFIG_CMDLINE="" 965CONFIG_CMDLINE=""
966CONFIG_SYS_SUPPORTS_KGDB=y
967# CONFIG_SB1XXX_CORELIS is not set 966# CONFIG_SB1XXX_CORELIS is not set
968 967
969# 968#
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 7f86c43d1bd..ea8249c75b3 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -827,8 +827,6 @@ CONFIG_FORCED_INLINING=y
827CONFIG_CROSSCOMPILE=y 827CONFIG_CROSSCOMPILE=y
828CONFIG_CMDLINE="" 828CONFIG_CMDLINE=""
829# CONFIG_DEBUG_STACK_USAGE is not set 829# CONFIG_DEBUG_STACK_USAGE is not set
830# CONFIG_KGDB is not set
831CONFIG_SYS_SUPPORTS_KGDB=y
832# CONFIG_RUNTIME_DEBUG is not set 830# CONFIG_RUNTIME_DEBUG is not set
833 831
834# 832#
diff --git a/arch/mips/emma2rh/markeins/platform.c b/arch/mips/emma2rh/markeins/platform.c
index 11567702b15..d70627de7cf 100644
--- a/arch/mips/emma2rh/markeins/platform.c
+++ b/arch/mips/emma2rh/markeins/platform.c
@@ -34,7 +34,6 @@
34#include <asm/bcache.h> 34#include <asm/bcache.h>
35#include <asm/irq.h> 35#include <asm/irq.h>
36#include <asm/reboot.h> 36#include <asm/reboot.h>
37#include <asm/gdb-stub.h>
38#include <asm/traps.h> 37#include <asm/traps.h>
39#include <asm/debug.h> 38#include <asm/debug.h>
40 39
diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c
index 62bfb455d1b..a56c4b804b0 100644
--- a/arch/mips/emma2rh/markeins/setup.c
+++ b/arch/mips/emma2rh/markeins/setup.c
@@ -41,7 +41,6 @@
41#include <asm/bcache.h> 41#include <asm/bcache.h>
42#include <asm/irq.h> 42#include <asm/irq.h>
43#include <asm/reboot.h> 43#include <asm/reboot.h>
44#include <asm/gdb-stub.h>
45#include <asm/traps.h> 44#include <asm/traps.h>
46#include <asm/debug.h> 45#include <asm/debug.h>
47 46
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 0fd31974ba2..706f9397479 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -71,7 +71,7 @@ obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o
71obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o 71obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o
72obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o 72obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o
73 73
74obj-$(CONFIG_KGDB) += gdb-low.o gdb-stub.o 74obj-$(CONFIG_KGDB) += kgdb.o
75obj-$(CONFIG_PROC_FS) += proc.o 75obj-$(CONFIG_PROC_FS) += proc.o
76 76
77obj-$(CONFIG_64BIT) += cpu-bugs64.o 77obj-$(CONFIG_64BIT) += cpu-bugs64.o
diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S
deleted file mode 100644
index 2c446063636..00000000000
--- a/arch/mips/kernel/gdb-low.S
+++ /dev/null
@@ -1,394 +0,0 @@
1/*
2 * gdb-low.S contains the low-level trap handler for the GDB stub.
3 *
4 * Copyright (C) 1995 Andreas Busse
5 */
6#include <linux/sys.h>
7
8#include <asm/asm.h>
9#include <asm/errno.h>
10#include <asm/irqflags.h>
11#include <asm/mipsregs.h>
12#include <asm/regdef.h>
13#include <asm/stackframe.h>
14#include <asm/gdb-stub.h>
15
16#ifdef CONFIG_32BIT
17#define DMFC0 mfc0
18#define DMTC0 mtc0
19#define LDC1 lwc1
20#define SDC1 lwc1
21#endif
22#ifdef CONFIG_64BIT
23#define DMFC0 dmfc0
24#define DMTC0 dmtc0
25#define LDC1 ldc1
26#define SDC1 ldc1
27#endif
28
29/*
30 * [jsun] We reserves about 2x GDB_FR_SIZE in stack. The lower (addressed)
31 * part is used to store registers and passed to exception handler.
32 * The upper part is reserved for "call func" feature where gdb client
33 * saves some of the regs, setups call frame and passes args.
34 *
35 * A trace shows about 200 bytes are used to store about half of all regs.
36 * The rest should be big enough for frame setup and passing args.
37 */
38
39/*
40 * The low level trap handler
41 */
42 .align 5
43 NESTED(trap_low, GDB_FR_SIZE, sp)
44 .set noat
45 .set noreorder
46
47 mfc0 k0, CP0_STATUS
48 sll k0, 3 /* extract cu0 bit */
49 bltz k0, 1f
50 move k1, sp
51
52 /*
53 * Called from user mode, go somewhere else.
54 */
55 mfc0 k0, CP0_CAUSE
56 andi k0, k0, 0x7c
57#ifdef CONFIG_64BIT
58 dsll k0, k0, 1
59#endif
60 PTR_L k1, saved_vectors(k0)
61 jr k1
62 nop
631:
64 move k0, sp
65 PTR_SUBU sp, k1, GDB_FR_SIZE*2 # see comment above
66 LONG_S k0, GDB_FR_REG29(sp)
67 LONG_S $2, GDB_FR_REG2(sp)
68
69/*
70 * First save the CP0 and special registers
71 */
72
73 mfc0 v0, CP0_STATUS
74 LONG_S v0, GDB_FR_STATUS(sp)
75 mfc0 v0, CP0_CAUSE
76 LONG_S v0, GDB_FR_CAUSE(sp)
77 DMFC0 v0, CP0_EPC
78 LONG_S v0, GDB_FR_EPC(sp)
79 DMFC0 v0, CP0_BADVADDR
80 LONG_S v0, GDB_FR_BADVADDR(sp)
81 mfhi v0
82 LONG_S v0, GDB_FR_HI(sp)
83 mflo v0
84 LONG_S v0, GDB_FR_LO(sp)
85
86/*
87 * Now the integer registers
88 */
89
90 LONG_S zero, GDB_FR_REG0(sp) /* I know... */
91 LONG_S $1, GDB_FR_REG1(sp)
92 /* v0 already saved */
93 LONG_S $3, GDB_FR_REG3(sp)
94 LONG_S $4, GDB_FR_REG4(sp)
95 LONG_S $5, GDB_FR_REG5(sp)
96 LONG_S $6, GDB_FR_REG6(sp)
97 LONG_S $7, GDB_FR_REG7(sp)
98 LONG_S $8, GDB_FR_REG8(sp)
99 LONG_S $9, GDB_FR_REG9(sp)
100 LONG_S $10, GDB_FR_REG10(sp)
101 LONG_S $11, GDB_FR_REG11(sp)
102 LONG_S $12, GDB_FR_REG12(sp)
103 LONG_S $13, GDB_FR_REG13(sp)
104 LONG_S $14, GDB_FR_REG14(sp)
105 LONG_S $15, GDB_FR_REG15(sp)
106 LONG_S $16, GDB_FR_REG16(sp)
107 LONG_S $17, GDB_FR_REG17(sp)
108 LONG_S $18, GDB_FR_REG18(sp)
109 LONG_S $19, GDB_FR_REG19(sp)
110 LONG_S $20, GDB_FR_REG20(sp)
111 LONG_S $21, GDB_FR_REG21(sp)
112 LONG_S $22, GDB_FR_REG22(sp)
113 LONG_S $23, GDB_FR_REG23(sp)
114 LONG_S $24, GDB_FR_REG24(sp)
115 LONG_S $25, GDB_FR_REG25(sp)
116 LONG_S $26, GDB_FR_REG26(sp)
117 LONG_S $27, GDB_FR_REG27(sp)
118 LONG_S $28, GDB_FR_REG28(sp)
119 /* sp already saved */
120 LONG_S $30, GDB_FR_REG30(sp)
121 LONG_S $31, GDB_FR_REG31(sp)
122
123 CLI /* disable interrupts */
124 TRACE_IRQS_OFF
125
126/*
127 * Followed by the floating point registers
128 */
129 mfc0 v0, CP0_STATUS /* FPU enabled? */
130 srl v0, v0, 16
131 andi v0, v0, (ST0_CU1 >> 16)
132
133 beqz v0,2f /* disabled, skip */
134 nop
135
136 SDC1 $0, GDB_FR_FPR0(sp)
137 SDC1 $1, GDB_FR_FPR1(sp)
138 SDC1 $2, GDB_FR_FPR2(sp)
139 SDC1 $3, GDB_FR_FPR3(sp)
140 SDC1 $4, GDB_FR_FPR4(sp)
141 SDC1 $5, GDB_FR_FPR5(sp)
142 SDC1 $6, GDB_FR_FPR6(sp)
143 SDC1 $7, GDB_FR_FPR7(sp)
144 SDC1 $8, GDB_FR_FPR8(sp)
145 SDC1 $9, GDB_FR_FPR9(sp)
146 SDC1 $10, GDB_FR_FPR10(sp)
147 SDC1 $11, GDB_FR_FPR11(sp)
148 SDC1 $12, GDB_FR_FPR12(sp)
149 SDC1 $13, GDB_FR_FPR13(sp)
150 SDC1 $14, GDB_FR_FPR14(sp)
151 SDC1 $15, GDB_FR_FPR15(sp)
152 SDC1 $16, GDB_FR_FPR16(sp)
153 SDC1 $17, GDB_FR_FPR17(sp)
154 SDC1 $18, GDB_FR_FPR18(sp)
155 SDC1 $19, GDB_FR_FPR19(sp)
156 SDC1 $20, GDB_FR_FPR20(sp)
157 SDC1 $21, GDB_FR_FPR21(sp)
158 SDC1 $22, GDB_FR_FPR22(sp)
159 SDC1 $23, GDB_FR_FPR23(sp)
160 SDC1 $24, GDB_FR_FPR24(sp)
161 SDC1 $25, GDB_FR_FPR25(sp)
162 SDC1 $26, GDB_FR_FPR26(sp)
163 SDC1 $27, GDB_FR_FPR27(sp)
164 SDC1 $28, GDB_FR_FPR28(sp)
165 SDC1 $29, GDB_FR_FPR29(sp)
166 SDC1 $30, GDB_FR_FPR30(sp)
167 SDC1 $31, GDB_FR_FPR31(sp)
168
169/*
170 * FPU control registers
171 */
172
173 cfc1 v0, CP1_STATUS
174 LONG_S v0, GDB_FR_FSR(sp)
175 cfc1 v0, CP1_REVISION
176 LONG_S v0, GDB_FR_FIR(sp)
177
178/*
179 * Current stack frame ptr
180 */
181
1822:
183 LONG_S sp, GDB_FR_FRP(sp)
184
185/*
186 * CP0 registers (R4000/R4400 unused registers skipped)
187 */
188
189 mfc0 v0, CP0_INDEX
190 LONG_S v0, GDB_FR_CP0_INDEX(sp)
191 mfc0 v0, CP0_RANDOM
192 LONG_S v0, GDB_FR_CP0_RANDOM(sp)
193 DMFC0 v0, CP0_ENTRYLO0
194 LONG_S v0, GDB_FR_CP0_ENTRYLO0(sp)
195 DMFC0 v0, CP0_ENTRYLO1
196 LONG_S v0, GDB_FR_CP0_ENTRYLO1(sp)
197 DMFC0 v0, CP0_CONTEXT
198 LONG_S v0, GDB_FR_CP0_CONTEXT(sp)
199 mfc0 v0, CP0_PAGEMASK
200 LONG_S v0, GDB_FR_CP0_PAGEMASK(sp)
201 mfc0 v0, CP0_WIRED
202 LONG_S v0, GDB_FR_CP0_WIRED(sp)
203 DMFC0 v0, CP0_ENTRYHI
204 LONG_S v0, GDB_FR_CP0_ENTRYHI(sp)
205 mfc0 v0, CP0_PRID
206 LONG_S v0, GDB_FR_CP0_PRID(sp)
207
208 .set at
209
210/*
211 * Continue with the higher level handler
212 */
213
214 move a0,sp
215
216 jal handle_exception
217 nop
218
219/*
220 * Restore all writable registers, in reverse order
221 */
222
223 .set noat
224
225 LONG_L v0, GDB_FR_CP0_ENTRYHI(sp)
226 LONG_L v1, GDB_FR_CP0_WIRED(sp)
227 DMTC0 v0, CP0_ENTRYHI
228 mtc0 v1, CP0_WIRED
229 LONG_L v0, GDB_FR_CP0_PAGEMASK(sp)
230 LONG_L v1, GDB_FR_CP0_ENTRYLO1(sp)
231 mtc0 v0, CP0_PAGEMASK
232 DMTC0 v1, CP0_ENTRYLO1
233 LONG_L v0, GDB_FR_CP0_ENTRYLO0(sp)
234 LONG_L v1, GDB_FR_CP0_INDEX(sp)
235 DMTC0 v0, CP0_ENTRYLO0
236 LONG_L v0, GDB_FR_CP0_CONTEXT(sp)
237 mtc0 v1, CP0_INDEX
238 DMTC0 v0, CP0_CONTEXT
239
240
241/*
242 * Next, the floating point registers
243 */
244 mfc0 v0, CP0_STATUS /* check if the FPU is enabled */
245 srl v0, v0, 16
246 andi v0, v0, (ST0_CU1 >> 16)
247
248 beqz v0, 3f /* disabled, skip */
249 nop
250
251 LDC1 $31, GDB_FR_FPR31(sp)
252 LDC1 $30, GDB_FR_FPR30(sp)
253 LDC1 $29, GDB_FR_FPR29(sp)
254 LDC1 $28, GDB_FR_FPR28(sp)
255 LDC1 $27, GDB_FR_FPR27(sp)
256 LDC1 $26, GDB_FR_FPR26(sp)
257 LDC1 $25, GDB_FR_FPR25(sp)
258 LDC1 $24, GDB_FR_FPR24(sp)
259 LDC1 $23, GDB_FR_FPR23(sp)
260 LDC1 $22, GDB_FR_FPR22(sp)
261 LDC1 $21, GDB_FR_FPR21(sp)
262 LDC1 $20, GDB_FR_FPR20(sp)
263 LDC1 $19, GDB_FR_FPR19(sp)
264 LDC1 $18, GDB_FR_FPR18(sp)
265 LDC1 $17, GDB_FR_FPR17(sp)
266 LDC1 $16, GDB_FR_FPR16(sp)
267 LDC1 $15, GDB_FR_FPR15(sp)
268 LDC1 $14, GDB_FR_FPR14(sp)
269 LDC1 $13, GDB_FR_FPR13(sp)
270 LDC1 $12, GDB_FR_FPR12(sp)
271 LDC1 $11, GDB_FR_FPR11(sp)
272 LDC1 $10, GDB_FR_FPR10(sp)
273 LDC1 $9, GDB_FR_FPR9(sp)
274 LDC1 $8, GDB_FR_FPR8(sp)
275 LDC1 $7, GDB_FR_FPR7(sp)
276 LDC1 $6, GDB_FR_FPR6(sp)
277 LDC1 $5, GDB_FR_FPR5(sp)
278 LDC1 $4, GDB_FR_FPR4(sp)
279 LDC1 $3, GDB_FR_FPR3(sp)
280 LDC1 $2, GDB_FR_FPR2(sp)
281 LDC1 $1, GDB_FR_FPR1(sp)
282 LDC1 $0, GDB_FR_FPR0(sp)
283
284/*
285 * Now the CP0 and integer registers
286 */
287
2883:
289#ifdef CONFIG_MIPS_MT_SMTC
290 /* Read-modify write of Status must be atomic */
291 mfc0 t2, CP0_TCSTATUS
292 ori t1, t2, TCSTATUS_IXMT
293 mtc0 t1, CP0_TCSTATUS
294 andi t2, t2, TCSTATUS_IXMT
295 _ehb
296 DMT 9 # dmt t1
297 jal mips_ihb
298 nop
299#endif /* CONFIG_MIPS_MT_SMTC */
300 mfc0 t0, CP0_STATUS
301 ori t0, 0x1f
302 xori t0, 0x1f
303 mtc0 t0, CP0_STATUS
304#ifdef CONFIG_MIPS_MT_SMTC
305 andi t1, t1, VPECONTROL_TE
306 beqz t1, 9f
307 nop
308 EMT # emt
3099:
310 mfc0 t1, CP0_TCSTATUS
311 xori t1, t1, TCSTATUS_IXMT
312 or t1, t1, t2
313 mtc0 t1, CP0_TCSTATUS
314 _ehb
315#endif /* CONFIG_MIPS_MT_SMTC */
316 LONG_L v0, GDB_FR_STATUS(sp)
317 LONG_L v1, GDB_FR_EPC(sp)
318 mtc0 v0, CP0_STATUS
319 DMTC0 v1, CP0_EPC
320 LONG_L v0, GDB_FR_HI(sp)
321 LONG_L v1, GDB_FR_LO(sp)
322 mthi v0
323 mtlo v1
324 LONG_L $31, GDB_FR_REG31(sp)
325 LONG_L $30, GDB_FR_REG30(sp)
326 LONG_L $28, GDB_FR_REG28(sp)
327 LONG_L $27, GDB_FR_REG27(sp)
328 LONG_L $26, GDB_FR_REG26(sp)
329 LONG_L $25, GDB_FR_REG25(sp)
330 LONG_L $24, GDB_FR_REG24(sp)
331 LONG_L $23, GDB_FR_REG23(sp)
332 LONG_L $22, GDB_FR_REG22(sp)
333 LONG_L $21, GDB_FR_REG21(sp)
334 LONG_L $20, GDB_FR_REG20(sp)
335 LONG_L $19, GDB_FR_REG19(sp)
336 LONG_L $18, GDB_FR_REG18(sp)
337 LONG_L $17, GDB_FR_REG17(sp)
338 LONG_L $16, GDB_FR_REG16(sp)
339 LONG_L $15, GDB_FR_REG15(sp)
340 LONG_L $14, GDB_FR_REG14(sp)
341 LONG_L $13, GDB_FR_REG13(sp)
342 LONG_L $12, GDB_FR_REG12(sp)
343 LONG_L $11, GDB_FR_REG11(sp)
344 LONG_L $10, GDB_FR_REG10(sp)
345 LONG_L $9, GDB_FR_REG9(sp)
346 LONG_L $8, GDB_FR_REG8(sp)
347 LONG_L $7, GDB_FR_REG7(sp)
348 LONG_L $6, GDB_FR_REG6(sp)
349 LONG_L $5, GDB_FR_REG5(sp)
350 LONG_L $4, GDB_FR_REG4(sp)
351 LONG_L $3, GDB_FR_REG3(sp)
352 LONG_L $2, GDB_FR_REG2(sp)
353 LONG_L $1, GDB_FR_REG1(sp)
354#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
355 LONG_L k0, GDB_FR_EPC(sp)
356 LONG_L $29, GDB_FR_REG29(sp) /* Deallocate stack */
357 jr k0
358 rfe
359#else
360 LONG_L sp, GDB_FR_REG29(sp) /* Deallocate stack */
361
362 .set mips3
363 eret
364 .set mips0
365#endif
366 .set at
367 .set reorder
368 END(trap_low)
369
370LEAF(kgdb_read_byte)
3714: lb t0, (a0)
372 sb t0, (a1)
373 li v0, 0
374 jr ra
375 .section __ex_table,"a"
376 PTR 4b, kgdbfault
377 .previous
378 END(kgdb_read_byte)
379
380LEAF(kgdb_write_byte)
3815: sb a0, (a1)
382 li v0, 0
383 jr ra
384 .section __ex_table,"a"
385 PTR 5b, kgdbfault
386 .previous
387 END(kgdb_write_byte)
388
389 .type kgdbfault@function
390 .ent kgdbfault
391
392kgdbfault: li v0, -EFAULT
393 jr ra
394 .end kgdbfault
diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c
deleted file mode 100644
index 25f4eab8ea9..00000000000
--- a/arch/mips/kernel/gdb-stub.c
+++ /dev/null
@@ -1,1155 +0,0 @@
1/*
2 * arch/mips/kernel/gdb-stub.c
3 *
4 * Originally written by Glenn Engel, Lake Stevens Instrument Division
5 *
6 * Contributed by HP Systems
7 *
8 * Modified for SPARC by Stu Grossman, Cygnus Support.
9 *
10 * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
11 * Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
12 *
13 * Copyright (C) 1995 Andreas Busse
14 *
15 * Copyright (C) 2003 MontaVista Software Inc.
16 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
17 */
18
19/*
20 * To enable debugger support, two things need to happen. One, a
21 * call to set_debug_traps() is necessary in order to allow any breakpoints
22 * or error conditions to be properly intercepted and reported to gdb.
23 * Two, a breakpoint needs to be generated to begin communication. This
24 * is most easily accomplished by a call to breakpoint(). Breakpoint()
25 * simulates a breakpoint by executing a BREAK instruction.
26 *
27 *
28 * The following gdb commands are supported:
29 *
30 * command function Return value
31 *
32 * g return the value of the CPU registers hex data or ENN
33 * G set the value of the CPU registers OK or ENN
34 *
35 * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
36 * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
37 *
38 * c Resume at current address SNN ( signal NN)
39 * cAA..AA Continue at address AA..AA SNN
40 *
41 * s Step one instruction SNN
42 * sAA..AA Step one instruction from AA..AA SNN
43 *
44 * k kill
45 *
46 * ? What was the last sigval ? SNN (signal NN)
47 *
48 * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
49 * baud rate
50 *
51 * All commands and responses are sent with a packet which includes a
52 * checksum. A packet consists of
53 *
54 * $<packet info>#<checksum>.
55 *
56 * where
57 * <packet info> :: <characters representing the command or response>
58 * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
59 *
60 * When a packet is received, it is first acknowledged with either '+' or '-'.
61 * '+' indicates a successful transfer. '-' indicates a failed transfer.
62 *
63 * Example:
64 *
65 * Host: Reply:
66 * $m0,10#2a +$00010203040506070809101112131415#42
67 *
68 *
69 * ==============
70 * MORE EXAMPLES:
71 * ==============
72 *
73 * For reference -- the following are the steps that one
74 * company took (RidgeRun Inc) to get remote gdb debugging
75 * going. In this scenario the host machine was a PC and the
76 * target platform was a Galileo EVB64120A MIPS evaluation
77 * board.
78 *
79 * Step 1:
80 * First download gdb-5.0.tar.gz from the internet.
81 * and then build/install the package.
82 *
83 * Example:
84 * $ tar zxf gdb-5.0.tar.gz
85 * $ cd gdb-5.0
86 * $ ./configure --target=mips-linux-elf
87 * $ make
88 * $ install
89 * $ which mips-linux-elf-gdb
90 * /usr/local/bin/mips-linux-elf-gdb
91 *
92 * Step 2:
93 * Configure linux for remote debugging and build it.
94 *
95 * Example:
96 * $ cd ~/linux
97 * $ make menuconfig <go to "Kernel Hacking" and turn on remote debugging>
98 * $ make
99 *
100 * Step 3:
101 * Download the kernel to the remote target and start
102 * the kernel running. It will promptly halt and wait
103 * for the host gdb session to connect. It does this
104 * since the "Kernel Hacking" option has defined
105 * CONFIG_KGDB which in turn enables your calls
106 * to:
107 * set_debug_traps();
108 * breakpoint();
109 *
110 * Step 4:
111 * Start the gdb session on the host.
112 *
113 * Example:
114 * $ mips-linux-elf-gdb vmlinux
115 * (gdb) set remotebaud 115200
116 * (gdb) target remote /dev/ttyS1
117 * ...at this point you are connected to
118 * the remote target and can use gdb
119 * in the normal fasion. Setting
120 * breakpoints, single stepping,
121 * printing variables, etc.
122 */
123#include <linux/string.h>
124#include <linux/kernel.h>
125#include <linux/signal.h>
126#include <linux/sched.h>
127#include <linux/mm.h>
128#include <linux/console.h>
129#include <linux/init.h>
130#include <linux/smp.h>
131#include <linux/spinlock.h>
132#include <linux/slab.h>
133#include <linux/reboot.h>
134
135#include <asm/asm.h>
136#include <asm/cacheflush.h>
137#include <asm/mipsregs.h>
138#include <asm/pgtable.h>
139#include <asm/system.h>
140#include <asm/gdb-stub.h>
141#include <asm/inst.h>
142
143/*
144 * external low-level support routines
145 */
146
147extern int putDebugChar(char c); /* write a single character */
148extern char getDebugChar(void); /* read and return a single char */
149extern void trap_low(void);
150
151/*
152 * breakpoint and test functions
153 */
154extern void breakpoint(void);
155extern void breakinst(void);
156extern void async_breakpoint(void);
157extern void async_breakinst(void);
158extern void adel(void);
159
160/*
161 * local prototypes
162 */
163
164static void getpacket(char *buffer);
165static void putpacket(char *buffer);
166static int computeSignal(int tt);
167static int hex(unsigned char ch);
168static int hexToInt(char **ptr, int *intValue);
169static int hexToLong(char **ptr, long *longValue);
170static unsigned char *mem2hex(char *mem, char *buf, int count, int may_fault);
171void handle_exception(struct gdb_regs *regs);
172
173int kgdb_enabled;
174
175/*
176 * spin locks for smp case
177 */
178static DEFINE_SPINLOCK(kgdb_lock);
179static raw_spinlock_t kgdb_cpulock[NR_CPUS] = {
180 [0 ... NR_CPUS-1] = __RAW_SPIN_LOCK_UNLOCKED,
181};
182
183/*
184 * BUFMAX defines the maximum number of characters in inbound/outbound buffers
185 * at least NUMREGBYTES*2 are needed for register packets
186 */
187#define BUFMAX 2048
188
189static char input_buffer[BUFMAX];
190static char output_buffer[BUFMAX];
191static int initialized; /* !0 means we've been initialized */
192static int kgdb_started;
193static const char hexchars[]="0123456789abcdef";
194
195/* Used to prevent crashes in memory access. Note that they'll crash anyway if
196 we haven't set up fault handlers yet... */
197int kgdb_read_byte(unsigned char *address, unsigned char *dest);
198int kgdb_write_byte(unsigned char val, unsigned char *dest);
199
200/*
201 * Convert ch from a hex digit to an int
202 */
203static int hex(unsigned char ch)
204{
205 if (ch >= 'a' && ch <= 'f')
206 return ch-'a'+10;
207 if (ch >= '0' && ch <= '9')
208 return ch-'0';
209 if (ch >= 'A' && ch <= 'F')
210 return ch-'A'+10;
211 return -1;
212}
213
214/*
215 * scan for the sequence $<data>#<checksum>
216 */
217static void getpacket(char *buffer)
218{
219 unsigned char checksum;
220 unsigned char xmitcsum;
221 int i;
222 int count;
223 unsigned char ch;
224
225 do {
226 /*
227 * wait around for the start character,
228 * ignore all other characters
229 */
230 while ((ch = (getDebugChar() & 0x7f)) != '$') ;
231
232 checksum = 0;
233 xmitcsum = -1;
234 count = 0;
235
236 /*
237 * now, read until a # or end of buffer is found
238 */
239 while (count < BUFMAX) {
240 ch = getDebugChar();
241 if (ch == '#')
242 break;
243 checksum = checksum + ch;
244 buffer[count] = ch;
245 count = count + 1;
246 }
247
248 if (count >= BUFMAX)
249 continue;
250
251 buffer[count] = 0;
252
253 if (ch == '#') {
254 xmitcsum = hex(getDebugChar() & 0x7f) << 4;
255 xmitcsum |= hex(getDebugChar() & 0x7f);
256
257 if (checksum != xmitcsum)
258 putDebugChar('-'); /* failed checksum */
259 else {
260 putDebugChar('+'); /* successful transfer */
261
262 /*
263 * if a sequence char is present,
264 * reply the sequence ID
265 */
266 if (buffer[2] == ':') {
267 putDebugChar(buffer[0]);
268 putDebugChar(buffer[1]);
269
270 /*
271 * remove sequence chars from buffer
272 */
273 count = strlen(buffer);
274 for (i=3; i <= count; i++)
275 buffer[i-3] = buffer[i];
276 }
277 }
278 }
279 }
280 while (checksum != xmitcsum);
281}
282
283/*
284 * send the packet in buffer.
285 */
286static void putpacket(char *buffer)
287{
288 unsigned char checksum;
289 int count;
290 unsigned char ch;
291
292 /*
293 * $<packet info>#<checksum>.
294 */
295
296 do {
297 putDebugChar('$');
298 checksum = 0;
299 count = 0;
300
301 while ((ch = buffer[count]) != 0) {
302 if (!(putDebugChar(ch)))
303 return;
304 checksum += ch;
305 count += 1;
306 }
307
308 putDebugChar('#');
309 putDebugChar(hexchars[checksum >> 4]);
310 putDebugChar(hexchars[checksum & 0xf]);
311
312 }
313 while ((getDebugChar() & 0x7f) != '+');
314}
315
316
317/*
318 * Convert the memory pointed to by mem into hex, placing result in buf.
319 * Return a pointer to the last char put in buf (null), in case of mem fault,
320 * return 0.
321 * may_fault is non-zero if we are reading from arbitrary memory, but is currently
322 * not used.
323 */
324static unsigned char *mem2hex(char *mem, char *buf, int count, int may_fault)
325{
326 unsigned char ch;
327
328 while (count-- > 0) {
329 if (kgdb_read_byte(mem++, &ch) != 0)
330 return 0;
331 *buf++ = hexchars[ch >> 4];
332 *buf++ = hexchars[ch & 0xf];
333 }
334
335 *buf = 0;
336
337 return buf;
338}
339
340/*
341 * convert the hex array pointed to by buf into binary to be placed in mem
342 * return a pointer to the character AFTER the last byte written
343 * may_fault is non-zero if we are reading from arbitrary memory, but is currently
344 * not used.
345 */
346static char *hex2mem(char *buf, char *mem, int count, int binary, int may_fault)
347{
348 int i;
349 unsigned char ch;
350
351 for (i=0; i<count; i++)
352 {
353 if (binary) {
354 ch = *buf++;
355 if (ch == 0x7d)
356 ch = 0x20 ^ *buf++;
357 }
358 else {
359 ch = hex(*buf++) << 4;
360 ch |= hex(*buf++);
361 }
362 if (kgdb_write_byte(ch, mem++) != 0)
363 return 0;
364 }
365
366 return mem;
367}
368
369/*
370 * This table contains the mapping between SPARC hardware trap types, and
371 * signals, which are primarily what GDB understands. It also indicates
372 * which hardware traps we need to commandeer when initializing the stub.
373 */
374static struct hard_trap_info {
375 unsigned char tt; /* Trap type code for MIPS R3xxx and R4xxx */
376 unsigned char signo; /* Signal that we map this trap into */
377} hard_trap_info[] = {
378 { 6, SIGBUS }, /* instruction bus error */
379 { 7, SIGBUS }, /* data bus error */
380 { 9, SIGTRAP }, /* break */
381 { 10, SIGILL }, /* reserved instruction */
382/* { 11, SIGILL }, */ /* CPU unusable */
383 { 12, SIGFPE }, /* overflow */
384 { 13, SIGTRAP }, /* trap */
385 { 14, SIGSEGV }, /* virtual instruction cache coherency */
386 { 15, SIGFPE }, /* floating point exception */
387 { 23, SIGSEGV }, /* watch */
388 { 31, SIGSEGV }, /* virtual data cache coherency */
389 { 0, 0} /* Must be last */
390};
391
392/* Save the normal trap handlers for user-mode traps. */
393void *saved_vectors[32];
394
395/*
396 * Set up exception handlers for tracing and breakpoints
397 */
398void set_debug_traps(void)
399{
400 struct hard_trap_info *ht;
401 unsigned long flags;
402 unsigned char c;
403
404 local_irq_save(flags);
405 for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
406 saved_vectors[ht->tt] = set_except_vector(ht->tt, trap_low);
407
408 putDebugChar('+'); /* 'hello world' */
409 /*
410 * In case GDB is started before us, ack any packets
411 * (presumably "$?#xx") sitting there.
412 */
413 while((c = getDebugChar()) != '$');
414 while((c = getDebugChar()) != '#');
415 c = getDebugChar(); /* eat first csum byte */
416 c = getDebugChar(); /* eat second csum byte */
417 putDebugChar('+'); /* ack it */
418
419 initialized = 1;
420 local_irq_restore(flags);
421}
422
423void restore_debug_traps(void)
424{
425 struct hard_trap_info *ht;
426 unsigned long flags;
427
428 local_irq_save(flags);
429 for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
430 set_except_vector(ht->tt, saved_vectors[ht->tt]);
431 local_irq_restore(flags);
432}
433
434/*
435 * Convert the MIPS hardware trap type code to a Unix signal number.
436 */
437static int computeSignal(int tt)
438{
439 struct hard_trap_info *ht;
440
441 for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
442 if (ht->tt == tt)
443 return ht->signo;
444
445 return SIGHUP; /* default for things we don't know about */
446}
447
448/*
449 * While we find nice hex chars, build an int.
450 * Return number of chars processed.
451 */
452static int hexToInt(char **ptr, int *intValue)
453{
454 int numChars = 0;
455 int hexValue;
456
457 *intValue = 0;
458
459 while (**ptr) {
460 hexValue = hex(**ptr);
461 if (hexValue < 0)
462 break;
463
464 *intValue = (*intValue << 4) | hexValue;
465 numChars ++;
466
467 (*ptr)++;
468 }
469
470 return (numChars);
471}
472
473static int hexToLong(char **ptr, long *longValue)
474{
475 int numChars = 0;
476 int hexValue;
477
478 *longValue = 0;
479
480 while (**ptr) {
481 hexValue = hex(**ptr);
482 if (hexValue < 0)
483 break;
484
485 *longValue = (*longValue << 4) | hexValue;
486 numChars ++;
487
488 (*ptr)++;
489 }
490
491 return numChars;
492}
493
494
495#if 0
496/*
497 * Print registers (on target console)
498 * Used only to debug the stub...
499 */
500void show_gdbregs(struct gdb_regs * regs)
501{
502 /*
503 * Saved main processor registers
504 */
505 printk("$0 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
506 regs->reg0, regs->reg1, regs->reg2, regs->reg3,
507 regs->reg4, regs->reg5, regs->reg6, regs->reg7);
508 printk("$8 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
509 regs->reg8, regs->reg9, regs->reg10, regs->reg11,
510 regs->reg12, regs->reg13, regs->reg14, regs->reg15);
511 printk("$16: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
512 regs->reg16, regs->reg17, regs->reg18, regs->reg19,
513 regs->reg20, regs->reg21, regs->reg22, regs->reg23);
514 printk("$24: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
515 regs->reg24, regs->reg25, regs->reg26, regs->reg27,
516 regs->reg28, regs->reg29, regs->reg30, regs->reg31);
517
518 /*
519 * Saved cp0 registers
520 */
521 printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\n",
522 regs->cp0_epc, regs->cp0_status, regs->cp0_cause);
523}
524#endif /* dead code */
525
526/*
527 * We single-step by setting breakpoints. When an exception
528 * is handled, we need to restore the instructions hoisted
529 * when the breakpoints were set.
530 *
531 * This is where we save the original instructions.
532 */
533static struct gdb_bp_save {
534 unsigned long addr;
535 unsigned int val;
536} step_bp[2];
537
538#define BP 0x0000000d /* break opcode */
539
540/*
541 * Set breakpoint instructions for single stepping.
542 */
543static void single_step(struct gdb_regs *regs)
544{
545 union mips_instruction insn;
546 unsigned long targ;
547 int is_branch, is_cond, i;
548
549 targ = regs->cp0_epc;
550 insn.word = *(unsigned int *)targ;
551 is_branch = is_cond = 0;
552
553 switch (insn.i_format.opcode) {
554 /*
555 * jr and jalr are in r_format format.
556 */
557 case spec_op:
558 switch (insn.r_format.func) {
559 case jalr_op:
560 case jr_op:
561 targ = *(&regs->reg0 + insn.r_format.rs);
562 is_branch = 1;
563 break;
564 }
565 break;
566
567 /*
568 * This group contains:
569 * bltz_op, bgez_op, bltzl_op, bgezl_op,
570 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
571 */
572 case bcond_op:
573 is_branch = is_cond = 1;
574 targ += 4 + (insn.i_format.simmediate << 2);
575 break;
576
577 /*
578 * These are unconditional and in j_format.
579 */
580 case jal_op:
581 case j_op:
582 is_branch = 1;
583 targ += 4;
584 targ >>= 28;
585 targ <<= 28;
586 targ |= (insn.j_format.target << 2);
587 break;
588
589 /*
590 * These are conditional.
591 */
592 case beq_op:
593 case beql_op:
594 case bne_op:
595 case bnel_op:
596 case blez_op:
597 case blezl_op:
598 case bgtz_op:
599 case bgtzl_op:
600 case cop0_op:
601 case cop1_op:
602 case cop2_op:
603 case cop1x_op:
604 is_branch = is_cond = 1;
605 targ += 4 + (insn.i_format.simmediate << 2);
606 break;
607 }
608
609 if (is_branch) {
610 i = 0;
611 if (is_cond && targ != (regs->cp0_epc + 8)) {
612 step_bp[i].addr = regs->cp0_epc + 8;
613 step_bp[i++].val = *(unsigned *)(regs->cp0_epc + 8);
614 *(unsigned *)(regs->cp0_epc + 8) = BP;
615 }
616 step_bp[i].addr = targ;
617 step_bp[i].val = *(unsigned *)targ;
618 *(unsigned *)targ = BP;
619 } else {
620 step_bp[0].addr = regs->cp0_epc + 4;
621 step_bp[0].val = *(unsigned *)(regs->cp0_epc + 4);
622 *(unsigned *)(regs->cp0_epc + 4) = BP;
623 }
624}
625
626/*
627 * If asynchronously interrupted by gdb, then we need to set a breakpoint
628 * at the interrupted instruction so that we wind up stopped with a
629 * reasonable stack frame.
630 */
631static struct gdb_bp_save async_bp;
632
633/*
634 * Swap the interrupted EPC with our asynchronous breakpoint routine.
635 * This is safer than stuffing the breakpoint in-place, since no cache
636 * flushes (or resulting smp_call_functions) are required. The
637 * assumption is that only one CPU will be handling asynchronous bp's,
638 * and only one can be active at a time.
639 */
640extern spinlock_t smp_call_lock;
641
642void set_async_breakpoint(unsigned long *epc)
643{
644 /* skip breaking into userland */
645 if ((*epc & 0x80000000) == 0)
646 return;
647
648#ifdef CONFIG_SMP
649 /* avoid deadlock if someone is make IPC */
650 if (spin_is_locked(&smp_call_lock))
651 return;
652#endif
653
654 async_bp.addr = *epc;
655 *epc = (unsigned long)async_breakpoint;
656}
657
658#ifdef CONFIG_SMP
659static void kgdb_wait(void *arg)
660{
661 unsigned flags;
662 int cpu = smp_processor_id();
663
664 local_irq_save(flags);
665
666 __raw_spin_lock(&kgdb_cpulock[cpu]);
667 __raw_spin_unlock(&kgdb_cpulock[cpu]);
668
669 local_irq_restore(flags);
670}
671#endif
672
673/*
674 * GDB stub needs to call kgdb_wait on all processor with interrupts
675 * disabled, so it uses it's own special variant.
676 */
677static int kgdb_smp_call_kgdb_wait(void)
678{
679#ifdef CONFIG_SMP
680 cpumask_t mask = cpu_online_map;
681 struct call_data_struct data;
682 int cpu = smp_processor_id();
683 int cpus;
684
685 /*
686 * Can die spectacularly if this CPU isn't yet marked online
687 */
688 BUG_ON(!cpu_online(cpu));
689
690 cpu_clear(cpu, mask);
691 cpus = cpus_weight(mask);
692 if (!cpus)
693 return 0;
694
695 if (spin_is_locked(&smp_call_lock)) {
696 /*
697 * Some other processor is trying to make us do something
698 * but we're not going to respond... give up
699 */
700 return -1;
701 }
702
703 /*
704 * We will continue here, accepting the fact that
705 * the kernel may deadlock if another CPU attempts
706 * to call smp_call_function now...
707 */
708
709 data.func = kgdb_wait;
710 data.info = NULL;
711 atomic_set(&data.started, 0);
712 data.wait = 0;
713
714 spin_lock(&smp_call_lock);
715 call_data = &data;
716 mb();
717
718 core_send_ipi_mask(mask, SMP_CALL_FUNCTION);
719
720 /* Wait for response */
721 /* FIXME: lock-up detection, backtrace on lock-up */
722 while (atomic_read(&data.started) != cpus)
723 barrier();
724
725 call_data = NULL;
726 spin_unlock(&smp_call_lock);
727#endif
728
729 return 0;
730}
731
732/*
733 * This function does all command processing for interfacing to gdb. It
734 * returns 1 if you should skip the instruction at the trap address, 0
735 * otherwise.
736 */
737void handle_exception(struct gdb_regs *regs)
738{
739 int trap; /* Trap type */
740 int sigval;
741 long addr;
742 int length;
743 char *ptr;
744 unsigned long *stack;
745 int i;
746 int bflag = 0;
747
748 kgdb_started = 1;
749
750 /*
751 * acquire the big kgdb spinlock
752 */
753 if (!spin_trylock(&kgdb_lock)) {
754 /*
755 * some other CPU has the lock, we should go back to
756 * receive the gdb_wait IPC
757 */
758 return;
759 }
760
761 /*
762 * If we're in async_breakpoint(), restore the real EPC from
763 * the breakpoint.
764 */
765 if (regs->cp0_epc == (unsigned long)async_breakinst) {
766 regs->cp0_epc = async_bp.addr;
767 async_bp.addr = 0;
768 }
769
770 /*
771 * acquire the CPU spinlocks
772 */
773 for_each_online_cpu(i)
774 if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0)
775 panic("kgdb: couldn't get cpulock %d\n", i);
776
777 /*
778 * force other cpus to enter kgdb
779 */
780 kgdb_smp_call_kgdb_wait();
781
782 /*
783 * If we're in breakpoint() increment the PC
784 */
785 trap = (regs->cp0_cause & 0x7c) >> 2;
786 if (trap == 9 && regs->cp0_epc == (unsigned long)breakinst)
787 regs->cp0_epc += 4;
788
789 /*
790 * If we were single_stepping, restore the opcodes hoisted
791 * for the breakpoint[s].
792 */
793 if (step_bp[0].addr) {
794 *(unsigned *)step_bp[0].addr = step_bp[0].val;
795 step_bp[0].addr = 0;
796
797 if (step_bp[1].addr) {
798 *(unsigned *)step_bp[1].addr = step_bp[1].val;
799 step_bp[1].addr = 0;
800 }
801 }
802
803 stack = (long *)regs->reg29; /* stack ptr */
804 sigval = computeSignal(trap);
805
806 /*
807 * reply to host that an exception has occurred
808 */
809 ptr = output_buffer;
810
811 /*
812 * Send trap type (converted to signal)
813 */
814 *ptr++ = 'T';
815 *ptr++ = hexchars[sigval >> 4];
816 *ptr++ = hexchars[sigval & 0xf];
817
818 /*
819 * Send Error PC
820 */
821 *ptr++ = hexchars[REG_EPC >> 4];
822 *ptr++ = hexchars[REG_EPC & 0xf];
823 *ptr++ = ':';
824 ptr = mem2hex((char *)&regs->cp0_epc, ptr, sizeof(long), 0);
825 *ptr++ = ';';
826
827 /*
828 * Send frame pointer
829 */
830 *ptr++ = hexchars[REG_FP >> 4];
831 *ptr++ = hexchars[REG_FP & 0xf];
832 *ptr++ = ':';
833 ptr = mem2hex((char *)&regs->reg30, ptr, sizeof(long), 0);
834 *ptr++ = ';';
835
836 /*
837 * Send stack pointer
838 */
839 *ptr++ = hexchars[REG_SP >> 4];
840 *ptr++ = hexchars[REG_SP & 0xf];
841 *ptr++ = ':';
842 ptr = mem2hex((char *)&regs->reg29, ptr, sizeof(long), 0);
843 *ptr++ = ';';
844
845 *ptr++ = 0;
846 putpacket(output_buffer); /* send it off... */
847
848 /*
849 * Wait for input from remote GDB
850 */
851 while (1) {
852 output_buffer[0] = 0;
853 getpacket(input_buffer);
854
855 switch (input_buffer[0])
856 {
857 case '?':
858 output_buffer[0] = 'S';
859 output_buffer[1] = hexchars[sigval >> 4];
860 output_buffer[2] = hexchars[sigval & 0xf];
861 output_buffer[3] = 0;
862 break;
863
864 /*
865 * Detach debugger; let CPU run
866 */
867 case 'D':
868 putpacket(output_buffer);
869 goto finish_kgdb;
870 break;
871
872 case 'd':
873 /* toggle debug flag */
874 break;
875
876 /*
877 * Return the value of the CPU registers
878 */
879 case 'g':
880 ptr = output_buffer;
881 ptr = mem2hex((char *)&regs->reg0, ptr, 32*sizeof(long), 0); /* r0...r31 */
882 ptr = mem2hex((char *)&regs->cp0_status, ptr, 6*sizeof(long), 0); /* cp0 */
883 ptr = mem2hex((char *)&regs->fpr0, ptr, 32*sizeof(long), 0); /* f0...31 */
884 ptr = mem2hex((char *)&regs->cp1_fsr, ptr, 2*sizeof(long), 0); /* cp1 */
885 ptr = mem2hex((char *)&regs->frame_ptr, ptr, 2*sizeof(long), 0); /* frp */
886 ptr = mem2hex((char *)&regs->cp0_index, ptr, 16*sizeof(long), 0); /* cp0 */
887 break;
888
889 /*
890 * set the value of the CPU registers - return OK
891 */
892 case 'G':
893 {
894 ptr = &input_buffer[1];
895 hex2mem(ptr, (char *)&regs->reg0, 32*sizeof(long), 0, 0);
896 ptr += 32*(2*sizeof(long));
897 hex2mem(ptr, (char *)&regs->cp0_status, 6*sizeof(long), 0, 0);
898 ptr += 6*(2*sizeof(long));
899 hex2mem(ptr, (char *)&regs->fpr0, 32*sizeof(long), 0, 0);
900 ptr += 32*(2*sizeof(long));
901 hex2mem(ptr, (char *)&regs->cp1_fsr, 2*sizeof(long), 0, 0);
902 ptr += 2*(2*sizeof(long));
903 hex2mem(ptr, (char *)&regs->frame_ptr, 2*sizeof(long), 0, 0);
904 ptr += 2*(2*sizeof(long));
905 hex2mem(ptr, (char *)&regs->cp0_index, 16*sizeof(long), 0, 0);
906 strcpy(output_buffer, "OK");
907 }
908 break;
909
910 /*
911 * mAA..AA,LLLL Read LLLL bytes at address AA..AA
912 */
913 case 'm':
914 ptr = &input_buffer[1];
915
916 if (hexToLong(&ptr, &addr)
917 && *ptr++ == ','
918 && hexToInt(&ptr, &length)) {
919 if (mem2hex((char *)addr, output_buffer, length, 1))
920 break;
921 strcpy(output_buffer, "E03");
922 } else
923 strcpy(output_buffer, "E01");
924 break;
925
926 /*
927 * XAA..AA,LLLL: Write LLLL escaped binary bytes at address AA.AA
928 */
929 case 'X':
930 bflag = 1;
931 /* fall through */
932
933 /*
934 * MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK
935 */
936 case 'M':
937 ptr = &input_buffer[1];
938
939 if (hexToLong(&ptr, &addr)
940 && *ptr++ == ','
941 && hexToInt(&ptr, &length)
942 && *ptr++ == ':') {
943 if (hex2mem(ptr, (char *)addr, length, bflag, 1))
944 strcpy(output_buffer, "OK");
945 else
946 strcpy(output_buffer, "E03");
947 }
948 else
949 strcpy(output_buffer, "E02");
950 break;
951
952 /*
953 * cAA..AA Continue at address AA..AA(optional)
954 */
955 case 'c':
956 /* try to read optional parameter, pc unchanged if no parm */
957
958 ptr = &input_buffer[1];
959 if (hexToLong(&ptr, &addr))
960 regs->cp0_epc = addr;
961
962 goto exit_kgdb_exception;
963 break;
964
965 /*
966 * kill the program; let us try to restart the machine
967 * Reset the whole machine.
968 */
969 case 'k':
970 case 'r':
971 machine_restart("kgdb restarts machine");
972 break;
973
974 /*
975 * Step to next instruction
976 */
977 case 's':
978 /*
979 * There is no single step insn in the MIPS ISA, so we
980 * use breakpoints and continue, instead.
981 */
982 single_step(regs);
983 goto exit_kgdb_exception;
984 /* NOTREACHED */
985 break;
986
987 /*
988 * Set baud rate (bBB)
989 * FIXME: Needs to be written
990 */
991 case 'b':
992 {
993#if 0
994 int baudrate;
995 extern void set_timer_3();
996
997 ptr = &input_buffer[1];
998 if (!hexToInt(&ptr, &baudrate))
999 {
1000 strcpy(output_buffer, "B01");
1001 break;
1002 }
1003
1004 /* Convert baud rate to uart clock divider */
1005
1006 switch (baudrate)
1007 {
1008 case 38400:
1009 baudrate = 16;
1010 break;
1011 case 19200:
1012 baudrate = 33;
1013 break;
1014 case 9600:
1015 baudrate = 65;
1016 break;
1017 default:
1018 baudrate = 0;
1019 strcpy(output_buffer, "B02");
1020 goto x1;
1021 }
1022
1023 if (baudrate) {
1024 putpacket("OK"); /* Ack before changing speed */
1025 set_timer_3(baudrate); /* Set it */
1026 }
1027#endif
1028 }
1029 break;
1030
1031 } /* switch */
1032
1033 /*
1034 * reply to the request
1035 */
1036
1037 putpacket(output_buffer);
1038
1039 } /* while */
1040
1041 return;
1042
1043finish_kgdb:
1044 restore_debug_traps();
1045
1046exit_kgdb_exception:
1047 /* release locks so other CPUs can go */
1048 for_each_online_cpu(i)
1049 __raw_spin_unlock(&kgdb_cpulock[i]);
1050 spin_unlock(&kgdb_lock);
1051
1052 __flush_cache_all();
1053 return;
1054}
1055
1056/*
1057 * This function will generate a breakpoint exception. It is used at the
1058 * beginning of a program to sync up with a debugger and can be used
1059 * otherwise as a quick means to stop program execution and "break" into
1060 * the debugger.
1061 */
1062void breakpoint(void)
1063{
1064 if (!initialized)
1065 return;
1066
1067 __asm__ __volatile__(
1068 ".globl breakinst\n\t"
1069 ".set\tnoreorder\n\t"
1070 "nop\n"
1071 "breakinst:\tbreak\n\t"
1072 "nop\n\t"
1073 ".set\treorder"
1074 );
1075}
1076
1077/* Nothing but the break; don't pollute any registers */
1078void async_breakpoint(void)
1079{
1080 __asm__ __volatile__(
1081 ".globl async_breakinst\n\t"
1082 ".set\tnoreorder\n\t"
1083 "nop\n"
1084 "async_breakinst:\tbreak\n\t"
1085 "nop\n\t"
1086 ".set\treorder"
1087 );
1088}
1089
1090void adel(void)
1091{
1092 __asm__ __volatile__(
1093 ".globl\tadel\n\t"
1094 "lui\t$8,0x8000\n\t"
1095 "lw\t$9,1($8)\n\t"
1096 );
1097}
1098
1099/*
1100 * malloc is needed by gdb client in "call func()", even a private one
1101 * will make gdb happy
1102 */
1103static void __used *malloc(size_t size)
1104{
1105 return kmalloc(size, GFP_ATOMIC);
1106}
1107
1108static void __used free(void *where)
1109{
1110 kfree(where);
1111}
1112
1113#ifdef CONFIG_GDB_CONSOLE
1114
1115void gdb_putsn(const char *str, int l)
1116{
1117 char outbuf[18];
1118
1119 if (!kgdb_started)
1120 return;
1121
1122 outbuf[0]='O';
1123
1124 while(l) {
1125 int i = (l>8)?8:l;
1126 mem2hex((char *)str, &outbuf[1], i, 0);
1127 outbuf[(i*2)+1]=0;
1128 putpacket(outbuf);
1129 str += i;
1130 l -= i;
1131 }
1132}
1133
1134static void gdb_console_write(struct console *con, const char *s, unsigned n)
1135{
1136 gdb_putsn(s, n);
1137}
1138
1139static struct console gdb_console = {
1140 .name = "gdb",
1141 .write = gdb_console_write,
1142 .flags = CON_PRINTBUFFER,
1143 .index = -1
1144};
1145
1146static int __init register_gdb_console(void)
1147{
1148 register_console(&gdb_console);
1149
1150 return 0;
1151}
1152
1153console_initcall(register_gdb_console);
1154
1155#endif
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 6045b9a51a3..4b4007b3083 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -21,11 +21,16 @@
21#include <linux/sched.h> 21#include <linux/sched.h>
22#include <linux/seq_file.h> 22#include <linux/seq_file.h>
23#include <linux/kallsyms.h> 23#include <linux/kallsyms.h>
24#include <linux/kgdb.h>
24 25
25#include <asm/atomic.h> 26#include <asm/atomic.h>
26#include <asm/system.h> 27#include <asm/system.h>
27#include <asm/uaccess.h> 28#include <asm/uaccess.h>
28 29
30#ifdef CONFIG_KGDB
31int kgdb_early_setup;
32#endif
33
29static unsigned long irq_map[NR_IRQS / BITS_PER_LONG]; 34static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
30 35
31int allocate_irqno(void) 36int allocate_irqno(void)
@@ -126,33 +131,22 @@ asmlinkage void spurious_interrupt(void)
126 atomic_inc(&irq_err_count); 131 atomic_inc(&irq_err_count);
127} 132}
128 133
129#ifdef CONFIG_KGDB
130extern void breakpoint(void);
131extern void set_debug_traps(void);
132
133static int kgdb_flag = 1;
134static int __init nokgdb(char *str)
135{
136 kgdb_flag = 0;
137 return 1;
138}
139__setup("nokgdb", nokgdb);
140#endif
141
142void __init init_IRQ(void) 134void __init init_IRQ(void)
143{ 135{
144 int i; 136 int i;
145 137
138#ifdef CONFIG_KGDB
139 if (kgdb_early_setup)
140 return;
141#endif
142
146 for (i = 0; i < NR_IRQS; i++) 143 for (i = 0; i < NR_IRQS; i++)
147 set_irq_noprobe(i); 144 set_irq_noprobe(i);
148 145
149 arch_init_irq(); 146 arch_init_irq();
150 147
151#ifdef CONFIG_KGDB 148#ifdef CONFIG_KGDB
152 if (kgdb_flag) { 149 if (!kgdb_early_setup)
153 printk("Wait for gdb client connection ...\n"); 150 kgdb_early_setup = 1;
154 set_debug_traps();
155 breakpoint();
156 }
157#endif 151#endif
158} 152}
diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c
new file mode 100644
index 00000000000..c5a8b2d21ca
--- /dev/null
+++ b/arch/mips/kernel/kgdb.c
@@ -0,0 +1,281 @@
1/*
2 * Originally written by Glenn Engel, Lake Stevens Instrument Division
3 *
4 * Contributed by HP Systems
5 *
6 * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
7 * Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
8 *
9 * Copyright (C) 1995 Andreas Busse
10 *
11 * Copyright (C) 2003 MontaVista Software Inc.
12 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
13 *
14 * Copyright (C) 2004-2005 MontaVista Software Inc.
15 * Author: Manish Lachwani, mlachwani@mvista.com or manish@koffee-break.com
16 *
17 * Copyright (C) 2007-2008 Wind River Systems, Inc.
18 * Author/Maintainer: Jason Wessel, jason.wessel@windriver.com
19 *
20 * This file is licensed under the terms of the GNU General Public License
21 * version 2. This program is licensed "as is" without any warranty of any
22 * kind, whether express or implied.
23 */
24
25#include <linux/ptrace.h> /* for linux pt_regs struct */
26#include <linux/kgdb.h>
27#include <linux/kdebug.h>
28#include <linux/sched.h>
29#include <asm/inst.h>
30#include <asm/fpu.h>
31#include <asm/cacheflush.h>
32#include <asm/processor.h>
33#include <asm/sigcontext.h>
34
35static struct hard_trap_info {
36 unsigned char tt; /* Trap type code for MIPS R3xxx and R4xxx */
37 unsigned char signo; /* Signal that we map this trap into */
38} hard_trap_info[] = {
39 { 6, SIGBUS }, /* instruction bus error */
40 { 7, SIGBUS }, /* data bus error */
41 { 9, SIGTRAP }, /* break */
42/* { 11, SIGILL }, */ /* CPU unusable */
43 { 12, SIGFPE }, /* overflow */
44 { 13, SIGTRAP }, /* trap */
45 { 14, SIGSEGV }, /* virtual instruction cache coherency */
46 { 15, SIGFPE }, /* floating point exception */
47 { 23, SIGSEGV }, /* watch */
48 { 31, SIGSEGV }, /* virtual data cache coherency */
49 { 0, 0} /* Must be last */
50};
51
52void arch_kgdb_breakpoint(void)
53{
54 __asm__ __volatile__(
55 ".globl breakinst\n\t"
56 ".set\tnoreorder\n\t"
57 "nop\n"
58 "breakinst:\tbreak\n\t"
59 "nop\n\t"
60 ".set\treorder");
61}
62
63static void kgdb_call_nmi_hook(void *ignored)
64{
65 kgdb_nmicallback(raw_smp_processor_id(), (void *)0);
66}
67
68void kgdb_roundup_cpus(unsigned long flags)
69{
70 local_irq_enable();
71 smp_call_function(kgdb_call_nmi_hook, NULL, NULL);
72 local_irq_disable();
73}
74
75static int compute_signal(int tt)
76{
77 struct hard_trap_info *ht;
78
79 for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
80 if (ht->tt == tt)
81 return ht->signo;
82
83 return SIGHUP; /* default for things we don't know about */
84}
85
86void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
87{
88 int reg;
89
90#if (KGDB_GDB_REG_SIZE == 32)
91 u32 *ptr = (u32 *)gdb_regs;
92#else
93 u64 *ptr = (u64 *)gdb_regs;
94#endif
95
96 for (reg = 0; reg < 32; reg++)
97 *(ptr++) = regs->regs[reg];
98
99 *(ptr++) = regs->cp0_status;
100 *(ptr++) = regs->lo;
101 *(ptr++) = regs->hi;
102 *(ptr++) = regs->cp0_badvaddr;
103 *(ptr++) = regs->cp0_cause;
104 *(ptr++) = regs->cp0_epc;
105
106 /* FP REGS */
107 if (!(current && (regs->cp0_status & ST0_CU1)))
108 return;
109
110 save_fp(current);
111 for (reg = 0; reg < 32; reg++)
112 *(ptr++) = current->thread.fpu.fpr[reg];
113}
114
115void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
116{
117 int reg;
118
119#if (KGDB_GDB_REG_SIZE == 32)
120 const u32 *ptr = (u32 *)gdb_regs;
121#else
122 const u64 *ptr = (u64 *)gdb_regs;
123#endif
124
125 for (reg = 0; reg < 32; reg++)
126 regs->regs[reg] = *(ptr++);
127
128 regs->cp0_status = *(ptr++);
129 regs->lo = *(ptr++);
130 regs->hi = *(ptr++);
131 regs->cp0_badvaddr = *(ptr++);
132 regs->cp0_cause = *(ptr++);
133 regs->cp0_epc = *(ptr++);
134
135 /* FP REGS from current */
136 if (!(current && (regs->cp0_status & ST0_CU1)))
137 return;
138
139 for (reg = 0; reg < 32; reg++)
140 current->thread.fpu.fpr[reg] = *(ptr++);
141 restore_fp(current);
142}
143
144/*
145 * Similar to regs_to_gdb_regs() except that process is sleeping and so
146 * we may not be able to get all the info.
147 */
148void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
149{
150 int reg;
151 struct thread_info *ti = task_thread_info(p);
152 unsigned long ksp = (unsigned long)ti + THREAD_SIZE - 32;
153 struct pt_regs *regs = (struct pt_regs *)ksp - 1;
154#if (KGDB_GDB_REG_SIZE == 32)
155 u32 *ptr = (u32 *)gdb_regs;
156#else
157 u64 *ptr = (u64 *)gdb_regs;
158#endif
159
160 for (reg = 0; reg < 16; reg++)
161 *(ptr++) = regs->regs[reg];
162
163 /* S0 - S7 */
164 for (reg = 16; reg < 24; reg++)
165 *(ptr++) = regs->regs[reg];
166
167 for (reg = 24; reg < 28; reg++)
168 *(ptr++) = 0;
169
170 /* GP, SP, FP, RA */
171 for (reg = 28; reg < 32; reg++)
172 *(ptr++) = regs->regs[reg];
173
174 *(ptr++) = regs->cp0_status;
175 *(ptr++) = regs->lo;
176 *(ptr++) = regs->hi;
177 *(ptr++) = regs->cp0_badvaddr;
178 *(ptr++) = regs->cp0_cause;
179 *(ptr++) = regs->cp0_epc;
180}
181
182/*
183 * Calls linux_debug_hook before the kernel dies. If KGDB is enabled,
184 * then try to fall into the debugger
185 */
186static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd,
187 void *ptr)
188{
189 struct die_args *args = (struct die_args *)ptr;
190 struct pt_regs *regs = args->regs;
191 int trap = (regs->cp0_cause & 0x7c) >> 2;
192
193 if (fixup_exception(regs))
194 return NOTIFY_DONE;
195
196 /* Userpace events, ignore. */
197 if (user_mode(regs))
198 return NOTIFY_DONE;
199
200 if (atomic_read(&kgdb_active) != -1)
201 kgdb_nmicallback(smp_processor_id(), regs);
202
203 if (kgdb_handle_exception(trap, compute_signal(trap), 0, regs))
204 return NOTIFY_DONE;
205
206 if (atomic_read(&kgdb_setting_breakpoint))
207 if ((trap == 9) && (regs->cp0_epc == (unsigned long)breakinst))
208 regs->cp0_epc += 4;
209
210 /* In SMP mode, __flush_cache_all does IPI */
211 local_irq_enable();
212 __flush_cache_all();
213
214 return NOTIFY_STOP;
215}
216
217static struct notifier_block kgdb_notifier = {
218 .notifier_call = kgdb_mips_notify,
219};
220
221/*
222 * Handle the 's' and 'c' commands
223 */
224int kgdb_arch_handle_exception(int vector, int signo, int err_code,
225 char *remcom_in_buffer, char *remcom_out_buffer,
226 struct pt_regs *regs)
227{
228 char *ptr;
229 unsigned long address;
230 int cpu = smp_processor_id();
231
232 switch (remcom_in_buffer[0]) {
233 case 's':
234 case 'c':
235 /* handle the optional parameter */
236 ptr = &remcom_in_buffer[1];
237 if (kgdb_hex2long(&ptr, &address))
238 regs->cp0_epc = address;
239
240 atomic_set(&kgdb_cpu_doing_single_step, -1);
241 if (remcom_in_buffer[0] == 's')
242 if (kgdb_contthread)
243 atomic_set(&kgdb_cpu_doing_single_step, cpu);
244
245 return 0;
246 }
247
248 return -1;
249}
250
251struct kgdb_arch arch_kgdb_ops;
252
253/*
254 * We use kgdb_early_setup so that functions we need to call now don't
255 * cause trouble when called again later.
256 */
257int kgdb_arch_init(void)
258{
259 union mips_instruction insn = {
260 .r_format = {
261 .opcode = spec_op,
262 .func = break_op,
263 }
264 };
265 memcpy(arch_kgdb_ops.gdb_bpt_instr, insn.byte, BREAK_INSTR_SIZE);
266
267 register_die_notifier(&kgdb_notifier);
268
269 return 0;
270}
271
272/*
273 * kgdb_arch_exit - Perform any architecture specific uninitalization.
274 *
275 * This function will handle the uninitalization of any architecture
276 * specific callbacks, for dynamic registration and unregistration.
277 */
278void kgdb_arch_exit(void)
279{
280 unregister_die_notifier(&kgdb_notifier);
281}
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index b8ea4e9d0d8..426cced1e9d 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -23,6 +23,8 @@
23#include <linux/bootmem.h> 23#include <linux/bootmem.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/ptrace.h> 25#include <linux/ptrace.h>
26#include <linux/kgdb.h>
27#include <linux/kdebug.h>
26 28
27#include <asm/bootinfo.h> 29#include <asm/bootinfo.h>
28#include <asm/branch.h> 30#include <asm/branch.h>
@@ -425,6 +427,10 @@ asmlinkage void do_be(struct pt_regs *regs)
425 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 427 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
426 data ? "Data" : "Instruction", 428 data ? "Data" : "Instruction",
427 field, regs->cp0_epc, field, regs->regs[31]); 429 field, regs->cp0_epc, field, regs->regs[31]);
430 if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0)
431 == NOTIFY_STOP)
432 return;
433
428 die_if_kernel("Oops", regs); 434 die_if_kernel("Oops", regs);
429 force_sig(SIGBUS, current); 435 force_sig(SIGBUS, current);
430} 436}
@@ -623,6 +629,9 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
623{ 629{
624 siginfo_t info; 630 siginfo_t info;
625 631
632 if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0)
633 == NOTIFY_STOP)
634 return;
626 die_if_kernel("FP exception in kernel code", regs); 635 die_if_kernel("FP exception in kernel code", regs);
627 636
628 if (fcr31 & FPU_CSR_UNI_X) { 637 if (fcr31 & FPU_CSR_UNI_X) {
@@ -682,6 +691,9 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
682 siginfo_t info; 691 siginfo_t info;
683 char b[40]; 692 char b[40];
684 693
694 if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP)
695 return;
696
685 /* 697 /*
686 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 698 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
687 * insns, even for trap and break codes that indicate arithmetic 699 * insns, even for trap and break codes that indicate arithmetic
@@ -762,6 +774,10 @@ asmlinkage void do_ri(struct pt_regs *regs)
762 unsigned int opcode = 0; 774 unsigned int opcode = 0;
763 int status = -1; 775 int status = -1;
764 776
777 if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0)
778 == NOTIFY_STOP)
779 return;
780
765 die_if_kernel("Reserved instruction in kernel code", regs); 781 die_if_kernel("Reserved instruction in kernel code", regs);
766 782
767 if (unlikely(compute_return_epc(regs) < 0)) 783 if (unlikely(compute_return_epc(regs) < 0))
@@ -1537,6 +1553,11 @@ void __init trap_init(void)
1537 extern char except_vec4; 1553 extern char except_vec4;
1538 unsigned long i; 1554 unsigned long i;
1539 1555
1556#if defined(CONFIG_KGDB)
1557 if (kgdb_early_setup)
1558 return; /* Already done */
1559#endif
1560
1540 if (cpu_has_veic || cpu_has_vint) 1561 if (cpu_has_veic || cpu_has_vint)
1541 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); 1562 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
1542 else 1563 else
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index a782549ac80..f0cf46adb97 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -246,10 +246,6 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
246 old_pagemask = read_c0_pagemask(); 246 old_pagemask = read_c0_pagemask();
247 w = read_c0_wired(); 247 w = read_c0_wired();
248 write_c0_wired(w + 1); 248 write_c0_wired(w + 1);
249 if (read_c0_wired() != w + 1) {
250 printk("[tlbwired] No WIRED reg?\n");
251 return;
252 }
253 write_c0_index(w << 8); 249 write_c0_index(w << 8);
254 write_c0_pagemask(pagemask); 250 write_c0_pagemask(pagemask);
255 write_c0_entryhi(entryhi); 251 write_c0_entryhi(entryhi);
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index f8064446e81..3b7dd722c32 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -13,7 +13,6 @@ obj-y := malta-amon.o malta-cmdline.o \
13 13
14obj-$(CONFIG_EARLY_PRINTK) += malta-console.o 14obj-$(CONFIG_EARLY_PRINTK) += malta-console.o
15obj-$(CONFIG_PCI) += malta-pci.o 15obj-$(CONFIG_PCI) += malta-pci.o
16obj-$(CONFIG_KGDB) += malta-kgdb.o
17 16
18# FIXME FIXME FIXME 17# FIXME FIXME FIXME
19obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o 18obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index c0653021a17..4832af25166 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -37,15 +37,6 @@
37 37
38#include <asm/mips-boards/malta.h> 38#include <asm/mips-boards/malta.h>
39 39
40#ifdef CONFIG_KGDB
41extern int rs_kgdb_hook(int, int);
42extern int rs_putDebugChar(char);
43extern char rs_getDebugChar(void);
44extern int saa9730_kgdb_hook(int);
45extern int saa9730_putDebugChar(char);
46extern char saa9730_getDebugChar(void);
47#endif
48
49int prom_argc; 40int prom_argc;
50int *_prom_argv, *_prom_envp; 41int *_prom_argv, *_prom_envp;
51 42
@@ -173,51 +164,6 @@ static void __init console_config(void)
173} 164}
174#endif 165#endif
175 166
176#ifdef CONFIG_KGDB
177void __init kgdb_config(void)
178{
179 extern int (*generic_putDebugChar)(char);
180 extern char (*generic_getDebugChar)(void);
181 char *argptr;
182 int line, speed;
183
184 argptr = prom_getcmdline();
185 if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
186 argptr += strlen("kgdb=ttyS");
187 if (*argptr != '0' && *argptr != '1')
188 printk("KGDB: Unknown serial line /dev/ttyS%c, "
189 "falling back to /dev/ttyS1\n", *argptr);
190 line = *argptr == '0' ? 0 : 1;
191 printk("KGDB: Using serial line /dev/ttyS%d for session\n", line);
192
193 speed = 0;
194 if (*++argptr == ',')
195 {
196 int c;
197 while ((c = *++argptr) && ('0' <= c && c <= '9'))
198 speed = speed * 10 + c - '0';
199 }
200 {
201 speed = rs_kgdb_hook(line, speed);
202 generic_putDebugChar = rs_putDebugChar;
203 generic_getDebugChar = rs_getDebugChar;
204 }
205
206 pr_info("KGDB: Using serial line /dev/ttyS%d at %d for "
207 "session, please connect your debugger\n",
208 line ? 1 : 0, speed);
209
210 {
211 char *s;
212 for (s = "Please connect GDB to this port\r\n"; *s; )
213 generic_putDebugChar(*s++);
214 }
215
216 /* Breakpoint is invoked after interrupts are initialised */
217 }
218}
219#endif
220
221static void __init mips_nmi_setup(void) 167static void __init mips_nmi_setup(void)
222{ 168{
223 void *base; 169 void *base;
diff --git a/arch/mips/mti-malta/malta-kgdb.c b/arch/mips/mti-malta/malta-kgdb.c
deleted file mode 100644
index 6a1854de457..00000000000
--- a/arch/mips/mti-malta/malta-kgdb.c
+++ /dev/null
@@ -1,133 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * This is the interface to the remote debugger stub.
19 */
20#include <linux/types.h>
21#include <linux/serial.h>
22#include <linux/serialP.h>
23#include <linux/serial_reg.h>
24
25#include <asm/serial.h>
26#include <asm/io.h>
27
28static struct serial_state rs_table[] = {
29 SERIAL_PORT_DFNS /* Defined in serial.h */
30};
31
32static struct async_struct kdb_port_info = {0};
33
34int (*generic_putDebugChar)(char);
35char (*generic_getDebugChar)(void);
36
37static __inline__ unsigned int serial_in(struct async_struct *info, int offset)
38{
39 return inb(info->port + offset);
40}
41
42static __inline__ void serial_out(struct async_struct *info, int offset,
43 int value)
44{
45 outb(value, info->port+offset);
46}
47
48int rs_kgdb_hook(int tty_no, int speed) {
49 int t;
50 struct serial_state *ser = &rs_table[tty_no];
51
52 kdb_port_info.state = ser;
53 kdb_port_info.magic = SERIAL_MAGIC;
54 kdb_port_info.port = ser->port;
55 kdb_port_info.flags = ser->flags;
56
57 /*
58 * Clear all interrupts
59 */
60 serial_in(&kdb_port_info, UART_LSR);
61 serial_in(&kdb_port_info, UART_RX);
62 serial_in(&kdb_port_info, UART_IIR);
63 serial_in(&kdb_port_info, UART_MSR);
64
65 /*
66 * Now, initialize the UART
67 */
68 serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */
69 if (kdb_port_info.flags & ASYNC_FOURPORT) {
70 kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS;
71 t = UART_MCR_DTR | UART_MCR_OUT1;
72 } else {
73 kdb_port_info.MCR
74 = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2;
75 t = UART_MCR_DTR | UART_MCR_RTS;
76 }
77
78 kdb_port_info.MCR = t; /* no interrupts, please */
79 serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR);
80
81 /*
82 * and set the speed of the serial port
83 */
84 if (speed == 0)
85 speed = 9600;
86
87 t = kdb_port_info.state->baud_base / speed;
88 /* set DLAB */
89 serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB);
90 serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */
91 serial_out(&kdb_port_info, UART_DLM, t >> 8); /* MS of divisor */
92 /* reset DLAB */
93 serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8);
94
95 return speed;
96}
97
98int putDebugChar(char c)
99{
100 return generic_putDebugChar(c);
101}
102
103char getDebugChar(void)
104{
105 return generic_getDebugChar();
106}
107
108int rs_putDebugChar(char c)
109{
110
111 if (!kdb_port_info.state) { /* need to init device first */
112 return 0;
113 }
114
115 while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0)
116 ;
117
118 serial_out(&kdb_port_info, UART_TX, c);
119
120 return 1;
121}
122
123char rs_getDebugChar(void)
124{
125 if (!kdb_port_info.state) { /* need to init device first */
126 return 0;
127 }
128
129 while (!(serial_in(&kdb_port_info, UART_LSR) & 1))
130 ;
131
132 return serial_in(&kdb_port_info, UART_RX);
133}
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index e7cad54936c..dc78b8983ee 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -199,10 +199,6 @@ void __init plat_mem_setup(void)
199 */ 199 */
200 enable_dma(4); 200 enable_dma(4);
201 201
202#ifdef CONFIG_KGDB
203 kgdb_config();
204#endif
205
206#ifdef CONFIG_DMA_COHERENT 202#ifdef CONFIG_DMA_COHERENT
207 if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO) 203 if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
208 panic("Hardware DMA cache coherency not supported"); 204 panic("Hardware DMA cache coherency not supported");
diff --git a/arch/mips/nxp/pnx8550/common/Makefile b/arch/mips/nxp/pnx8550/common/Makefile
index 31cc1a5cec3..dd9e7b1f7fd 100644
--- a/arch/mips/nxp/pnx8550/common/Makefile
+++ b/arch/mips/nxp/pnx8550/common/Makefile
@@ -24,6 +24,5 @@
24 24
25obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o 25obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o
26obj-$(CONFIG_PCI) += pci.o 26obj-$(CONFIG_PCI) += pci.o
27obj-$(CONFIG_KGDB) += gdb_hook.o
28 27
29EXTRA_CFLAGS += -Werror 28EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx8550/common/gdb_hook.c b/arch/mips/nxp/pnx8550/common/gdb_hook.c
deleted file mode 100644
index ad4624f6d9b..00000000000
--- a/arch/mips/nxp/pnx8550/common/gdb_hook.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * This is the interface to the remote debugger stub.
23 *
24 */
25#include <linux/types.h>
26#include <linux/serial.h>
27#include <linux/serialP.h>
28#include <linux/serial_reg.h>
29#include <linux/serial_ip3106.h>
30
31#include <asm/serial.h>
32#include <asm/io.h>
33
34#include <uart.h>
35
36static struct serial_state rs_table[IP3106_NR_PORTS] = {
37};
38static struct async_struct kdb_port_info = {0};
39
40void rs_kgdb_hook(int tty_no)
41{
42 struct serial_state *ser = &rs_table[tty_no];
43
44 kdb_port_info.state = ser;
45 kdb_port_info.magic = SERIAL_MAGIC;
46 kdb_port_info.port = tty_no;
47 kdb_port_info.flags = ser->flags;
48
49 /*
50 * Clear all interrupts
51 */
52 /* Clear all the transmitter FIFO counters (pointer and status) */
53 ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST;
54 /* Clear all the receiver FIFO counters (pointer and status) */
55 ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST;
56 /* Clear all interrupts */
57 ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX |
58 IP3106_UART_INT_ALLTX;
59
60 /*
61 * Now, initialize the UART
62 */
63 ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT;
64 ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud
65}
66
67int putDebugChar(char c)
68{
69 /* Wait until FIFO not full */
70 while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16)
71 ;
72 /* Send one char */
73 ip3106_fifo(UART_BASE, kdb_port_info.port) = c;
74
75 return 1;
76}
77
78char getDebugChar(void)
79{
80 char ch;
81
82 /* Wait until there is a char in the FIFO */
83 while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) &
84 IP3106_UART_FIFO_RXFIFO) >> 8))
85 ;
86 /* Read one char */
87 ch = ip3106_fifo(UART_BASE, kdb_port_info.port) &
88 IP3106_UART_FIFO_RBRTHR;
89 /* Advance the RX FIFO read pointer */
90 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT;
91 return (ch);
92}
93
94void rs_disable_debug_interrupts(void)
95{
96 ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */
97}
98
99void rs_enable_debug_interrupts(void)
100{
101 /* Clear all the transmitter FIFO counters (pointer and status) */
102 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST;
103 /* Clear all the receiver FIFO counters (pointer and status) */
104 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST;
105 /* Clear all interrupts */
106 ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX |
107 IP3106_UART_INT_ALLTX;
108 ip3106_ien(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */
109}
diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/nxp/pnx8550/common/int.c
index aad03429a5e..f080f114a1b 100644
--- a/arch/mips/nxp/pnx8550/common/int.c
+++ b/arch/mips/nxp/pnx8550/common/int.c
@@ -34,7 +34,6 @@
34#include <linux/module.h> 34#include <linux/module.h>
35 35
36#include <asm/io.h> 36#include <asm/io.h>
37#include <asm/gdb-stub.h>
38#include <int.h> 37#include <int.h>
39#include <uart.h> 38#include <uart.h>
40 39
diff --git a/arch/mips/nxp/pnx8550/common/proc.c b/arch/mips/nxp/pnx8550/common/proc.c
index 18b125e3b65..acf1fa88944 100644
--- a/arch/mips/nxp/pnx8550/common/proc.c
+++ b/arch/mips/nxp/pnx8550/common/proc.c
@@ -22,7 +22,6 @@
22#include <linux/random.h> 22#include <linux/random.h>
23 23
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/gdb-stub.h>
26#include <int.h> 25#include <int.h>
27#include <uart.h> 26#include <uart.h>
28 27
diff --git a/arch/mips/nxp/pnx8550/common/setup.c b/arch/mips/nxp/pnx8550/common/setup.c
index 92d764c9770..2aed50fef10 100644
--- a/arch/mips/nxp/pnx8550/common/setup.c
+++ b/arch/mips/nxp/pnx8550/common/setup.c
@@ -47,7 +47,6 @@ extern void pnx8550_machine_halt(void);
47extern void pnx8550_machine_power_off(void); 47extern void pnx8550_machine_power_off(void);
48extern struct resource ioport_resource; 48extern struct resource ioport_resource;
49extern struct resource iomem_resource; 49extern struct resource iomem_resource;
50extern void rs_kgdb_hook(int tty_no);
51extern char *prom_getcmdline(void); 50extern char *prom_getcmdline(void);
52 51
53struct resource standard_io_resources[] = { 52struct resource standard_io_resources[] = {
@@ -142,16 +141,5 @@ void __init plat_mem_setup(void)
142 ip3106_baud(UART_BASE, pnx8550_console_port) = 5; 141 ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
143 } 142 }
144 143
145#ifdef CONFIG_KGDB
146 argptr = prom_getcmdline();
147 if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
148 int line;
149 argptr += strlen("kgdb=ttyS");
150 line = *argptr == '0' ? 0 : 1;
151 rs_kgdb_hook(line);
152 pr_info("KGDB: Using ttyS%i for session, "
153 "please connect your debugger\n", line ? 1 : 0);
154 }
155#endif
156 return; 144 return;
157} 145}
diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c
index 8a17a39e5bf..31c15019659 100644
--- a/arch/mips/pci/ops-tx3927.c
+++ b/arch/mips/pci/ops-tx3927.c
@@ -37,45 +37,48 @@
37#include <linux/pci.h> 37#include <linux/pci.h>
38#include <linux/kernel.h> 38#include <linux/kernel.h>
39#include <linux/init.h> 39#include <linux/init.h>
40#include <linux/interrupt.h>
40 41
41#include <asm/addrspace.h> 42#include <asm/addrspace.h>
43#include <asm/txx9irq.h>
44#include <asm/txx9/pci.h>
42#include <asm/txx9/tx3927.h> 45#include <asm/txx9/tx3927.h>
43 46
44static inline int mkaddr(unsigned char bus, unsigned char dev_fn, 47static int mkaddr(struct pci_bus *bus, unsigned char devfn, unsigned char where)
45 unsigned char where)
46{ 48{
47 if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0)) 49 if (bus->parent == NULL &&
48 return PCIBIOS_DEVICE_NOT_FOUND; 50 devfn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
49 51 return -1;
50 tx3927_pcicptr->ica = ((bus & 0xff) << 0x10) | 52 tx3927_pcicptr->ica =
51 ((dev_fn & 0xff) << 0x08) | 53 ((bus->number & 0xff) << 0x10) |
52 (where & 0xfc); 54 ((devfn & 0xff) << 0x08) |
55 (where & 0xfc) | (bus->parent ? 1 : 0);
53 56
54 /* clear M_ABORT and Disable M_ABORT Int. */ 57 /* clear M_ABORT and Disable M_ABORT Int. */
55 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT; 58 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
56 tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT; 59 tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
57 60 return 0;
58 return PCIBIOS_SUCCESSFUL;
59} 61}
60 62
61static inline int check_abort(void) 63static inline int check_abort(void)
62{ 64{
63 if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) 65 if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) {
64 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT; 66 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
65 tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT; 67 tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
68 /* flush write buffer */
69 iob();
66 return PCIBIOS_DEVICE_NOT_FOUND; 70 return PCIBIOS_DEVICE_NOT_FOUND;
67 71 }
68 return PCIBIOS_SUCCESSFUL; 72 return PCIBIOS_SUCCESSFUL;
69} 73}
70 74
71static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, 75static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
72 int where, int size, u32 * val) 76 int where, int size, u32 * val)
73{ 77{
74 int ret; 78 if (mkaddr(bus, devfn, where)) {
75 79 *val = 0xffffffff;
76 ret = mkaddr(bus->number, devfn, where); 80 return PCIBIOS_DEVICE_NOT_FOUND;
77 if (ret) 81 }
78 return ret;
79 82
80 switch (size) { 83 switch (size) {
81 case 1: 84 case 1:
@@ -97,11 +100,8 @@ static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
97static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, 100static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
98 int where, int size, u32 val) 101 int where, int size, u32 val)
99{ 102{
100 int ret; 103 if (mkaddr(bus, devfn, where))
101 104 return PCIBIOS_DEVICE_NOT_FOUND;
102 ret = mkaddr(bus->number, devfn, where);
103 if (ret)
104 return ret;
105 105
106 switch (size) { 106 switch (size) {
107 case 1: 107 case 1:
@@ -117,11 +117,6 @@ static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
117 tx3927_pcicptr->icd = cpu_to_le32(val); 117 tx3927_pcicptr->icd = cpu_to_le32(val);
118 } 118 }
119 119
120 if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT)
121 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
122 tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
123 return PCIBIOS_DEVICE_NOT_FOUND;
124
125 return check_abort(); 120 return check_abort();
126} 121}
127 122
@@ -202,3 +197,34 @@ void __init tx3927_pcic_setup(struct pci_controller *channel,
202 PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 197 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
203 local_irq_restore(flags); 198 local_irq_restore(flags);
204} 199}
200
201static irqreturn_t tx3927_pcierr_interrupt(int irq, void *dev_id)
202{
203 struct pt_regs *regs = get_irq_regs();
204
205 if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
206 printk(KERN_WARNING "PCI error interrupt at 0x%08lx.\n",
207 regs->cp0_epc);
208 printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
209 tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
210 }
211 if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
212 /* clear all pci errors */
213 tx3927_pcicptr->pcistat |= TX3927_PCIC_PCISTATIM_ALL;
214 tx3927_pcicptr->istat = TX3927_PCIC_IIM_ALL;
215 tx3927_pcicptr->tstat = TX3927_PCIC_TIM_ALL;
216 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
217 return IRQ_HANDLED;
218 }
219 console_verbose();
220 panic("PCI error.");
221}
222
223void __init tx3927_setup_pcierr_irq(void)
224{
225 if (request_irq(TXX9_IRQ_BASE + TX3927_IR_PCI,
226 tx3927_pcierr_interrupt,
227 IRQF_DISABLED, "PCI error",
228 (void *)TX3927_PCIC_REG))
229 printk(KERN_WARNING "Failed to request irq for PCIERR\n");
230}
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index c6b49bccd27..5989e747527 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -16,6 +16,8 @@
16 * option) any later version. 16 * option) any later version.
17 */ 17 */
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/interrupt.h>
20#include <asm/txx9/pci.h>
19#include <asm/txx9/tx4927pcic.h> 21#include <asm/txx9/tx4927pcic.h>
20 22
21static struct { 23static struct {
@@ -85,6 +87,8 @@ static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
85 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) 87 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
86 | (PCI_STATUS_REC_MASTER_ABORT << 16), 88 | (PCI_STATUS_REC_MASTER_ABORT << 16),
87 &pcicptr->pcistatus); 89 &pcicptr->pcistatus);
90 /* flush write buffer */
91 iob();
88 code = PCIBIOS_DEVICE_NOT_FOUND; 92 code = PCIBIOS_DEVICE_NOT_FOUND;
89 } 93 }
90 return code; 94 return code;
@@ -192,6 +196,28 @@ static struct {
192 .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */ 196 .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
193}; 197};
194 198
199char *__devinit tx4927_pcibios_setup(char *str)
200{
201 unsigned long val;
202
203 if (!strncmp(str, "trdyto=", 7)) {
204 if (strict_strtoul(str + 7, 0, &val) == 0)
205 tx4927_pci_opts.trdyto = val;
206 return NULL;
207 }
208 if (!strncmp(str, "retryto=", 8)) {
209 if (strict_strtoul(str + 8, 0, &val) == 0)
210 tx4927_pci_opts.retryto = val;
211 return NULL;
212 }
213 if (!strncmp(str, "gbwc=", 5)) {
214 if (strict_strtoul(str + 5, 0, &val) == 0)
215 tx4927_pci_opts.gbwc = val;
216 return NULL;
217 }
218 return str;
219}
220
195void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, 221void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
196 struct pci_controller *channel, int extarb) 222 struct pci_controller *channel, int extarb)
197{ 223{
@@ -406,3 +432,95 @@ void tx4927_report_pcic_status(void)
406 tx4927_report_pcic_status1(pcicptrs[i].pcicptr); 432 tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
407 } 433 }
408} 434}
435
436static void tx4927_dump_pcic_settings1(struct tx4927_pcic_reg __iomem *pcicptr)
437{
438 int i;
439 __u32 __iomem *preg = (__u32 __iomem *)pcicptr;
440
441 printk(KERN_INFO "tx4927 pcic (0x%p) settings:", pcicptr);
442 for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4, preg++) {
443 if (i % 32 == 0) {
444 printk(KERN_CONT "\n");
445 printk(KERN_INFO "%04x:", i);
446 }
447 /* skip registers with side-effects */
448 if (i == offsetof(struct tx4927_pcic_reg, g2pintack)
449 || i == offsetof(struct tx4927_pcic_reg, g2pspc)
450 || i == offsetof(struct tx4927_pcic_reg, g2pcfgadrs)
451 || i == offsetof(struct tx4927_pcic_reg, g2pcfgdata)) {
452 printk(KERN_CONT " XXXXXXXX");
453 continue;
454 }
455 printk(KERN_CONT " %08x", __raw_readl(preg));
456 }
457 printk(KERN_CONT "\n");
458}
459
460void tx4927_dump_pcic_settings(void)
461{
462 int i;
463
464 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
465 if (pcicptrs[i].pcicptr)
466 tx4927_dump_pcic_settings1(pcicptrs[i].pcicptr);
467 }
468}
469
470irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
471{
472 struct pt_regs *regs = get_irq_regs();
473 struct tx4927_pcic_reg __iomem *pcicptr =
474 (struct tx4927_pcic_reg __iomem *)(unsigned long)dev_id;
475
476 if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
477 printk(KERN_WARNING "PCIERR interrupt at 0x%0*lx\n",
478 (int)(2 * sizeof(unsigned long)), regs->cp0_epc);
479 tx4927_report_pcic_status1(pcicptr);
480 }
481 if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
482 /* clear all pci errors */
483 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
484 | (TX4927_PCIC_PCISTATUS_ALL << 16),
485 &pcicptr->pcistatus);
486 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
487 __raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus);
488 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
489 return IRQ_HANDLED;
490 }
491 console_verbose();
492 tx4927_dump_pcic_settings1(pcicptr);
493 panic("PCI error.");
494}
495
496#ifdef CONFIG_TOSHIBA_FPCIB0
497static void __init tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
498{
499 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
500
501 if (!pcicptr)
502 return;
503 if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) {
504 /* Reset Bus Arbiter */
505 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
506 /*
507 * swap reqBP and reqXP (raise priority of SLC90E66).
508 * SLC90E66(PCI-ISA bridge) is connected to REQ2 on
509 * PCI Backplane board.
510 */
511 __raw_writel(0x72543610, &pcicptr->pbareqport);
512 __raw_writel(0, &pcicptr->pbabm);
513 /* Use Fixed ParkMaster (required by SLC90E66) */
514 __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg);
515 /* Enable Bus Arbiter */
516 __raw_writel(TX4927_PCIC_PBACFG_FIXPA |
517 TX4927_PCIC_PBACFG_PBAEN,
518 &pcicptr->pbacfg);
519 printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n",
520 __raw_readl(&pcicptr->pbareqport));
521 }
522}
523#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
524DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
525 tx4927_quirk_slc90e66_bridge);
526#endif
diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c
index 27e86a09dd4..aaa90059679 100644
--- a/arch/mips/pci/pci-tx4927.c
+++ b/arch/mips/pci/pci-tx4927.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/pci.h> 16#include <linux/pci.h>
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/interrupt.h>
18#include <asm/txx9/generic.h> 19#include <asm/txx9/generic.h>
19#include <asm/txx9/tx4927.h> 20#include <asm/txx9/tx4927.h>
20 21
@@ -81,3 +82,12 @@ int __init tx4927_pciclk66_setup(void)
81 pciclk = -1; 82 pciclk = -1;
82 return pciclk; 83 return pciclk;
83} 84}
85
86void __init tx4927_setup_pcierr_irq(void)
87{
88 if (request_irq(TXX9_IRQ_BASE + TX4927_IR_PCIERR,
89 tx4927_pcierr_interrupt,
90 IRQF_DISABLED, "PCI error",
91 (void *)TX4927_PCIC_REG))
92 printk(KERN_WARNING "Failed to request irq for PCIERR\n");
93}
diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c
index e5375511c2b..60e2c52c2c5 100644
--- a/arch/mips/pci/pci-tx4938.c
+++ b/arch/mips/pci/pci-tx4938.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/pci.h> 16#include <linux/pci.h>
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/interrupt.h>
18#include <asm/txx9/generic.h> 19#include <asm/txx9/generic.h>
19#include <asm/txx9/tx4938.h> 20#include <asm/txx9/tx4938.h>
20 21
@@ -132,3 +133,12 @@ int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
132 } 133 }
133 return -1; 134 return -1;
134} 135}
136
137void __init tx4938_setup_pcierr_irq(void)
138{
139 if (request_irq(TXX9_IRQ_BASE + TX4938_IR_PCIERR,
140 tx4927_pcierr_interrupt,
141 IRQF_DISABLED, "PCI error",
142 (void *)TX4927_PCIC_REG))
143 printk(KERN_WARNING "Failed to request irq for PCIERR\n");
144}
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 77bd5b68dc4..c7fe6ec621e 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -328,7 +328,11 @@ EXPORT_SYMBOL(PCIBIOS_MIN_IO);
328EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 328EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
329#endif 329#endif
330 330
331char *pcibios_setup(char *str) 331char * (*pcibios_plat_setup)(char *str) __devinitdata;
332
333char *__devinit pcibios_setup(char *str)
332{ 334{
335 if (pcibios_plat_setup)
336 return pcibios_plat_setup(str);
333 return str; 337 return str;
334} 338}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
index 9de34302e5f..f7261628d8a 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
@@ -38,68 +38,6 @@
38#include <msp_int.h> 38#include <msp_int.h>
39#include <msp_regs.h> 39#include <msp_regs.h>
40 40
41#ifdef CONFIG_KGDB
42/*
43 * kgdb uses serial port 1 so the console can remain on port 0.
44 * To use port 0 change the definition to read as follows:
45 * #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART0_BASE)
46 */
47#define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART1_BASE)
48
49int putDebugChar(char c)
50{
51 volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
52 uint32_t val = (uint32_t)c;
53
54 local_irq_disable();
55 while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
56 uart[0] = val;
57 while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
58 local_irq_enable();
59
60 return 1;
61}
62
63char getDebugChar(void)
64{
65 volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
66 uint32_t val;
67
68 while( !(uart[5] & 0x01) ); /* Wait for RXRDY */
69 val = uart[0];
70
71 return (char)val;
72}
73
74void initDebugPort(unsigned int uartclk, unsigned int baudrate)
75{
76 unsigned int baud_divisor = (uartclk + 8 * baudrate)/(16 * baudrate);
77
78 /* Enable FIFOs */
79 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
80 UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4,
81 (char *)DEBUG_PORT_BASE + (UART_FCR * 4));
82
83 /* Select brtc divisor */
84 writeb(UART_LCR_DLAB, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
85
86 /* Store divisor lsb */
87 writeb(baud_divisor, (char *)DEBUG_PORT_BASE + (UART_TX * 4));
88
89 /* Store divisor msb */
90 writeb(baud_divisor >> 8, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
91
92 /* Set 8N1 mode */
93 writeb(UART_LCR_WLEN8, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
94
95 /* Disable flow control */
96 writeb(0, (char *)DEBUG_PORT_BASE + (UART_MCR * 4));
97
98 /* Disable receive interrupt(!) */
99 writeb(0, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
100}
101#endif
102
103void __init msp_serial_setup(void) 41void __init msp_serial_setup(void)
104{ 42{
105 char *s; 43 char *s;
@@ -139,17 +77,6 @@ void __init msp_serial_setup(void)
139 case MACH_MSP7120_FPGA: 77 case MACH_MSP7120_FPGA:
140 /* Enable UART1 on MSP4200 and MSP7120 */ 78 /* Enable UART1 on MSP4200 and MSP7120 */
141 *GPIO_CFG2_REG = 0x00002299; 79 *GPIO_CFG2_REG = 0x00002299;
142
143#ifdef CONFIG_KGDB
144 /* Initialize UART1 for kgdb since PMON doesn't */
145 if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) {
146 if( mips_machtype == MACH_MSP4200_FPGA
147 || mips_machtype == MACH_MSP7120_FPGA )
148 initDebugPort(uartclk, 19200);
149 else
150 initDebugPort(uartclk, 57600);
151 }
152#endif
153 break; 80 break;
154 81
155 default: 82 default:
diff --git a/arch/mips/pmc-sierra/yosemite/Makefile b/arch/mips/pmc-sierra/yosemite/Makefile
index 8fd9a04e353..b16f95c3df6 100644
--- a/arch/mips/pmc-sierra/yosemite/Makefile
+++ b/arch/mips/pmc-sierra/yosemite/Makefile
@@ -4,7 +4,6 @@
4 4
5obj-y += irq.o prom.o py-console.o setup.o 5obj-y += irq.o prom.o py-console.o setup.o
6 6
7obj-$(CONFIG_KGDB) += dbg_io.o
8obj-$(CONFIG_SMP) += smp.o 7obj-$(CONFIG_SMP) += smp.o
9 8
10EXTRA_CFLAGS += -Werror 9EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/pmc-sierra/yosemite/dbg_io.c b/arch/mips/pmc-sierra/yosemite/dbg_io.c
deleted file mode 100644
index 6362c702e38..00000000000
--- a/arch/mips/pmc-sierra/yosemite/dbg_io.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/*
2 * Copyright 2003 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
27 * Support for KGDB for the Yosemite board. We make use of single serial
28 * port to be used for KGDB as well as console. The second serial port
29 * seems to be having a problem. Single IRQ is allocated for both the
30 * ports. Hence, the interrupt routing code needs to figure out whether
31 * the interrupt came from channel A or B.
32 */
33
34#include <asm/serial.h>
35
36/*
37 * Baud rate, Parity, Data and Stop bit settings for the
38 * serial port on the Yosemite. Note that the Early printk
39 * patch has been added. So, we should be all set to go
40 */
41#define YOSEMITE_BAUD_2400 2400
42#define YOSEMITE_BAUD_4800 4800
43#define YOSEMITE_BAUD_9600 9600
44#define YOSEMITE_BAUD_19200 19200
45#define YOSEMITE_BAUD_38400 38400
46#define YOSEMITE_BAUD_57600 57600
47#define YOSEMITE_BAUD_115200 115200
48
49#define YOSEMITE_PARITY_NONE 0
50#define YOSEMITE_PARITY_ODD 0x08
51#define YOSEMITE_PARITY_EVEN 0x18
52#define YOSEMITE_PARITY_MARK 0x28
53#define YOSEMITE_PARITY_SPACE 0x38
54
55#define YOSEMITE_DATA_5BIT 0x0
56#define YOSEMITE_DATA_6BIT 0x1
57#define YOSEMITE_DATA_7BIT 0x2
58#define YOSEMITE_DATA_8BIT 0x3
59
60#define YOSEMITE_STOP_1BIT 0x0
61#define YOSEMITE_STOP_2BIT 0x4
62
63/* This is crucial */
64#define SERIAL_REG_OFS 0x1
65
66#define SERIAL_RCV_BUFFER 0x0
67#define SERIAL_TRANS_HOLD 0x0
68#define SERIAL_SEND_BUFFER 0x0
69#define SERIAL_INTR_ENABLE (1 * SERIAL_REG_OFS)
70#define SERIAL_INTR_ID (2 * SERIAL_REG_OFS)
71#define SERIAL_DATA_FORMAT (3 * SERIAL_REG_OFS)
72#define SERIAL_LINE_CONTROL (3 * SERIAL_REG_OFS)
73#define SERIAL_MODEM_CONTROL (4 * SERIAL_REG_OFS)
74#define SERIAL_RS232_OUTPUT (4 * SERIAL_REG_OFS)
75#define SERIAL_LINE_STATUS (5 * SERIAL_REG_OFS)
76#define SERIAL_MODEM_STATUS (6 * SERIAL_REG_OFS)
77#define SERIAL_RS232_INPUT (6 * SERIAL_REG_OFS)
78#define SERIAL_SCRATCH_PAD (7 * SERIAL_REG_OFS)
79
80#define SERIAL_DIVISOR_LSB (0 * SERIAL_REG_OFS)
81#define SERIAL_DIVISOR_MSB (1 * SERIAL_REG_OFS)
82
83/*
84 * Functions to READ and WRITE to serial port 0
85 */
86#define SERIAL_READ(ofs) (*((volatile unsigned char*) \
87 (TITAN_SERIAL_BASE + ofs)))
88
89#define SERIAL_WRITE(ofs, val) ((*((volatile unsigned char*) \
90 (TITAN_SERIAL_BASE + ofs))) = val)
91
92/*
93 * Functions to READ and WRITE to serial port 1
94 */
95#define SERIAL_READ_1(ofs) (*((volatile unsigned char*) \
96 (TITAN_SERIAL_BASE_1 + ofs)))
97
98#define SERIAL_WRITE_1(ofs, val) ((*((volatile unsigned char*) \
99 (TITAN_SERIAL_BASE_1 + ofs))) = val)
100
101/*
102 * Second serial port initialization
103 */
104void init_second_port(void)
105{
106 /* Disable Interrupts */
107 SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0);
108 SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0x0);
109
110 {
111 unsigned int divisor;
112
113 SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x80);
114 divisor = TITAN_SERIAL_BASE_BAUD / YOSEMITE_BAUD_115200;
115 SERIAL_WRITE_1(SERIAL_DIVISOR_LSB, divisor & 0xff);
116
117 SERIAL_WRITE_1(SERIAL_DIVISOR_MSB,
118 (divisor & 0xff00) >> 8);
119 SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0);
120 }
121
122 SERIAL_WRITE_1(SERIAL_DATA_FORMAT, YOSEMITE_DATA_8BIT |
123 YOSEMITE_PARITY_NONE | YOSEMITE_STOP_1BIT);
124
125 /* Enable Interrupts */
126 SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0xf);
127}
128
129/* Initialize the serial port for KGDB debugging */
130void debugInit(unsigned int baud, unsigned char data, unsigned char parity,
131 unsigned char stop)
132{
133 /* Disable Interrupts */
134 SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0);
135 SERIAL_WRITE(SERIAL_INTR_ENABLE, 0x0);
136
137 {
138 unsigned int divisor;
139
140 SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x80);
141
142 divisor = TITAN_SERIAL_BASE_BAUD / baud;
143 SERIAL_WRITE(SERIAL_DIVISOR_LSB, divisor & 0xff);
144
145 SERIAL_WRITE(SERIAL_DIVISOR_MSB, (divisor & 0xff00) >> 8);
146 SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0);
147 }
148
149 SERIAL_WRITE(SERIAL_DATA_FORMAT, data | parity | stop);
150}
151
152static int remoteDebugInitialized = 0;
153
154unsigned char getDebugChar(void)
155{
156 if (!remoteDebugInitialized) {
157 remoteDebugInitialized = 1;
158 debugInit(YOSEMITE_BAUD_115200,
159 YOSEMITE_DATA_8BIT,
160 YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT);
161 }
162
163 while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x1) == 0);
164 return SERIAL_READ(SERIAL_RCV_BUFFER);
165}
166
167int putDebugChar(unsigned char byte)
168{
169 if (!remoteDebugInitialized) {
170 remoteDebugInitialized = 1;
171 debugInit(YOSEMITE_BAUD_115200,
172 YOSEMITE_DATA_8BIT,
173 YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT);
174 }
175
176 while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x20) == 0);
177 SERIAL_WRITE(SERIAL_SEND_BUFFER, byte);
178
179 return 1;
180}
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
index 4decc280786..5f673eba142 100644
--- a/arch/mips/pmc-sierra/yosemite/irq.c
+++ b/arch/mips/pmc-sierra/yosemite/irq.c
@@ -141,10 +141,6 @@ asmlinkage void plat_irq_dispatch(void)
141 } 141 }
142} 142}
143 143
144#ifdef CONFIG_KGDB
145extern void init_second_port(void);
146#endif
147
148/* 144/*
149 * Initialize the next level interrupt handler 145 * Initialize the next level interrupt handler
150 */ 146 */
@@ -156,11 +152,6 @@ void __init arch_init_irq(void)
156 rm7k_cpu_irq_init(); 152 rm7k_cpu_irq_init();
157 rm9k_cpu_irq_init(); 153 rm9k_cpu_irq_init();
158 154
159#ifdef CONFIG_KGDB
160 /* At this point, initialize the second serial port */
161 init_second_port();
162#endif
163
164#ifdef CONFIG_GDB_CONSOLE 155#ifdef CONFIG_GDB_CONSOLE
165 register_gdb_console(); 156 register_gdb_console();
166#endif 157#endif
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index b2fe82dba0a..00a1c7877bf 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -64,7 +64,8 @@ static struct resource rb532_dev3_ctl_res[] = {
64 64
65void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val) 65void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
66{ 66{
67 unsigned flags, data; 67 unsigned long flags;
68 unsigned data;
68 unsigned i = 0; 69 unsigned i = 0;
69 70
70 spin_lock_irqsave(&dev3.lock, flags); 71 spin_lock_irqsave(&dev3.lock, flags);
@@ -90,7 +91,7 @@ EXPORT_SYMBOL(get_434_reg);
90 91
91void set_latch_u5(unsigned char or_mask, unsigned char nand_mask) 92void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
92{ 93{
93 unsigned flags; 94 unsigned long flags;
94 95
95 spin_lock_irqsave(&dev3.lock, flags); 96 spin_lock_irqsave(&dev3.lock, flags);
96 97
diff --git a/arch/mips/rb532/time.c b/arch/mips/rb532/time.c
index db74edf8cef..8e7a46855b5 100644
--- a/arch/mips/rb532/time.c
+++ b/arch/mips/rb532/time.c
@@ -49,8 +49,8 @@ static unsigned long __init cal_r4koff(void)
49 49
50void __init plat_time_init(void) 50void __init plat_time_init(void)
51{ 51{
52 unsigned int est_freq, flags; 52 unsigned int est_freq;
53 unsigned long r4k_offset; 53 unsigned long flags, r4k_offset;
54 54
55 local_irq_save(flags); 55 local_irq_save(flags);
56 56
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index 5f389ee26fc..896a1ef8482 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -20,7 +20,6 @@
20#include <asm/irq.h> 20#include <asm/irq.h>
21#include <asm/reboot.h> 21#include <asm/reboot.h>
22#include <asm/time.h> 22#include <asm/time.h>
23#include <asm/gdb-stub.h>
24#include <asm/io.h> 23#include <asm/io.h>
25#include <asm/traps.h> 24#include <asm/traps.h>
26#include <asm/sgialib.h> 25#include <asm/sgialib.h>
@@ -81,30 +80,6 @@ void __init plat_mem_setup(void)
81 add_preferred_console("arc", 0, NULL); 80 add_preferred_console("arc", 0, NULL);
82 } 81 }
83 82
84#ifdef CONFIG_KGDB
85 {
86 char *kgdb_ttyd = prom_getcmdline();
87
88 if ((kgdb_ttyd = strstr(kgdb_ttyd, "kgdb=ttyd")) != NULL) {
89 int line;
90 kgdb_ttyd += strlen("kgdb=ttyd");
91 if (*kgdb_ttyd != '1' && *kgdb_ttyd != '2')
92 printk(KERN_INFO "KGDB: Uknown serial line /dev/ttyd%c"
93 ", falling back to /dev/ttyd1\n", *kgdb_ttyd);
94 line = *kgdb_ttyd == '2' ? 0 : 1;
95 printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for "
96 "session\n", line ? 1 : 2);
97 rs_kgdb_hook(line);
98
99 printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for "
100 "session, please connect your debugger\n", line ? 1:2);
101
102 kgdb_enabled = 1;
103 /* Breakpoints and stuff are in sgi_irq_setup() */
104 }
105 }
106#endif
107
108#if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE) 83#if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE)
109 { 84 {
110 ULONG *gfxinfo; 85 ULONG *gfxinfo;
diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile
index e0a6871d56e..31f4931b848 100644
--- a/arch/mips/sgi-ip27/Makefile
+++ b/arch/mips/sgi-ip27/Makefile
@@ -7,7 +7,6 @@ obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \
7 ip27-xtalk.o 7 ip27-xtalk.o
8 8
9obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o 9obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o
10obj-$(CONFIG_KGDB) += ip27-dbgio.o
11obj-$(CONFIG_SMP) += ip27-smp.o 10obj-$(CONFIG_SMP) += ip27-smp.o
12 11
13EXTRA_CFLAGS += -Werror 12EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip27/ip27-dbgio.c b/arch/mips/sgi-ip27/ip27-dbgio.c
deleted file mode 100644
index 08fd88b36f8..00000000000
--- a/arch/mips/sgi-ip27/ip27-dbgio.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Copyright 2004 Ralf Baechle <ralf@linux-mips.org>
23 */
24#include <asm/sn/addrs.h>
25#include <asm/sn/sn0/hub.h>
26#include <asm/sn/klconfig.h>
27#include <asm/sn/ioc3.h>
28#include <asm/sn/sn_private.h>
29
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32#include <linux/serial_reg.h>
33
34#define IOC3_CLK (22000000 / 3)
35#define IOC3_FLAGS (0)
36
37static inline struct ioc3_uartregs *console_uart(void)
38{
39 struct ioc3 *ioc3;
40
41 ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(get_nasid())->memory_base;
42
43 return &ioc3->sregs.uarta;
44}
45
46unsigned char getDebugChar(void)
47{
48 struct ioc3_uartregs *uart = console_uart();
49
50 while ((uart->iu_lsr & UART_LSR_DR) == 0);
51 return uart->iu_rbr;
52}
53
54void putDebugChar(unsigned char c)
55{
56 struct ioc3_uartregs *uart = console_uart();
57
58 while ((uart->iu_lsr & UART_LSR_THRE) == 0);
59 uart->iu_thr = c;
60}
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index db372a0f106..a35818ed426 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -57,30 +57,6 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
57extern unsigned long ht_eoi_space; 57extern unsigned long ht_eoi_space;
58#endif 58#endif
59 59
60#ifdef CONFIG_KGDB
61#include <asm/gdb-stub.h>
62extern void breakpoint(void);
63static int kgdb_irq;
64#ifdef CONFIG_GDB_CONSOLE
65extern void register_gdb_console(void);
66#endif
67
68/* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */
69static int kgdb_flag = 1;
70static int __init nokgdb(char *str)
71{
72 kgdb_flag = 0;
73 return 1;
74}
75__setup("nokgdb", nokgdb);
76
77/* Default to UART1 */
78int kgdb_port = 1;
79#ifdef CONFIG_SERIAL_SB1250_DUART
80extern char sb1250_duart_present[];
81#endif
82#endif
83
84static struct irq_chip bcm1480_irq_type = { 60static struct irq_chip bcm1480_irq_type = {
85 .name = "BCM1480-IMR", 61 .name = "BCM1480-IMR",
86 .ack = ack_bcm1480_irq, 62 .ack = ack_bcm1480_irq,
@@ -355,61 +331,10 @@ void __init arch_init_irq(void)
355 * does its own management of IP7. 331 * does its own management of IP7.
356 */ 332 */
357 333
358#ifdef CONFIG_KGDB
359 imask |= STATUSF_IP6;
360#endif
361 /* Enable necessary IPs, disable the rest */ 334 /* Enable necessary IPs, disable the rest */
362 change_c0_status(ST0_IM, imask); 335 change_c0_status(ST0_IM, imask);
363
364#ifdef CONFIG_KGDB
365 if (kgdb_flag) {
366 kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port;
367
368#ifdef CONFIG_SERIAL_SB1250_DUART
369 sb1250_duart_present[kgdb_port] = 0;
370#endif
371 /* Setup uart 1 settings, mapper */
372 /* QQQ FIXME */
373 __raw_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port)));
374
375 __raw_writeq(IMR_IP6_VAL,
376 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
377 (kgdb_irq << 3)));
378 bcm1480_unmask_irq(0, kgdb_irq);
379
380#ifdef CONFIG_GDB_CONSOLE
381 register_gdb_console();
382#endif
383 printk("Waiting for GDB on UART port %d\n", kgdb_port);
384 set_debug_traps();
385 breakpoint();
386 }
387#endif
388}
389
390#ifdef CONFIG_KGDB
391
392#include <linux/delay.h>
393
394#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
395#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
396
397static void bcm1480_kgdb_interrupt(void)
398{
399 /*
400 * Clear break-change status (allow some time for the remote
401 * host to stop the break, since we would see another
402 * interrupt on the end-of-break too)
403 */
404 kstat.irqs[smp_processor_id()][kgdb_irq]++;
405 mdelay(500);
406 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
407 M_DUART_RX_EN | M_DUART_TX_EN);
408 set_async_breakpoint(&get_irq_regs()->cp0_epc);
409} 336}
410 337
411#endif /* CONFIG_KGDB */
412
413extern void bcm1480_mailbox_interrupt(void); 338extern void bcm1480_mailbox_interrupt(void);
414 339
415static inline void dispatch_ip2(void) 340static inline void dispatch_ip2(void)
@@ -462,11 +387,6 @@ asmlinkage void plat_irq_dispatch(void)
462 bcm1480_mailbox_interrupt(); 387 bcm1480_mailbox_interrupt();
463#endif 388#endif
464 389
465#ifdef CONFIG_KGDB
466 else if (pending & CAUSEF_IP6)
467 bcm1480_kgdb_interrupt(); /* KGDB (uart 1) */
468#endif
469
470 else if (pending & CAUSEF_IP2) 390 else if (pending & CAUSEF_IP2)
471 dispatch_ip2(); 391 dispatch_ip2();
472} 392}
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
index fd9604d5555..3de30f79db3 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -59,10 +59,6 @@ int cfe_cons_handle;
59extern unsigned long initrd_start, initrd_end; 59extern unsigned long initrd_start, initrd_end;
60#endif 60#endif
61 61
62#ifdef CONFIG_KGDB
63extern int kgdb_port;
64#endif
65
66static void __noreturn cfe_linux_exit(void *arg) 62static void __noreturn cfe_linux_exit(void *arg)
67{ 63{
68 int warm = *(int *)arg; 64 int warm = *(int *)arg;
@@ -246,9 +242,6 @@ void __init prom_init(void)
246 int argc = fw_arg0; 242 int argc = fw_arg0;
247 char **envp = (char **) fw_arg2; 243 char **envp = (char **) fw_arg2;
248 int *prom_vec = (int *) fw_arg3; 244 int *prom_vec = (int *) fw_arg3;
249#ifdef CONFIG_KGDB
250 char *arg;
251#endif
252 245
253 _machine_restart = cfe_linux_restart; 246 _machine_restart = cfe_linux_restart;
254 _machine_halt = cfe_linux_halt; 247 _machine_halt = cfe_linux_halt;
@@ -309,13 +302,6 @@ void __init prom_init(void)
309 } 302 }
310 } 303 }
311 304
312#ifdef CONFIG_KGDB
313 if ((arg = strstr(arcs_cmdline, "kgdb=duart")) != NULL)
314 kgdb_port = (arg[10] == '0') ? 0 : 1;
315 else
316 kgdb_port = 1;
317#endif
318
319#ifdef CONFIG_BLK_DEV_INITRD 305#ifdef CONFIG_BLK_DEV_INITRD
320 { 306 {
321 char *ptr; 307 char *ptr;
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index eac9065ffe0..a5158483986 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -57,16 +57,6 @@ static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
57extern unsigned long ldt_eoi_space; 57extern unsigned long ldt_eoi_space;
58#endif 58#endif
59 59
60#ifdef CONFIG_KGDB
61static int kgdb_irq;
62
63/* Default to UART1 */
64int kgdb_port = 1;
65#ifdef CONFIG_SERIAL_SB1250_DUART
66extern char sb1250_duart_present[];
67#endif
68#endif
69
70static struct irq_chip sb1250_irq_type = { 60static struct irq_chip sb1250_irq_type = {
71 .name = "SB1250-IMR", 61 .name = "SB1250-IMR",
72 .ack = ack_sb1250_irq, 62 .ack = ack_sb1250_irq,
@@ -313,55 +303,10 @@ void __init arch_init_irq(void)
313 * does its own management of IP7. 303 * does its own management of IP7.
314 */ 304 */
315 305
316#ifdef CONFIG_KGDB
317 imask |= STATUSF_IP6;
318#endif
319 /* Enable necessary IPs, disable the rest */ 306 /* Enable necessary IPs, disable the rest */
320 change_c0_status(ST0_IM, imask); 307 change_c0_status(ST0_IM, imask);
321
322#ifdef CONFIG_KGDB
323 if (kgdb_flag) {
324 kgdb_irq = K_INT_UART_0 + kgdb_port;
325
326#ifdef CONFIG_SERIAL_SB1250_DUART
327 sb1250_duart_present[kgdb_port] = 0;
328#endif
329 /* Setup uart 1 settings, mapper */
330 __raw_writeq(M_DUART_IMR_BRK,
331 IOADDR(A_DUART_IMRREG(kgdb_port)));
332
333 __raw_writeq(IMR_IP6_VAL,
334 IOADDR(A_IMR_REGISTER(0,
335 R_IMR_INTERRUPT_MAP_BASE) +
336 (kgdb_irq << 3)));
337 sb1250_unmask_irq(0, kgdb_irq);
338 }
339#endif
340}
341
342#ifdef CONFIG_KGDB
343
344#include <linux/delay.h>
345
346#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
347#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
348
349static void sb1250_kgdb_interrupt(void)
350{
351 /*
352 * Clear break-change status (allow some time for the remote
353 * host to stop the break, since we would see another
354 * interrupt on the end-of-break too)
355 */
356 kstat_this_cpu.irqs[kgdb_irq]++;
357 mdelay(500);
358 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
359 M_DUART_RX_EN | M_DUART_TX_EN);
360 set_async_breakpoint(&get_irq_regs()->cp0_epc);
361} 308}
362 309
363#endif /* CONFIG_KGDB */
364
365extern void sb1250_mailbox_interrupt(void); 310extern void sb1250_mailbox_interrupt(void);
366 311
367static inline void dispatch_ip2(void) 312static inline void dispatch_ip2(void)
@@ -407,11 +352,6 @@ asmlinkage void plat_irq_dispatch(void)
407 sb1250_mailbox_interrupt(); 352 sb1250_mailbox_interrupt();
408#endif 353#endif
409 354
410#ifdef CONFIG_KGDB
411 else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
412 sb1250_kgdb_interrupt();
413#endif
414
415 else if (pending & CAUSEF_IP2) 355 else if (pending & CAUSEF_IP2)
416 dispatch_ip2(); 356 dispatch_ip2();
417 else 357 else
diff --git a/arch/mips/sibyte/swarm/Makefile b/arch/mips/sibyte/swarm/Makefile
index 255d692bfa1..f18ba9201bb 100644
--- a/arch/mips/sibyte/swarm/Makefile
+++ b/arch/mips/sibyte/swarm/Makefile
@@ -1,4 +1,3 @@
1obj-y := setup.o rtc_xicor1241.o rtc_m41t81.o 1obj-y := setup.o rtc_xicor1241.o rtc_m41t81.o
2 2
3obj-$(CONFIG_I2C_BOARDINFO) += swarm-i2c.o 3obj-$(CONFIG_I2C_BOARDINFO) += swarm-i2c.o
4obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/sibyte/swarm/dbg_io.c b/arch/mips/sibyte/swarm/dbg_io.c
deleted file mode 100644
index b97ae304848..00000000000
--- a/arch/mips/sibyte/swarm/dbg_io.c
+++ /dev/null
@@ -1,76 +0,0 @@
1/*
2 * kgdb debug routines for SiByte boards.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/* -------------------- BEGINNING OF CONFIG --------------------- */
15
16#include <linux/delay.h>
17#include <asm/io.h>
18#include <asm/sibyte/sb1250.h>
19#include <asm/sibyte/sb1250_regs.h>
20#include <asm/sibyte/sb1250_uart.h>
21#include <asm/sibyte/sb1250_int.h>
22#include <asm/addrspace.h>
23
24/*
25 * We use the second serial port for kgdb traffic.
26 * 115200, 8, N, 1.
27 */
28
29#define BAUD_RATE 115200
30#define CLK_DIVISOR V_DUART_BAUD_RATE(BAUD_RATE)
31#define DATA_BITS V_DUART_BITS_PER_CHAR_8 /* or 7 */
32#define PARITY V_DUART_PARITY_MODE_NONE /* or even */
33#define STOP_BITS M_DUART_STOP_BIT_LEN_1 /* or 2 */
34
35static int duart_initialized = 0; /* 0: need to be init'ed by kgdb */
36
37/* -------------------- END OF CONFIG --------------------- */
38extern int kgdb_port;
39
40#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
41#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
42
43void putDebugChar(unsigned char c);
44unsigned char getDebugChar(void);
45static void
46duart_init(int clk_divisor, int data, int parity, int stop)
47{
48 duart_out(R_DUART_MODE_REG_1, data | parity);
49 duart_out(R_DUART_MODE_REG_2, stop);
50 duart_out(R_DUART_CLK_SEL, clk_divisor);
51
52 duart_out(R_DUART_CMD, M_DUART_RX_EN | M_DUART_TX_EN); /* enable rx and tx */
53}
54
55void
56putDebugChar(unsigned char c)
57{
58 if (!duart_initialized) {
59 duart_initialized = 1;
60 duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS);
61 }
62 while ((duart_in(R_DUART_STATUS) & M_DUART_TX_RDY) == 0);
63 duart_out(R_DUART_TX_HOLD, c);
64}
65
66unsigned char
67getDebugChar(void)
68{
69 if (!duart_initialized) {
70 duart_initialized = 1;
71 duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS);
72 }
73 while ((duart_in(R_DUART_STATUS) & M_DUART_RX_RDY) == 0) ;
74 return duart_in(R_DUART_RX_HOLD);
75}
76
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 6de4c5aa92b..840fe757c48 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -1,3 +1,27 @@
1config MACH_TX39XX
2 bool
3 select MACH_TXX9
4 select SYS_HAS_CPU_TX39XX
5
6config MACH_TX49XX
7 bool
8 select MACH_TXX9
9 select CEVT_R4K
10 select CSRC_R4K
11 select IRQ_CPU
12 select SYS_HAS_CPU_TX49XX
13 select SYS_SUPPORTS_64BIT_KERNEL
14
15config MACH_TXX9
16 bool
17 select DMA_NONCOHERENT
18 select SWAP_IO_SPACE
19 select SYS_HAS_EARLY_PRINTK
20 select SYS_SUPPORTS_32BIT_KERNEL
21 select SYS_SUPPORTS_LITTLE_ENDIAN
22 select SYS_SUPPORTS_BIG_ENDIAN
23 select GENERIC_HARDIRQS_NO__DO_IRQ
24
1config TOSHIBA_JMR3927 25config TOSHIBA_JMR3927
2 bool "Toshiba JMR-TX3927 board" 26 bool "Toshiba JMR-TX3927 board"
3 depends on MACH_TX39XX 27 depends on MACH_TX39XX
@@ -24,68 +48,37 @@ config TOSHIBA_RBTX4938
24config SOC_TX3927 48config SOC_TX3927
25 bool 49 bool
26 select CEVT_TXX9 50 select CEVT_TXX9
27 select DMA_NONCOHERENT
28 select HAS_TXX9_SERIAL 51 select HAS_TXX9_SERIAL
29 select HW_HAS_PCI 52 select HW_HAS_PCI
30 select IRQ_TXX9 53 select IRQ_TXX9
31 select SWAP_IO_SPACE
32 select SYS_HAS_CPU_TX39XX
33 select SYS_SUPPORTS_32BIT_KERNEL
34 select SYS_SUPPORTS_LITTLE_ENDIAN
35 select SYS_SUPPORTS_BIG_ENDIAN
36 select GENERIC_HARDIRQS_NO__DO_IRQ
37 select GPIO_TXX9 54 select GPIO_TXX9
38 55
39config SOC_TX4927 56config SOC_TX4927
40 bool 57 bool
41 select CEVT_R4K
42 select CSRC_R4K
43 select CEVT_TXX9 58 select CEVT_TXX9
44 select DMA_NONCOHERENT
45 select HAS_TXX9_SERIAL 59 select HAS_TXX9_SERIAL
46 select HW_HAS_PCI 60 select HW_HAS_PCI
47 select IRQ_CPU
48 select IRQ_TXX9 61 select IRQ_TXX9
49 select PCI_TX4927 62 select PCI_TX4927
50 select SWAP_IO_SPACE
51 select SYS_HAS_CPU_TX49XX
52 select SYS_SUPPORTS_32BIT_KERNEL
53 select SYS_SUPPORTS_64BIT_KERNEL
54 select SYS_SUPPORTS_LITTLE_ENDIAN
55 select SYS_SUPPORTS_BIG_ENDIAN
56 select SYS_SUPPORTS_KGDB
57 select GENERIC_HARDIRQS_NO__DO_IRQ
58 select GPIO_TXX9 63 select GPIO_TXX9
59 64
60config SOC_TX4938 65config SOC_TX4938
61 bool 66 bool
62 select CEVT_R4K
63 select CSRC_R4K
64 select CEVT_TXX9 67 select CEVT_TXX9
65 select DMA_NONCOHERENT
66 select HAS_TXX9_SERIAL 68 select HAS_TXX9_SERIAL
67 select HW_HAS_PCI 69 select HW_HAS_PCI
68 select IRQ_CPU
69 select IRQ_TXX9 70 select IRQ_TXX9
70 select PCI_TX4927 71 select PCI_TX4927
71 select SWAP_IO_SPACE
72 select SYS_HAS_CPU_TX49XX
73 select SYS_SUPPORTS_32BIT_KERNEL
74 select SYS_SUPPORTS_64BIT_KERNEL
75 select SYS_SUPPORTS_LITTLE_ENDIAN
76 select SYS_SUPPORTS_BIG_ENDIAN
77 select SYS_SUPPORTS_KGDB
78 select GENERIC_HARDIRQS_NO__DO_IRQ
79 select GPIO_TXX9 72 select GPIO_TXX9
80 73
81config TOSHIBA_FPCIB0 74config TOSHIBA_FPCIB0
82 bool "FPCIB0 Backplane Support" 75 bool "FPCIB0 Backplane Support"
83 depends on PCI && (MACH_TX39XX || MACH_TX49XX) 76 depends on PCI && MACH_TXX9
84 select I8259 77 select I8259
85 78
86config PICMG_PCI_BACKPLANE_DEFAULT 79config PICMG_PCI_BACKPLANE_DEFAULT
87 bool "Support for PICMG PCI Backplane" 80 bool "Support for PICMG PCI Backplane"
88 depends on PCI && (MACH_TX39XX || MACH_TX49XX) 81 depends on PCI && MACH_TXX9
89 default y if !TOSHIBA_FPCIB0 82 default y if !TOSHIBA_FPCIB0
90 83
91if TOSHIBA_RBTX4938 84if TOSHIBA_RBTX4938
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 9c120771e65..9bb34af26b7 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -4,9 +4,9 @@
4 4
5obj-y += setup.o 5obj-y += setup.o
6obj-$(CONFIG_PCI) += pci.o 6obj-$(CONFIG_PCI) += pci.o
7obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o
7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o 8obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
8obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o 9obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 10obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
10obj-$(CONFIG_KGDB) += dbgio.o
11 11
12EXTRA_CFLAGS += -Werror 12EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/generic/dbgio.c b/arch/mips/txx9/generic/dbgio.c
deleted file mode 100644
index 33b9c672a32..00000000000
--- a/arch/mips/txx9/generic/dbgio.c
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * linux/arch/mips/tx4938/common/dbgio.c
3 *
4 * kgdb interface for gdb
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2005 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 * Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>
32 */
33
34#include <linux/types>
35
36extern u8 txx9_sio_kdbg_rd(void);
37extern int txx9_sio_kdbg_wr( u8 ch );
38
39u8 getDebugChar(void)
40{
41 return (txx9_sio_kdbg_rd());
42}
43
44int putDebugChar(u8 byte)
45{
46 return (txx9_sio_kdbg_wr(byte));
47}
48
diff --git a/arch/mips/txx9/generic/irq_tx3927.c b/arch/mips/txx9/generic/irq_tx3927.c
new file mode 100644
index 00000000000..c683f593eda
--- /dev/null
+++ b/arch/mips/txx9/generic/irq_tx3927.c
@@ -0,0 +1,25 @@
1/*
2 * Common tx3927 irq handler
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright 2001 MontaVista Software Inc.
9 * Copyright (C) 2000-2001 Toshiba Corporation
10 */
11#include <linux/init.h>
12#include <asm/txx9irq.h>
13#include <asm/txx9/tx3927.h>
14
15void __init tx3927_irq_init(void)
16{
17 int i;
18
19 txx9_irq_init(TX3927_IRC_REG);
20 /* raise priority for timers, sio */
21 for (i = 0; i < TX3927_NR_TMR; i++)
22 txx9_irq_set_pri(TX3927_IR_TMR(i), 6);
23 for (i = 0; i < TX3927_NR_SIO; i++)
24 txx9_irq_set_pri(TX3927_IR_SIO(i), 7);
25}
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index 0b92d8c1320..7b637a7c0e6 100644
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -386,3 +386,39 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
386{ 386{
387 return txx9_board_vec->pci_map_irq(dev, slot, pin); 387 return txx9_board_vec->pci_map_irq(dev, slot, pin);
388} 388}
389
390char * (*txx9_board_pcibios_setup)(char *str) __devinitdata;
391
392char *__devinit txx9_pcibios_setup(char *str)
393{
394 if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
395 return NULL;
396 if (!strcmp(str, "picmg")) {
397 /* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
398 (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
399 txx9_pci_option |= TXX9_PCI_OPT_PICMG;
400 return NULL;
401 } else if (!strcmp(str, "nopicmg")) {
402 /* non-PICMG compliant backplane (TOSHIBA
403 RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
404 txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
405 return NULL;
406 } else if (!strncmp(str, "clk=", 4)) {
407 char *val = str + 4;
408 txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
409 if (strcmp(val, "33") == 0)
410 txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
411 else if (strcmp(val, "66") == 0)
412 txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
413 else /* "auto" */
414 txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
415 return NULL;
416 } else if (!strncmp(str, "err=", 4)) {
417 if (!strcmp(str + 4, "panic"))
418 txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
419 else if (!strcmp(str + 4, "ignore"))
420 txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
421 return NULL;
422 }
423 return str;
424}
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 8c60c78b9a9..1bc57d0f4c5 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -20,9 +20,13 @@
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/platform_device.h>
24#include <linux/serial_core.h>
23#include <asm/bootinfo.h> 25#include <asm/bootinfo.h>
24#include <asm/time.h> 26#include <asm/time.h>
27#include <asm/reboot.h>
25#include <asm/txx9/generic.h> 28#include <asm/txx9/generic.h>
29#include <asm/txx9/pci.h>
26#ifdef CONFIG_CPU_TX49XX 30#ifdef CONFIG_CPU_TX49XX
27#include <asm/txx9/tx4938.h> 31#include <asm/txx9/tx4938.h>
28#endif 32#endif
@@ -187,6 +191,117 @@ char * __init prom_getcmdline(void)
187 return &(arcs_cmdline[0]); 191 return &(arcs_cmdline[0]);
188} 192}
189 193
194static void __noreturn txx9_machine_halt(void)
195{
196 local_irq_disable();
197 clear_c0_status(ST0_IM);
198 while (1) {
199 if (cpu_wait) {
200 (*cpu_wait)();
201 if (cpu_has_counter) {
202 /*
203 * Clear counter interrupt while it
204 * breaks WAIT instruction even if
205 * masked.
206 */
207 write_c0_compare(0);
208 }
209 }
210 }
211}
212
213/* Watchdog support */
214void __init txx9_wdt_init(unsigned long base)
215{
216 struct resource res = {
217 .start = base,
218 .end = base + 0x100 - 1,
219 .flags = IORESOURCE_MEM,
220 };
221 platform_device_register_simple("txx9wdt", -1, &res, 1);
222}
223
224/* SPI support */
225void __init txx9_spi_init(int busid, unsigned long base, int irq)
226{
227 struct resource res[] = {
228 {
229 .start = base,
230 .end = base + 0x20 - 1,
231 .flags = IORESOURCE_MEM,
232 }, {
233 .start = irq,
234 .flags = IORESOURCE_IRQ,
235 },
236 };
237 platform_device_register_simple("spi_txx9", busid,
238 res, ARRAY_SIZE(res));
239}
240
241void __init txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr)
242{
243 struct platform_device *pdev =
244 platform_device_alloc("tc35815-mac", id);
245 if (!pdev ||
246 platform_device_add_data(pdev, ethaddr, 6) ||
247 platform_device_add(pdev))
248 platform_device_put(pdev);
249}
250
251void __init txx9_sio_init(unsigned long baseaddr, int irq,
252 unsigned int line, unsigned int sclk, int nocts)
253{
254#ifdef CONFIG_SERIAL_TXX9
255 struct uart_port req;
256
257 memset(&req, 0, sizeof(req));
258 req.line = line;
259 req.iotype = UPIO_MEM;
260 req.membase = ioremap(baseaddr, 0x24);
261 req.mapbase = baseaddr;
262 req.irq = irq;
263 if (!nocts)
264 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
265 if (sclk) {
266 req.flags |= UPF_MAGIC_MULTIPLIER /*USE_SCLK*/;
267 req.uartclk = sclk;
268 } else
269 req.uartclk = TXX9_IMCLK;
270 early_serial_txx9_setup(&req);
271#endif /* CONFIG_SERIAL_TXX9 */
272}
273
274#ifdef CONFIG_EARLY_PRINTK
275static void __init null_prom_putchar(char c)
276{
277}
278void (*txx9_prom_putchar)(char c) __initdata = null_prom_putchar;
279
280void __init prom_putchar(char c)
281{
282 txx9_prom_putchar(c);
283}
284
285static void __iomem *early_txx9_sio_port;
286
287static void __init early_txx9_sio_putchar(char c)
288{
289#define TXX9_SICISR 0x0c
290#define TXX9_SITFIFO 0x1c
291#define TXX9_SICISR_TXALS 0x00000002
292 while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) &
293 TXX9_SICISR_TXALS))
294 ;
295 __raw_writel(c, early_txx9_sio_port + TXX9_SITFIFO);
296}
297
298void __init txx9_sio_putchar_init(unsigned long baseaddr)
299{
300 early_txx9_sio_port = ioremap(baseaddr, 0x24);
301 txx9_prom_putchar = early_txx9_sio_putchar;
302}
303#endif /* CONFIG_EARLY_PRINTK */
304
190/* wrappers */ 305/* wrappers */
191void __init plat_mem_setup(void) 306void __init plat_mem_setup(void)
192{ 307{
@@ -194,6 +309,15 @@ void __init plat_mem_setup(void)
194 ioport_resource.end = ~0UL; /* no limit */ 309 ioport_resource.end = ~0UL; /* no limit */
195 iomem_resource.start = 0; 310 iomem_resource.start = 0;
196 iomem_resource.end = ~0UL; /* no limit */ 311 iomem_resource.end = ~0UL; /* no limit */
312
313 /* fallback restart/halt routines */
314 _machine_restart = (void (*)(char *))txx9_machine_halt;
315 _machine_halt = txx9_machine_halt;
316 pm_power_off = txx9_machine_halt;
317
318#ifdef CONFIG_PCI
319 pcibios_plat_setup = txx9_pcibios_setup;
320#endif
197 txx9_board_vec->mem_setup(); 321 txx9_board_vec->mem_setup();
198} 322}
199 323
diff --git a/arch/mips/txx9/generic/setup_tx3927.c b/arch/mips/txx9/generic/setup_tx3927.c
new file mode 100644
index 00000000000..7bd963d37fc
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx3927.c
@@ -0,0 +1,130 @@
1/*
2 * TX3927 setup routines
3 * Based on linux/arch/mips/txx9/jmr3927/setup.c
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Copyright (C) 2000-2001 Toshiba Corporation
7 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/param.h>
17#include <linux/io.h>
18#include <asm/mipsregs.h>
19#include <asm/txx9irq.h>
20#include <asm/txx9tmr.h>
21#include <asm/txx9pio.h>
22#include <asm/txx9/generic.h>
23#include <asm/txx9/tx3927.h>
24
25void __init tx3927_wdt_init(void)
26{
27 txx9_wdt_init(TX3927_TMR_REG(2));
28}
29
30void __init tx3927_setup(void)
31{
32 int i;
33 unsigned int conf;
34
35 /* don't enable - see errata */
36 txx9_ccfg_toeon = 0;
37 if (strstr(prom_getcmdline(), "toeon") != NULL)
38 txx9_ccfg_toeon = 1;
39
40 txx9_reg_res_init(TX3927_REV_PCODE(), TX3927_REG_BASE,
41 TX3927_REG_SIZE);
42
43 /* SDRAMC,ROMC are configured by PROM */
44 for (i = 0; i < 8; i++) {
45 if (!(tx3927_romcptr->cr[i] & 0x8))
46 continue; /* disabled */
47 txx9_ce_res[i].start = (unsigned long)TX3927_ROMC_BA(i);
48 txx9_ce_res[i].end =
49 txx9_ce_res[i].start + TX3927_ROMC_SIZE(i) - 1;
50 request_resource(&iomem_resource, &txx9_ce_res[i]);
51 }
52
53 /* clocks */
54 txx9_gbus_clock = txx9_cpu_clock / 2;
55 /* change default value to udelay/mdelay take reasonable time */
56 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
57
58 /* CCFG */
59 /* enable Timeout BusError */
60 if (txx9_ccfg_toeon)
61 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
62
63 /* clear BusErrorOnWrite flag */
64 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
65 if (read_c0_conf() & TX39_CONF_WBON)
66 /* Disable PCI snoop */
67 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
68 else
69 /* Enable PCI SNOOP - with write through only */
70 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
71 /* do reset on watchdog */
72 tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
73
74 printk(KERN_INFO "TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
75 tx3927_ccfgptr->crir,
76 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
77
78 /* TMR */
79 for (i = 0; i < TX3927_NR_TMR; i++)
80 txx9_tmr_init(TX3927_TMR_REG(i));
81
82 /* DMA */
83 tx3927_dmaptr->mcr = 0;
84 for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
85 /* reset channel */
86 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
87 tx3927_dmaptr->ch[i].ccr = 0;
88 }
89 /* enable DMA */
90#ifdef __BIG_ENDIAN
91 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
92#else
93 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
94#endif
95
96 /* PIO */
97 __raw_writel(0, &tx3927_pioptr->maskcpu);
98 __raw_writel(0, &tx3927_pioptr->maskext);
99 txx9_gpio_init(TX3927_PIO_REG, 0, 16);
100
101 conf = read_c0_conf();
102 if (!(conf & TX39_CONF_ICE))
103 printk(KERN_INFO "TX3927 I-Cache disabled.\n");
104 if (!(conf & TX39_CONF_DCE))
105 printk(KERN_INFO "TX3927 D-Cache disabled.\n");
106 else if (!(conf & TX39_CONF_WBON))
107 printk(KERN_INFO "TX3927 D-Cache WriteThrough.\n");
108 else if (!(conf & TX39_CONF_CWFON))
109 printk(KERN_INFO "TX3927 D-Cache WriteBack.\n");
110 else
111 printk(KERN_INFO "TX3927 D-Cache WriteBack (CWF) .\n");
112}
113
114void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr)
115{
116 txx9_clockevent_init(TX3927_TMR_REG(evt_tmrnr),
117 TXX9_IRQ_BASE + TX3927_IR_TMR(evt_tmrnr),
118 TXX9_IMCLK);
119 txx9_clocksource_init(TX3927_TMR_REG(src_tmrnr), TXX9_IMCLK);
120}
121
122void __init tx3927_sio_init(unsigned int sclk, unsigned int cts_mask)
123{
124 int i;
125
126 for (i = 0; i < 2; i++)
127 txx9_sio_init(TX3927_SIO_REG(i),
128 TXX9_IRQ_BASE + TX3927_IR_SIO(i),
129 i, sclk, (1 << i) & cts_mask);
130}
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
index 89d6e28add9..f80d4b7a694 100644
--- a/arch/mips/txx9/generic/setup_tx4927.c
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -13,7 +13,6 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/ioport.h> 14#include <linux/ioport.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h> 16#include <linux/param.h>
18#include <asm/txx9irq.h> 17#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h> 18#include <asm/txx9tmr.h>
@@ -21,7 +20,7 @@
21#include <asm/txx9/generic.h> 20#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4927.h> 21#include <asm/txx9/tx4927.h>
23 22
24void __init tx4927_wdr_init(void) 23static void __init tx4927_wdr_init(void)
25{ 24{
26 /* clear WatchDogReset (W1C) */ 25 /* clear WatchDogReset (W1C) */
27 tx4927_ccfg_set(TX4927_CCFG_WDRST); 26 tx4927_ccfg_set(TX4927_CCFG_WDRST);
@@ -29,6 +28,11 @@ void __init tx4927_wdr_init(void)
29 tx4927_ccfg_set(TX4927_CCFG_WR); 28 tx4927_ccfg_set(TX4927_CCFG_WR);
30} 29}
31 30
31void __init tx4927_wdt_init(void)
32{
33 txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
34}
35
32static struct resource tx4927_sdram_resource[4]; 36static struct resource tx4927_sdram_resource[4];
33 37
34void __init tx4927_setup(void) 38void __init tx4927_setup(void)
@@ -173,22 +177,12 @@ void __init tx4927_time_init(unsigned int tmrnr)
173 TXX9_IMCLK); 177 TXX9_IMCLK);
174} 178}
175 179
176void __init tx4927_setup_serial(void) 180void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask)
177{ 181{
178#ifdef CONFIG_SERIAL_TXX9
179 int i; 182 int i;
180 struct uart_port req; 183
181 184 for (i = 0; i < 2; i++)
182 for (i = 0; i < 2; i++) { 185 txx9_sio_init(TX4927_SIO_REG(i) & 0xfffffffffULL,
183 memset(&req, 0, sizeof(req)); 186 TXX9_IRQ_BASE + TX4927_IR_SIO(i),
184 req.line = i; 187 i, sclk, (1 << i) & cts_mask);
185 req.iotype = UPIO_MEM;
186 req.membase = (unsigned char __iomem *)TX4927_SIO_REG(i);
187 req.mapbase = TX4927_SIO_REG(i) & 0xfffffffffULL;
188 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
189 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
190 req.uartclk = TXX9_IMCLK;
191 early_serial_txx9_setup(&req);
192 }
193#endif /* CONFIG_SERIAL_TXX9 */
194} 188}
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index 317378d8579..f3040b9ba05 100644
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -13,7 +13,6 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/ioport.h> 14#include <linux/ioport.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h> 16#include <linux/param.h>
18#include <asm/txx9irq.h> 17#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h> 18#include <asm/txx9tmr.h>
@@ -21,7 +20,7 @@
21#include <asm/txx9/generic.h> 20#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4938.h> 21#include <asm/txx9/tx4938.h>
23 22
24void __init tx4938_wdr_init(void) 23static void __init tx4938_wdr_init(void)
25{ 24{
26 /* clear WatchDogReset (W1C) */ 25 /* clear WatchDogReset (W1C) */
27 tx4938_ccfg_set(TX4938_CCFG_WDRST); 26 tx4938_ccfg_set(TX4938_CCFG_WDRST);
@@ -29,6 +28,11 @@ void __init tx4938_wdr_init(void)
29 tx4938_ccfg_set(TX4938_CCFG_WR); 28 tx4938_ccfg_set(TX4938_CCFG_WR);
30} 29}
31 30
31void __init tx4938_wdt_init(void)
32{
33 txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
34}
35
32static struct resource tx4938_sdram_resource[4]; 36static struct resource tx4938_sdram_resource[4];
33static struct resource tx4938_sram_resource; 37static struct resource tx4938_sram_resource;
34 38
@@ -233,11 +237,9 @@ void __init tx4938_time_init(unsigned int tmrnr)
233 TXX9_IMCLK); 237 TXX9_IMCLK);
234} 238}
235 239
236void __init tx4938_setup_serial(void) 240void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask)
237{ 241{
238#ifdef CONFIG_SERIAL_TXX9
239 int i; 242 int i;
240 struct uart_port req;
241 unsigned int ch_mask = 0; 243 unsigned int ch_mask = 0;
242 244
243 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL) 245 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
@@ -245,15 +247,24 @@ void __init tx4938_setup_serial(void)
245 for (i = 0; i < 2; i++) { 247 for (i = 0; i < 2; i++) {
246 if ((1 << i) & ch_mask) 248 if ((1 << i) & ch_mask)
247 continue; 249 continue;
248 memset(&req, 0, sizeof(req)); 250 txx9_sio_init(TX4938_SIO_REG(i) & 0xfffffffffULL,
249 req.line = i; 251 TXX9_IRQ_BASE + TX4938_IR_SIO(i),
250 req.iotype = UPIO_MEM; 252 i, sclk, (1 << i) & cts_mask);
251 req.membase = (unsigned char __iomem *)TX4938_SIO_REG(i);
252 req.mapbase = TX4938_SIO_REG(i) & 0xfffffffffULL;
253 req.irq = TXX9_IRQ_BASE + TX4938_IR_SIO(i);
254 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
255 req.uartclk = TXX9_IMCLK;
256 early_serial_txx9_setup(&req);
257 } 253 }
258#endif /* CONFIG_SERIAL_TXX9 */ 254}
255
256void __init tx4938_spi_init(int busid)
257{
258 txx9_spi_init(busid, TX4938_SPI_REG & 0xfffffffffULL,
259 TXX9_IRQ_BASE + TX4938_IR_SPI);
260}
261
262void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
263{
264 u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
265
266 if (addr0 && (pcfg & TX4938_PCFG_ETH0_SEL))
267 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH0, addr0);
268 if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL))
269 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1);
259} 270}
diff --git a/arch/mips/txx9/generic/smsc_fdc37m81x.c b/arch/mips/txx9/generic/smsc_fdc37m81x.c
index 69e487467fa..a2b2d62d88e 100644
--- a/arch/mips/txx9/generic/smsc_fdc37m81x.c
+++ b/arch/mips/txx9/generic/smsc_fdc37m81x.c
@@ -15,8 +15,6 @@
15#include <asm/io.h> 15#include <asm/io.h>
16#include <asm/txx9/smsc_fdc37m81x.h> 16#include <asm/txx9/smsc_fdc37m81x.h>
17 17
18#define DEBUG
19
20/* Common Registers */ 18/* Common Registers */
21#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 19#define SMSC_FDC37M81X_CONFIG_INDEX 0x00
22#define SMSC_FDC37M81X_CONFIG_DATA 0x01 20#define SMSC_FDC37M81X_CONFIG_DATA 0x01
@@ -55,7 +53,7 @@
55#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa 53#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
56#define SMSC_FDC37M81X_CHIP_ID 0x4d 54#define SMSC_FDC37M81X_CHIP_ID 0x4d
57 55
58static unsigned long g_smsc_fdc37m81x_base = 0; 56static unsigned long g_smsc_fdc37m81x_base;
59 57
60static inline unsigned char smsc_fdc37m81x_rd(unsigned char index) 58static inline unsigned char smsc_fdc37m81x_rd(unsigned char index)
61{ 59{
@@ -107,7 +105,8 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port)
107 u8 chip_id; 105 u8 chip_id;
108 106
109 if (g_smsc_fdc37m81x_base) 107 if (g_smsc_fdc37m81x_base)
110 printk("smsc_fdc37m81x_init() stepping on old base=0x%0*lx\n", 108 printk(KERN_WARNING "%s: stepping on old base=0x%0*lx\n",
109 __func__,
111 field, g_smsc_fdc37m81x_base); 110 field, g_smsc_fdc37m81x_base);
112 111
113 g_smsc_fdc37m81x_base = port; 112 g_smsc_fdc37m81x_base = port;
@@ -118,7 +117,7 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port)
118 if (chip_id == SMSC_FDC37M81X_CHIP_ID) 117 if (chip_id == SMSC_FDC37M81X_CHIP_ID)
119 smsc_fdc37m81x_config_end(); 118 smsc_fdc37m81x_config_end();
120 else { 119 else {
121 printk("smsc_fdc37m81x_init() unknow chip id 0x%02x\n", 120 printk(KERN_WARNING "%s: unknow chip id 0x%02x\n", __func__,
122 chip_id); 121 chip_id);
123 g_smsc_fdc37m81x_base = 0; 122 g_smsc_fdc37m81x_base = 0;
124 } 123 }
@@ -127,22 +126,23 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port)
127} 126}
128 127
129#ifdef DEBUG 128#ifdef DEBUG
130void smsc_fdc37m81x_config_dump_one(char *key, u8 dev, u8 reg) 129static void smsc_fdc37m81x_config_dump_one(const char *key, u8 dev, u8 reg)
131{ 130{
132 printk("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg, 131 printk(KERN_INFO "%s: dev=0x%02x reg=0x%02x val=0x%02x\n",
132 key, dev, reg,
133 smsc_fdc37m81x_rd(reg)); 133 smsc_fdc37m81x_rd(reg));
134} 134}
135 135
136void smsc_fdc37m81x_config_dump(void) 136void smsc_fdc37m81x_config_dump(void)
137{ 137{
138 u8 orig; 138 u8 orig;
139 char *fname = "smsc_fdc37m81x_config_dump()"; 139 const char *fname = __func__;
140 140
141 smsc_fdc37m81x_config_beg(); 141 smsc_fdc37m81x_config_beg();
142 142
143 orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM); 143 orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM);
144 144
145 printk("%s: common\n", fname); 145 printk(KERN_INFO "%s: common\n", fname);
146 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, 146 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
147 SMSC_FDC37M81X_DNUM); 147 SMSC_FDC37M81X_DNUM);
148 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, 148 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
@@ -154,7 +154,7 @@ void smsc_fdc37m81x_config_dump(void)
154 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, 154 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
155 SMSC_FDC37M81X_PMGT); 155 SMSC_FDC37M81X_PMGT);
156 156
157 printk("%s: keyboard\n", fname); 157 printk(KERN_INFO "%s: keyboard\n", fname);
158 smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD); 158 smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD);
159 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, 159 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
160 SMSC_FDC37M81X_ACTIVE); 160 SMSC_FDC37M81X_ACTIVE);
diff --git a/arch/mips/txx9/jmr3927/Makefile b/arch/mips/txx9/jmr3927/Makefile
index ba292c94566..20d61ac543e 100644
--- a/arch/mips/txx9/jmr3927/Makefile
+++ b/arch/mips/txx9/jmr3927/Makefile
@@ -3,6 +3,5 @@
3# 3#
4 4
5obj-y += prom.o irq.o setup.o 5obj-y += prom.o irq.o setup.o
6obj-$(CONFIG_KGDB) += kgdb_io.o
7 6
8EXTRA_CFLAGS += -Werror 7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c
index 070c9a115e5..6ec626c9473 100644
--- a/arch/mips/txx9/jmr3927/irq.c
+++ b/arch/mips/txx9/jmr3927/irq.c
@@ -30,15 +30,11 @@
30 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */ 31 */
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/sched.h>
34#include <linux/types.h> 33#include <linux/types.h>
35#include <linux/interrupt.h> 34#include <linux/interrupt.h>
36 35
37#include <asm/io.h> 36#include <asm/io.h>
38#include <asm/mipsregs.h> 37#include <asm/mipsregs.h>
39#include <asm/system.h>
40
41#include <asm/processor.h>
42#include <asm/txx9/generic.h> 38#include <asm/txx9/generic.h>
43#include <asm/txx9/jmr3927.h> 39#include <asm/txx9/jmr3927.h>
44 40
@@ -46,13 +42,6 @@
46#error JMR3927_IRQ_END > NR_IRQS 42#error JMR3927_IRQ_END > NR_IRQS
47#endif 43#endif
48 44
49static unsigned char irc_level[TX3927_NUM_IR] = {
50 5, 5, 5, 5, 5, 5, /* INT[5:0] */
51 7, 7, /* SIO */
52 5, 5, 5, 0, 0, /* DMA, PIO, PCI */
53 6, 6, 6 /* TMR */
54};
55
56/* 45/*
57 * CP0_STATUS is a thread's resource (saved/restored on context switch). 46 * CP0_STATUS is a thread's resource (saved/restored on context switch).
58 * So disable_irq/enable_irq MUST handle IOC/IRC registers. 47 * So disable_irq/enable_irq MUST handle IOC/IRC registers.
@@ -103,26 +92,18 @@ static int jmr3927_irq_dispatch(int pending)
103 return irq; 92 return irq;
104} 93}
105 94
106#ifdef CONFIG_PCI 95static struct irq_chip jmr3927_irq_ioc = {
107static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) 96 .name = "jmr3927_ioc",
108{ 97 .ack = mask_irq_ioc,
109 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); 98 .mask = mask_irq_ioc,
110 printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", 99 .mask_ack = mask_irq_ioc,
111 tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); 100 .unmask = unmask_irq_ioc,
112
113 return IRQ_HANDLED;
114}
115static struct irqaction pcierr_action = {
116 .handler = jmr3927_pcierr_interrupt,
117 .mask = CPU_MASK_NONE,
118 .name = "PCI error",
119}; 101};
120#endif
121
122static void __init jmr3927_irq_init(void);
123 102
124void __init jmr3927_irq_setup(void) 103void __init jmr3927_irq_setup(void)
125{ 104{
105 int i;
106
126 txx9_irq_dispatch = jmr3927_irq_dispatch; 107 txx9_irq_dispatch = jmr3927_irq_dispatch;
127 /* Now, interrupt control disabled, */ 108 /* Now, interrupt control disabled, */
128 /* all IRC interrupts are masked, */ 109 /* all IRC interrupts are masked, */
@@ -138,34 +119,10 @@ void __init jmr3927_irq_setup(void)
138 /* clear PCI Reset interrupts */ 119 /* clear PCI Reset interrupts */
139 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); 120 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
140 121
141 jmr3927_irq_init(); 122 tx3927_irq_init();
123 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
124 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
142 125
143 /* setup IOC interrupt 1 (PCI, MODEM) */ 126 /* setup IOC interrupt 1 (PCI, MODEM) */
144 set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); 127 set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
145
146#ifdef CONFIG_PCI
147 setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
148#endif
149
150 /* enable all CPU interrupt bits. */
151 set_c0_status(ST0_IM); /* IE bit is still 0. */
152}
153
154static struct irq_chip jmr3927_irq_ioc = {
155 .name = "jmr3927_ioc",
156 .ack = mask_irq_ioc,
157 .mask = mask_irq_ioc,
158 .mask_ack = mask_irq_ioc,
159 .unmask = unmask_irq_ioc,
160};
161
162static void __init jmr3927_irq_init(void)
163{
164 u32 i;
165
166 txx9_irq_init(TX3927_IRC_REG);
167 for (i = 0; i < TXx9_MAX_IR; i++)
168 txx9_irq_set_pri(i, irc_level[i]);
169 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
170 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
171} 128}
diff --git a/arch/mips/txx9/jmr3927/kgdb_io.c b/arch/mips/txx9/jmr3927/kgdb_io.c
deleted file mode 100644
index 5bd757e56f7..00000000000
--- a/arch/mips/txx9/jmr3927/kgdb_io.c
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Low level uart routines to directly access a TX[34]927 SIO.
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ahennessy@mvista.com or source@mvista.com
8 *
9 * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c
10 *
11 * Copyright (C) 2000-2001 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34#include <asm/txx9/jmr3927.h>
35
36#define TIMEOUT 0xffffff
37
38static int remoteDebugInitialized = 0;
39static void debugInit(int baud);
40
41int putDebugChar(unsigned char c)
42{
43 int i = 0;
44
45 if (!remoteDebugInitialized) {
46 remoteDebugInitialized = 1;
47 debugInit(38400);
48 }
49
50 do {
51 slow_down();
52 i++;
53 if (i>TIMEOUT) {
54 break;
55 }
56 } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS));
57 tx3927_sioptr(0)->tfifo = c;
58
59 return 1;
60}
61
62unsigned char getDebugChar(void)
63{
64 int i = 0;
65 int dicr;
66 char c;
67
68 if (!remoteDebugInitialized) {
69 remoteDebugInitialized = 1;
70 debugInit(38400);
71 }
72
73 /* diable RX int. */
74 dicr = tx3927_sioptr(0)->dicr;
75 tx3927_sioptr(0)->dicr = 0;
76
77 do {
78 slow_down();
79 i++;
80 if (i>TIMEOUT) {
81 break;
82 }
83 } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID)
84 ;
85 c = tx3927_sioptr(0)->rfifo;
86
87 /* clear RX int. status */
88 tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS;
89 /* enable RX int. */
90 tx3927_sioptr(0)->dicr = dicr;
91
92 return c;
93}
94
95static void debugInit(int baud)
96{
97 tx3927_sioptr(0)->lcr = 0x020;
98 tx3927_sioptr(0)->dicr = 0;
99 tx3927_sioptr(0)->disr = 0x4100;
100 tx3927_sioptr(0)->cisr = 0x014;
101 tx3927_sioptr(0)->fcr = 0;
102 tx3927_sioptr(0)->flcr = 0x02;
103 tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) |
104 TXx927_SIBGR_BCLK_T0;
105}
diff --git a/arch/mips/txx9/jmr3927/prom.c b/arch/mips/txx9/jmr3927/prom.c
index 2cadb423fac..70c4c8ec3e8 100644
--- a/arch/mips/txx9/jmr3927/prom.c
+++ b/arch/mips/txx9/jmr3927/prom.c
@@ -36,41 +36,18 @@
36 * 675 Mass Ave, Cambridge, MA 02139, USA. 36 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 */ 37 */
38#include <linux/init.h> 38#include <linux/init.h>
39#include <linux/kernel.h>
39#include <asm/bootinfo.h> 40#include <asm/bootinfo.h>
40#include <asm/txx9/generic.h> 41#include <asm/txx9/generic.h>
41#include <asm/txx9/jmr3927.h> 42#include <asm/txx9/jmr3927.h>
42 43
43#define TIMEOUT 0xffffff
44
45void
46prom_putchar(char c)
47{
48 int i = 0;
49
50 do {
51 i++;
52 if (i>TIMEOUT)
53 break;
54 } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
55 tx3927_sioptr(1)->tfifo = c;
56 return;
57}
58
59void
60puts(const char *cp)
61{
62 while (*cp)
63 prom_putchar(*cp++);
64 prom_putchar('\r');
65 prom_putchar('\n');
66}
67
68void __init jmr3927_prom_init(void) 44void __init jmr3927_prom_init(void)
69{ 45{
70 /* CCFG */ 46 /* CCFG */
71 if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) 47 if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
72 puts("Warning: TX3927 TLB off\n"); 48 printk(KERN_ERR "TX3927 TLB off\n");
73 49
74 prom_init_cmdline(); 50 prom_init_cmdline();
75 add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); 51 add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM);
52 txx9_sio_putchar_init(TX3927_SIO_REG(1));
76} 53}
diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c
index 03647ebe413..87db41be8a5 100644
--- a/arch/mips/txx9/jmr3927/setup.c
+++ b/arch/mips/txx9/jmr3927/setup.c
@@ -32,27 +32,18 @@
32#include <linux/types.h> 32#include <linux/types.h>
33#include <linux/ioport.h> 33#include <linux/ioport.h>
34#include <linux/delay.h> 34#include <linux/delay.h>
35#include <linux/pm.h>
36#include <linux/platform_device.h> 35#include <linux/platform_device.h>
37#include <linux/gpio.h> 36#include <linux/gpio.h>
38#ifdef CONFIG_SERIAL_TXX9
39#include <linux/serial_core.h>
40#endif
41#include <asm/txx9tmr.h>
42#include <asm/txx9pio.h>
43#include <asm/reboot.h> 37#include <asm/reboot.h>
38#include <asm/txx9pio.h>
44#include <asm/txx9/generic.h> 39#include <asm/txx9/generic.h>
45#include <asm/txx9/pci.h> 40#include <asm/txx9/pci.h>
46#include <asm/txx9/jmr3927.h> 41#include <asm/txx9/jmr3927.h>
47#include <asm/mipsregs.h> 42#include <asm/mipsregs.h>
48 43
49extern void puts(const char *cp); 44static void jmr3927_machine_restart(char *command)
50
51/* don't enable - see errata */
52static int jmr3927_ccfg_toeon;
53
54static inline void do_reset(void)
55{ 45{
46 local_irq_disable();
56#if 1 /* Resetting PCI bus */ 47#if 1 /* Resetting PCI bus */
57 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); 48 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
58 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); 49 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
@@ -61,33 +52,13 @@ static inline void do_reset(void)
61 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); 52 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
62#endif 53#endif
63 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); 54 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
64} 55 /* fallback */
65 56 (*_machine_halt)();
66static void jmr3927_machine_restart(char *command)
67{
68 local_irq_disable();
69 puts("Rebooting...");
70 do_reset();
71}
72
73static void jmr3927_machine_halt(void)
74{
75 puts("JMR-TX3927 halted.\n");
76 while (1);
77}
78
79static void jmr3927_machine_power_off(void)
80{
81 puts("JMR-TX3927 halted. Please turn off the power.\n");
82 while (1);
83} 57}
84 58
85static void __init jmr3927_time_init(void) 59static void __init jmr3927_time_init(void)
86{ 60{
87 txx9_clockevent_init(TX3927_TMR_REG(0), 61 tx3927_time_init(0, 1);
88 TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0),
89 JMR3927_IMCLK);
90 txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK);
91} 62}
92 63
93#define DO_WRITE_THROUGH 64#define DO_WRITE_THROUGH
@@ -102,11 +73,6 @@ static void __init jmr3927_mem_setup(void)
102 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); 73 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
103 74
104 _machine_restart = jmr3927_machine_restart; 75 _machine_restart = jmr3927_machine_restart;
105 _machine_halt = jmr3927_machine_halt;
106 pm_power_off = jmr3927_machine_power_off;
107
108 /* Reboot on panic */
109 panic_timeout = 180;
110 76
111 /* cache setup */ 77 /* cache setup */
112 { 78 {
@@ -125,7 +91,8 @@ static void __init jmr3927_mem_setup(void)
125#endif 91#endif
126 92
127 conf = read_c0_conf(); 93 conf = read_c0_conf();
128 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); 94 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE |
95 TX39_CONF_WBON | TX39_CONF_CWFON);
129 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; 96 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
130 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; 97 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
131 conf |= mips_config_wbon ? TX39_CONF_WBON : 0; 98 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
@@ -138,47 +105,14 @@ static void __init jmr3927_mem_setup(void)
138 /* initialize board */ 105 /* initialize board */
139 jmr3927_board_init(); 106 jmr3927_board_init();
140 107
141 argptr = prom_getcmdline(); 108 tx3927_sio_init(0, 1 << 1); /* ch1: noCTS */
142
143 if ((argptr = strstr(argptr, "toeon")) != NULL)
144 jmr3927_ccfg_toeon = 1;
145 argptr = prom_getcmdline();
146 if ((argptr = strstr(argptr, "ip=")) == NULL) {
147 argptr = prom_getcmdline();
148 strcat(argptr, " ip=bootp");
149 }
150
151#ifdef CONFIG_SERIAL_TXX9
152 {
153 extern int early_serial_txx9_setup(struct uart_port *port);
154 int i;
155 struct uart_port req;
156 for(i = 0; i < 2; i++) {
157 memset(&req, 0, sizeof(req));
158 req.line = i;
159 req.iotype = UPIO_MEM;
160 req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
161 req.mapbase = TX3927_SIO_REG(i);
162 req.irq = i == 0 ?
163 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
164 if (i == 0)
165 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
166 req.uartclk = JMR3927_IMCLK;
167 early_serial_txx9_setup(&req);
168 }
169 }
170#ifdef CONFIG_SERIAL_TXX9_CONSOLE 109#ifdef CONFIG_SERIAL_TXX9_CONSOLE
171 argptr = prom_getcmdline(); 110 argptr = prom_getcmdline();
172 if ((argptr = strstr(argptr, "console=")) == NULL) { 111 if (!strstr(argptr, "console="))
173 argptr = prom_getcmdline();
174 strcat(argptr, " console=ttyS1,115200"); 112 strcat(argptr, " console=ttyS1,115200");
175 }
176#endif
177#endif 113#endif
178} 114}
179 115
180static void tx3927_setup(void);
181
182static void __init jmr3927_pci_setup(void) 116static void __init jmr3927_pci_setup(void)
183{ 117{
184#ifdef CONFIG_PCI 118#ifdef CONFIG_PCI
@@ -199,32 +133,13 @@ static void __init jmr3927_pci_setup(void)
199 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); 133 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
200 } 134 }
201 tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb); 135 tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb);
136 tx3927_setup_pcierr_irq();
202#endif /* CONFIG_PCI */ 137#endif /* CONFIG_PCI */
203} 138}
204 139
205static void __init jmr3927_board_init(void) 140static void __init jmr3927_board_init(void)
206{ 141{
207 tx3927_setup();
208 jmr3927_pci_setup();
209
210 /* SIO0 DTR on */
211 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
212
213 jmr3927_led_set(0);
214
215 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
216 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
217 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
218 jmr3927_dipsw1(), jmr3927_dipsw2(),
219 jmr3927_dipsw3(), jmr3927_dipsw4());
220}
221
222static void __init tx3927_setup(void)
223{
224 int i;
225
226 txx9_cpu_clock = JMR3927_CORECLK; 142 txx9_cpu_clock = JMR3927_CORECLK;
227 txx9_gbus_clock = JMR3927_GBUSCLK;
228 /* SDRAMC are configured by PROM */ 143 /* SDRAMC are configured by PROM */
229 144
230 /* ROMC */ 145 /* ROMC */
@@ -233,74 +148,32 @@ static void __init tx3927_setup(void)
233 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; 148 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
234 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; 149 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
235 150
236 /* CCFG */
237 /* enable Timeout BusError */
238 if (jmr3927_ccfg_toeon)
239 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
240
241 /* clear BusErrorOnWrite flag */
242 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
243 /* Disable PCI snoop */
244 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
245 /* do reset on watchdog */
246 tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
247
248#ifdef DO_WRITE_THROUGH
249 /* Enable PCI SNOOP - with write through only */
250 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
251#endif
252
253 /* Pin selection */ 151 /* Pin selection */
254 tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; 152 tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
255 tx3927_ccfgptr->pcfg |= 153 tx3927_ccfgptr->pcfg |=
256 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | 154 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
257 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); 155 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
258 156
259 printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", 157 tx3927_setup();
260 tx3927_ccfgptr->crir,
261 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
262
263 /* TMR */
264 for (i = 0; i < TX3927_NR_TMR; i++)
265 txx9_tmr_init(TX3927_TMR_REG(i));
266
267 /* DMA */
268 tx3927_dmaptr->mcr = 0;
269 for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
270 /* reset channel */
271 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
272 tx3927_dmaptr->ch[i].ccr = 0;
273 }
274 /* enable DMA */
275#ifdef __BIG_ENDIAN
276 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
277#else
278 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
279#endif
280 158
281 /* PIO */
282 /* PIO[15:12] connected to LEDs */ 159 /* PIO[15:12] connected to LEDs */
283 __raw_writel(0x0000f000, &tx3927_pioptr->dir); 160 __raw_writel(0x0000f000, &tx3927_pioptr->dir);
284 __raw_writel(0, &tx3927_pioptr->maskcpu);
285 __raw_writel(0, &tx3927_pioptr->maskext);
286 txx9_gpio_init(TX3927_PIO_REG, 0, 16);
287 gpio_request(11, "dipsw1"); 161 gpio_request(11, "dipsw1");
288 gpio_request(10, "dipsw2"); 162 gpio_request(10, "dipsw2");
289 {
290 unsigned int conf;
291 163
292 conf = read_c0_conf(); 164 jmr3927_pci_setup();
293 if (!(conf & TX39_CONF_ICE)) 165
294 printk("TX3927 I-Cache disabled.\n"); 166 /* SIO0 DTR on */
295 if (!(conf & TX39_CONF_DCE)) 167 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
296 printk("TX3927 D-Cache disabled.\n"); 168
297 else if (!(conf & TX39_CONF_WBON)) 169 jmr3927_led_set(0);
298 printk("TX3927 D-Cache WriteThrough.\n"); 170
299 else if (!(conf & TX39_CONF_CWFON)) 171 printk(KERN_INFO
300 printk("TX3927 D-Cache WriteBack.\n"); 172 "JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
301 else 173 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
302 printk("TX3927 D-Cache WriteBack (CWF) .\n"); 174 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
303 } 175 jmr3927_dipsw1(), jmr3927_dipsw2(),
176 jmr3927_dipsw3(), jmr3927_dipsw4());
304} 177}
305 178
306/* This trick makes rtc-ds1742 driver usable as is. */ 179/* This trick makes rtc-ds1742 driver usable as is. */
@@ -316,42 +189,21 @@ static unsigned long jmr3927_swizzle_addr_b(unsigned long port)
316#endif 189#endif
317} 190}
318 191
319static int __init jmr3927_rtc_init(void) 192static void __init jmr3927_rtc_init(void)
320{ 193{
321 static struct resource __initdata res = { 194 static struct resource __initdata res = {
322 .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE, 195 .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
323 .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1, 196 .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
324 .flags = IORESOURCE_MEM, 197 .flags = IORESOURCE_MEM,
325 }; 198 };
326 struct platform_device *dev; 199 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
327 dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1);
328 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
329}
330
331/* Watchdog support */
332
333static int __init txx9_wdt_init(unsigned long base)
334{
335 struct resource res = {
336 .start = base,
337 .end = base + 0x100 - 1,
338 .flags = IORESOURCE_MEM,
339 };
340 struct platform_device *dev =
341 platform_device_register_simple("txx9wdt", -1, &res, 1);
342 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
343}
344
345static int __init jmr3927_wdt_init(void)
346{
347 return txx9_wdt_init(TX3927_TMR_REG(2));
348} 200}
349 201
350static void __init jmr3927_device_init(void) 202static void __init jmr3927_device_init(void)
351{ 203{
352 __swizzle_addr_b = jmr3927_swizzle_addr_b; 204 __swizzle_addr_b = jmr3927_swizzle_addr_b;
353 jmr3927_rtc_init(); 205 jmr3927_rtc_init();
354 jmr3927_wdt_init(); 206 tx3927_wdt_init();
355} 207}
356 208
357struct txx9_board_vec jmr3927_vec __initdata = { 209struct txx9_board_vec jmr3927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index cd748a93032..00cd5231da3 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -27,85 +27,86 @@
27 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */ 28 */
29/* 29/*
30IRQ Device 30 * I8259A_IRQ_BASE+00
3100 RBTX4927-ISA/00 31 * I8259A_IRQ_BASE+01 PS2/Keyboard
3201 RBTX4927-ISA/01 PS2/Keyboard 32 * I8259A_IRQ_BASE+02 Cascade RBTX4927-ISA (irqs 8-15)
3302 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) 33 * I8259A_IRQ_BASE+03
3403 RBTX4927-ISA/03 34 * I8259A_IRQ_BASE+04
3504 RBTX4927-ISA/04 35 * I8259A_IRQ_BASE+05
3605 RBTX4927-ISA/05 36 * I8259A_IRQ_BASE+06
3706 RBTX4927-ISA/06 37 * I8259A_IRQ_BASE+07
3807 RBTX4927-ISA/07 38 * I8259A_IRQ_BASE+08
3908 RBTX4927-ISA/08 39 * I8259A_IRQ_BASE+09
4009 RBTX4927-ISA/09 40 * I8259A_IRQ_BASE+10
4110 RBTX4927-ISA/10 41 * I8259A_IRQ_BASE+11
4211 RBTX4927-ISA/11 42 * I8259A_IRQ_BASE+12 PS2/Mouse (not supported at this time)
4312 RBTX4927-ISA/12 PS2/Mouse (not supported at this time) 43 * I8259A_IRQ_BASE+13
4413 RBTX4927-ISA/13 44 * I8259A_IRQ_BASE+14 IDE
4514 RBTX4927-ISA/14 IDE 45 * I8259A_IRQ_BASE+15
4615 RBTX4927-ISA/15 46 *
47 47 * MIPS_CPU_IRQ_BASE+00 Software 0
4816 TX4927-CP0/00 Software 0 48 * MIPS_CPU_IRQ_BASE+01 Software 1
4917 TX4927-CP0/01 Software 1 49 * MIPS_CPU_IRQ_BASE+02 Cascade TX4927-CP0
5018 TX4927-CP0/02 Cascade TX4927-CP0 50 * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
5119 TX4927-CP0/03 Multiplexed -- do not use 51 * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
5220 TX4927-CP0/04 Multiplexed -- do not use 52 * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
5321 TX4927-CP0/05 Multiplexed -- do not use 53 * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
5422 TX4927-CP0/06 Multiplexed -- do not use 54 * MIPS_CPU_IRQ_BASE+07 CPU TIMER
5523 TX4927-CP0/07 CPU TIMER 55 *
56 56 * TXX9_IRQ_BASE+00
5724 TX4927-PIC/00 57 * TXX9_IRQ_BASE+01
5825 TX4927-PIC/01 58 * TXX9_IRQ_BASE+02
5926 TX4927-PIC/02 59 * TXX9_IRQ_BASE+03 Cascade RBTX4927-IOC
6027 TX4927-PIC/03 Cascade RBTX4927-IOC 60 * TXX9_IRQ_BASE+04
6128 TX4927-PIC/04 61 * TXX9_IRQ_BASE+05 RBTX4927 RTL-8019AS ethernet
6229 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet 62 * TXX9_IRQ_BASE+06
6330 TX4927-PIC/06 63 * TXX9_IRQ_BASE+07
6431 TX4927-PIC/07 64 * TXX9_IRQ_BASE+08 TX4927 SerialIO Channel 0
6532 TX4927-PIC/08 TX4927 SerialIO Channel 0 65 * TXX9_IRQ_BASE+09 TX4927 SerialIO Channel 1
6633 TX4927-PIC/09 TX4927 SerialIO Channel 1 66 * TXX9_IRQ_BASE+10
6734 TX4927-PIC/10 67 * TXX9_IRQ_BASE+11
6835 TX4927-PIC/11 68 * TXX9_IRQ_BASE+12
6936 TX4927-PIC/12 69 * TXX9_IRQ_BASE+13
7037 TX4927-PIC/13 70 * TXX9_IRQ_BASE+14
7138 TX4927-PIC/14 71 * TXX9_IRQ_BASE+15
7239 TX4927-PIC/15 72 * TXX9_IRQ_BASE+16 TX4927 PCI PCI-C
7340 TX4927-PIC/16 TX4927 PCI PCI-C 73 * TXX9_IRQ_BASE+17
7441 TX4927-PIC/17 74 * TXX9_IRQ_BASE+18
7542 TX4927-PIC/18 75 * TXX9_IRQ_BASE+19
7643 TX4927-PIC/19 76 * TXX9_IRQ_BASE+20
7744 TX4927-PIC/20 77 * TXX9_IRQ_BASE+21
7845 TX4927-PIC/21 78 * TXX9_IRQ_BASE+22 TX4927 PCI PCI-ERR
7946 TX4927-PIC/22 TX4927 PCI PCI-ERR 79 * TXX9_IRQ_BASE+23 TX4927 PCI PCI-PMA (not used)
8047 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) 80 * TXX9_IRQ_BASE+24
8148 TX4927-PIC/24 81 * TXX9_IRQ_BASE+25
8249 TX4927-PIC/25 82 * TXX9_IRQ_BASE+26
8350 TX4927-PIC/26 83 * TXX9_IRQ_BASE+27
8451 TX4927-PIC/27 84 * TXX9_IRQ_BASE+28
8552 TX4927-PIC/28 85 * TXX9_IRQ_BASE+29
8653 TX4927-PIC/29 86 * TXX9_IRQ_BASE+30
8754 TX4927-PIC/30 87 * TXX9_IRQ_BASE+31
8855 TX4927-PIC/31 88 *
89 89 * RBTX4927_IRQ_IOC+00 FPCIB0 PCI-D (SouthBridge)
9056 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4] 90 * RBTX4927_IRQ_IOC+01 FPCIB0 PCI-C (SouthBridge)
9157 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5] 91 * RBTX4927_IRQ_IOC+02 FPCIB0 PCI-B (SouthBridge/IDE/pin=1,INTR)
9258 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported] 92 * RBTX4927_IRQ_IOC+03 FPCIB0 PCI-A (SouthBridge/USB/pin=4)
9359 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6] 93 * RBTX4927_IRQ_IOC+04
9460 RBTX4927-IOC/04 94 * RBTX4927_IRQ_IOC+05
9561 RBTX4927-IOC/05 95 * RBTX4927_IRQ_IOC+06
9662 RBTX4927-IOC/06 96 * RBTX4927_IRQ_IOC+07
9763 RBTX4927-IOC/07 97 *
98 98 * NOTES:
99NOTES: 99 * SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
100SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 100 * SouthBridge/ISA/pin=0 no pci irq used by this device
101SouthBridge/ISA/pin=0 no pci irq used by this device 101 * SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR
102SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 102 * via ISA IRQ14
103SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59 103 * SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
104SouthBridge/PMC/pin=0 no pci irq used by this device 104 * SouthBridge/PMC/pin=0 no pci irq used by this device
105SuperIO/PS2/Keyboard, using INTR via ISA IRQ1 105 * SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
106SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported) 106 * SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
107JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6 107 * JP7 is not bus master -- do NOT use -- only 4 pci bus master's
108*/ 108 * allowed -- SouthBridge, JP4, JP5, JP6
109 */
109 110
110#include <linux/init.h> 111#include <linux/init.h>
111#include <linux/types.h> 112#include <linux/types.h>
@@ -134,7 +135,7 @@ static int toshiba_rbtx4927_irq_nested(int sw_irq)
134 level3 = readb(rbtx4927_imstat_addr) & 0x1f; 135 level3 = readb(rbtx4927_imstat_addr) & 0x1f;
135 if (level3) 136 if (level3)
136 sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1; 137 sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1;
137 return (sw_irq); 138 return sw_irq;
138} 139}
139 140
140static void __init toshiba_rbtx4927_irq_ioc_init(void) 141static void __init toshiba_rbtx4927_irq_ioc_init(void)
diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c
index 5c0de54ebdd..1dc0a5b1956 100644
--- a/arch/mips/txx9/rbtx4927/prom.c
+++ b/arch/mips/txx9/rbtx4927/prom.c
@@ -38,4 +38,5 @@ void __init rbtx4927_prom_init(void)
38{ 38{
39 prom_init_cmdline(); 39 prom_init_cmdline();
40 add_memory_region(0, tx4927_get_mem_size(), BOOT_MEM_RAM); 40 add_memory_region(0, tx4927_get_mem_size(), BOOT_MEM_RAM);
41 txx9_sio_putchar_init(TX4927_SIO_REG(0) & 0xfffffffffULL);
41} 42}
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 3da20ea3e55..0d39bafea79 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -46,12 +46,9 @@
46#include <linux/kernel.h> 46#include <linux/kernel.h>
47#include <linux/types.h> 47#include <linux/types.h>
48#include <linux/ioport.h> 48#include <linux/ioport.h>
49#include <linux/interrupt.h>
50#include <linux/pm.h>
51#include <linux/platform_device.h> 49#include <linux/platform_device.h>
52#include <linux/delay.h> 50#include <linux/delay.h>
53#include <asm/io.h> 51#include <asm/io.h>
54#include <asm/processor.h>
55#include <asm/reboot.h> 52#include <asm/reboot.h>
56#include <asm/txx9/generic.h> 53#include <asm/txx9/generic.h>
57#include <asm/txx9/pci.h> 54#include <asm/txx9/pci.h>
@@ -103,6 +100,7 @@ static void __init tx4927_pci_setup(void)
103 tx4927_report_pciclk(); 100 tx4927_report_pciclk();
104 tx4927_pcic_setup(tx4927_pcicptr, c, extarb); 101 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
105 } 102 }
103 tx4927_setup_pcierr_irq();
106} 104}
107 105
108static void __init tx4937_pci_setup(void) 106static void __init tx4937_pci_setup(void)
@@ -149,6 +147,7 @@ static void __init tx4937_pci_setup(void)
149 tx4938_report_pciclk(); 147 tx4938_report_pciclk();
150 tx4927_pcic_setup(tx4938_pcicptr, c, extarb); 148 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
151 } 149 }
150 tx4938_setup_pcierr_irq();
152} 151}
153 152
154static void __init rbtx4927_arch_init(void) 153static void __init rbtx4927_arch_init(void)
@@ -165,17 +164,8 @@ static void __init rbtx4937_arch_init(void)
165#define rbtx4937_arch_init NULL 164#define rbtx4937_arch_init NULL
166#endif /* CONFIG_PCI */ 165#endif /* CONFIG_PCI */
167 166
168static void __noreturn wait_forever(void)
169{
170 while (1)
171 if (cpu_wait)
172 (*cpu_wait)();
173}
174
175static void toshiba_rbtx4927_restart(char *command) 167static void toshiba_rbtx4927_restart(char *command)
176{ 168{
177 printk(KERN_NOTICE "System Rebooting...\n");
178
179 /* enable the s/w reset register */ 169 /* enable the s/w reset register */
180 writeb(1, rbtx4927_softresetlock_addr); 170 writeb(1, rbtx4927_softresetlock_addr);
181 171
@@ -186,24 +176,8 @@ static void toshiba_rbtx4927_restart(char *command)
186 /* do a s/w reset */ 176 /* do a s/w reset */
187 writeb(1, rbtx4927_softreset_addr); 177 writeb(1, rbtx4927_softreset_addr);
188 178
189 /* do something passive while waiting for reset */ 179 /* fallback */
190 local_irq_disable(); 180 (*_machine_halt)();
191 wait_forever();
192 /* no return */
193}
194
195static void toshiba_rbtx4927_halt(void)
196{
197 printk(KERN_NOTICE "System Halted\n");
198 local_irq_disable();
199 wait_forever();
200 /* no return */
201}
202
203static void toshiba_rbtx4927_power_off(void)
204{
205 toshiba_rbtx4927_halt();
206 /* no return */
207} 181}
208 182
209static void __init rbtx4927_clock_init(void); 183static void __init rbtx4927_clock_init(void);
@@ -214,9 +188,6 @@ static void __init rbtx4927_mem_setup(void)
214 u32 cp0_config; 188 u32 cp0_config;
215 char *argptr; 189 char *argptr;
216 190
217 /* f/w leaves this on at startup */
218 clear_c0_status(ST0_ERL);
219
220 /* enable caches -- HCP5 does this, pmon does not */ 191 /* enable caches -- HCP5 does this, pmon does not */
221 cp0_config = read_c0_config(); 192 cp0_config = read_c0_config();
222 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); 193 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
@@ -231,37 +202,21 @@ static void __init rbtx4927_mem_setup(void)
231 } 202 }
232 203
233 _machine_restart = toshiba_rbtx4927_restart; 204 _machine_restart = toshiba_rbtx4927_restart;
234 _machine_halt = toshiba_rbtx4927_halt;
235 pm_power_off = toshiba_rbtx4927_power_off;
236 205
237#ifdef CONFIG_PCI 206#ifdef CONFIG_PCI
238 txx9_alloc_pci_controller(&txx9_primary_pcic, 207 txx9_alloc_pci_controller(&txx9_primary_pcic,
239 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, 208 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
240 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); 209 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
210 txx9_board_pcibios_setup = tx4927_pcibios_setup;
241#else 211#else
242 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); 212 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
243#endif 213#endif
244 214
245 tx4927_setup_serial(); 215 tx4927_sio_init(0, 0);
246#ifdef CONFIG_SERIAL_TXX9_CONSOLE 216#ifdef CONFIG_SERIAL_TXX9_CONSOLE
247 argptr = prom_getcmdline(); 217 argptr = prom_getcmdline();
248 if (strstr(argptr, "console=") == NULL) { 218 if (!strstr(argptr, "console="))
249 strcat(argptr, " console=ttyS0,38400"); 219 strcat(argptr, " console=ttyS0,38400");
250 }
251#endif
252
253#ifdef CONFIG_ROOT_NFS
254 argptr = prom_getcmdline();
255 if (strstr(argptr, "root=") == NULL) {
256 strcat(argptr, " root=/dev/nfs rw");
257 }
258#endif
259
260#ifdef CONFIG_IP_PNP
261 argptr = prom_getcmdline();
262 if (strstr(argptr, "ip=") == NULL) {
263 strcat(argptr, " ip=any");
264 }
265#endif 220#endif
266} 221}
267 222
@@ -324,19 +279,17 @@ static void __init rbtx4927_time_init(void)
324 tx4927_time_init(0); 279 tx4927_time_init(0);
325} 280}
326 281
327static int __init toshiba_rbtx4927_rtc_init(void) 282static void __init toshiba_rbtx4927_rtc_init(void)
328{ 283{
329 struct resource res = { 284 struct resource res = {
330 .start = RBTX4927_BRAMRTC_BASE - IO_BASE, 285 .start = RBTX4927_BRAMRTC_BASE - IO_BASE,
331 .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1, 286 .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1,
332 .flags = IORESOURCE_MEM, 287 .flags = IORESOURCE_MEM,
333 }; 288 };
334 struct platform_device *dev = 289 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
335 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
336 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
337} 290}
338 291
339static int __init rbtx4927_ne_init(void) 292static void __init rbtx4927_ne_init(void)
340{ 293{
341 struct resource res[] = { 294 struct resource res[] = {
342 { 295 {
@@ -348,36 +301,14 @@ static int __init rbtx4927_ne_init(void)
348 .flags = IORESOURCE_IRQ, 301 .flags = IORESOURCE_IRQ,
349 } 302 }
350 }; 303 };
351 struct platform_device *dev = 304 platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
352 platform_device_register_simple("ne", -1,
353 res, ARRAY_SIZE(res));
354 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
355}
356
357/* Watchdog support */
358
359static int __init txx9_wdt_init(unsigned long base)
360{
361 struct resource res = {
362 .start = base,
363 .end = base + 0x100 - 1,
364 .flags = IORESOURCE_MEM,
365 };
366 struct platform_device *dev =
367 platform_device_register_simple("txx9wdt", -1, &res, 1);
368 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
369}
370
371static int __init rbtx4927_wdt_init(void)
372{
373 return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
374} 305}
375 306
376static void __init rbtx4927_device_init(void) 307static void __init rbtx4927_device_init(void)
377{ 308{
378 toshiba_rbtx4927_rtc_init(); 309 toshiba_rbtx4927_rtc_init();
379 rbtx4927_ne_init(); 310 rbtx4927_ne_init();
380 rbtx4927_wdt_init(); 311 tx4927_wdt_init();
381} 312}
382 313
383struct txx9_board_vec rbtx4927_vec __initdata = { 314struct txx9_board_vec rbtx4927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
index 3971a061657..ca2f8306ce9 100644
--- a/arch/mips/txx9/rbtx4938/irq.c
+++ b/arch/mips/txx9/rbtx4938/irq.c
@@ -11,59 +11,57 @@
11 */ 11 */
12 12
13/* 13/*
14IRQ Device 14 * MIPS_CPU_IRQ_BASE+00 Software 0
15 15 * MIPS_CPU_IRQ_BASE+01 Software 1
1616 TX4938-CP0/00 Software 0 16 * MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
1717 TX4938-CP0/01 Software 1 17 * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
1818 TX4938-CP0/02 Cascade TX4938-CP0 18 * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
1919 TX4938-CP0/03 Multiplexed -- do not use 19 * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
2020 TX4938-CP0/04 Multiplexed -- do not use 20 * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
2121 TX4938-CP0/05 Multiplexed -- do not use 21 * MIPS_CPU_IRQ_BASE+07 CPU TIMER
2222 TX4938-CP0/06 Multiplexed -- do not use 22 *
2323 TX4938-CP0/07 CPU TIMER 23 * TXX9_IRQ_BASE+00
24 24 * TXX9_IRQ_BASE+01
2524 TX4938-PIC/00 25 * TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC
2625 TX4938-PIC/01 26 * TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet
2726 TX4938-PIC/02 Cascade RBTX4938-IOC 27 * TXX9_IRQ_BASE+04
2827 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet 28 * TXX9_IRQ_BASE+05 TX4938 ETH1
2928 TX4938-PIC/04 29 * TXX9_IRQ_BASE+06 TX4938 ETH0
3029 TX4938-PIC/05 TX4938 ETH1 30 * TXX9_IRQ_BASE+07
3130 TX4938-PIC/06 TX4938 ETH0 31 * TXX9_IRQ_BASE+08 TX4938 SIO 0
3231 TX4938-PIC/07 32 * TXX9_IRQ_BASE+09 TX4938 SIO 1
3332 TX4938-PIC/08 TX4938 SIO 0 33 * TXX9_IRQ_BASE+10 TX4938 DMA0
3433 TX4938-PIC/09 TX4938 SIO 1 34 * TXX9_IRQ_BASE+11 TX4938 DMA1
3534 TX4938-PIC/10 TX4938 DMA0 35 * TXX9_IRQ_BASE+12 TX4938 DMA2
3635 TX4938-PIC/11 TX4938 DMA1 36 * TXX9_IRQ_BASE+13 TX4938 DMA3
3736 TX4938-PIC/12 TX4938 DMA2 37 * TXX9_IRQ_BASE+14
3837 TX4938-PIC/13 TX4938 DMA3 38 * TXX9_IRQ_BASE+15
3938 TX4938-PIC/14 39 * TXX9_IRQ_BASE+16 TX4938 PCIC
4039 TX4938-PIC/15 40 * TXX9_IRQ_BASE+17 TX4938 TMR0
4140 TX4938-PIC/16 TX4938 PCIC 41 * TXX9_IRQ_BASE+18 TX4938 TMR1
4241 TX4938-PIC/17 TX4938 TMR0 42 * TXX9_IRQ_BASE+19 TX4938 TMR2
4342 TX4938-PIC/18 TX4938 TMR1 43 * TXX9_IRQ_BASE+20
4443 TX4938-PIC/19 TX4938 TMR2 44 * TXX9_IRQ_BASE+21
4544 TX4938-PIC/20 45 * TXX9_IRQ_BASE+22 TX4938 PCIERR
4645 TX4938-PIC/21 46 * TXX9_IRQ_BASE+23
4746 TX4938-PIC/22 TX4938 PCIERR 47 * TXX9_IRQ_BASE+24
4847 TX4938-PIC/23 48 * TXX9_IRQ_BASE+25
4948 TX4938-PIC/24 49 * TXX9_IRQ_BASE+26
5049 TX4938-PIC/25 50 * TXX9_IRQ_BASE+27
5150 TX4938-PIC/26 51 * TXX9_IRQ_BASE+28
5251 TX4938-PIC/27 52 * TXX9_IRQ_BASE+29
5352 TX4938-PIC/28 53 * TXX9_IRQ_BASE+30
5453 TX4938-PIC/29 54 * TXX9_IRQ_BASE+31 TX4938 SPI
5554 TX4938-PIC/30 55 *
5655 TX4938-PIC/31 TX4938 SPI 56 * RBTX4938_IRQ_IOC+00 PCI-D
57 57 * RBTX4938_IRQ_IOC+01 PCI-C
5856 RBTX4938-IOC/00 PCI-D 58 * RBTX4938_IRQ_IOC+02 PCI-B
5957 RBTX4938-IOC/01 PCI-C 59 * RBTX4938_IRQ_IOC+03 PCI-A
6058 RBTX4938-IOC/02 PCI-B 60 * RBTX4938_IRQ_IOC+04 RTC
6159 RBTX4938-IOC/03 PCI-A 61 * RBTX4938_IRQ_IOC+05 ATA
6260 RBTX4938-IOC/04 RTC 62 * RBTX4938_IRQ_IOC+06 MODEM
6361 RBTX4938-IOC/05 ATA 63 * RBTX4938_IRQ_IOC+07 SWINT
6462 RBTX4938-IOC/06 MODEM 64 */
6563 RBTX4938-IOC/07 SWINT
66*/
67#include <linux/init.h> 65#include <linux/init.h>
68#include <linux/interrupt.h> 66#include <linux/interrupt.h>
69#include <asm/mipsregs.h> 67#include <asm/mipsregs.h>
@@ -93,9 +91,6 @@ static int toshiba_rbtx4938_irq_nested(int sw_irq)
93 return sw_irq; 91 return sw_irq;
94} 92}
95 93
96/**********************************************************************************/
97/* Functions for ioc */
98/**********************************************************************************/
99static void __init 94static void __init
100toshiba_rbtx4938_irq_ioc_init(void) 95toshiba_rbtx4938_irq_ioc_init(void)
101{ 96{
diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c
index ee189519ce5..d73123cd2ab 100644
--- a/arch/mips/txx9/rbtx4938/prom.c
+++ b/arch/mips/txx9/rbtx4938/prom.c
@@ -22,4 +22,5 @@ void __init rbtx4938_prom_init(void)
22 prom_init_cmdline(); 22 prom_init_cmdline();
23#endif 23#endif
24 add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM); 24 add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM);
25 txx9_sio_putchar_init(TX4938_SIO_REG(0) & 0xfffffffffULL);
25} 26}
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index 6c2b99bb8af..9ab48dec0fe 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -13,9 +13,6 @@
13#include <linux/types.h> 13#include <linux/types.h>
14#include <linux/ioport.h> 14#include <linux/ioport.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/console.h>
18#include <linux/pm.h>
19#include <linux/platform_device.h> 16#include <linux/platform_device.h>
20#include <linux/gpio.h> 17#include <linux/gpio.h>
21 18
@@ -28,33 +25,14 @@
28#include <asm/txx9/spi.h> 25#include <asm/txx9/spi.h>
29#include <asm/txx9pio.h> 26#include <asm/txx9pio.h>
30 27
31static void rbtx4938_machine_halt(void)
32{
33 printk(KERN_NOTICE "System Halted\n");
34 local_irq_disable();
35
36 while (1)
37 __asm__(".set\tmips3\n\t"
38 "wait\n\t"
39 ".set\tmips0");
40}
41
42static void rbtx4938_machine_power_off(void)
43{
44 rbtx4938_machine_halt();
45 /* no return */
46}
47
48static void rbtx4938_machine_restart(char *command) 28static void rbtx4938_machine_restart(char *command)
49{ 29{
50 local_irq_disable(); 30 local_irq_disable();
51
52 printk("Rebooting...");
53 writeb(1, rbtx4938_softresetlock_addr); 31 writeb(1, rbtx4938_softresetlock_addr);
54 writeb(1, rbtx4938_sfvol_addr); 32 writeb(1, rbtx4938_sfvol_addr);
55 writeb(1, rbtx4938_softreset_addr); 33 writeb(1, rbtx4938_softreset_addr);
56 while(1) 34 /* fallback */
57 ; 35 (*_machine_halt)();
58} 36}
59 37
60static void __init rbtx4938_pci_setup(void) 38static void __init rbtx4938_pci_setup(void)
@@ -121,6 +99,7 @@ static void __init rbtx4938_pci_setup(void)
121 register_pci_controller(c); 99 register_pci_controller(c);
122 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0); 100 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
123 } 101 }
102 tx4938_setup_pcierr_irq();
124#endif /* CONFIG_PCI */ 103#endif /* CONFIG_PCI */
125} 104}
126 105
@@ -151,19 +130,7 @@ static int __init rbtx4938_ethaddr_init(void)
151 if (sum) 130 if (sum)
152 printk(KERN_WARNING "seeprom: bad checksum.\n"); 131 printk(KERN_WARNING "seeprom: bad checksum.\n");
153 } 132 }
154 for (i = 0; i < 2; i++) { 133 tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
155 unsigned int id =
156 TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0);
157 struct platform_device *pdev;
158 if (!(__raw_readq(&tx4938_ccfgptr->pcfg) &
159 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
160 continue;
161 pdev = platform_device_alloc("tc35815-mac", id);
162 if (!pdev ||
163 platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
164 platform_device_add(pdev))
165 platform_device_put(pdev);
166 }
167#endif /* CONFIG_PCI */ 134#endif /* CONFIG_PCI */
168 return 0; 135 return 0;
169} 136}
@@ -193,51 +160,36 @@ static void __init rbtx4938_mem_setup(void)
193 160
194#ifdef CONFIG_PCI 161#ifdef CONFIG_PCI
195 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0); 162 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
163 txx9_board_pcibios_setup = tx4927_pcibios_setup;
196#else 164#else
197 set_io_port_base(RBTX4938_ETHER_BASE); 165 set_io_port_base(RBTX4938_ETHER_BASE);
198#endif 166#endif
199 167
200 tx4938_setup_serial(); 168 tx4938_sio_init(7372800, 0);
201#ifdef CONFIG_SERIAL_TXX9_CONSOLE 169#ifdef CONFIG_SERIAL_TXX9_CONSOLE
202 argptr = prom_getcmdline(); 170 argptr = prom_getcmdline();
203 if (strstr(argptr, "console=") == NULL) { 171 if (!strstr(argptr, "console="))
204 strcat(argptr, " console=ttyS0,38400"); 172 strcat(argptr, " console=ttyS0,38400");
205 }
206#endif 173#endif
207 174
208#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 175#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
209 printk("PIOSEL: disabling both ata and nand selection\n"); 176 printk(KERN_INFO "PIOSEL: disabling both ata and nand selection\n");
210 local_irq_disable();
211 txx9_clear64(&tx4938_ccfgptr->pcfg, 177 txx9_clear64(&tx4938_ccfgptr->pcfg,
212 TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); 178 TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
213#endif 179#endif
214 180
215#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND 181#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
216 printk("PIOSEL: enabling nand selection\n"); 182 printk(KERN_INFO "PIOSEL: enabling nand selection\n");
217 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); 183 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
218 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); 184 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
219#endif 185#endif
220 186
221#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA 187#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
222 printk("PIOSEL: enabling ata selection\n"); 188 printk(KERN_INFO "PIOSEL: enabling ata selection\n");
223 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); 189 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
224 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); 190 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
225#endif 191#endif
226 192
227#ifdef CONFIG_IP_PNP
228 argptr = prom_getcmdline();
229 if (strstr(argptr, "ip=") == NULL) {
230 strcat(argptr, " ip=any");
231 }
232#endif
233
234
235#ifdef CONFIG_FB
236 {
237 conswitchp = &dummy_con;
238 }
239#endif
240
241 rbtx4938_spi_setup(); 193 rbtx4938_spi_setup();
242 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */ 194 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */
243 /* fixup piosel */ 195 /* fixup piosel */
@@ -258,11 +210,9 @@ static void __init rbtx4938_mem_setup(void)
258 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; 210 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
259 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; 211 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
260 if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource)) 212 if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
261 printk("request resource for fpga failed\n"); 213 printk(KERN_ERR "request resource for fpga failed\n");
262 214
263 _machine_restart = rbtx4938_machine_restart; 215 _machine_restart = rbtx4938_machine_restart;
264 _machine_halt = rbtx4938_machine_halt;
265 pm_power_off = rbtx4938_machine_power_off;
266 216
267 writeb(0xff, rbtx4938_led_addr); 217 writeb(0xff, rbtx4938_led_addr);
268 printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", 218 printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
@@ -270,7 +220,7 @@ static void __init rbtx4938_mem_setup(void)
270 readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr)); 220 readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
271} 221}
272 222
273static int __init rbtx4938_ne_init(void) 223static void __init rbtx4938_ne_init(void)
274{ 224{
275 struct resource res[] = { 225 struct resource res[] = {
276 { 226 {
@@ -282,10 +232,7 @@ static int __init rbtx4938_ne_init(void)
282 .flags = IORESOURCE_IRQ, 232 .flags = IORESOURCE_IRQ,
283 } 233 }
284 }; 234 };
285 struct platform_device *dev = 235 platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
286 platform_device_register_simple("ne", -1,
287 res, ARRAY_SIZE(res));
288 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
289} 236}
290 237
291static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock); 238static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
@@ -321,24 +268,6 @@ static struct gpio_chip rbtx4938_spi_gpio_chip = {
321 .ngpio = 3, 268 .ngpio = 3,
322}; 269};
323 270
324/* SPI support */
325
326static void __init txx9_spi_init(unsigned long base, int irq)
327{
328 struct resource res[] = {
329 {
330 .start = base,
331 .end = base + 0x20 - 1,
332 .flags = IORESOURCE_MEM,
333 }, {
334 .start = irq,
335 .flags = IORESOURCE_IRQ,
336 },
337 };
338 platform_device_register_simple("spi_txx9", 0,
339 res, ARRAY_SIZE(res));
340}
341
342static int __init rbtx4938_spi_init(void) 271static int __init rbtx4938_spi_init(void)
343{ 272{
344 struct spi_board_info srtc_info = { 273 struct spi_board_info srtc_info = {
@@ -361,7 +290,7 @@ static int __init rbtx4938_spi_init(void)
361 gpio_direction_output(16 + SEEPROM2_CS, 1); 290 gpio_direction_output(16 + SEEPROM2_CS, 1);
362 gpio_request(16 + SEEPROM3_CS, "seeprom3"); 291 gpio_request(16 + SEEPROM3_CS, "seeprom3");
363 gpio_direction_output(16 + SEEPROM3_CS, 1); 292 gpio_direction_output(16 + SEEPROM3_CS, 1);
364 txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI); 293 tx4938_spi_init(0);
365 return 0; 294 return 0;
366} 295}
367 296
@@ -372,30 +301,11 @@ static void __init rbtx4938_arch_init(void)
372 rbtx4938_spi_init(); 301 rbtx4938_spi_init();
373} 302}
374 303
375/* Watchdog support */
376
377static int __init txx9_wdt_init(unsigned long base)
378{
379 struct resource res = {
380 .start = base,
381 .end = base + 0x100 - 1,
382 .flags = IORESOURCE_MEM,
383 };
384 struct platform_device *dev =
385 platform_device_register_simple("txx9wdt", -1, &res, 1);
386 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
387}
388
389static int __init rbtx4938_wdt_init(void)
390{
391 return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
392}
393
394static void __init rbtx4938_device_init(void) 304static void __init rbtx4938_device_init(void)
395{ 305{
396 rbtx4938_ethaddr_init(); 306 rbtx4938_ethaddr_init();
397 rbtx4938_ne_init(); 307 rbtx4938_ne_init();
398 rbtx4938_wdt_init(); 308 tx4938_wdt_init();
399} 309}
400 310
401struct txx9_board_vec rbtx4938_vec __initdata = { 311struct txx9_board_vec rbtx4938_vec __initdata = {
diff --git a/include/asm-mips/gdb-stub.h b/include/asm-mips/gdb-stub.h
deleted file mode 100644
index 22f67d4a71a..00000000000
--- a/include/asm-mips/gdb-stub.h
+++ /dev/null
@@ -1,215 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995 Andreas Busse
7 * Copyright (C) 2003 Ralf Baechle
8 */
9#ifndef _ASM_GDB_STUB_H
10#define _ASM_GDB_STUB_H
11
12
13/*
14 * important register numbers
15 */
16
17#define REG_EPC 37
18#define REG_FP 72
19#define REG_SP 29
20
21/*
22 * Stack layout for the GDB exception handler
23 * Derived from the stack layout described in asm-mips/stackframe.h
24 *
25 * The first PTRSIZE*6 bytes are argument save space for C subroutines.
26 */
27#define NUMREGS 90
28
29#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */
30#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */
31#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */
32#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */
33#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */
34#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */
35#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */
36#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */
37#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */
38#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */
39#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */
40#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */
41#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */
42#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */
43#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */
44#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */
45#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */
46#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */
47#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */
48#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */
49#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */
50#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */
51#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */
52#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */
53#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */
54#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */
55#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */
56#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */
57#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */
58#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */
59#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */
60#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */
61
62/*
63 * Saved special registers
64 */
65#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */
66#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */
67#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */
68#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */
69#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */
70#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */
71
72/*
73 * Saved floating point registers
74 */
75#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */
76#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */
77#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */
78#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */
79#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */
80#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */
81#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */
82#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */
83#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */
84#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */
85#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */
86#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */
87#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */
88#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */
89#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */
90#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */
91#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */
92#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */
93#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */
94#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */
95#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */
96#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */
97#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */
98#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */
99#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */
100#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */
101#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */
102#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */
103#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */
104#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */
105#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */
106#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */
107
108#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */
109#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */
110#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */
111
112#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */
113
114/*
115 * Again, CP0 registers
116 */
117#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */
118#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
119#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
120#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
121#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
122#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
123#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
124#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
125#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */
126#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */
127#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */
128#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
129#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
130#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
131#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
132#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
133
134#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
135
136#ifndef __ASSEMBLY__
137
138/*
139 * This is the same as above, but for the high-level
140 * part of the GDB stub.
141 */
142
143struct gdb_regs {
144 /*
145 * Pad bytes for argument save space on the stack
146 * 24/48 Bytes for 32/64 bit code
147 */
148 unsigned long pad0[6];
149
150 /*
151 * saved main processor registers
152 */
153 long reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
154 long reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15;
155 long reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23;
156 long reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31;
157
158 /*
159 * Saved special registers
160 */
161 long cp0_status;
162 long lo;
163 long hi;
164 long cp0_badvaddr;
165 long cp0_cause;
166 long cp0_epc;
167
168 /*
169 * Saved floating point registers
170 */
171 long fpr0, fpr1, fpr2, fpr3, fpr4, fpr5, fpr6, fpr7;
172 long fpr8, fpr9, fpr10, fpr11, fpr12, fpr13, fpr14, fpr15;
173 long fpr16, fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23;
174 long fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31;
175
176 long cp1_fsr;
177 long cp1_fir;
178
179 /*
180 * Frame pointer
181 */
182 long frame_ptr;
183 long dummy; /* unused */
184
185 /*
186 * saved cp0 registers
187 */
188 long cp0_index;
189 long cp0_random;
190 long cp0_entrylo0;
191 long cp0_entrylo1;
192 long cp0_context;
193 long cp0_pagemask;
194 long cp0_wired;
195 long cp0_reg7;
196 long cp0_reg8;
197 long cp0_reg9;
198 long cp0_entryhi;
199 long cp0_reg11;
200 long cp0_reg12;
201 long cp0_reg13;
202 long cp0_reg14;
203 long cp0_prid;
204};
205
206/*
207 * Prototypes
208 */
209
210extern int kgdb_enabled;
211void set_debug_traps(void);
212void set_async_breakpoint(unsigned long *epc);
213
214#endif /* !__ASSEMBLY__ */
215#endif /* _ASM_GDB_STUB_H */
diff --git a/include/asm-mips/kdebug.h b/include/asm-mips/kdebug.h
index 6ece1b03766..5bf62aafc89 100644
--- a/include/asm-mips/kdebug.h
+++ b/include/asm-mips/kdebug.h
@@ -1 +1,13 @@
1#include <asm-generic/kdebug.h> 1#ifndef _ASM_MIPS_KDEBUG_H
2#define _ASM_MIPS_KDEBUG_H
3
4#include <linux/notifier.h>
5
6enum die_val {
7 DIE_OOPS = 1,
8 DIE_FP,
9 DIE_TRAP,
10 DIE_RI,
11};
12
13#endif /* _ASM_MIPS_KDEBUG_H */
diff --git a/include/asm-mips/kgdb.h b/include/asm-mips/kgdb.h
new file mode 100644
index 00000000000..48223b09396
--- /dev/null
+++ b/include/asm-mips/kgdb.h
@@ -0,0 +1,44 @@
1#ifndef __ASM_KGDB_H_
2#define __ASM_KGDB_H_
3
4#ifdef __KERNEL__
5
6#include <asm/sgidefs.h>
7
8#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
9 (_MIPS_ISA == _MIPS_ISA_MIPS32)
10
11#define KGDB_GDB_REG_SIZE 32
12
13#elif (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
14 (_MIPS_ISA == _MIPS_ISA_MIPS64)
15
16#ifdef CONFIG_32BIT
17#define KGDB_GDB_REG_SIZE 32
18#else /* CONFIG_CPU_32BIT */
19#define KGDB_GDB_REG_SIZE 64
20#endif
21#else
22#error "Need to set KGDB_GDB_REG_SIZE for MIPS ISA"
23#endif /* _MIPS_ISA */
24
25#define BUFMAX 2048
26#if (KGDB_GDB_REG_SIZE == 32)
27#define NUMREGBYTES (90*sizeof(u32))
28#define NUMCRITREGBYTES (12*sizeof(u32))
29#else
30#define NUMREGBYTES (90*sizeof(u64))
31#define NUMCRITREGBYTES (12*sizeof(u64))
32#endif
33#define BREAK_INSTR_SIZE 4
34#define CACHE_FLUSH_IS_SAFE 0
35
36extern void arch_kgdb_breakpoint(void);
37extern int kgdb_early_setup;
38extern void *saved_vectors[32];
39extern void handle_exception(struct pt_regs *regs);
40extern void breakinst(void);
41
42#endif /* __KERNEL__ */
43
44#endif /* __ASM_KGDB_H_ */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index c205875d7f3..5510c53b7fe 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -174,4 +174,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
174 174
175extern int pci_probe_only; 175extern int pci_probe_only;
176 176
177extern char * (*pcibios_plat_setup)(char *str);
178
177#endif /* _ASM_PCI_H */ 179#endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
index cbae37ec3d8..5b1ccf901c6 100644
--- a/include/asm-mips/txx9/generic.h
+++ b/include/asm-mips/txx9/generic.h
@@ -44,5 +44,19 @@ extern struct txx9_board_vec *txx9_board_vec;
44extern int (*txx9_irq_dispatch)(int pending); 44extern int (*txx9_irq_dispatch)(int pending);
45void prom_init_cmdline(void); 45void prom_init_cmdline(void);
46char *prom_getcmdline(void); 46char *prom_getcmdline(void);
47void txx9_wdt_init(unsigned long base);
48void txx9_spi_init(int busid, unsigned long base, int irq);
49void txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr);
50void txx9_sio_init(unsigned long baseaddr, int irq,
51 unsigned int line, unsigned int sclk, int nocts);
52void prom_putchar(char c);
53#ifdef CONFIG_EARLY_PRINTK
54extern void (*txx9_prom_putchar)(char c);
55void txx9_sio_putchar_init(unsigned long baseaddr);
56#else
57static inline void txx9_sio_putchar_init(unsigned long baseaddr)
58{
59}
60#endif
47 61
48#endif /* __ASM_TXX9_GENERIC_H */ 62#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/include/asm-mips/txx9/jmr3927.h b/include/asm-mips/txx9/jmr3927.h
index d6eb1b6a54e..a409c446bf1 100644
--- a/include/asm-mips/txx9/jmr3927.h
+++ b/include/asm-mips/txx9/jmr3927.h
@@ -149,8 +149,6 @@
149 149
150/* Clocks */ 150/* Clocks */
151#define JMR3927_CORECLK 132710400 /* 132.7MHz */ 151#define JMR3927_CORECLK 132710400 /* 132.7MHz */
152#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
153#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
154 152
155/* 153/*
156 * TX3927 Pin Configuration: 154 * TX3927 Pin Configuration:
diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h
index d89a45091e2..3d32529060a 100644
--- a/include/asm-mips/txx9/pci.h
+++ b/include/asm-mips/txx9/pci.h
@@ -33,4 +33,7 @@ enum txx9_pci_err_action {
33}; 33};
34extern enum txx9_pci_err_action txx9_pci_err_action; 34extern enum txx9_pci_err_action txx9_pci_err_action;
35 35
36extern char * (*txx9_board_pcibios_setup)(char *str);
37char *txx9_pcibios_setup(char *str);
38
36#endif /* __ASM_TXX9_PCI_H */ 39#endif /* __ASM_TXX9_PCI_H */
diff --git a/include/asm-mips/txx9/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h
index 9375e4fc228..02e161d0755 100644
--- a/include/asm-mips/txx9/smsc_fdc37m81x.h
+++ b/include/asm-mips/txx9/smsc_fdc37m81x.h
@@ -56,7 +56,7 @@
56#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa 56#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
57#define SMSC_FDC37M81X_CHIP_ID 0x4d 57#define SMSC_FDC37M81X_CHIP_ID 0x4d
58 58
59unsigned long __init smsc_fdc37m81x_init(unsigned long port); 59unsigned long smsc_fdc37m81x_init(unsigned long port);
60 60
61void smsc_fdc37m81x_config_beg(void); 61void smsc_fdc37m81x_config_beg(void);
62 62
diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h
index ea79e1b16e7..587deb9592d 100644
--- a/include/asm-mips/txx9/tx3927.h
+++ b/include/asm-mips/txx9/tx3927.h
@@ -8,9 +8,8 @@
8#ifndef __ASM_TXX9_TX3927_H 8#ifndef __ASM_TXX9_TX3927_H
9#define __ASM_TXX9_TX3927_H 9#define __ASM_TXX9_TX3927_H
10 10
11#include <asm/txx9/txx927.h>
12
13#define TX3927_REG_BASE 0xfffe0000UL 11#define TX3927_REG_BASE 0xfffe0000UL
12#define TX3927_REG_SIZE 0x00010000
14#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000) 13#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
15#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000) 14#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
16#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000) 15#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
@@ -236,11 +235,17 @@ struct tx3927_ccfg_reg {
236/* see PCI_STATUS_XXX in linux/pci.h */ 235/* see PCI_STATUS_XXX in linux/pci.h */
237#define PCI_STATUS_NEW_CAP 0x0010 236#define PCI_STATUS_NEW_CAP 0x0010
238 237
238/* bits for ISTAT/IIM */
239#define TX3927_PCIC_IIM_ALL 0x00001600
240
239/* bits for TC */ 241/* bits for TC */
240#define TX3927_PCIC_TC_OF16E 0x00000020 242#define TX3927_PCIC_TC_OF16E 0x00000020
241#define TX3927_PCIC_TC_IF8E 0x00000010 243#define TX3927_PCIC_TC_IF8E 0x00000010
242#define TX3927_PCIC_TC_OF8E 0x00000008 244#define TX3927_PCIC_TC_OF8E 0x00000008
243 245
246/* bits for TSTAT/TIM */
247#define TX3927_PCIC_TIM_ALL 0x0003ffff
248
244/* bits for IOBA/MBA */ 249/* bits for IOBA/MBA */
245/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ 250/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
246 251
@@ -313,12 +318,22 @@ struct tx3927_ccfg_reg {
313#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) 318#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
314#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) 319#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
315#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) 320#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
316#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
317#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) 321#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
318#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) 322#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
319 323
324#define TX3927_REV_PCODE() (tx3927_ccfgptr->crir >> 16)
325#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000)
326#define TX3927_ROMC_SIZE(ch) \
327 (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
328
329void tx3927_wdt_init(void);
330void tx3927_setup(void);
331void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr);
332void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask);
320struct pci_controller; 333struct pci_controller;
321void __init tx3927_pcic_setup(struct pci_controller *channel, 334void tx3927_pcic_setup(struct pci_controller *channel,
322 unsigned long sdram_size, int extarb); 335 unsigned long sdram_size, int extarb);
336void tx3927_setup_pcierr_irq(void);
337void tx3927_irq_init(void);
323 338
324#endif /* __ASM_TXX9_TX3927_H */ 339#endif /* __ASM_TXX9_TX3927_H */
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
index ceb4b79ff4e..195f6515db9 100644
--- a/include/asm-mips/txx9/tx4927.h
+++ b/include/asm-mips/txx9/tx4927.h
@@ -243,12 +243,13 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new)
243} 243}
244 244
245unsigned int tx4927_get_mem_size(void); 245unsigned int tx4927_get_mem_size(void);
246void tx4927_wdr_init(void); 246void tx4927_wdt_init(void);
247void tx4927_setup(void); 247void tx4927_setup(void);
248void tx4927_time_init(unsigned int tmrnr); 248void tx4927_time_init(unsigned int tmrnr);
249void tx4927_setup_serial(void); 249void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
250int tx4927_report_pciclk(void); 250int tx4927_report_pciclk(void);
251int tx4927_pciclk66_setup(void); 251int tx4927_pciclk66_setup(void);
252void tx4927_setup_pcierr_irq(void);
252void tx4927_irq_init(void); 253void tx4927_irq_init(void);
253 254
254#endif /* __ASM_TXX9_TX4927_H */ 255#endif /* __ASM_TXX9_TX4927_H */
diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h
index d61c3d09c4a..c470b8a5fe5 100644
--- a/include/asm-mips/txx9/tx4927pcic.h
+++ b/include/asm-mips/txx9/tx4927pcic.h
@@ -10,6 +10,7 @@
10#define __ASM_TXX9_TX4927PCIC_H 10#define __ASM_TXX9_TX4927PCIC_H
11 11
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/irqreturn.h>
13 14
14struct tx4927_pcic_reg { 15struct tx4927_pcic_reg {
15 u32 pciid; 16 u32 pciid;
@@ -192,8 +193,11 @@ struct tx4927_pcic_reg {
192 193
193struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( 194struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
194 struct pci_controller *channel); 195 struct pci_controller *channel);
195void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, 196void tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
196 struct pci_controller *channel, int extarb); 197 struct pci_controller *channel, int extarb);
197void tx4927_report_pcic_status(void); 198void tx4927_report_pcic_status(void);
199char *tx4927_pcibios_setup(char *str);
200void tx4927_dump_pcic_settings(void);
201irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id);
198 202
199#endif /* __ASM_TXX9_TX4927PCIC_H */ 203#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
index 1ed969d381d..8175d4ccbc3 100644
--- a/include/asm-mips/txx9/tx4938.h
+++ b/include/asm-mips/txx9/tx4938.h
@@ -276,15 +276,18 @@ struct tx4938_ccfg_reg {
276#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch) 276#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
277 277
278#define tx4938_get_mem_size() tx4927_get_mem_size() 278#define tx4938_get_mem_size() tx4927_get_mem_size()
279void tx4938_wdr_init(void); 279void tx4938_wdt_init(void);
280void tx4938_setup(void); 280void tx4938_setup(void);
281void tx4938_time_init(unsigned int tmrnr); 281void tx4938_time_init(unsigned int tmrnr);
282void tx4938_setup_serial(void); 282void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask);
283void tx4938_spi_init(int busid);
284void tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
283int tx4938_report_pciclk(void); 285int tx4938_report_pciclk(void);
284void tx4938_report_pci1clk(void); 286void tx4938_report_pci1clk(void);
285int tx4938_pciclk66_setup(void); 287int tx4938_pciclk66_setup(void);
286struct pci_dev; 288struct pci_dev;
287int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); 289int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
290void tx4938_setup_pcierr_irq(void);
288void tx4938_irq_init(void); 291void tx4938_irq_init(void);
289 292
290#endif 293#endif
diff --git a/include/asm-mips/txx9/txx927.h b/include/asm-mips/txx9/txx927.h
deleted file mode 100644
index 97dd7ad1a89..00000000000
--- a/include/asm-mips/txx9/txx927.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * Common definitions for TX3927/TX4927
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Toshiba Corporation
9 */
10#ifndef __ASM_TXX9_TXX927_H
11#define __ASM_TXX9_TXX927_H
12
13struct txx927_sio_reg {
14 volatile unsigned long lcr;
15 volatile unsigned long dicr;
16 volatile unsigned long disr;
17 volatile unsigned long cisr;
18 volatile unsigned long fcr;
19 volatile unsigned long flcr;
20 volatile unsigned long bgr;
21 volatile unsigned long tfifo;
22 volatile unsigned long rfifo;
23};
24
25/*
26 * SIO
27 */
28/* SILCR : Line Control */
29#define TXx927_SILCR_SCS_MASK 0x00000060
30#define TXx927_SILCR_SCS_IMCLK 0x00000000
31#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020
32#define TXx927_SILCR_SCS_SCLK 0x00000040
33#define TXx927_SILCR_SCS_SCLK_BG 0x00000060
34#define TXx927_SILCR_UEPS 0x00000010
35#define TXx927_SILCR_UPEN 0x00000008
36#define TXx927_SILCR_USBL_MASK 0x00000004
37#define TXx927_SILCR_USBL_1BIT 0x00000004
38#define TXx927_SILCR_USBL_2BIT 0x00000000
39#define TXx927_SILCR_UMODE_MASK 0x00000003
40#define TXx927_SILCR_UMODE_8BIT 0x00000000
41#define TXx927_SILCR_UMODE_7BIT 0x00000001
42
43/* SIDICR : DMA/Int. Control */
44#define TXx927_SIDICR_TDE 0x00008000
45#define TXx927_SIDICR_RDE 0x00004000
46#define TXx927_SIDICR_TIE 0x00002000
47#define TXx927_SIDICR_RIE 0x00001000
48#define TXx927_SIDICR_SPIE 0x00000800
49#define TXx927_SIDICR_CTSAC 0x00000600
50#define TXx927_SIDICR_STIE_MASK 0x0000003f
51#define TXx927_SIDICR_STIE_OERS 0x00000020
52#define TXx927_SIDICR_STIE_CTSS 0x00000010
53#define TXx927_SIDICR_STIE_RBRKD 0x00000008
54#define TXx927_SIDICR_STIE_TRDY 0x00000004
55#define TXx927_SIDICR_STIE_TXALS 0x00000002
56#define TXx927_SIDICR_STIE_UBRKD 0x00000001
57
58/* SIDISR : DMA/Int. Status */
59#define TXx927_SIDISR_UBRK 0x00008000
60#define TXx927_SIDISR_UVALID 0x00004000
61#define TXx927_SIDISR_UFER 0x00002000
62#define TXx927_SIDISR_UPER 0x00001000
63#define TXx927_SIDISR_UOER 0x00000800
64#define TXx927_SIDISR_ERI 0x00000400
65#define TXx927_SIDISR_TOUT 0x00000200
66#define TXx927_SIDISR_TDIS 0x00000100
67#define TXx927_SIDISR_RDIS 0x00000080
68#define TXx927_SIDISR_STIS 0x00000040
69#define TXx927_SIDISR_RFDN_MASK 0x0000001f
70
71/* SICISR : Change Int. Status */
72#define TXx927_SICISR_OERS 0x00000020
73#define TXx927_SICISR_CTSS 0x00000010
74#define TXx927_SICISR_RBRKD 0x00000008
75#define TXx927_SICISR_TRDY 0x00000004
76#define TXx927_SICISR_TXALS 0x00000002
77#define TXx927_SICISR_UBRKD 0x00000001
78
79/* SIFCR : FIFO Control */
80#define TXx927_SIFCR_SWRST 0x00008000
81#define TXx927_SIFCR_RDIL_MASK 0x00000180
82#define TXx927_SIFCR_RDIL_1 0x00000000
83#define TXx927_SIFCR_RDIL_4 0x00000080
84#define TXx927_SIFCR_RDIL_8 0x00000100
85#define TXx927_SIFCR_RDIL_12 0x00000180
86#define TXx927_SIFCR_RDIL_MAX 0x00000180
87#define TXx927_SIFCR_TDIL_MASK 0x00000018
88#define TXx927_SIFCR_TDIL_MASK 0x00000018
89#define TXx927_SIFCR_TDIL_1 0x00000000
90#define TXx927_SIFCR_TDIL_4 0x00000001
91#define TXx927_SIFCR_TDIL_8 0x00000010
92#define TXx927_SIFCR_TDIL_MAX 0x00000010
93#define TXx927_SIFCR_TFRST 0x00000004
94#define TXx927_SIFCR_RFRST 0x00000002
95#define TXx927_SIFCR_FRSTE 0x00000001
96#define TXx927_SIO_TX_FIFO 8
97#define TXx927_SIO_RX_FIFO 16
98
99/* SIFLCR : Flow Control */
100#define TXx927_SIFLCR_RCS 0x00001000
101#define TXx927_SIFLCR_TES 0x00000800
102#define TXx927_SIFLCR_RTSSC 0x00000200
103#define TXx927_SIFLCR_RSDE 0x00000100
104#define TXx927_SIFLCR_TSDE 0x00000080
105#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e
106#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e
107#define TXx927_SIFLCR_TBRK 0x00000001
108
109/* SIBGR : Baudrate Control */
110#define TXx927_SIBGR_BCLK_MASK 0x00000300
111#define TXx927_SIBGR_BCLK_T0 0x00000000
112#define TXx927_SIBGR_BCLK_T2 0x00000100
113#define TXx927_SIBGR_BCLK_T4 0x00000200
114#define TXx927_SIBGR_BCLK_T6 0x00000300
115#define TXx927_SIBGR_BRD_MASK 0x000000ff
116
117/*
118 * PIO
119 */
120
121#endif /* __ASM_TXX9_TXX927_H */
diff --git a/include/asm-mips/txx9irq.h b/include/asm-mips/txx9irq.h
index 1c439e51b87..5620879be37 100644
--- a/include/asm-mips/txx9irq.h
+++ b/include/asm-mips/txx9irq.h
@@ -14,8 +14,12 @@
14#ifdef CONFIG_IRQ_CPU 14#ifdef CONFIG_IRQ_CPU
15#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) 15#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
16#else 16#else
17#ifdef CONFIG_I8259
18#define TXX9_IRQ_BASE (I8259A_IRQ_BASE + 16)
19#else
17#define TXX9_IRQ_BASE 0 20#define TXX9_IRQ_BASE 0
18#endif 21#endif
22#endif
19 23
20#ifdef CONFIG_CPU_TX39XX 24#ifdef CONFIG_CPU_TX39XX
21#define TXx9_MAX_IR 16 25#define TXx9_MAX_IR 16
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-02 08:41:12 -0500