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-rw-r--r--MAINTAINERS2
-rw-r--r--arch/sh/Kconfig12
-rw-r--r--arch/sh/include/asm/processor.h2
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h5
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7734.h306
-rw-r--r--arch/sh/kernel/cpu/proc.c3
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c6
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c2
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c16
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c8
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c4
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c6
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c4
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c4
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c3
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c4
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile3
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7734.c266
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c2497
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7734.c800
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c20
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c10
-rw-r--r--arch/sh/mm/fault_32.c38
-rw-r--r--arch/sh/mm/tlbflush_64.c114
-rw-r--r--arch/sparc/kernel/leon_pci.c13
-rw-r--r--arch/sparc/mm/fault_32.c37
-rw-r--r--arch/sparc/mm/fault_64.c37
-rw-r--r--arch/um/drivers/cow.h35
-rw-r--r--arch/um/drivers/cow_user.c43
-rw-r--r--arch/um/drivers/mconsole_kern.c1
-rw-r--r--arch/um/include/asm/Kbuild3
-rw-r--r--arch/um/kernel/Makefile7
-rw-r--r--arch/um/kernel/process.c6
-rw-r--r--arch/um/kernel/skas/mmu.c1
-rw-r--r--arch/x86/Makefile.um3
-rw-r--r--arch/x86/um/asm/barrier.h75
-rw-r--r--arch/x86/um/asm/system.h135
-rw-r--r--crypto/Kconfig6
-rw-r--r--drivers/i2c/busses/i2c-designware-pcidrv.c1
-rw-r--r--drivers/regulator/anatop-regulator.c6
-rw-r--r--drivers/sh/clk/cpg.c77
-rw-r--r--drivers/staging/android/lowmemorykiller.c48
-rw-r--r--drivers/tty/serial/sh-sci.c30
-rw-r--r--include/linux/serial_sci.h2
-rw-r--r--include/linux/sh_clk.h34
-rw-r--r--scripts/mod/modpost.c7
-rw-r--r--scripts/mod/modpost.h1
56 files changed, 4327 insertions, 482 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 2dcfca85063..0b568b6f116 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6545,7 +6545,7 @@ M: Paul Mundt <lethal@linux-sh.org>
6545L: linux-sh@vger.kernel.org 6545L: linux-sh@vger.kernel.org
6546W: http://www.linux-sh.org 6546W: http://www.linux-sh.org
6547Q: http://patchwork.kernel.org/project/linux-sh/list/ 6547Q: http://patchwork.kernel.org/project/linux-sh/list/
6548T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.git sh-latest 6548T: git git://github.com/pmundt/linux-sh.git sh-latest
6549S: Supported 6549S: Supported
6550F: Documentation/sh/ 6550F: Documentation/sh/
6551F: arch/sh/ 6551F: arch/sh/
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index ff9e033ce62..ed2419f7afe 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -427,6 +427,16 @@ config CPU_SUBTYPE_SH7724
427 help 427 help
428 Select SH7724 if you have an SH-MobileR2R CPU. 428 Select SH7724 if you have an SH-MobileR2R CPU.
429 429
430config CPU_SUBTYPE_SH7734
431 bool "Support SH7734 processor"
432 select CPU_SH4A
433 select CPU_SHX2
434 select ARCH_WANT_OPTIONAL_GPIOLIB
435 select USB_ARCH_HAS_OHCI
436 select USB_ARCH_HAS_EHCI
437 help
438 Select SH7734 if you have a SH4A SH7734 CPU.
439
430config CPU_SUBTYPE_SH7757 440config CPU_SUBTYPE_SH7757
431 bool "Support SH7757 processor" 441 bool "Support SH7757 processor"
432 select CPU_SH4A 442 select CPU_SH4A
@@ -584,7 +594,7 @@ config SH_CLK_CPG
584config SH_CLK_CPG_LEGACY 594config SH_CLK_CPG_LEGACY
585 depends on SH_CLK_CPG 595 depends on SH_CLK_CPG
586 def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ 596 def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
587 !CPU_SHX3 && !CPU_SUBTYPE_SH7757 597 !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && !CPU_SUBTYPE_SH7734
588 598
589source "kernel/time/Kconfig" 599source "kernel/time/Kconfig"
590 600
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index a229c393826..26b12fd8fcb 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -32,7 +32,7 @@ enum cpu_type {
32 32
33 /* SH-4A types */ 33 /* SH-4A types */
34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
35 CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3, 35 CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3,
36 36
37 /* SH4AL-DSP types */ 37 /* SH4AL-DSP types */
38 CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372, 38 CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372,
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index cffd25ed024..1631fc238e6 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -47,6 +47,11 @@
47#define MSTPCR1 0xa4150034 47#define MSTPCR1 0xa4150034
48#define MSTPCR2 0xa4150038 48#define MSTPCR2 0xa4150038
49 49
50#elif defined(CONFIG_CPU_SUBTYPE_SH7734)
51#define FRQCR0 0xffc80000
52#define FRQCR2 0xffc80008
53#define FRQMR1 0xffc80014
54#define FRQMR2 0xffc80018
50#elif defined(CONFIG_CPU_SUBTYPE_SH7785) 55#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
51#define FRQCR0 0xffc80000 56#define FRQCR0 0xffc80000
52#define FRQCR1 0xffc80004 57#define FRQCR1 0xffc80004
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7734.h b/arch/sh/include/cpu-sh4/cpu/sh7734.h
new file mode 100644
index 00000000000..2fb9a7b71b4
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7734.h
@@ -0,0 +1,306 @@
1#ifndef __ASM_SH7734_H__
2#define __ASM_SH7734_H__
3
4/* Pin Function Controller:
5 * GPIO_FN_xx - GPIO used to select pin function
6 * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
7 */
8enum {
9 GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
10 GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
11 GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
12 GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
13 GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
14 GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
15 GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
16 GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
17
18 GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
19 GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
20 GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
21 GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
22 GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
23 GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
24 GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
25 GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
26
27 GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
28 GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
29 GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
30 GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
31 GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
32 GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
33 GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
34 GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
35
36 GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
37 GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
38 GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
39 GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
40 GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
41 GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
42 GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
43 GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
44
45 GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
46 GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
47 GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
48 GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
49 GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
50 GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
51 GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
52 GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
53
54 GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
55 GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
56 GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
57
58 GPIO_FN_CLKOUT, GPIO_FN_BS, GPIO_FN_CS0, GPIO_FN_EX_CS0, GPIO_FN_RD,
59 GPIO_FN_WE0, GPIO_FN_WE1,
60
61 GPIO_FN_SCL0, GPIO_FN_PENC0, GPIO_FN_USB_OVC0,
62
63 GPIO_FN_IRQ2_B, GPIO_FN_IRQ3_B,
64
65 /* IPSR0 */
66 GPIO_FN_A15, GPIO_FN_ST0_VCO_CLKIN, GPIO_FN_LCD_DATA15_A,
67 GPIO_FN_TIOC3D_C,
68 GPIO_FN_A14, GPIO_FN_LCD_DATA14_A, GPIO_FN_TIOC3C_C,
69 GPIO_FN_A13, GPIO_FN_LCD_DATA13_A, GPIO_FN_TIOC3B_C,
70 GPIO_FN_A12, GPIO_FN_LCD_DATA12_A, GPIO_FN_TIOC3A_C,
71 GPIO_FN_A11, GPIO_FN_ST0_D7, GPIO_FN_LCD_DATA11_A,
72 GPIO_FN_TIOC2B_C,
73 GPIO_FN_A10, GPIO_FN_ST0_D6, GPIO_FN_LCD_DATA10_A,
74 GPIO_FN_TIOC2A_C,
75 GPIO_FN_A9, GPIO_FN_ST0_D5, GPIO_FN_LCD_DATA9_A,
76 GPIO_FN_TIOC1B_C,
77 GPIO_FN_A8, GPIO_FN_ST0_D4, GPIO_FN_LCD_DATA8_A,
78 GPIO_FN_TIOC1A_C,
79 GPIO_FN_A7, GPIO_FN_ST0_D3, GPIO_FN_LCD_DATA7_A, GPIO_FN_TIOC0D_C,
80 GPIO_FN_A6, GPIO_FN_ST0_D2, GPIO_FN_LCD_DATA6_A, GPIO_FN_TIOC0C_C,
81 GPIO_FN_A5, GPIO_FN_ST0_D1, GPIO_FN_LCD_DATA5_A, GPIO_FN_TIOC0B_C,
82 GPIO_FN_A4, GPIO_FN_ST0_D0, GPIO_FN_LCD_DATA4_A, GPIO_FN_TIOC0A_C,
83 GPIO_FN_A3, GPIO_FN_ST0_VLD, GPIO_FN_LCD_DATA3_A, GPIO_FN_TCLKD_C,
84 GPIO_FN_A2, GPIO_FN_ST0_SYC, GPIO_FN_LCD_DATA2_A, GPIO_FN_TCLKC_C,
85 GPIO_FN_A1, GPIO_FN_ST0_REQ, GPIO_FN_LCD_DATA1_A, GPIO_FN_TCLKB_C,
86 GPIO_FN_A0, GPIO_FN_ST0_CLKIN, GPIO_FN_LCD_DATA0_A, GPIO_FN_TCLKA_C,
87
88 /* IPSR1 */
89 GPIO_FN_D3, GPIO_FN_SD0_DAT3_A, GPIO_FN_MMC_D3_A, GPIO_FN_ST1_D6,
90 GPIO_FN_FD3_A,
91 GPIO_FN_D2, GPIO_FN_SD0_DAT2_A, GPIO_FN_MMC_D2_A, GPIO_FN_ST1_D5,
92 GPIO_FN_FD2_A,
93 GPIO_FN_D1, GPIO_FN_SD0_DAT1_A, GPIO_FN_MMC_D1_A, GPIO_FN_ST1_D4,
94 GPIO_FN_FD1_A,
95 GPIO_FN_D0, GPIO_FN_SD0_DAT0_A, GPIO_FN_MMC_D0_A, GPIO_FN_ST1_D3,
96 GPIO_FN_FD0_A,
97 GPIO_FN_A25, GPIO_FN_TX2_D, GPIO_FN_ST1_D2,
98 GPIO_FN_A24, GPIO_FN_RX2_D, GPIO_FN_ST1_D1,
99 GPIO_FN_A23, GPIO_FN_ST1_D0, GPIO_FN_LCD_M_DISP_A,
100 GPIO_FN_A22, GPIO_FN_ST1_VLD, GPIO_FN_LCD_VEPWC_A,
101 GPIO_FN_A21, GPIO_FN_ST1_SYC, GPIO_FN_LCD_VCPWC_A,
102 GPIO_FN_A20, GPIO_FN_ST1_REQ, GPIO_FN_LCD_FLM_A,
103 GPIO_FN_A19, GPIO_FN_ST1_CLKIN, GPIO_FN_LCD_CLK_A, GPIO_FN_TIOC4D_C,
104 GPIO_FN_A18, GPIO_FN_ST1_PWM, GPIO_FN_LCD_CL2_A, GPIO_FN_TIOC4C_C,
105 GPIO_FN_A17, GPIO_FN_ST1_VCO_CLKIN, GPIO_FN_LCD_CL1_A, GPIO_FN_TIOC4B_C,
106 GPIO_FN_A16, GPIO_FN_ST0_PWM, GPIO_FN_LCD_DON_A, GPIO_FN_TIOC4A_C,
107
108 /* IPSR2 */
109 GPIO_FN_D14, GPIO_FN_TX2_B, GPIO_FN_FSE_A, GPIO_FN_ET0_TX_CLK_B,
110 GPIO_FN_D13, GPIO_FN_RX2_B, GPIO_FN_FRB_A, GPIO_FN_ET0_ETXD6_B,
111 GPIO_FN_D12, GPIO_FN_FWE_A, GPIO_FN_ET0_ETXD5_B,
112 GPIO_FN_D11, GPIO_FN_RSPI_MISO_A, GPIO_FN_QMI_QIO1_A,
113 GPIO_FN_FRE_A, GPIO_FN_ET0_ETXD3_B,
114 GPIO_FN_D10, GPIO_FN_RSPI_MOSI_A, GPIO_FN_QMO_QIO0_A,
115 GPIO_FN_FALE_A, GPIO_FN_ET0_ETXD2_B,
116 GPIO_FN_D9, GPIO_FN_SD0_CMD_A, GPIO_FN_MMC_CMD_A, GPIO_FN_QIO3_A,
117 GPIO_FN_FCLE_A, GPIO_FN_ET0_ETXD1_B,
118 GPIO_FN_D8, GPIO_FN_SD0_CLK_A, GPIO_FN_MMC_CLK_A, GPIO_FN_QIO2_A,
119 GPIO_FN_FCE_A, GPIO_FN_ET0_GTX_CLK_B,
120 GPIO_FN_D7, GPIO_FN_RSPI_SSL_A, GPIO_FN_MMC_D7_A, GPIO_FN_QSSL_A,
121 GPIO_FN_FD7_A,
122 GPIO_FN_D6, GPIO_FN_RSPI_RSPCK_A, GPIO_FN_MMC_D6_A, GPIO_FN_QSPCLK_A,
123 GPIO_FN_FD6_A,
124 GPIO_FN_D5, GPIO_FN_SD0_WP_A, GPIO_FN_MMC_D5_A, GPIO_FN_FD5_A,
125 GPIO_FN_D4, GPIO_FN_SD0_CD_A, GPIO_FN_MMC_D4_A, GPIO_FN_ST1_D7,
126 GPIO_FN_FD4_A,
127
128 /* IPSR3 */
129 GPIO_FN_DRACK0, GPIO_FN_SD1_DAT2_A, GPIO_FN_ATAG, GPIO_FN_TCLK1_A,
130 GPIO_FN_ET0_ETXD7,
131 GPIO_FN_EX_WAIT2, GPIO_FN_SD1_DAT1_A, GPIO_FN_DACK2, GPIO_FN_CAN1_RX_C,
132 GPIO_FN_ET0_MAGIC_C, GPIO_FN_ET0_ETXD6_A,
133 GPIO_FN_EX_WAIT1, GPIO_FN_SD1_DAT0_A, GPIO_FN_DREQ2, GPIO_FN_CAN1_TX_C,
134 GPIO_FN_ET0_LINK_C, GPIO_FN_ET0_ETXD5_A,
135 GPIO_FN_EX_WAIT0, GPIO_FN_TCLK1_B,
136 GPIO_FN_RD_WR, GPIO_FN_TCLK0,
137 GPIO_FN_EX_CS5, GPIO_FN_SD1_CMD_A, GPIO_FN_ATADIR, GPIO_FN_QSSL_B,
138 GPIO_FN_ET0_ETXD3_A,
139 GPIO_FN_EX_CS4, GPIO_FN_SD1_WP_A, GPIO_FN_ATAWR, GPIO_FN_QMI_QIO1_B,
140 GPIO_FN_ET0_ETXD2_A,
141 GPIO_FN_EX_CS3, GPIO_FN_SD1_CD_A, GPIO_FN_ATARD, GPIO_FN_QMO_QIO0_B,
142 GPIO_FN_ET0_ETXD1_A,
143 GPIO_FN_EX_CS2, GPIO_FN_TX3_B, GPIO_FN_ATACS1, GPIO_FN_QSPCLK_B,
144 GPIO_FN_ET0_GTX_CLK_A,
145 GPIO_FN_EX_CS1, GPIO_FN_RX3_B, GPIO_FN_ATACS0, GPIO_FN_QIO2_B,
146 GPIO_FN_ET0_ETXD0,
147 GPIO_FN_CS1_A26, GPIO_FN_QIO3_B,
148 GPIO_FN_D15, GPIO_FN_SCK2_B,
149
150 /* IPSR4 */
151 GPIO_FN_SCK2_A, GPIO_FN_VI0_G3,
152 GPIO_FN_RTS1_B, GPIO_FN_VI0_G2,
153 GPIO_FN_CTS1_B, GPIO_FN_VI0_DATA7_VI0_G1,
154 GPIO_FN_TX1_B, GPIO_FN_VI0_DATA6_VI0_G0, GPIO_FN_ET0_PHY_INT_A,
155 GPIO_FN_RX1_B, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_ET0_MAGIC_A,
156 GPIO_FN_SCK1_B, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ET0_LINK_A,
157 GPIO_FN_RTS0_B, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ET0_MDIO_A,
158 GPIO_FN_CTS0_B, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_RMII0_MDIO_A,
159 GPIO_FN_ET0_MDC,
160 GPIO_FN_HTX0_A, GPIO_FN_TX1_A, GPIO_FN_VI0_DATA1_VI0_B1,
161 GPIO_FN_RMII0_MDC_A, GPIO_FN_ET0_COL,
162 GPIO_FN_HRX0_A, GPIO_FN_RX1_A, GPIO_FN_VI0_DATA0_VI0_B0,
163 GPIO_FN_RMII0_CRS_DV_A, GPIO_FN_ET0_CRS,
164 GPIO_FN_HSCK0_A, GPIO_FN_SCK1_A, GPIO_FN_VI0_VSYNC,
165 GPIO_FN_RMII0_RX_ER_A, GPIO_FN_ET0_RX_ER,
166 GPIO_FN_HRTS0_A, GPIO_FN_RTS1_A, GPIO_FN_VI0_HSYNC,
167 GPIO_FN_RMII0_TXD_EN_A, GPIO_FN_ET0_RX_DV,
168 GPIO_FN_HCTS0_A, GPIO_FN_CTS1_A, GPIO_FN_VI0_FIELD,
169 GPIO_FN_RMII0_RXD1_A, GPIO_FN_ET0_ERXD7,
170
171 /* IPSR5 */
172 GPIO_FN_SD2_CLK_A, GPIO_FN_RX2_A, GPIO_FN_VI0_G4, GPIO_FN_ET0_RX_CLK_B,
173 GPIO_FN_SD2_CMD_A, GPIO_FN_TX2_A, GPIO_FN_VI0_G5, GPIO_FN_ET0_ERXD2_B,
174 GPIO_FN_SD2_DAT0_A, GPIO_FN_RX3_A, GPIO_FN_VI0_R0, GPIO_FN_ET0_ERXD3_B,
175 GPIO_FN_SD2_DAT1_A, GPIO_FN_TX3_A, GPIO_FN_VI0_R1, GPIO_FN_ET0_MDIO_B,
176 GPIO_FN_SD2_DAT2_A, GPIO_FN_RX4_A, GPIO_FN_VI0_R2, GPIO_FN_ET0_LINK_B,
177 GPIO_FN_SD2_DAT3_A, GPIO_FN_TX4_A, GPIO_FN_VI0_R3, GPIO_FN_ET0_MAGIC_B,
178 GPIO_FN_SD2_CD_A, GPIO_FN_RX5_A, GPIO_FN_VI0_R4, GPIO_FN_ET0_PHY_INT_B,
179 GPIO_FN_SD2_WP_A, GPIO_FN_TX5_A, GPIO_FN_VI0_R5,
180 GPIO_FN_REF125CK, GPIO_FN_ADTRG, GPIO_FN_RX5_C,
181 GPIO_FN_REF50CK, GPIO_FN_CTS1_E, GPIO_FN_HCTS0_D,
182
183 /* IPSR6 */
184 GPIO_FN_DU0_DR0, GPIO_FN_SCIF_CLK_B, GPIO_FN_HRX0_D, GPIO_FN_IETX_A,
185 GPIO_FN_TCLKA_A, GPIO_FN_HIFD00,
186 GPIO_FN_DU0_DR1, GPIO_FN_SCK0_B, GPIO_FN_HTX0_D, GPIO_FN_IERX_A,
187 GPIO_FN_TCLKB_A, GPIO_FN_HIFD01,
188 GPIO_FN_DU0_DR2, GPIO_FN_RX0_B, GPIO_FN_TCLKC_A, GPIO_FN_HIFD02,
189 GPIO_FN_DU0_DR3, GPIO_FN_TX0_B, GPIO_FN_TCLKD_A, GPIO_FN_HIFD03,
190 GPIO_FN_DU0_DR4, GPIO_FN_CTS0_C, GPIO_FN_TIOC0A_A, GPIO_FN_HIFD04,
191 GPIO_FN_DU0_DR5, GPIO_FN_RTS0_C, GPIO_FN_TIOC0B_A, GPIO_FN_HIFD05,
192 GPIO_FN_DU0_DR6, GPIO_FN_SCK1_C, GPIO_FN_TIOC0C_A, GPIO_FN_HIFD06,
193 GPIO_FN_DU0_DR7, GPIO_FN_RX1_C, GPIO_FN_TIOC0D_A, GPIO_FN_HIFD07,
194 GPIO_FN_DU0_DG0, GPIO_FN_TX1_C, GPIO_FN_HSCK0_D, GPIO_FN_IECLK_A,
195 GPIO_FN_TIOC1A_A, GPIO_FN_HIFD08,
196 GPIO_FN_DU0_DG1, GPIO_FN_CTS1_C, GPIO_FN_HRTS0_D, GPIO_FN_TIOC1B_A,
197 GPIO_FN_HIFD09,
198
199 /* IPSR7 */
200 GPIO_FN_DU0_DG2, GPIO_FN_RTS1_C, GPIO_FN_RMII0_MDC_B, GPIO_FN_TIOC2A_A,
201 GPIO_FN_HIFD10,
202 GPIO_FN_DU0_DG3, GPIO_FN_SCK2_C, GPIO_FN_RMII0_MDIO_B, GPIO_FN_TIOC2B_A,
203 GPIO_FN_HIFD11,
204 GPIO_FN_DU0_DG4, GPIO_FN_RX2_C, GPIO_FN_RMII0_CRS_DV_B,
205 GPIO_FN_TIOC3A_A, GPIO_FN_HIFD12,
206 GPIO_FN_DU0_DG5, GPIO_FN_TX2_C, GPIO_FN_RMII0_RX_ER_B,
207 GPIO_FN_TIOC3B_A, GPIO_FN_HIFD13,
208 GPIO_FN_DU0_DG6, GPIO_FN_RX3_C, GPIO_FN_RMII0_RXD0_B,
209 GPIO_FN_TIOC3C_A, GPIO_FN_HIFD14,
210 GPIO_FN_DU0_DG7, GPIO_FN_TX3_C, GPIO_FN_RMII0_RXD1_B,
211 GPIO_FN_TIOC3D_A, GPIO_FN_HIFD15,
212 GPIO_FN_DU0_DB0, GPIO_FN_RX4_C, GPIO_FN_RMII0_TXD_EN_B,
213 GPIO_FN_TIOC4A_A, GPIO_FN_HIFCS,
214 GPIO_FN_DU0_DB1, GPIO_FN_TX4_C, GPIO_FN_RMII0_TXD0_B,
215 GPIO_FN_TIOC4B_A, GPIO_FN_HIFRS,
216 GPIO_FN_DU0_DB2, GPIO_FN_RX5_B, GPIO_FN_RMII0_TXD1_B,
217 GPIO_FN_TIOC4C_A, GPIO_FN_HIFWR,
218 GPIO_FN_DU0_DB3, GPIO_FN_TX5_B, GPIO_FN_TIOC4D_A, GPIO_FN_HIFRD,
219 GPIO_FN_DU0_DB4, GPIO_FN_HIFINT,
220
221 /* IPSR8 */
222 GPIO_FN_DU0_DB5, GPIO_FN_HIFDREQ,
223 GPIO_FN_DU0_DB6, GPIO_FN_HIFRDY,
224 GPIO_FN_DU0_DB7, GPIO_FN_SSI_SCK0_B, GPIO_FN_HIFEBL_B,
225 GPIO_FN_DU0_DOTCLKIN, GPIO_FN_HSPI_CS0_C, GPIO_FN_SSI_WS0_B,
226 GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_HSPI_CLK0_C, GPIO_FN_SSI_SDATA0_B,
227 GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_HSPI_TX0_C, GPIO_FN_SSI_SCK1_B,
228 GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_HSPI_RX0_C, GPIO_FN_SSI_WS1_B,
229 GPIO_FN_DU0_EXODDF_DU0_ODDF, GPIO_FN_CAN0_RX_B, GPIO_FN_HSCK0_B,
230 GPIO_FN_SSI_SDATA1_B,
231 GPIO_FN_DU0_DISP, GPIO_FN_CAN0_TX_B, GPIO_FN_HRX0_B,
232 GPIO_FN_AUDIO_CLKA_B,
233 GPIO_FN_DU0_CDE, GPIO_FN_HTX0_B, GPIO_FN_AUDIO_CLKB_B,
234 GPIO_FN_LCD_VCPWC_B,
235 GPIO_FN_IRQ0_A, GPIO_FN_HSPI_TX_B, GPIO_FN_RX3_E, GPIO_FN_ET0_ERXD0,
236 GPIO_FN_IRQ1_A, GPIO_FN_HSPI_RX_B, GPIO_FN_TX3_E, GPIO_FN_ET0_ERXD1,
237 GPIO_FN_IRQ2_A, GPIO_FN_CTS0_A, GPIO_FN_HCTS0_B, GPIO_FN_ET0_ERXD2_A,
238 GPIO_FN_IRQ3_A, GPIO_FN_RTS0_A, GPIO_FN_HRTS0_B, GPIO_FN_ET0_ERXD3_A,
239
240 /* IPSR9 */
241 GPIO_FN_VI1_CLK_A, GPIO_FN_FD0_B, GPIO_FN_LCD_DATA0_B,
242 GPIO_FN_VI1_0_A, GPIO_FN_FD1_B, GPIO_FN_LCD_DATA1_B,
243 GPIO_FN_VI1_1_A, GPIO_FN_FD2_B, GPIO_FN_LCD_DATA2_B,
244 GPIO_FN_VI1_2_A, GPIO_FN_FD3_B, GPIO_FN_LCD_DATA3_B,
245 GPIO_FN_VI1_3_A, GPIO_FN_FD4_B, GPIO_FN_LCD_DATA4_B,
246 GPIO_FN_VI1_4_A, GPIO_FN_FD5_B, GPIO_FN_LCD_DATA5_B,
247 GPIO_FN_VI1_5_A, GPIO_FN_FD6_B, GPIO_FN_LCD_DATA6_B,
248 GPIO_FN_VI1_6_A, GPIO_FN_FD7_B, GPIO_FN_LCD_DATA7_B,
249 GPIO_FN_VI1_7_A, GPIO_FN_FCE_B, GPIO_FN_LCD_DATA8_B,
250 GPIO_FN_SSI_SCK0_A, GPIO_FN_TIOC1A_B, GPIO_FN_LCD_DATA9_B,
251 GPIO_FN_SSI_WS0_A, GPIO_FN_TIOC1B_B, GPIO_FN_LCD_DATA10_B,
252 GPIO_FN_SSI_SDATA0_A, GPIO_FN_VI1_0_B, GPIO_FN_TIOC2A_B,
253 GPIO_FN_LCD_DATA11_B,
254 GPIO_FN_SSI_SCK1_A, GPIO_FN_VI1_1_B, GPIO_FN_TIOC2B_B,
255 GPIO_FN_LCD_DATA12_B,
256 GPIO_FN_SSI_WS1_A, GPIO_FN_VI1_2_B, GPIO_FN_LCD_DATA13_B,
257 GPIO_FN_SSI_SDATA1_A, GPIO_FN_VI1_3_B, GPIO_FN_LCD_DATA14_B,
258
259 /* IPSR10 */
260 GPIO_FN_SSI_SCK23, GPIO_FN_VI1_4_B, GPIO_FN_RX1_D, GPIO_FN_FCLE_B,
261 GPIO_FN_LCD_DATA15_B,
262 GPIO_FN_SSI_WS23, GPIO_FN_VI1_5_B, GPIO_FN_TX1_D, GPIO_FN_HSCK0_C,
263 GPIO_FN_FALE_B, GPIO_FN_LCD_DON_B,
264 GPIO_FN_SSI_SDATA2, GPIO_FN_VI1_6_B, GPIO_FN_HRX0_C, GPIO_FN_FRE_B,
265 GPIO_FN_LCD_CL1_B,
266 GPIO_FN_SSI_SDATA3, GPIO_FN_VI1_7_B, GPIO_FN_HTX0_C, GPIO_FN_FWE_B,
267 GPIO_FN_LCD_CL2_B,
268 GPIO_FN_AUDIO_CLKA_A, GPIO_FN_VI1_CLK_B, GPIO_FN_SCK1_D,
269 GPIO_FN_IECLK_B, GPIO_FN_LCD_FLM_B,
270 GPIO_FN_AUDIO_CLKB_A, GPIO_FN_LCD_CLK_B,
271 GPIO_FN_AUDIO_CLKC, GPIO_FN_SCK1_E, GPIO_FN_HCTS0_C, GPIO_FN_FRB_B,
272 GPIO_FN_LCD_VEPWC_B,
273 GPIO_FN_AUDIO_CLKOUT, GPIO_FN_TX1_E, GPIO_FN_HRTS0_C, GPIO_FN_FSE_B,
274 GPIO_FN_LCD_M_DISP_B,
275 GPIO_FN_CAN_CLK_A, GPIO_FN_RX4_D,
276 GPIO_FN_CAN0_TX_A, GPIO_FN_TX4_D, GPIO_FN_MLB_CLK,
277 GPIO_FN_CAN1_RX_A, GPIO_FN_IRQ1_B,
278 GPIO_FN_CAN0_RX_A, GPIO_FN_IRQ0_B, GPIO_FN_MLB_SIG,
279 GPIO_FN_CAN1_TX_A, GPIO_FN_TX5_C, GPIO_FN_MLB_DAT,
280
281 /* IPSR11 */
282 GPIO_FN_SCL1, GPIO_FN_SCIF_CLK_C,
283 GPIO_FN_SDA1, GPIO_FN_RX1_E,
284 GPIO_FN_SDA0, GPIO_FN_HIFEBL_A,
285 GPIO_FN_SDSELF, GPIO_FN_RTS1_E,
286 GPIO_FN_SCIF_CLK_A, GPIO_FN_HSPI_CLK_A, GPIO_FN_VI0_CLK,
287 GPIO_FN_RMII0_TXD0_A, GPIO_FN_ET0_ERXD4,
288 GPIO_FN_SCK0_A, GPIO_FN_HSPI_CS_A, GPIO_FN_VI0_CLKENB,
289 GPIO_FN_RMII0_TXD1_A, GPIO_FN_ET0_ERXD5,
290 GPIO_FN_RX0_A, GPIO_FN_HSPI_RX_A, GPIO_FN_RMII0_RXD0_A,
291 GPIO_FN_ET0_ERXD6,
292 GPIO_FN_TX0_A, GPIO_FN_HSPI_TX_A,
293 GPIO_FN_PENC1, GPIO_FN_TX3_D, GPIO_FN_CAN1_TX_B, GPIO_FN_TX5_D,
294 GPIO_FN_IETX_B,
295 GPIO_FN_USB_OVC1, GPIO_FN_RX3_D, GPIO_FN_CAN1_RX_B, GPIO_FN_RX5_D,
296 GPIO_FN_IERX_B,
297 GPIO_FN_DREQ0, GPIO_FN_SD1_CLK_A, GPIO_FN_ET0_TX_EN,
298 GPIO_FN_DACK0, GPIO_FN_SD1_DAT3_A, GPIO_FN_ET0_TX_ER,
299 GPIO_FN_DREQ1, GPIO_FN_HSPI_CLK_B, GPIO_FN_RX4_B, GPIO_FN_ET0_PHY_INT_C,
300 GPIO_FN_ET0_TX_CLK_A,
301 GPIO_FN_DACK1, GPIO_FN_HSPI_CS_B, GPIO_FN_TX4_B, GPIO_FN_ET0_RX_CLK_A,
302 GPIO_FN_PRESETOUT, GPIO_FN_ST_CLKOUT,
303
304};
305
306#endif /* __ASM_SH7734_H__ */
diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c
index f47be8727b3..e3a16d10452 100644
--- a/arch/sh/kernel/cpu/proc.c
+++ b/arch/sh/kernel/cpu/proc.c
@@ -25,7 +25,8 @@ static const char *cpu_name[] = {
25 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", 25 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
26 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723", 26 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
27 [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724", 27 [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
28 [CPU_SH7372] = "SH7372", [CPU_SH_NONE] = "Unknown" 28 [CPU_SH7372] = "SH7372", [CPU_SH7734] = "SH7734",
29 [CPU_SH_NONE] = "Unknown"
29}; 30};
30 31
31const char *get_cpu_subtype(struct sh_cpuinfo *c) 32const char *get_cpu_subtype(struct sh_cpuinfo *c)
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 0f8befccf9f..e0b740c831c 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -65,7 +65,7 @@ static struct plat_sci_port scif0_platform_data = {
65 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 65 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
66 .scbrr_algo_id = SCBRR_ALGO_2, 66 .scbrr_algo_id = SCBRR_ALGO_2,
67 .type = PORT_SCIF, 67 .type = PORT_SCIF,
68 .irqs = { 88, 88, 88, 88 }, 68 .irqs = SCIx_IRQ_MUXED(88),
69}; 69};
70 70
71static struct platform_device scif0_device = { 71static struct platform_device scif0_device = {
@@ -82,7 +82,7 @@ static struct plat_sci_port scif1_platform_data = {
82 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 82 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
83 .scbrr_algo_id = SCBRR_ALGO_2, 83 .scbrr_algo_id = SCBRR_ALGO_2,
84 .type = PORT_SCIF, 84 .type = PORT_SCIF,
85 .irqs = { 92, 92, 92, 92 }, 85 .irqs = SCIx_IRQ_MUXED(92),
86}; 86};
87 87
88static struct platform_device scif1_device = { 88static struct platform_device scif1_device = {
@@ -99,7 +99,7 @@ static struct plat_sci_port scif2_platform_data = {
99 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 99 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
100 .scbrr_algo_id = SCBRR_ALGO_2, 100 .scbrr_algo_id = SCBRR_ALGO_2,
101 .type = PORT_SCIF, 101 .type = PORT_SCIF,
102 .irqs = { 96, 96, 96, 96 }, 102 .irqs = SCIx_IRQ_MUXED(96),
103}; 103};
104 104
105static struct platform_device scif2_device = { 105static struct platform_device scif2_device = {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index 949bf2bac28..f7f1cf2af30 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -204,7 +204,7 @@ static struct plat_sci_port scif0_platform_data = {
204 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 204 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
205 .scbrr_algo_id = SCBRR_ALGO_2, 205 .scbrr_algo_id = SCBRR_ALGO_2,
206 .type = PORT_SCIF, 206 .type = PORT_SCIF,
207 .irqs = { 220, 220, 220, 220 }, 207 .irqs = SCIx_IRQ_MUXED(220),
208}; 208};
209 209
210static struct platform_device scif0_device = { 210static struct platform_device scif0_device = {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 9df558dcdb8..7b84785b896 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -183,7 +183,7 @@ static struct plat_sci_port scif0_platform_data = {
183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
184 .scbrr_algo_id = SCBRR_ALGO_2, 184 .scbrr_algo_id = SCBRR_ALGO_2,
185 .type = PORT_SCIF, 185 .type = PORT_SCIF,
186 .irqs = { 180, 180, 180, 180 } 186 .irqs = SCIx_IRQ_MUXED(180),
187}; 187};
188 188
189static struct platform_device scif0_device = { 189static struct platform_device scif0_device = {
@@ -200,7 +200,7 @@ static struct plat_sci_port scif1_platform_data = {
200 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 200 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
201 .scbrr_algo_id = SCBRR_ALGO_2, 201 .scbrr_algo_id = SCBRR_ALGO_2,
202 .type = PORT_SCIF, 202 .type = PORT_SCIF,
203 .irqs = { 184, 184, 184, 184 } 203 .irqs = SCIx_IRQ_MUXED(184),
204}; 204};
205 205
206static struct platform_device scif1_device = { 206static struct platform_device scif1_device = {
@@ -217,7 +217,7 @@ static struct plat_sci_port scif2_platform_data = {
217 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 217 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
218 .scbrr_algo_id = SCBRR_ALGO_2, 218 .scbrr_algo_id = SCBRR_ALGO_2,
219 .type = PORT_SCIF, 219 .type = PORT_SCIF,
220 .irqs = { 188, 188, 188, 188 } 220 .irqs = SCIx_IRQ_MUXED(188),
221}; 221};
222 222
223static struct platform_device scif2_device = { 223static struct platform_device scif2_device = {
@@ -234,7 +234,7 @@ static struct plat_sci_port scif3_platform_data = {
234 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 234 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
235 .scbrr_algo_id = SCBRR_ALGO_2, 235 .scbrr_algo_id = SCBRR_ALGO_2,
236 .type = PORT_SCIF, 236 .type = PORT_SCIF,
237 .irqs = { 192, 192, 192, 192 } 237 .irqs = SCIx_IRQ_MUXED(192),
238}; 238};
239 239
240static struct platform_device scif3_device = { 240static struct platform_device scif3_device = {
@@ -251,7 +251,7 @@ static struct plat_sci_port scif4_platform_data = {
251 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 251 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
252 .scbrr_algo_id = SCBRR_ALGO_2, 252 .scbrr_algo_id = SCBRR_ALGO_2,
253 .type = PORT_SCIF, 253 .type = PORT_SCIF,
254 .irqs = { 196, 196, 196, 196 } 254 .irqs = SCIx_IRQ_MUXED(196),
255}; 255};
256 256
257static struct platform_device scif4_device = { 257static struct platform_device scif4_device = {
@@ -268,7 +268,7 @@ static struct plat_sci_port scif5_platform_data = {
268 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 268 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
269 .scbrr_algo_id = SCBRR_ALGO_2, 269 .scbrr_algo_id = SCBRR_ALGO_2,
270 .type = PORT_SCIF, 270 .type = PORT_SCIF,
271 .irqs = { 200, 200, 200, 200 } 271 .irqs = SCIx_IRQ_MUXED(200),
272}; 272};
273 273
274static struct platform_device scif5_device = { 274static struct platform_device scif5_device = {
@@ -285,7 +285,7 @@ static struct plat_sci_port scif6_platform_data = {
285 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 285 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
286 .scbrr_algo_id = SCBRR_ALGO_2, 286 .scbrr_algo_id = SCBRR_ALGO_2,
287 .type = PORT_SCIF, 287 .type = PORT_SCIF,
288 .irqs = { 204, 204, 204, 204 } 288 .irqs = SCIx_IRQ_MUXED(204),
289}; 289};
290 290
291static struct platform_device scif6_device = { 291static struct platform_device scif6_device = {
@@ -302,7 +302,7 @@ static struct plat_sci_port scif7_platform_data = {
302 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 302 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
303 .scbrr_algo_id = SCBRR_ALGO_2, 303 .scbrr_algo_id = SCBRR_ALGO_2,
304 .type = PORT_SCIF, 304 .type = PORT_SCIF,
305 .irqs = { 208, 208, 208, 208 } 305 .irqs = SCIx_IRQ_MUXED(208),
306}; 306};
307 307
308static struct platform_device scif7_device = { 308static struct platform_device scif7_device = {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index 0bd744f9a3b..bfc33f6a28c 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -180,7 +180,7 @@ static struct plat_sci_port scif0_platform_data = {
180 SCSCR_REIE, 180 SCSCR_REIE,
181 .scbrr_algo_id = SCBRR_ALGO_2, 181 .scbrr_algo_id = SCBRR_ALGO_2,
182 .type = PORT_SCIF, 182 .type = PORT_SCIF,
183 .irqs = { 192, 192, 192, 192 }, 183 .irqs = SCIx_IRQ_MUXED(192),
184 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 184 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
185}; 185};
186 186
@@ -199,7 +199,7 @@ static struct plat_sci_port scif1_platform_data = {
199 SCSCR_REIE, 199 SCSCR_REIE,
200 .scbrr_algo_id = SCBRR_ALGO_2, 200 .scbrr_algo_id = SCBRR_ALGO_2,
201 .type = PORT_SCIF, 201 .type = PORT_SCIF,
202 .irqs = { 196, 196, 196, 196 }, 202 .irqs = SCIx_IRQ_MUXED(196),
203 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 203 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
204}; 204};
205 205
@@ -218,7 +218,7 @@ static struct plat_sci_port scif2_platform_data = {
218 SCSCR_REIE, 218 SCSCR_REIE,
219 .scbrr_algo_id = SCBRR_ALGO_2, 219 .scbrr_algo_id = SCBRR_ALGO_2,
220 .type = PORT_SCIF, 220 .type = PORT_SCIF,
221 .irqs = { 200, 200, 200, 200 }, 221 .irqs = SCIx_IRQ_MUXED(200),
222 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 222 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
223}; 223};
224 224
@@ -237,7 +237,7 @@ static struct plat_sci_port scif3_platform_data = {
237 SCSCR_REIE, 237 SCSCR_REIE,
238 .scbrr_algo_id = SCBRR_ALGO_2, 238 .scbrr_algo_id = SCBRR_ALGO_2,
239 .type = PORT_SCIF, 239 .type = PORT_SCIF,
240 .irqs = { 204, 204, 204, 204 }, 240 .irqs = SCIx_IRQ_MUXED(204),
241 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 241 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
242}; 242};
243 243
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index 5d14f849aea..a5010741de8 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -139,7 +139,7 @@ static struct plat_sci_port scif0_platform_data = {
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
140 .scbrr_algo_id = SCBRR_ALGO_2, 140 .scbrr_algo_id = SCBRR_ALGO_2,
141 .type = PORT_SCIF, 141 .type = PORT_SCIF,
142 .irqs = { 240, 240, 240, 240 }, 142 .irqs = SCIx_IRQ_MUXED(240),
143}; 143};
144 144
145static struct platform_device scif0_device = { 145static struct platform_device scif0_device = {
@@ -156,7 +156,7 @@ static struct plat_sci_port scif1_platform_data = {
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
157 .scbrr_algo_id = SCBRR_ALGO_2, 157 .scbrr_algo_id = SCBRR_ALGO_2,
158 .type = PORT_SCIF, 158 .type = PORT_SCIF,
159 .irqs = { 244, 244, 244, 244 }, 159 .irqs = SCIx_IRQ_MUXED(244),
160}; 160};
161 161
162static struct platform_device scif1_device = { 162static struct platform_device scif1_device = {
@@ -173,7 +173,7 @@ static struct plat_sci_port scif2_platform_data = {
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
174 .scbrr_algo_id = SCBRR_ALGO_2, 174 .scbrr_algo_id = SCBRR_ALGO_2,
175 .type = PORT_SCIF, 175 .type = PORT_SCIF,
176 .irqs = { 248, 248, 248, 248 }, 176 .irqs = SCIx_IRQ_MUXED(248),
177}; 177};
178 178
179static struct platform_device scif2_device = { 179static struct platform_device scif2_device = {
@@ -190,7 +190,7 @@ static struct plat_sci_port scif3_platform_data = {
190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
191 .scbrr_algo_id = SCBRR_ALGO_2, 191 .scbrr_algo_id = SCBRR_ALGO_2,
192 .type = PORT_SCIF, 192 .type = PORT_SCIF,
193 .irqs = { 252, 252, 252, 252 }, 193 .irqs = SCIx_IRQ_MUXED(252),
194}; 194};
195 195
196static struct platform_device scif3_device = { 196static struct platform_device scif3_device = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 2309618c015..97416a597dd 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -75,7 +75,7 @@ static struct plat_sci_port scif0_platform_data = {
75 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, 75 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
76 .scbrr_algo_id = SCBRR_ALGO_4, 76 .scbrr_algo_id = SCBRR_ALGO_4,
77 .type = PORT_SCIF, 77 .type = PORT_SCIF,
78 .irqs = { 56, 56, 56 }, 78 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
79 .ops = &sh770x_sci_port_ops, 79 .ops = &sh770x_sci_port_ops,
80 .regtype = SCIx_SH7705_SCIF_REGTYPE, 80 .regtype = SCIx_SH7705_SCIF_REGTYPE,
81}; 81};
@@ -94,7 +94,7 @@ static struct plat_sci_port scif1_platform_data = {
94 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, 94 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
95 .scbrr_algo_id = SCBRR_ALGO_4, 95 .scbrr_algo_id = SCBRR_ALGO_4,
96 .type = PORT_SCIF, 96 .type = PORT_SCIF,
97 .irqs = { 52, 52, 52 }, 97 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
98 .ops = &sh770x_sci_port_ops, 98 .ops = &sh770x_sci_port_ops,
99 .regtype = SCIx_SH7705_SCIF_REGTYPE, 99 .regtype = SCIx_SH7705_SCIF_REGTYPE,
100}; 100};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 3f3d5fe5892..50f95a32a8c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -114,7 +114,7 @@ static struct plat_sci_port scif0_platform_data = {
114 .scscr = SCSCR_TE | SCSCR_RE, 114 .scscr = SCSCR_TE | SCSCR_RE,
115 .scbrr_algo_id = SCBRR_ALGO_2, 115 .scbrr_algo_id = SCBRR_ALGO_2,
116 .type = PORT_SCI, 116 .type = PORT_SCI,
117 .irqs = { 23, 23, 23, 0 }, 117 .irqs = SCIx_IRQ_MUXED(evt2irq(0x4E0)),
118 .ops = &sh770x_sci_port_ops, 118 .ops = &sh770x_sci_port_ops,
119 .regshift = 1, 119 .regshift = 1,
120}; 120};
@@ -135,7 +135,7 @@ static struct plat_sci_port scif1_platform_data = {
135 .scscr = SCSCR_TE | SCSCR_RE, 135 .scscr = SCSCR_TE | SCSCR_RE,
136 .scbrr_algo_id = SCBRR_ALGO_2, 136 .scbrr_algo_id = SCBRR_ALGO_2,
137 .type = PORT_SCIF, 137 .type = PORT_SCIF,
138 .irqs = { 56, 56, 56, 56 }, 138 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
139 .ops = &sh770x_sci_port_ops, 139 .ops = &sh770x_sci_port_ops,
140 .regtype = SCIx_SH3_SCIF_REGTYPE, 140 .regtype = SCIx_SH3_SCIF_REGTYPE,
141}; 141};
@@ -157,7 +157,7 @@ static struct plat_sci_port scif2_platform_data = {
157 .scscr = SCSCR_TE | SCSCR_RE, 157 .scscr = SCSCR_TE | SCSCR_RE,
158 .scbrr_algo_id = SCBRR_ALGO_2, 158 .scbrr_algo_id = SCBRR_ALGO_2,
159 .type = PORT_IRDA, 159 .type = PORT_IRDA,
160 .irqs = { 52, 52, 52, 52 }, 160 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
161 .ops = &sh770x_sci_port_ops, 161 .ops = &sh770x_sci_port_ops,
162 .regshift = 1, 162 .regshift = 1,
163}; 163};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 78f6b01d42c..7ef24873182 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -103,7 +103,7 @@ static struct plat_sci_port scif0_platform_data = {
103 SCSCR_CKE1 | SCSCR_CKE0, 103 SCSCR_CKE1 | SCSCR_CKE0,
104 .scbrr_algo_id = SCBRR_ALGO_2, 104 .scbrr_algo_id = SCBRR_ALGO_2,
105 .type = PORT_SCIF, 105 .type = PORT_SCIF,
106 .irqs = { 52, 52, 52, 52 }, 106 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
107}; 107};
108 108
109static struct platform_device scif0_device = { 109static struct platform_device scif0_device = {
@@ -121,7 +121,7 @@ static struct plat_sci_port scif1_platform_data = {
121 SCSCR_CKE1 | SCSCR_CKE0, 121 SCSCR_CKE1 | SCSCR_CKE0,
122 .scbrr_algo_id = SCBRR_ALGO_2, 122 .scbrr_algo_id = SCBRR_ALGO_2,
123 .type = PORT_SCIF, 123 .type = PORT_SCIF,
124 .irqs = { 56, 56, 56, 56 }, 124 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
125}; 125};
126 126
127static struct platform_device scif1_device = { 127static struct platform_device scif1_device = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 94920345c14..b2557485d0c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -55,7 +55,7 @@ static struct plat_sci_port scif0_platform_data = {
55 .scscr = SCSCR_RE | SCSCR_TE, 55 .scscr = SCSCR_RE | SCSCR_TE,
56 .scbrr_algo_id = SCBRR_ALGO_4, 56 .scbrr_algo_id = SCBRR_ALGO_4,
57 .type = PORT_SCIF, 57 .type = PORT_SCIF,
58 .irqs = { 80, 80, 80, 80 }, 58 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)),
59 .ops = &sh7720_sci_port_ops, 59 .ops = &sh7720_sci_port_ops,
60 .regtype = SCIx_SH7705_SCIF_REGTYPE, 60 .regtype = SCIx_SH7705_SCIF_REGTYPE,
61}; 61};
@@ -74,7 +74,7 @@ static struct plat_sci_port scif1_platform_data = {
74 .scscr = SCSCR_RE | SCSCR_TE, 74 .scscr = SCSCR_RE | SCSCR_TE,
75 .scbrr_algo_id = SCBRR_ALGO_4, 75 .scbrr_algo_id = SCBRR_ALGO_4,
76 .type = PORT_SCIF, 76 .type = PORT_SCIF,
77 .irqs = { 81, 81, 81, 81 }, 77 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)),
78 .ops = &sh7720_sci_port_ops, 78 .ops = &sh7720_sci_port_ops,
79 .regtype = SCIx_SH7705_SCIF_REGTYPE, 79 .regtype = SCIx_SH7705_SCIF_REGTYPE,
80}; 80};
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 971cf0fce4f..0fbbd50bc8a 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -158,6 +158,9 @@ void __cpuinit cpu_probe(void)
158 case 0x40: /* yon-ten-go */ 158 case 0x40: /* yon-ten-go */
159 boot_cpu_data.type = CPU_SH7372; 159 boot_cpu_data.type = CPU_SH7372;
160 break; 160 break;
161 case 0xE0: /* 0x4E0 */
162 boot_cpu_data.type = CPU_SH7734; /* SH7733/SH7734 */
163 break;
161 164
162 } 165 }
163 break; 166 break;
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 98cc0c794c7..56b3bdc0b28 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -43,7 +43,7 @@ static struct plat_sci_port sci_platform_data = {
43 .scscr = SCSCR_TE | SCSCR_RE, 43 .scscr = SCSCR_TE | SCSCR_RE,
44 .scbrr_algo_id = SCBRR_ALGO_2, 44 .scbrr_algo_id = SCBRR_ALGO_2,
45 .type = PORT_SCI, 45 .type = PORT_SCI,
46 .irqs = { 23, 23, 23, 0 }, 46 .irqs = SCIx_IRQ_MUXED(evt2irq(0xE40)),
47 .regshift = 2, 47 .regshift = 2,
48}; 48};
49 49
@@ -61,7 +61,7 @@ static struct plat_sci_port scif_platform_data = {
61 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, 61 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
62 .scbrr_algo_id = SCBRR_ALGO_2, 62 .scbrr_algo_id = SCBRR_ALGO_2,
63 .type = PORT_SCIF, 63 .type = PORT_SCIF,
64 .irqs = { 40, 40, 40, 40 }, 64 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
65}; 65};
66 66
67static struct platform_device scif_device = { 67static struct platform_device scif_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 0b22d108f4c..8fc6ec2be2f 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o serial-sh7722.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o serial-sh7722.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7734) += setup-sh7734.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o 17obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
17obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o 18obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o
18 19
@@ -30,6 +31,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o 32clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o 33clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
34clock-$(CONFIG_CPU_SUBTYPE_SH7734) := clock-sh7734.o
33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o 35clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 36clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
35 37
@@ -37,6 +39,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
37pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o 39pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
38pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o 40pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
39pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o 41pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
42pinmux-$(CONFIG_CPU_SUBTYPE_SH7734) := pinmux-sh7734.o
40pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o 43pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o
41pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 44pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
42pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o 45pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7734.c b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c
new file mode 100644
index 00000000000..1697642c1f7
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c
@@ -0,0 +1,266 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7734.c
3 *
4 * Clock framework for SH7734
5 *
6 * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * Copyright (C) 2011, 2012 Renesas Solutions Corp.
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/io.h>
17#include <linux/clkdev.h>
18#include <linux/delay.h>
19#include <asm/clock.h>
20#include <asm/freq.h>
21
22static struct clk extal_clk = {
23 .rate = 33333333,
24};
25
26#define MODEMR (0xFFCC0020)
27#define MODEMR_MASK (0x6)
28#define MODEMR_533MHZ (0x2)
29
30static unsigned long pll_recalc(struct clk *clk)
31{
32 int mode = 12;
33 u32 r = __raw_readl(MODEMR);
34
35 if ((r & MODEMR_MASK) & MODEMR_533MHZ)
36 mode = 16;
37
38 return clk->parent->rate * mode;
39}
40
41static struct sh_clk_ops pll_clk_ops = {
42 .recalc = pll_recalc,
43};
44
45static struct clk pll_clk = {
46 .ops = &pll_clk_ops,
47 .parent = &extal_clk,
48 .flags = CLK_ENABLE_ON_INIT,
49};
50
51static struct clk *main_clks[] = {
52 &extal_clk,
53 &pll_clk,
54};
55
56static int multipliers[] = { 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
57static int divisors[] = { 1, 3, 2, 3, 4, 6, 8, 9, 12, 16, 18, 24 };
58
59static struct clk_div_mult_table div4_div_mult_table = {
60 .divisors = divisors,
61 .nr_divisors = ARRAY_SIZE(divisors),
62 .multipliers = multipliers,
63 .nr_multipliers = ARRAY_SIZE(multipliers),
64};
65
66static struct clk_div4_table div4_table = {
67 .div_mult_table = &div4_div_mult_table,
68};
69
70enum { DIV4_I, DIV4_S, DIV4_B, DIV4_M, DIV4_S1, DIV4_P, DIV4_NR };
71
72#define DIV4(_reg, _bit, _mask, _flags) \
73 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
74
75struct clk div4_clks[DIV4_NR] = {
76 [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
77 [DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT),
78 [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),
79 [DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT),
80 [DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT),
81 [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),
82};
83
84#define MSTPCR0 0xFFC80030
85#define MSTPCR1 0xFFC80034
86#define MSTPCR3 0xFFC8003C
87
88enum {
89 MSTP030, MSTP029, /* IIC */
90 MSTP026, MSTP025, MSTP024, /* SCIF */
91 MSTP023,
92 MSTP022, MSTP021,
93 MSTP019, /* HSCIF */
94 MSTP016, MSTP015, MSTP014, /* TMU / TIMER */
95 MSTP012, MSTP011, MSTP010, MSTP009, MSTP008, /* SSI */
96 MSTP007, /* HSPI */
97 MSTP115, /* ADMAC */
98 MSTP114, /* GETHER */
99 MSTP111, /* DMAC */
100 MSTP109, /* VIDEOIN1 */
101 MSTP108, /* VIDEOIN0 */
102 MSTP107, /* RGPVBG */
103 MSTP106, /* 2DG */
104 MSTP103, /* VIEW */
105 MSTP100, /* USB */
106 MSTP331, /* MMC */
107 MSTP330, /* MIMLB */
108 MSTP323, /* SDHI0 */
109 MSTP322, /* SDHI1 */
110 MSTP321, /* SDHI2 */
111 MSTP320, /* RQSPI */
112 MSTP319, /* SRC0 */
113 MSTP318, /* SRC1 */
114 MSTP317, /* RSPI */
115 MSTP316, /* RCAN0 */
116 MSTP315, /* RCAN1 */
117 MSTP314, /* FLTCL */
118 MSTP313, /* ADC */
119 MSTP312, /* MTU */
120 MSTP304, /* IE-BUS */
121 MSTP303, /* RTC */
122 MSTP302, /* HIF */
123 MSTP301, /* STIF0 */
124 MSTP300, /* STIF1 */
125 MSTP_NR };
126
127static struct clk mstp_clks[MSTP_NR] = {
128 /* MSTPCR0 */
129 [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0),
130 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
131 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
132 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
133 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
134 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
135 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
136 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
137 [MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
138 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
139 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
140 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
141 [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
142 [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
143 [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
144 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
145 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
146 [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
147
148 /* MSTPCR1 */
149 [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0),
150 [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
151 [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
152 [MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
153 [MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
154 [MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0),
155 [MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0),
156 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
157 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0),
158
159 /* MSTPCR3 */
160 [MSTP331] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 31, 0),
161 [MSTP330] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 30, 0),
162 [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0),
163 [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0),
164 [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0),
165 [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0),
166 [MSTP319] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 19, 0),
167 [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 18, 0),
168 [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 17, 0),
169 [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 16, 0),
170 [MSTP315] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 15, 0),
171 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 14, 0),
172 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 13, 0),
173 [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 12, 0),
174 [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 4, 0),
175 [MSTP303] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 3, 0),
176 [MSTP302] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 2, 0),
177 [MSTP301] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 1, 0),
178 [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 0, 0),
179};
180
181static struct clk_lookup lookups[] = {
182 /* main clocks */
183 CLKDEV_CON_ID("extal", &extal_clk),
184 CLKDEV_CON_ID("pll_clk", &pll_clk),
185
186 /* clocks */
187 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
188 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
189 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_M]),
190 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
191 CLKDEV_CON_ID("shyway_clk1", &div4_clks[DIV4_S1]),
192 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
193
194 /* MSTP32 clocks */
195 CLKDEV_DEV_ID("i2c-sh7734.0", &mstp_clks[MSTP030]),
196 CLKDEV_DEV_ID("i2c-sh7734.1", &mstp_clks[MSTP029]),
197 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP026]),
198 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
199 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP024]),
200 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP023]),
201 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP022]),
202 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP021]),
203 CLKDEV_CON_ID("hscif", &mstp_clks[MSTP019]),
204 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP016]),
205 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP016]),
206 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[MSTP016]),
207 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[MSTP015]),
208 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[MSTP015]),
209 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[MSTP015]),
210 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.6", &mstp_clks[MSTP014]),
211 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.7", &mstp_clks[MSTP014]),
212 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.8", &mstp_clks[MSTP014]),
213 CLKDEV_CON_ID("ssi0", &mstp_clks[MSTP012]),
214 CLKDEV_CON_ID("ssi1", &mstp_clks[MSTP011]),
215 CLKDEV_CON_ID("ssi2", &mstp_clks[MSTP010]),
216 CLKDEV_CON_ID("ssi3", &mstp_clks[MSTP009]),
217 CLKDEV_CON_ID("sss", &mstp_clks[MSTP008]),
218 CLKDEV_CON_ID("hspi", &mstp_clks[MSTP007]),
219 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP100]),
220 CLKDEV_CON_ID("videoin0", &mstp_clks[MSTP109]),
221 CLKDEV_CON_ID("videoin1", &mstp_clks[MSTP108]),
222 CLKDEV_CON_ID("rgpvg", &mstp_clks[MSTP107]),
223 CLKDEV_CON_ID("2dg", &mstp_clks[MSTP106]),
224 CLKDEV_CON_ID("view", &mstp_clks[MSTP103]),
225
226 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP331]),
227 CLKDEV_CON_ID("mimlb0", &mstp_clks[MSTP330]),
228 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP323]),
229 CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP322]),
230 CLKDEV_CON_ID("sdhi2", &mstp_clks[MSTP321]),
231 CLKDEV_CON_ID("rqspi0", &mstp_clks[MSTP320]),
232 CLKDEV_CON_ID("src0", &mstp_clks[MSTP319]),
233 CLKDEV_CON_ID("src1", &mstp_clks[MSTP318]),
234 CLKDEV_CON_ID("rsp0", &mstp_clks[MSTP317]),
235 CLKDEV_CON_ID("rcan0", &mstp_clks[MSTP316]),
236 CLKDEV_CON_ID("rcan1", &mstp_clks[MSTP315]),
237 CLKDEV_CON_ID("fltcl0", &mstp_clks[MSTP314]),
238 CLKDEV_CON_ID("adc0", &mstp_clks[MSTP313]),
239 CLKDEV_CON_ID("mtu0", &mstp_clks[MSTP312]),
240 CLKDEV_CON_ID("iebus0", &mstp_clks[MSTP304]),
241 CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[MSTP114]),
242 CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP303]),
243 CLKDEV_CON_ID("hif0", &mstp_clks[MSTP302]),
244 CLKDEV_CON_ID("stif0", &mstp_clks[MSTP301]),
245 CLKDEV_CON_ID("stif1", &mstp_clks[MSTP300]),
246};
247
248int __init arch_clk_init(void)
249{
250 int i, ret = 0;
251
252 for (i = 0; i < ARRAY_SIZE(main_clks); i++)
253 ret |= clk_register(main_clks[i]);
254
255 for (i = 0; i < ARRAY_SIZE(lookups); i++)
256 clkdev_add(&lookups[i]);
257
258 if (!ret)
259 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
260 &div4_table);
261
262 if (!ret)
263 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
264
265 return ret;
266}
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c
new file mode 100644
index 00000000000..eed3b9d19d3
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c
@@ -0,0 +1,2497 @@
1/*
2 * SH7734 processor support - PFC hardware block
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/gpio.h>
14#include <linux/ioport.h>
15#include <cpu/sh7734.h>
16
17#define CPU_32_PORT(fn, pfx, sfx) \
18 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
19 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
20 PORT_1(fn, pfx##31, sfx)
21
22#define CPU_32_PORT5(fn, pfx, sfx) \
23 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
24 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
25 PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
26 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
27 PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx), \
28 PORT_1(fn, pfx##10, sfx), PORT_1(fn, pfx##11, sfx)
29
30/* GPSR0 - GPSR5 */
31#define CPU_ALL_PORT(fn, pfx, sfx) \
32 CPU_32_PORT(fn, pfx##_0_, sfx), \
33 CPU_32_PORT(fn, pfx##_1_, sfx), \
34 CPU_32_PORT(fn, pfx##_2_, sfx), \
35 CPU_32_PORT(fn, pfx##_3_, sfx), \
36 CPU_32_PORT(fn, pfx##_4_, sfx), \
37 CPU_32_PORT5(fn, pfx##_5_, sfx)
38
39#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
40#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
41 GP##pfx##_IN, GP##pfx##_OUT)
42
43#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
44#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
45
46#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
47#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
48#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
49
50#define PORT_10_REV(fn, pfx, sfx) \
51 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
52 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
53 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
54 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
55 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
56
57#define CPU_32_PORT_REV(fn, pfx, sfx) \
58 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
59 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
60 PORT_10_REV(fn, pfx, sfx)
61
62#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
63#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
64
65#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
66#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
67 FN_##ipsr, FN_##fn)
68
69enum {
70 PINMUX_RESERVED = 0,
71
72 PINMUX_DATA_BEGIN,
73 GP_ALL(DATA), /* GP_0_0_DATA -> GP_5_11_DATA */
74 PINMUX_DATA_END,
75
76 PINMUX_INPUT_BEGIN,
77 GP_ALL(IN), /* GP_0_0_IN -> GP_5_11_IN */
78 PINMUX_INPUT_END,
79
80 PINMUX_OUTPUT_BEGIN,
81 GP_ALL(OUT), /* GP_0_0_OUT -> GP_5_11_OUT */
82 PINMUX_OUTPUT_END,
83
84 PINMUX_FUNCTION_BEGIN,
85 GP_ALL(FN), /* GP_0_0_FN -> GP_5_11_FN */
86
87 /* GPSR0 */
88 FN_IP1_9_8, FN_IP1_11_10, FN_IP1_13_12, FN_IP1_15_14,
89 FN_IP0_7_6, FN_IP0_9_8, FN_IP0_11_10, FN_IP0_13_12,
90 FN_IP0_15_14, FN_IP0_17_16, FN_IP0_19_18, FN_IP0_21_20,
91 FN_IP0_23_22, FN_IP0_25_24, FN_IP0_27_26, FN_IP0_29_28,
92 FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4,
93 FN_IP1_7_6, FN_IP11_28, FN_IP0_1_0, FN_IP0_3_2,
94 FN_IP0_5_4, FN_IP1_17_16, FN_IP1_19_18, FN_IP1_22_20,
95 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0,
96
97 /* GPSR1 */
98 FN_IP3_20, FN_IP3_29_27, FN_IP11_20_19, FN_IP11_22_21,
99 FN_IP2_16_14, FN_IP2_19_17, FN_IP2_22_20, FN_IP2_24_23,
100 FN_IP2_27_25, FN_IP2_30_28, FN_IP3_1_0, FN_CLKOUT,
101 FN_BS, FN_CS0, FN_IP3_2, FN_EX_CS0,
102 FN_IP3_5_3, FN_IP3_8_6, FN_IP3_11_9, FN_IP3_14_12,
103 FN_IP3_17_15, FN_RD, FN_IP3_19_18, FN_WE0,
104 FN_WE1, FN_IP2_4_3, FN_IP3_23_21, FN_IP3_26_24,
105 FN_IP2_7_5, FN_IP2_10_8, FN_IP2_13_11, FN_IP11_25_23,
106
107 /* GPSR2 */
108 FN_IP11_6_4, FN_IP11_9_7, FN_IP11_11_10, FN_IP4_2_0,
109 FN_IP8_29_28, FN_IP11_27_26, FN_IP8_22_20, FN_IP8_25_23,
110 FN_IP11_12, FN_IP8_27_26, FN_IP4_5_3, FN_IP4_8_6,
111 FN_IP4_11_9, FN_IP4_14_12, FN_IP4_17_15, FN_IP4_19_18,
112 FN_IP4_21_20, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
113 FN_IP4_29_28, FN_IP4_31_30, FN_IP5_2_0, FN_IP5_5_3,
114 FN_IP5_8_6, FN_IP5_11_9, FN_IP5_14_12, FN_IP5_17_15,
115 FN_IP5_20_18, FN_IP5_22_21, FN_IP5_24_23, FN_IP5_26_25,
116
117 /* GPSR3 */
118 FN_IP6_2_0, FN_IP6_5_3, FN_IP6_7_6, FN_IP6_9_8,
119 FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_17_16,
120 FN_IP6_20_18, FN_IP6_23_21, FN_IP7_2_0, FN_IP7_5_3,
121 FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15,
122 FN_IP7_20_18, FN_IP7_23_21, FN_IP7_26_24, FN_IP7_28_27,
123 FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
124 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12,
125 FN_IP8_15_14, FN_IP8_17_16, FN_IP8_19_18, FN_IP9_1_0,
126
127 /* GPSR4 */
128 FN_IP9_19_18, FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24,
129 FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, FN_IP9_17_16,
130 FN_IP9_3_2, FN_IP9_5_4, FN_IP9_7_6, FN_IP9_9_8,
131 FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
132 FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_15,
133 FN_IP10_18_16, FN_IP10_21_19, FN_IP11_0, FN_IP11_1,
134 FN_SCL0, FN_IP11_2, FN_PENC0, FN_IP11_15_13, /* Need check*/
135 FN_USB_OVC0, FN_IP11_18_16,
136 FN_IP10_22, FN_IP10_24_23,
137
138 /* GPSR5 */
139 FN_IP10_25, FN_IP11_3, FN_IRQ2_B, FN_IRQ3_B,
140 FN_IP10_27_26, /* 10 */
141 FN_IP10_29_28, /* 11 */
142
143 /* IPSR0 */
144 FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, FN_TIOC3D_C,
145 FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C,
146 FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C,
147 FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C,
148 FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
149 FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
150 FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
151 FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
152 FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
153 FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
154 FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
155 FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
156 FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
157 FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
158 FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
159 FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C,
160
161 /* IPSR1 */
162 FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, FN_FD3_A,
163 FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5, FN_FD2_A,
164 FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4, FN_FD1_A,
165 FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3, FN_FD0_A,
166 FN_A25, FN_TX2_D, FN_ST1_D2,
167 FN_A24, FN_RX2_D, FN_ST1_D1,
168 FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A,
169 FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A,
170 FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A,
171 FN_A20, FN_ST1_REQ, FN_LCD_FLM_A,
172 FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C,
173 FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
174 FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
175 FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C,
176
177 /* IPSR2 */
178 FN_D14, FN_TX2_B, FN_FSE_A, FN_ET0_TX_CLK_B,
179 FN_D13, FN_RX2_B, FN_FRB_A, FN_ET0_ETXD6_B,
180 FN_D12, FN_FWE_A, FN_ET0_ETXD5_B,
181 FN_D11, FN_RSPI_MISO_A, FN_QMI_QIO1_A, FN_FRE_A,
182 FN_ET0_ETXD3_B,
183 FN_D10, FN_RSPI_MOSI_A, FN_QMO_QIO0_A, FN_FALE_A,
184 FN_ET0_ETXD2_B,
185 FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A, FN_FCLE_A,
186 FN_ET0_ETXD1_B,
187 FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A, FN_FCE_A,
188 FN_ET0_GTX_CLK_B,
189 FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A, FN_FD7_A,
190 FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A, FN_FD6_A,
191 FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
192 FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, FN_FD4_A,
193
194 /* IPSR3 */
195 FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A, FN_ET0_ETXD7,
196 FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
197 FN_ET0_MAGIC_C, FN_ET0_ETXD6_A,
198 FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
199 FN_ET0_LINK_C, FN_ET0_ETXD5_A,
200 FN_EX_WAIT0, FN_TCLK1_B,
201 FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
202 FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B, FN_ET0_ETXD3_A,
203 FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B, FN_ET0_ETXD2_A,
204 FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B, FN_ET0_ETXD1_A,
205 FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B, FN_ET0_GTX_CLK_A,
206 FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B, FN_ET0_ETXD0,
207 FN_CS1_A26, FN_QIO3_B,
208 FN_D15, FN_SCK2_B,
209
210 /* IPSR4 */
211 FN_SCK2_A, FN_VI0_G3,
212 FN_RTS1_B, FN_VI0_G2,
213 FN_CTS1_B, FN_VI0_DATA7_VI0_G1,
214 FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
215 FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
216 FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
217 FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
218 FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A, FN_ET0_MDC,
219 FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A, FN_ET0_COL,
220 FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A, FN_ET0_CRS,
221 FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A, FN_ET0_RX_ER,
222 FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A, FN_ET0_RX_DV,
223 FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, FN_ET0_ERXD7,
224
225 /* IPSR5 */
226 FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, FN_ET0_RX_CLK_B,
227 FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, FN_ET0_ERXD2_B,
228 FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, FN_ET0_ERXD3_B,
229 FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, FN_ET0_MDIO_B,
230 FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, FN_ET0_LINK_B,
231 FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, FN_ET0_MAGIC_B,
232 FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, FN_ET0_PHY_INT_B,
233 FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5,
234 FN_REF125CK, FN_ADTRG, FN_RX5_C,
235 FN_REF50CK, FN_CTS1_E, FN_HCTS0_D,
236
237 /* IPSR6 */
238 FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, FN_TCLKA_A, FN_HIFD00,
239 FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A, FN_TCLKB_A, FN_HIFD01,
240 FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
241 FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
242 FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
243 FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
244 FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
245 FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
246 FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A, FN_TIOC1A_A, FN_HIFD08,
247 FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A, FN_HIFD09,
248
249 /* IPSR7 */
250 FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, FN_HIFD10,
251 FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A, FN_HIFD11,
252 FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A, FN_HIFD12,
253 FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A, FN_HIFD13,
254 FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A, FN_HIFD14,
255 FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A, FN_HIFD15,
256 FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A, FN_HIFCS,
257 FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A, FN_HIFRS,
258 FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A, FN_HIFWR,
259 FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
260 FN_DU0_DB4, FN_HIFINT,
261
262 /* IPSR8 */
263 FN_DU0_DB5, FN_HIFDREQ,
264 FN_DU0_DB6, FN_HIFRDY,
265 FN_DU0_DB7, FN_SSI_SCK0_B, FN_HIFEBL_B,
266 FN_DU0_DOTCLKIN, FN_HSPI_CS0_C, FN_SSI_WS0_B,
267 FN_DU0_DOTCLKOUT, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
268 FN_DU0_EXHSYNC_DU0_HSYNC, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
269 FN_DU0_EXVSYNC_DU0_VSYNC, FN_HSPI_RX0_C, FN_SSI_WS1_B,
270 FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B, FN_SSI_SDATA1_B,
271 FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
272 FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
273 FN_IRQ0_A, FN_HSPI_TX_B, FN_RX3_E, FN_ET0_ERXD0,
274 FN_IRQ1_A, FN_HSPI_RX_B, FN_TX3_E, FN_ET0_ERXD1,
275 FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
276 FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
277
278 /* IPSR9 */
279 FN_VI1_CLK_A, FN_FD0_B, FN_LCD_DATA0_B,
280 FN_VI1_0_A, FN_FD1_B, FN_LCD_DATA1_B,
281 FN_VI1_1_A, FN_FD2_B, FN_LCD_DATA2_B,
282 FN_VI1_2_A, FN_FD3_B, FN_LCD_DATA3_B,
283 FN_VI1_3_A, FN_FD4_B, FN_LCD_DATA4_B,
284 FN_VI1_4_A, FN_FD5_B, FN_LCD_DATA5_B,
285 FN_VI1_5_A, FN_FD6_B, FN_LCD_DATA6_B,
286 FN_VI1_6_A, FN_FD7_B, FN_LCD_DATA7_B,
287 FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B,
288 FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B,
289 FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B,
290 FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
291 FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
292 FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B,
293 FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B,
294
295 /* IPSR10 */
296 FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, FN_LCD_DATA15_B,
297 FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B, FN_LCD_DON_B,
298 FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B, FN_LCD_CL1_B,
299 FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B, FN_LCD_CL2_B,
300 FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B, FN_LCD_FLM_B,
301 FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
302 FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B, FN_LCD_VEPWC_B,
303 FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B, FN_LCD_M_DISP_B,
304 FN_CAN_CLK_A, FN_RX4_D,
305 FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK,
306 FN_CAN1_RX_A, FN_IRQ1_B,
307 FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG,
308 FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT,
309
310 /* IPSR11 */
311 FN_SCL1, FN_SCIF_CLK_C,
312 FN_SDA1, FN_RX1_E,
313 FN_SDA0, FN_HIFEBL_A,
314 FN_SDSELF, FN_RTS1_E,
315 FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A, FN_ET0_ERXD4,
316 FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A, FN_ET0_ERXD5,
317 FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
318 FN_TX0_A, FN_HSPI_TX_A,
319 FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D, FN_IETX_B,
320 FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D, FN_IERX_B,
321 FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN,
322 FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER,
323 FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C, FN_ET0_TX_CLK_A,
324 FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
325 FN_PRESETOUT, FN_ST_CLKOUT,
326
327 /* MOD_SEL1 */
328 FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
329 FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
330 FN_SEL_VIN1_0, FN_SEL_VIN1_1,
331 FN_SEL_HIF_0, FN_SEL_HIF_1,
332 FN_SEL_RSPI_0, FN_SEL_RSPI_1,
333 FN_SEL_LCDC_0, FN_SEL_LCDC_1,
334 FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2,
335 FN_SEL_ET0_0, FN_SEL_ET0_1,
336 FN_SEL_RMII_0, FN_SEL_RMII_1,
337 FN_SEL_TMU_0, FN_SEL_TMU_1,
338 FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2,
339 FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
340 FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
341 FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2,
342 FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
343 FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
344 FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
345 FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
346 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
347 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
348 FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
349 FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
350 FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
351 FN_SEL_MMC_0, FN_SEL_MMC_1,
352 FN_SEL_INTC_0, FN_SEL_INTC_1,
353
354 /* MOD_SEL2 */
355 FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
356 FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
357 FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
358 FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2,
359 FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2,
360 FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
361 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
362 FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
363 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
364 FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
365 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
366 FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
367 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
368 FN_SEL_SCIF2_3,
369 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
370 FN_SEL_SCIF1_3, FN_SEL_SCIF1_4,
371 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
372 FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2,
373
374 PINMUX_FUNCTION_END,
375
376 PINMUX_MARK_BEGIN,
377
378 CLKOUT_MARK, BS_MARK, CS0_MARK, EX_CS0_MARK, RD_MARK,
379 WE0_MARK, WE1_MARK,
380
381 SCL0_MARK, PENC0_MARK, USB_OVC0_MARK,
382
383 IRQ2_B_MARK, IRQ3_B_MARK,
384
385 /* IPSR0 */
386 A15_MARK, ST0_VCO_CLKIN_MARK, LCD_DATA15_A_MARK, TIOC3D_C_MARK,
387 A14_MARK, LCD_DATA14_A_MARK, TIOC3C_C_MARK,
388 A13_MARK, LCD_DATA13_A_MARK, TIOC3B_C_MARK,
389 A12_MARK, LCD_DATA12_A_MARK, TIOC3A_C_MARK,
390 A11_MARK, ST0_D7_MARK, LCD_DATA11_A_MARK, TIOC2B_C_MARK,
391 A10_MARK, ST0_D6_MARK, LCD_DATA10_A_MARK, TIOC2A_C_MARK,
392 A9_MARK, ST0_D5_MARK, LCD_DATA9_A_MARK, TIOC1B_C_MARK,
393 A8_MARK, ST0_D4_MARK, LCD_DATA8_A_MARK, TIOC1A_C_MARK,
394 A7_MARK, ST0_D3_MARK, LCD_DATA7_A_MARK, TIOC0D_C_MARK,
395 A6_MARK, ST0_D2_MARK, LCD_DATA6_A_MARK, TIOC0C_C_MARK,
396 A5_MARK, ST0_D1_MARK, LCD_DATA5_A_MARK, TIOC0B_C_MARK,
397 A4_MARK, ST0_D0_MARK, LCD_DATA4_A_MARK, TIOC0A_C_MARK,
398 A3_MARK, ST0_VLD_MARK, LCD_DATA3_A_MARK, TCLKD_C_MARK,
399 A2_MARK, ST0_SYC_MARK, LCD_DATA2_A_MARK, TCLKC_C_MARK,
400 A1_MARK, ST0_REQ_MARK, LCD_DATA1_A_MARK, TCLKB_C_MARK,
401 A0_MARK, ST0_CLKIN_MARK, LCD_DATA0_A_MARK, TCLKA_C_MARK,
402
403 /* IPSR1 */
404 D3_MARK, SD0_DAT3_A_MARK, MMC_D3_A_MARK, ST1_D6_MARK, FD3_A_MARK,
405 D2_MARK, SD0_DAT2_A_MARK, MMC_D2_A_MARK, ST1_D5_MARK, FD2_A_MARK,
406 D1_MARK, SD0_DAT1_A_MARK, MMC_D1_A_MARK, ST1_D4_MARK, FD1_A_MARK,
407 D0_MARK, SD0_DAT0_A_MARK, MMC_D0_A_MARK, ST1_D3_MARK, FD0_A_MARK,
408 A25_MARK, TX2_D_MARK, ST1_D2_MARK,
409 A24_MARK, RX2_D_MARK, ST1_D1_MARK,
410 A23_MARK, ST1_D0_MARK, LCD_M_DISP_A_MARK,
411 A22_MARK, ST1_VLD_MARK, LCD_VEPWC_A_MARK,
412 A21_MARK, ST1_SYC_MARK, LCD_VCPWC_A_MARK,
413 A20_MARK, ST1_REQ_MARK, LCD_FLM_A_MARK,
414 A19_MARK, ST1_CLKIN_MARK, LCD_CLK_A_MARK, TIOC4D_C_MARK,
415 A18_MARK, ST1_PWM_MARK, LCD_CL2_A_MARK, TIOC4C_C_MARK,
416 A17_MARK, ST1_VCO_CLKIN_MARK, LCD_CL1_A_MARK, TIOC4B_C_MARK,
417 A16_MARK, ST0_PWM_MARK, LCD_DON_A_MARK, TIOC4A_C_MARK,
418
419 /* IPSR2 */
420 D14_MARK, TX2_B_MARK, FSE_A_MARK, ET0_TX_CLK_B_MARK,
421 D13_MARK, RX2_B_MARK, FRB_A_MARK, ET0_ETXD6_B_MARK,
422 D12_MARK, FWE_A_MARK, ET0_ETXD5_B_MARK,
423 D11_MARK, RSPI_MISO_A_MARK, QMI_QIO1_A_MARK, FRE_A_MARK,
424 ET0_ETXD3_B_MARK,
425 D10_MARK, RSPI_MOSI_A_MARK, QMO_QIO0_A_MARK, FALE_A_MARK,
426 ET0_ETXD2_B_MARK,
427 D9_MARK, SD0_CMD_A_MARK, MMC_CMD_A_MARK, QIO3_A_MARK,
428 FCLE_A_MARK, ET0_ETXD1_B_MARK,
429 D8_MARK, SD0_CLK_A_MARK, MMC_CLK_A_MARK, QIO2_A_MARK,
430 FCE_A_MARK, ET0_GTX_CLK_B_MARK,
431 D7_MARK, RSPI_SSL_A_MARK, MMC_D7_A_MARK, QSSL_A_MARK,
432 FD7_A_MARK,
433 D6_MARK, RSPI_RSPCK_A_MARK, MMC_D6_A_MARK, QSPCLK_A_MARK,
434 FD6_A_MARK,
435 D5_MARK, SD0_WP_A_MARK, MMC_D5_A_MARK, FD5_A_MARK,
436 D4_MARK, SD0_CD_A_MARK, MMC_D4_A_MARK, ST1_D7_MARK,
437 FD4_A_MARK,
438
439 /* IPSR3 */
440 DRACK0_MARK, SD1_DAT2_A_MARK, ATAG_MARK, TCLK1_A_MARK, ET0_ETXD7_MARK,
441 EX_WAIT2_MARK, SD1_DAT1_A_MARK, DACK2_MARK, CAN1_RX_C_MARK,
442 ET0_MAGIC_C_MARK, ET0_ETXD6_A_MARK,
443 EX_WAIT1_MARK, SD1_DAT0_A_MARK, DREQ2_MARK, CAN1_TX_C_MARK,
444 ET0_LINK_C_MARK, ET0_ETXD5_A_MARK,
445 EX_WAIT0_MARK, TCLK1_B_MARK,
446 RD_WR_MARK, TCLK0_MARK, CAN_CLK_B_MARK, ET0_ETXD4_MARK,
447 EX_CS5_MARK, SD1_CMD_A_MARK, ATADIR_MARK, QSSL_B_MARK,
448 ET0_ETXD3_A_MARK,
449 EX_CS4_MARK, SD1_WP_A_MARK, ATAWR_MARK, QMI_QIO1_B_MARK,
450 ET0_ETXD2_A_MARK,
451 EX_CS3_MARK, SD1_CD_A_MARK, ATARD_MARK, QMO_QIO0_B_MARK,
452 ET0_ETXD1_A_MARK,
453 EX_CS2_MARK, TX3_B_MARK, ATACS1_MARK, QSPCLK_B_MARK,
454 ET0_GTX_CLK_A_MARK,
455 EX_CS1_MARK, RX3_B_MARK, ATACS0_MARK, QIO2_B_MARK,
456 ET0_ETXD0_MARK,
457 CS1_A26_MARK, QIO3_B_MARK,
458 D15_MARK, SCK2_B_MARK,
459
460 /* IPSR4 */
461 SCK2_A_MARK, VI0_G3_MARK,
462 RTS1_B_MARK, VI0_G2_MARK,
463 CTS1_B_MARK, VI0_DATA7_VI0_G1_MARK,
464 TX1_B_MARK, VI0_DATA6_VI0_G0_MARK, ET0_PHY_INT_A_MARK,
465 RX1_B_MARK, VI0_DATA5_VI0_B5_MARK, ET0_MAGIC_A_MARK,
466 SCK1_B_MARK, VI0_DATA4_VI0_B4_MARK, ET0_LINK_A_MARK,
467 RTS0_B_MARK, VI0_DATA3_VI0_B3_MARK, ET0_MDIO_A_MARK,
468 CTS0_B_MARK, VI0_DATA2_VI0_B2_MARK, RMII0_MDIO_A_MARK,
469 ET0_MDC_MARK,
470 HTX0_A_MARK, TX1_A_MARK, VI0_DATA1_VI0_B1_MARK,
471 RMII0_MDC_A_MARK, ET0_COL_MARK,
472 HRX0_A_MARK, RX1_A_MARK, VI0_DATA0_VI0_B0_MARK,
473 RMII0_CRS_DV_A_MARK, ET0_CRS_MARK,
474 HSCK0_A_MARK, SCK1_A_MARK, VI0_VSYNC_MARK,
475 RMII0_RX_ER_A_MARK, ET0_RX_ER_MARK,
476 HRTS0_A_MARK, RTS1_A_MARK, VI0_HSYNC_MARK,
477 RMII0_TXD_EN_A_MARK, ET0_RX_DV_MARK,
478 HCTS0_A_MARK, CTS1_A_MARK, VI0_FIELD_MARK,
479 RMII0_RXD1_A_MARK, ET0_ERXD7_MARK,
480
481 /* IPSR5 */
482 SD2_CLK_A_MARK, RX2_A_MARK, VI0_G4_MARK, ET0_RX_CLK_B_MARK,
483 SD2_CMD_A_MARK, TX2_A_MARK, VI0_G5_MARK, ET0_ERXD2_B_MARK,
484 SD2_DAT0_A_MARK, RX3_A_MARK, VI0_R0_MARK, ET0_ERXD3_B_MARK,
485 SD2_DAT1_A_MARK, TX3_A_MARK, VI0_R1_MARK, ET0_MDIO_B_MARK,
486 SD2_DAT2_A_MARK, RX4_A_MARK, VI0_R2_MARK, ET0_LINK_B_MARK,
487 SD2_DAT3_A_MARK, TX4_A_MARK, VI0_R3_MARK, ET0_MAGIC_B_MARK,
488 SD2_CD_A_MARK, RX5_A_MARK, VI0_R4_MARK, ET0_PHY_INT_B_MARK,
489 SD2_WP_A_MARK, TX5_A_MARK, VI0_R5_MARK,
490 REF125CK_MARK, ADTRG_MARK, RX5_C_MARK,
491 REF50CK_MARK, CTS1_E_MARK, HCTS0_D_MARK,
492
493 /* IPSR6 */
494 DU0_DR0_MARK, SCIF_CLK_B_MARK, HRX0_D_MARK, IETX_A_MARK,
495 TCLKA_A_MARK, HIFD00_MARK,
496 DU0_DR1_MARK, SCK0_B_MARK, HTX0_D_MARK, IERX_A_MARK,
497 TCLKB_A_MARK, HIFD01_MARK,
498 DU0_DR2_MARK, RX0_B_MARK, TCLKC_A_MARK, HIFD02_MARK,
499 DU0_DR3_MARK, TX0_B_MARK, TCLKD_A_MARK, HIFD03_MARK,
500 DU0_DR4_MARK, CTS0_C_MARK, TIOC0A_A_MARK, HIFD04_MARK,
501 DU0_DR5_MARK, RTS0_C_MARK, TIOC0B_A_MARK, HIFD05_MARK,
502 DU0_DR6_MARK, SCK1_C_MARK, TIOC0C_A_MARK, HIFD06_MARK,
503 DU0_DR7_MARK, RX1_C_MARK, TIOC0D_A_MARK, HIFD07_MARK,
504 DU0_DG0_MARK, TX1_C_MARK, HSCK0_D_MARK, IECLK_A_MARK,
505 TIOC1A_A_MARK, HIFD08_MARK,
506 DU0_DG1_MARK, CTS1_C_MARK, HRTS0_D_MARK, TIOC1B_A_MARK,
507 HIFD09_MARK,
508
509 /* IPSR7 */
510 DU0_DG2_MARK, RTS1_C_MARK, RMII0_MDC_B_MARK, TIOC2A_A_MARK,
511 HIFD10_MARK,
512 DU0_DG3_MARK, SCK2_C_MARK, RMII0_MDIO_B_MARK, TIOC2B_A_MARK,
513 HIFD11_MARK,
514 DU0_DG4_MARK, RX2_C_MARK, RMII0_CRS_DV_B_MARK, TIOC3A_A_MARK,
515 HIFD12_MARK,
516 DU0_DG5_MARK, TX2_C_MARK, RMII0_RX_ER_B_MARK, TIOC3B_A_MARK,
517 HIFD13_MARK,
518 DU0_DG6_MARK, RX3_C_MARK, RMII0_RXD0_B_MARK, TIOC3C_A_MARK,
519 HIFD14_MARK,
520 DU0_DG7_MARK, TX3_C_MARK, RMII0_RXD1_B_MARK, TIOC3D_A_MARK,
521 HIFD15_MARK,
522 DU0_DB0_MARK, RX4_C_MARK, RMII0_TXD_EN_B_MARK, TIOC4A_A_MARK,
523 HIFCS_MARK,
524 DU0_DB1_MARK, TX4_C_MARK, RMII0_TXD0_B_MARK, TIOC4B_A_MARK,
525 HIFRS_MARK,
526 DU0_DB2_MARK, RX5_B_MARK, RMII0_TXD1_B_MARK, TIOC4C_A_MARK,
527 HIFWR_MARK,
528 DU0_DB3_MARK, TX5_B_MARK, TIOC4D_A_MARK, HIFRD_MARK,
529 DU0_DB4_MARK, HIFINT_MARK,
530
531 /* IPSR8 */
532 DU0_DB5_MARK, HIFDREQ_MARK,
533 DU0_DB6_MARK, HIFRDY_MARK,
534 DU0_DB7_MARK, SSI_SCK0_B_MARK, HIFEBL_B_MARK,
535 DU0_DOTCLKIN_MARK, HSPI_CS0_C_MARK, SSI_WS0_B_MARK,
536 DU0_DOTCLKOUT_MARK, HSPI_CLK0_C_MARK, SSI_SDATA0_B_MARK,
537 DU0_EXHSYNC_DU0_HSYNC_MARK, HSPI_TX0_C_MARK, SSI_SCK1_B_MARK,
538 DU0_EXVSYNC_DU0_VSYNC_MARK, HSPI_RX0_C_MARK, SSI_WS1_B_MARK,
539 DU0_EXODDF_DU0_ODDF_MARK, CAN0_RX_B_MARK, HSCK0_B_MARK,
540 SSI_SDATA1_B_MARK,
541 DU0_DISP_MARK, CAN0_TX_B_MARK, HRX0_B_MARK, AUDIO_CLKA_B_MARK,
542 DU0_CDE_MARK, HTX0_B_MARK, AUDIO_CLKB_B_MARK, LCD_VCPWC_B_MARK,
543 IRQ0_A_MARK, HSPI_TX_B_MARK, RX3_E_MARK, ET0_ERXD0_MARK,
544 IRQ1_A_MARK, HSPI_RX_B_MARK, TX3_E_MARK, ET0_ERXD1_MARK,
545 IRQ2_A_MARK, CTS0_A_MARK, HCTS0_B_MARK, ET0_ERXD2_A_MARK,
546 IRQ3_A_MARK, RTS0_A_MARK, HRTS0_B_MARK, ET0_ERXD3_A_MARK,
547
548 /* IPSR9 */
549 VI1_CLK_A_MARK, FD0_B_MARK, LCD_DATA0_B_MARK,
550 VI1_0_A_MARK, FD1_B_MARK, LCD_DATA1_B_MARK,
551 VI1_1_A_MARK, FD2_B_MARK, LCD_DATA2_B_MARK,
552 VI1_2_A_MARK, FD3_B_MARK, LCD_DATA3_B_MARK,
553 VI1_3_A_MARK, FD4_B_MARK, LCD_DATA4_B_MARK,
554 VI1_4_A_MARK, FD5_B_MARK, LCD_DATA5_B_MARK,
555 VI1_5_A_MARK, FD6_B_MARK, LCD_DATA6_B_MARK,
556 VI1_6_A_MARK, FD7_B_MARK, LCD_DATA7_B_MARK,
557 VI1_7_A_MARK, FCE_B_MARK, LCD_DATA8_B_MARK,
558 SSI_SCK0_A_MARK, TIOC1A_B_MARK, LCD_DATA9_B_MARK,
559 SSI_WS0_A_MARK, TIOC1B_B_MARK, LCD_DATA10_B_MARK,
560 SSI_SDATA0_A_MARK, VI1_0_B_MARK, TIOC2A_B_MARK, LCD_DATA11_B_MARK,
561 SSI_SCK1_A_MARK, VI1_1_B_MARK, TIOC2B_B_MARK, LCD_DATA12_B_MARK,
562 SSI_WS1_A_MARK, VI1_2_B_MARK, LCD_DATA13_B_MARK,
563 SSI_SDATA1_A_MARK, VI1_3_B_MARK, LCD_DATA14_B_MARK,
564
565 /* IPSR10 */
566 SSI_SCK23_MARK, VI1_4_B_MARK, RX1_D_MARK, FCLE_B_MARK,
567 LCD_DATA15_B_MARK,
568 SSI_WS23_MARK, VI1_5_B_MARK, TX1_D_MARK, HSCK0_C_MARK,
569 FALE_B_MARK, LCD_DON_B_MARK,
570 SSI_SDATA2_MARK, VI1_6_B_MARK, HRX0_C_MARK, FRE_B_MARK,
571 LCD_CL1_B_MARK,
572 SSI_SDATA3_MARK, VI1_7_B_MARK, HTX0_C_MARK, FWE_B_MARK,
573 LCD_CL2_B_MARK,
574 AUDIO_CLKA_A_MARK, VI1_CLK_B_MARK, SCK1_D_MARK, IECLK_B_MARK,
575 LCD_FLM_B_MARK,
576 AUDIO_CLKB_A_MARK, LCD_CLK_B_MARK,
577 AUDIO_CLKC_MARK, SCK1_E_MARK, HCTS0_C_MARK, FRB_B_MARK,
578 LCD_VEPWC_B_MARK,
579 AUDIO_CLKOUT_MARK, TX1_E_MARK, HRTS0_C_MARK, FSE_B_MARK,
580 LCD_M_DISP_B_MARK,
581 CAN_CLK_A_MARK, RX4_D_MARK,
582 CAN0_TX_A_MARK, TX4_D_MARK, MLB_CLK_MARK,
583 CAN1_RX_A_MARK, IRQ1_B_MARK,
584 CAN0_RX_A_MARK, IRQ0_B_MARK, MLB_SIG_MARK,
585 CAN1_TX_A_MARK, TX5_C_MARK, MLB_DAT_MARK,
586
587 /* IPSR11 */
588 SCL1_MARK, SCIF_CLK_C_MARK,
589 SDA1_MARK, RX1_E_MARK,
590 SDA0_MARK, HIFEBL_A_MARK,
591 SDSELF_MARK, RTS1_E_MARK,
592 SCIF_CLK_A_MARK, HSPI_CLK_A_MARK, VI0_CLK_MARK, RMII0_TXD0_A_MARK,
593 ET0_ERXD4_MARK,
594 SCK0_A_MARK, HSPI_CS_A_MARK, VI0_CLKENB_MARK, RMII0_TXD1_A_MARK,
595 ET0_ERXD5_MARK,
596 RX0_A_MARK, HSPI_RX_A_MARK, RMII0_RXD0_A_MARK, ET0_ERXD6_MARK,
597 TX0_A_MARK, HSPI_TX_A_MARK,
598 PENC1_MARK, TX3_D_MARK, CAN1_TX_B_MARK, TX5_D_MARK,
599 IETX_B_MARK,
600 USB_OVC1_MARK, RX3_D_MARK, CAN1_RX_B_MARK, RX5_D_MARK,
601 IERX_B_MARK,
602 DREQ0_MARK, SD1_CLK_A_MARK, ET0_TX_EN_MARK,
603 DACK0_MARK, SD1_DAT3_A_MARK, ET0_TX_ER_MARK,
604 DREQ1_MARK, HSPI_CLK_B_MARK, RX4_B_MARK, ET0_PHY_INT_C_MARK,
605 ET0_TX_CLK_A_MARK,
606 DACK1_MARK, HSPI_CS_B_MARK, TX4_B_MARK, ET0_RX_CLK_A_MARK,
607 PRESETOUT_MARK, ST_CLKOUT_MARK,
608
609 PINMUX_MARK_END,
610};
611
612static pinmux_enum_t pinmux_data[] = {
613 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
614
615 PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT),
616 PINMUX_DATA(BS_MARK, FN_BS), PINMUX_DATA(CS0_MARK, FN_CS0),
617 PINMUX_DATA(EX_CS0_MARK, FN_EX_CS0),
618 PINMUX_DATA(RD_MARK, FN_RD), PINMUX_DATA(WE0_MARK, FN_WE0),
619 PINMUX_DATA(WE1_MARK, FN_WE1),
620 PINMUX_DATA(SCL0_MARK, FN_SCL0), PINMUX_DATA(PENC0_MARK, FN_PENC0),
621 PINMUX_DATA(USB_OVC0_MARK, FN_USB_OVC0),
622 PINMUX_DATA(IRQ2_B_MARK, FN_IRQ2_B),
623 PINMUX_DATA(IRQ3_B_MARK, FN_IRQ3_B),
624
625 /* IPSR0 */
626 PINMUX_IPSR_DATA(IP0_1_0, A0),
627 PINMUX_IPSR_DATA(IP0_1_0, ST0_CLKIN),
628 PINMUX_IPSR_MODSEL_DATA(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
629 PINMUX_IPSR_MODSEL_DATA(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
630
631 PINMUX_IPSR_DATA(IP0_3_2, A1),
632 PINMUX_IPSR_DATA(IP0_3_2, ST0_REQ),
633 PINMUX_IPSR_MODSEL_DATA(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
634 PINMUX_IPSR_MODSEL_DATA(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
635
636 PINMUX_IPSR_DATA(IP0_5_4, A2),
637 PINMUX_IPSR_DATA(IP0_5_4, ST0_SYC),
638 PINMUX_IPSR_MODSEL_DATA(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
639 PINMUX_IPSR_MODSEL_DATA(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
640
641 PINMUX_IPSR_DATA(IP0_7_6, A3),
642 PINMUX_IPSR_DATA(IP0_7_6, ST0_VLD),
643 PINMUX_IPSR_MODSEL_DATA(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
644 PINMUX_IPSR_MODSEL_DATA(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
645
646 PINMUX_IPSR_DATA(IP0_9_8, A4),
647 PINMUX_IPSR_DATA(IP0_9_8, ST0_D0),
648 PINMUX_IPSR_MODSEL_DATA(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
649 PINMUX_IPSR_MODSEL_DATA(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
650
651 PINMUX_IPSR_DATA(IP0_11_10, A5),
652 PINMUX_IPSR_DATA(IP0_11_10, ST0_D1),
653 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
654 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
655
656 PINMUX_IPSR_DATA(IP0_13_12, A6),
657 PINMUX_IPSR_DATA(IP0_13_12, ST0_D2),
658 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
659 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
660
661 PINMUX_IPSR_DATA(IP0_15_14, A7),
662 PINMUX_IPSR_DATA(IP0_15_14, ST0_D3),
663 PINMUX_IPSR_MODSEL_DATA(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
664 PINMUX_IPSR_MODSEL_DATA(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
665
666 PINMUX_IPSR_DATA(IP0_17_16, A8),
667 PINMUX_IPSR_DATA(IP0_17_16, ST0_D4),
668 PINMUX_IPSR_MODSEL_DATA(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
669 PINMUX_IPSR_MODSEL_DATA(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
670
671 PINMUX_IPSR_DATA(IP0_19_18, A9),
672 PINMUX_IPSR_DATA(IP0_19_18, ST0_D5),
673 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
674 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
675
676 PINMUX_IPSR_DATA(IP0_21_20, A10),
677 PINMUX_IPSR_DATA(IP0_21_20, ST0_D6),
678 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
679 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
680
681 PINMUX_IPSR_DATA(IP0_23_22, A11),
682 PINMUX_IPSR_DATA(IP0_23_22, ST0_D7),
683 PINMUX_IPSR_MODSEL_DATA(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
684 PINMUX_IPSR_MODSEL_DATA(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
685
686 PINMUX_IPSR_DATA(IP0_25_24, A12),
687 PINMUX_IPSR_MODSEL_DATA(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
688 PINMUX_IPSR_MODSEL_DATA(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
689
690 PINMUX_IPSR_DATA(IP0_27_26, A13),
691 PINMUX_IPSR_MODSEL_DATA(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
692 PINMUX_IPSR_MODSEL_DATA(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
693
694 PINMUX_IPSR_DATA(IP0_29_28, A14),
695 PINMUX_IPSR_MODSEL_DATA(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
696 PINMUX_IPSR_MODSEL_DATA(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
697
698 PINMUX_IPSR_DATA(IP0_31_30, A15),
699 PINMUX_IPSR_DATA(IP0_31_30, ST0_VCO_CLKIN),
700 PINMUX_IPSR_MODSEL_DATA(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
701 PINMUX_IPSR_MODSEL_DATA(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
702
703
704 /* IPSR1 */
705 PINMUX_IPSR_DATA(IP1_1_0, A16),
706 PINMUX_IPSR_DATA(IP1_1_0, ST0_PWM),
707 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
708 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
709
710 PINMUX_IPSR_DATA(IP1_3_2, A17),
711 PINMUX_IPSR_DATA(IP1_3_2, ST1_VCO_CLKIN),
712 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
713 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
714
715 PINMUX_IPSR_DATA(IP1_5_4, A18),
716 PINMUX_IPSR_DATA(IP1_5_4, ST1_PWM),
717 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
718 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
719
720 PINMUX_IPSR_DATA(IP1_7_6, A19),
721 PINMUX_IPSR_DATA(IP1_7_6, ST1_CLKIN),
722 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
723 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
724
725 PINMUX_IPSR_DATA(IP1_9_8, A20),
726 PINMUX_IPSR_DATA(IP1_9_8, ST1_REQ),
727 PINMUX_IPSR_MODSEL_DATA(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
728
729 PINMUX_IPSR_DATA(IP1_11_10, A21),
730 PINMUX_IPSR_DATA(IP1_11_10, ST1_SYC),
731 PINMUX_IPSR_MODSEL_DATA(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
732
733 PINMUX_IPSR_DATA(IP1_13_12, A22),
734 PINMUX_IPSR_DATA(IP1_13_12, ST1_VLD),
735 PINMUX_IPSR_MODSEL_DATA(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
736
737 PINMUX_IPSR_DATA(IP1_15_14, A23),
738 PINMUX_IPSR_DATA(IP1_15_14, ST1_D0),
739 PINMUX_IPSR_MODSEL_DATA(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
740
741 PINMUX_IPSR_DATA(IP1_17_16, A24),
742 PINMUX_IPSR_MODSEL_DATA(IP1_17_16, RX2_D, SEL_SCIF2_3),
743 PINMUX_IPSR_DATA(IP1_17_16, ST1_D1),
744
745 PINMUX_IPSR_DATA(IP1_19_18, A25),
746 PINMUX_IPSR_MODSEL_DATA(IP1_17_16, RX2_D, SEL_SCIF2_3),
747 PINMUX_IPSR_DATA(IP1_17_16, ST1_D2),
748
749 PINMUX_IPSR_DATA(IP1_22_20, D0),
750 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
751 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, MMC_D0_A, SEL_MMC_0),
752 PINMUX_IPSR_DATA(IP1_22_20, ST1_D3),
753 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, FD0_A, SEL_FLCTL_0),
754
755 PINMUX_IPSR_DATA(IP1_25_23, D1),
756 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
757 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, MMC_D1_A, SEL_MMC_0),
758 PINMUX_IPSR_DATA(IP1_25_23, ST1_D4),
759 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FD1_A, SEL_FLCTL_0),
760
761 PINMUX_IPSR_DATA(IP1_28_26, D2),
762 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
763 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, MMC_D2_A, SEL_MMC_0),
764 PINMUX_IPSR_DATA(IP1_28_26, ST1_D5),
765 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, FD2_A, SEL_FLCTL_0),
766
767 PINMUX_IPSR_DATA(IP1_31_29, D3),
768 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
769 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, MMC_D3_A, SEL_MMC_0),
770 PINMUX_IPSR_DATA(IP1_31_29, ST1_D6),
771 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, FD3_A, SEL_FLCTL_0),
772
773 /* IPSR2 */
774 PINMUX_IPSR_DATA(IP2_2_0, D4),
775 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
776 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MMC_D4_A, SEL_MMC_0),
777 PINMUX_IPSR_DATA(IP2_2_0, ST1_D7),
778 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, FD4_A, SEL_FLCTL_0),
779
780 PINMUX_IPSR_DATA(IP2_4_3, D5),
781 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
782 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, MMC_D5_A, SEL_MMC_0),
783 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, FD5_A, SEL_FLCTL_0),
784
785 PINMUX_IPSR_DATA(IP2_7_5, D6),
786 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
787 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, MMC_D6_A, SEL_MMC_0),
788 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
789 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, FD6_A, SEL_FLCTL_0),
790
791 PINMUX_IPSR_DATA(IP2_10_8, D7),
792 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
793 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, MMC_D7_A, SEL_MMC_0),
794 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, QSSL_A, SEL_RQSPI_0),
795 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, FD7_A, SEL_FLCTL_0),
796
797 PINMUX_IPSR_DATA(IP2_13_11, D8),
798 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
799 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
800 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, QIO2_A, SEL_RQSPI_0),
801 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, FCE_A, SEL_FLCTL_0),
802 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
803
804 PINMUX_IPSR_DATA(IP2_16_14, D9),
805 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
806 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
807 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, QIO3_A, SEL_RQSPI_0),
808 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, FCLE_A, SEL_FLCTL_0),
809 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
810
811 PINMUX_IPSR_DATA(IP2_19_17, D10),
812 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
813 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
814 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, FALE_A, SEL_FLCTL_0),
815 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
816
817 PINMUX_IPSR_DATA(IP2_22_20, D11),
818 PINMUX_IPSR_MODSEL_DATA(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
819 PINMUX_IPSR_MODSEL_DATA(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
820 PINMUX_IPSR_MODSEL_DATA(IP2_22_20, FRE_A, SEL_FLCTL_0),
821
822 PINMUX_IPSR_DATA(IP2_24_23, D12),
823 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, FWE_A, SEL_FLCTL_0),
824 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
825
826 PINMUX_IPSR_DATA(IP2_27_25, D13),
827 PINMUX_IPSR_MODSEL_DATA(IP2_27_25, RX2_B, SEL_SCIF2_1),
828 PINMUX_IPSR_MODSEL_DATA(IP2_27_25, FRB_A, SEL_FLCTL_0),
829 PINMUX_IPSR_MODSEL_DATA(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
830
831 PINMUX_IPSR_DATA(IP2_30_28, D14),
832 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, TX2_B, SEL_SCIF2_1),
833 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, FSE_A, SEL_FLCTL_0),
834 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
835
836 /* IPSR3 */
837 PINMUX_IPSR_DATA(IP3_1_0, D15),
838 PINMUX_IPSR_MODSEL_DATA(IP3_1_0, SCK2_B, SEL_SCIF2_1),
839
840 PINMUX_IPSR_DATA(IP3_2, CS1_A26),
841 PINMUX_IPSR_MODSEL_DATA(IP3_2, QIO3_B, SEL_RQSPI_1),
842
843 PINMUX_IPSR_DATA(IP3_5_3, EX_CS1),
844 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, RX3_B, SEL_SCIF2_1),
845 PINMUX_IPSR_DATA(IP3_5_3, ATACS0),
846 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, QIO2_B, SEL_RQSPI_1),
847 PINMUX_IPSR_DATA(IP3_5_3, ET0_ETXD0),
848
849 PINMUX_IPSR_DATA(IP3_8_6, EX_CS2),
850 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, TX3_B, SEL_SCIF3_1),
851 PINMUX_IPSR_DATA(IP3_8_6, ATACS1),
852 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
853 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
854
855 PINMUX_IPSR_DATA(IP3_11_9, EX_CS3),
856 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
857 PINMUX_IPSR_DATA(IP3_11_9, ATARD),
858 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
859 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
860
861 PINMUX_IPSR_DATA(IP3_14_12, EX_CS4),
862 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
863 PINMUX_IPSR_DATA(IP3_14_12, ATAWR),
864 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
865 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
866
867 PINMUX_IPSR_DATA(IP3_17_15, EX_CS5),
868 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
869 PINMUX_IPSR_DATA(IP3_17_15, ATADIR),
870 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, QSSL_B, SEL_RQSPI_1),
871 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
872
873 PINMUX_IPSR_DATA(IP3_19_18, RD_WR),
874 PINMUX_IPSR_DATA(IP3_19_18, TCLK0),
875 PINMUX_IPSR_MODSEL_DATA(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
876 PINMUX_IPSR_DATA(IP3_19_18, ET0_ETXD4),
877
878 PINMUX_IPSR_DATA(IP3_20, EX_WAIT0),
879 PINMUX_IPSR_MODSEL_DATA(IP3_20, TCLK1_B, SEL_TMU_1),
880
881 PINMUX_IPSR_DATA(IP3_23_21, EX_WAIT1),
882 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
883 PINMUX_IPSR_DATA(IP3_23_21, DREQ2),
884 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
885 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
886 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
887
888 PINMUX_IPSR_DATA(IP3_26_24, EX_WAIT2),
889 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
890 PINMUX_IPSR_DATA(IP3_26_24, DACK2),
891 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
892 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
893 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
894
895 PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
896 PINMUX_IPSR_MODSEL_DATA(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
897 PINMUX_IPSR_DATA(IP3_29_27, ATAG),
898 PINMUX_IPSR_MODSEL_DATA(IP3_29_27, TCLK1_A, SEL_TMU_0),
899 PINMUX_IPSR_DATA(IP3_29_27, ET0_ETXD7),
900
901 /* IPSR4 */
902 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
903 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, CTS1_A, SEL_SCIF1_0),
904 PINMUX_IPSR_DATA(IP4_2_0, VI0_FIELD),
905 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
906 PINMUX_IPSR_DATA(IP4_2_0, ET0_ERXD7),
907
908 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
909 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, RTS1_A, SEL_SCIF1_0),
910 PINMUX_IPSR_DATA(IP4_5_3, VI0_HSYNC),
911 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
912 PINMUX_IPSR_DATA(IP4_5_3, ET0_RX_DV),
913
914 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
915 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, SCK1_A, SEL_SCIF1_0),
916 PINMUX_IPSR_DATA(IP4_8_6, VI0_VSYNC),
917 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
918 PINMUX_IPSR_DATA(IP4_8_6, ET0_RX_ER),
919
920 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, HRX0_A, SEL_HSCIF_0),
921 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, RX1_A, SEL_SCIF1_0),
922 PINMUX_IPSR_DATA(IP4_11_9, VI0_DATA0_VI0_B0),
923 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
924 PINMUX_IPSR_DATA(IP4_11_9, ET0_CRS),
925
926 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, HTX0_A, SEL_HSCIF_0),
927 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, TX1_A, SEL_SCIF1_0),
928 PINMUX_IPSR_DATA(IP4_14_12, VI0_DATA1_VI0_B1),
929 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
930 PINMUX_IPSR_DATA(IP4_14_12, ET0_COL),
931
932 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, CTS0_B, SEL_SCIF0_1),
933 PINMUX_IPSR_DATA(IP4_17_15, VI0_DATA2_VI0_B2),
934 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
935 PINMUX_IPSR_DATA(IP4_17_15, ET0_MDC),
936
937 PINMUX_IPSR_MODSEL_DATA(IP4_19_18, RTS0_B, SEL_SCIF0_1),
938 PINMUX_IPSR_DATA(IP4_19_18, VI0_DATA3_VI0_B3),
939 PINMUX_IPSR_MODSEL_DATA(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
940
941 PINMUX_IPSR_MODSEL_DATA(IP4_21_20, SCK1_B, SEL_SCIF1_1),
942 PINMUX_IPSR_DATA(IP4_21_20, VI0_DATA4_VI0_B4),
943 PINMUX_IPSR_MODSEL_DATA(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
944
945 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, RX1_B, SEL_SCIF1_1),
946 PINMUX_IPSR_DATA(IP4_23_22, VI0_DATA5_VI0_B5),
947 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
948
949 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, TX1_B, SEL_SCIF1_1),
950 PINMUX_IPSR_DATA(IP4_25_24, VI0_DATA6_VI0_G0),
951 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
952
953 PINMUX_IPSR_MODSEL_DATA(IP4_27_26, CTS1_B, SEL_SCIF1_1),
954 PINMUX_IPSR_DATA(IP4_27_26, VI0_DATA7_VI0_G1),
955
956 PINMUX_IPSR_MODSEL_DATA(IP4_29_28, RTS1_B, SEL_SCIF1_1),
957 PINMUX_IPSR_DATA(IP4_29_28, VI0_G2),
958
959 PINMUX_IPSR_MODSEL_DATA(IP4_31_30, SCK2_A, SEL_SCIF2_0),
960 PINMUX_IPSR_DATA(IP4_31_30, VI0_G3),
961
962 /* IPSR5 */
963 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
964 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX2_A, SEL_SCIF2_0),
965 PINMUX_IPSR_DATA(IP5_2_0, VI0_G4),
966 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
967
968 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
969 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TX2_A, SEL_SCIF2_0),
970 PINMUX_IPSR_DATA(IP5_5_3, VI0_G5),
971 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
972
973 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
974 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, RX3_A, SEL_SCIF3_0),
975 PINMUX_IPSR_DATA(IP4_8_6, VI0_R0),
976 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
977
978 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
979 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, TX3_A, SEL_SCIF3_0),
980 PINMUX_IPSR_DATA(IP5_11_9, VI0_R1),
981 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
982
983 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
984 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, RX4_A, SEL_SCIF4_0),
985 PINMUX_IPSR_DATA(IP5_14_12, VI0_R2),
986 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
987
988 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
989 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, TX4_A, SEL_SCIF4_0),
990 PINMUX_IPSR_DATA(IP5_17_15, VI0_R3),
991 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
992
993 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
994 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, RX5_A, SEL_SCIF5_0),
995 PINMUX_IPSR_DATA(IP5_20_18, VI0_R4),
996 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
997
998 PINMUX_IPSR_MODSEL_DATA(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
999 PINMUX_IPSR_MODSEL_DATA(IP5_22_21, TX5_A, SEL_SCIF5_0),
1000 PINMUX_IPSR_DATA(IP5_22_21, VI0_R5),
1001
1002 PINMUX_IPSR_DATA(IP5_24_23, REF125CK),
1003 PINMUX_IPSR_DATA(IP5_24_23, ADTRG),
1004 PINMUX_IPSR_MODSEL_DATA(IP5_24_23, RX5_C, SEL_SCIF5_2),
1005 PINMUX_IPSR_DATA(IP5_26_25, REF50CK),
1006 PINMUX_IPSR_MODSEL_DATA(IP5_26_25, CTS1_E, SEL_SCIF1_3),
1007 PINMUX_IPSR_MODSEL_DATA(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
1008
1009 /* IPSR6 */
1010 PINMUX_IPSR_DATA(IP6_2_0, DU0_DR0),
1011 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
1012 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, HRX0_D, SEL_HSCIF_3),
1013 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, IETX_A, SEL_IEBUS_0),
1014 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
1015 PINMUX_IPSR_DATA(IP6_2_0, HIFD00),
1016
1017 PINMUX_IPSR_DATA(IP6_5_3, DU0_DR1),
1018 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCK0_B, SEL_SCIF0_1),
1019 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, HTX0_D, SEL_HSCIF_3),
1020 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, IERX_A, SEL_IEBUS_0),
1021 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
1022 PINMUX_IPSR_DATA(IP6_5_3, HIFD01),
1023
1024 PINMUX_IPSR_DATA(IP6_7_6, DU0_DR2),
1025 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, RX0_B, SEL_SCIF0_1),
1026 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
1027 PINMUX_IPSR_DATA(IP6_7_6, HIFD02),
1028
1029 PINMUX_IPSR_DATA(IP6_9_8, DU0_DR3),
1030 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, TX0_B, SEL_SCIF0_1),
1031 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
1032 PINMUX_IPSR_DATA(IP6_9_8, HIFD03),
1033
1034 PINMUX_IPSR_DATA(IP6_11_10, DU0_DR4),
1035 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, CTS0_C, SEL_SCIF0_2),
1036 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
1037 PINMUX_IPSR_DATA(IP6_11_10, HIFD04),
1038
1039 PINMUX_IPSR_DATA(IP6_13_12, DU0_DR5),
1040 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, RTS0_C, SEL_SCIF0_1),
1041 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
1042 PINMUX_IPSR_DATA(IP6_13_12, HIFD05),
1043
1044 PINMUX_IPSR_DATA(IP6_15_14, DU0_DR6),
1045 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCK1_C, SEL_SCIF1_2),
1046 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
1047 PINMUX_IPSR_DATA(IP6_15_14, HIFD06),
1048
1049 PINMUX_IPSR_DATA(IP6_17_16, DU0_DR7),
1050 PINMUX_IPSR_MODSEL_DATA(IP6_17_16, RX1_C, SEL_SCIF1_2),
1051 PINMUX_IPSR_MODSEL_DATA(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
1052 PINMUX_IPSR_DATA(IP6_17_16, HIFD07),
1053
1054 PINMUX_IPSR_DATA(IP6_20_18, DU0_DG0),
1055 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, TX1_C, SEL_SCIF1_2),
1056 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
1057 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, IECLK_A, SEL_IEBUS_0),
1058 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
1059 PINMUX_IPSR_DATA(IP6_20_18, HIFD08),
1060
1061 PINMUX_IPSR_DATA(IP6_23_21, DU0_DG1),
1062 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, CTS1_C, SEL_SCIF1_2),
1063 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
1064 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
1065 PINMUX_IPSR_DATA(IP6_23_21, HIFD09),
1066
1067 /* IPSR7 */
1068 PINMUX_IPSR_DATA(IP7_2_0, DU0_DG2),
1069 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, RTS1_C, SEL_SCIF1_2),
1070 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
1071 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
1072 PINMUX_IPSR_DATA(IP7_2_0, HIFD10),
1073
1074 PINMUX_IPSR_DATA(IP7_5_3, DU0_DG3),
1075 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCK2_C, SEL_SCIF2_2),
1076 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
1077 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
1078 PINMUX_IPSR_DATA(IP7_5_3, HIFD11),
1079
1080 PINMUX_IPSR_DATA(IP7_8_6, DU0_DG4),
1081 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX2_C, SEL_SCIF2_2),
1082 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
1083 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
1084 PINMUX_IPSR_DATA(IP7_8_6, HIFD12),
1085
1086 PINMUX_IPSR_DATA(IP7_11_9, DU0_DG5),
1087 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, TX2_C, SEL_SCIF2_2),
1088 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
1089 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
1090 PINMUX_IPSR_DATA(IP7_11_9, HIFD13),
1091
1092 PINMUX_IPSR_DATA(IP7_14_12, DU0_DG6),
1093 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, RX3_C, SEL_SCIF3_2),
1094 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
1095 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
1096 PINMUX_IPSR_DATA(IP7_14_12, HIFD14),
1097
1098 PINMUX_IPSR_DATA(IP7_17_15, DU0_DG7),
1099 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, TX3_C, SEL_SCIF3_2),
1100 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
1101 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
1102 PINMUX_IPSR_DATA(IP7_17_15, HIFD15),
1103
1104 PINMUX_IPSR_DATA(IP7_20_18, DU0_DB0),
1105 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, RX4_C, SEL_SCIF4_2),
1106 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
1107 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
1108 PINMUX_IPSR_DATA(IP7_20_18, HIFCS),
1109
1110 PINMUX_IPSR_DATA(IP7_23_21, DU0_DB1),
1111 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX4_C, SEL_SCIF4_2),
1112 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
1113 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
1114 PINMUX_IPSR_DATA(IP7_23_21, HIFWR),
1115
1116 PINMUX_IPSR_DATA(IP7_26_24, DU0_DB2),
1117 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX5_B, SEL_SCIF5_1),
1118 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
1119 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
1120
1121 PINMUX_IPSR_DATA(IP7_28_27, DU0_DB3),
1122 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, TX5_B, SEL_SCIF5_1),
1123 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
1124 PINMUX_IPSR_DATA(IP7_28_27, HIFRD),
1125
1126 PINMUX_IPSR_DATA(IP7_30_29, DU0_DB4),
1127 PINMUX_IPSR_DATA(IP7_30_29, HIFINT),
1128
1129 /* IPSR8 */
1130 PINMUX_IPSR_DATA(IP8_1_0, DU0_DB5),
1131 PINMUX_IPSR_DATA(IP8_1_0, HIFDREQ),
1132
1133 PINMUX_IPSR_DATA(IP8_3_2, DU0_DB6),
1134 PINMUX_IPSR_DATA(IP8_3_2, HIFRDY),
1135
1136 PINMUX_IPSR_DATA(IP8_5_4, DU0_DB7),
1137 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
1138 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, HIFEBL_B, SEL_HIF_1),
1139
1140 PINMUX_IPSR_DATA(IP8_7_6, DU0_DOTCLKIN),
1141 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
1142 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
1143
1144 PINMUX_IPSR_DATA(IP8_9_8, DU0_DOTCLKOUT),
1145 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
1146 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
1147
1148 PINMUX_IPSR_DATA(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
1149 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
1150 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
1151
1152 PINMUX_IPSR_DATA(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
1153 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
1154 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
1155
1156 PINMUX_IPSR_DATA(IP8_15_14, DU0_EXODDF_DU0_ODDF),
1157 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
1158 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
1159 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
1160
1161 PINMUX_IPSR_DATA(IP8_17_16, DU0_DISP),
1162 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
1163 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, HRX0_B, SEL_HSCIF_1),
1164 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
1165
1166 PINMUX_IPSR_DATA(IP8_19_18, DU0_CDE),
1167 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, HTX0_B, SEL_HSCIF_1),
1168 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
1169 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
1170
1171 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, IRQ0_A, SEL_INTC_0),
1172 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
1173 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, RX3_E, SEL_SCIF3_4),
1174 PINMUX_IPSR_DATA(IP8_22_20, ET0_ERXD0),
1175
1176 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, IRQ1_A, SEL_INTC_0),
1177 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
1178 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TX3_E, SEL_SCIF3_4),
1179 PINMUX_IPSR_DATA(IP8_25_23, ET0_ERXD1),
1180
1181 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, IRQ2_A, SEL_INTC_0),
1182 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CTS0_A, SEL_SCIF0_0),
1183 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, HCTS0_B, SEL_HSCIF_1),
1184 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0),
1185
1186 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, IRQ3_A, SEL_INTC_0),
1187 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, RTS0_A, SEL_SCIF0_0),
1188 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, HRTS0_B, SEL_HSCIF_1),
1189 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0),
1190
1191 /* IPSR9 */
1192 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_CLK_A, SEL_VIN1_0),
1193 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, FD0_B, SEL_FLCTL_1),
1194 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1),
1195
1196 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_0_A, SEL_VIN1_0),
1197 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, FD1_B, SEL_FLCTL_1),
1198 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1),
1199
1200 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_1_A, SEL_VIN1_0),
1201 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, FD2_B, SEL_FLCTL_1),
1202 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1),
1203
1204 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_2_A, SEL_VIN1_0),
1205 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, FD3_B, SEL_FLCTL_1),
1206 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1),
1207
1208 PINMUX_IPSR_MODSEL_DATA(IP9_9_8, VI1_3_A, SEL_VIN1_0),
1209 PINMUX_IPSR_MODSEL_DATA(IP9_9_8, FD4_B, SEL_FLCTL_1),
1210 PINMUX_IPSR_MODSEL_DATA(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1),
1211
1212 PINMUX_IPSR_MODSEL_DATA(IP9_11_10, VI1_4_A, SEL_VIN1_0),
1213 PINMUX_IPSR_MODSEL_DATA(IP9_11_10, FD5_B, SEL_FLCTL_1),
1214 PINMUX_IPSR_MODSEL_DATA(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1),
1215
1216 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, VI1_5_A, SEL_VIN1_0),
1217 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, FD6_B, SEL_FLCTL_1),
1218 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1),
1219
1220 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, VI1_6_A, SEL_VIN1_0),
1221 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, FD7_B, SEL_FLCTL_1),
1222 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1),
1223
1224 PINMUX_IPSR_MODSEL_DATA(IP9_17_16, VI1_7_A, SEL_VIN1_0),
1225 PINMUX_IPSR_MODSEL_DATA(IP9_17_16, FCE_B, SEL_FLCTL_1),
1226 PINMUX_IPSR_MODSEL_DATA(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1),
1227
1228 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0),
1229 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1),
1230 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1),
1231
1232 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SSI_WS0_A, SEL_SSI0_0),
1233 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1),
1234 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1),
1235
1236 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0),
1237 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, VI1_0_B, SEL_VIN1_1),
1238 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1),
1239 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1),
1240
1241 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0),
1242 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, VI1_1_B, SEL_VIN1_1),
1243 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1),
1244 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1),
1245
1246 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SSI_WS1_A, SEL_SSI1_0),
1247 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, VI1_2_B, SEL_VIN1_1),
1248 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1),
1249
1250 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0),
1251 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, VI1_3_B, SEL_VIN1_1),
1252 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
1253
1254 /* IPSE10 */
1255 PINMUX_IPSR_DATA(IP10_2_0, SSI_SCK23),
1256 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, VI1_4_B, SEL_VIN1_1),
1257 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, RX1_D, SEL_SCIF1_3),
1258 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, FCLE_B, SEL_FLCTL_1),
1259 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
1260
1261 PINMUX_IPSR_DATA(IP10_5_3, SSI_WS23),
1262 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, VI1_5_B, SEL_VIN1_1),
1263 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, TX1_D, SEL_SCIF1_3),
1264 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
1265 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, FALE_B, SEL_FLCTL_1),
1266 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
1267
1268 PINMUX_IPSR_DATA(IP10_8_6, SSI_SDATA2),
1269 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, VI1_6_B, SEL_VIN1_1),
1270 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX0_C, SEL_HSCIF_2),
1271 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, FRE_B, SEL_FLCTL_1),
1272 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
1273
1274 PINMUX_IPSR_DATA(IP10_11_9, SSI_SDATA3),
1275 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, VI1_7_B, SEL_VIN1_1),
1276 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX0_C, SEL_HSCIF_2),
1277 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, FWE_B, SEL_FLCTL_1),
1278 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, LCD_CL2_B, SEL_LCDC_1),
1279
1280 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0),
1281 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, VI1_CLK_B, SEL_VIN1_1),
1282 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCK1_D, SEL_SCIF1_3),
1283 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, IECLK_B, SEL_IEBUS_1),
1284 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, LCD_FLM_B, SEL_LCDC_1),
1285
1286 PINMUX_IPSR_MODSEL_DATA(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
1287 PINMUX_IPSR_MODSEL_DATA(IP10_15, LCD_CLK_B, SEL_LCDC_1),
1288
1289 PINMUX_IPSR_DATA(IP10_18_16, AUDIO_CLKC),
1290 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, SCK1_E, SEL_SCIF1_4),
1291 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
1292 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, FRB_B, SEL_FLCTL_1),
1293 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
1294
1295 PINMUX_IPSR_DATA(IP10_21_19, AUDIO_CLKOUT),
1296 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TX1_E, SEL_SCIF1_4),
1297 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
1298 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, FSE_B, SEL_FLCTL_1),
1299 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1),
1300
1301 PINMUX_IPSR_MODSEL_DATA(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0),
1302 PINMUX_IPSR_MODSEL_DATA(IP10_22, RX4_D, SEL_SCIF4_3),
1303
1304 PINMUX_IPSR_MODSEL_DATA(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
1305 PINMUX_IPSR_MODSEL_DATA(IP10_24_23, TX4_D, SEL_SCIF4_3),
1306 PINMUX_IPSR_DATA(IP10_24_23, MLB_CLK),
1307
1308 PINMUX_IPSR_MODSEL_DATA(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
1309 PINMUX_IPSR_MODSEL_DATA(IP10_25, IRQ1_B, SEL_INTC_1),
1310
1311 PINMUX_IPSR_MODSEL_DATA(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
1312 PINMUX_IPSR_MODSEL_DATA(IP10_27_26, IRQ0_B, SEL_INTC_1),
1313 PINMUX_IPSR_DATA(IP10_27_26, MLB_SIG),
1314
1315 PINMUX_IPSR_MODSEL_DATA(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
1316 PINMUX_IPSR_MODSEL_DATA(IP10_29_28, TX5_C, SEL_SCIF1_2),
1317 PINMUX_IPSR_DATA(IP10_29_28, MLB_DAT),
1318
1319 /* IPSR11 */
1320 PINMUX_IPSR_DATA(IP11_0, SCL1),
1321 PINMUX_IPSR_MODSEL_DATA(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
1322
1323 PINMUX_IPSR_DATA(IP11_1, SDA1),
1324 PINMUX_IPSR_MODSEL_DATA(IP11_0, RX1_E, SEL_SCIF1_4),
1325
1326 PINMUX_IPSR_DATA(IP11_2, SDA0),
1327 PINMUX_IPSR_MODSEL_DATA(IP11_2, HIFEBL_A, SEL_HIF_0),
1328
1329 PINMUX_IPSR_DATA(IP11_3, SDSELF),
1330 PINMUX_IPSR_MODSEL_DATA(IP11_3, RTS1_E, SEL_SCIF1_3),
1331
1332 PINMUX_IPSR_MODSEL_DATA(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
1333 PINMUX_IPSR_MODSEL_DATA(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
1334 PINMUX_IPSR_DATA(IP11_6_4, VI0_CLK),
1335 PINMUX_IPSR_MODSEL_DATA(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
1336 PINMUX_IPSR_DATA(IP11_6_4, ET0_ERXD4),
1337
1338 PINMUX_IPSR_MODSEL_DATA(IP11_9_7, SCK0_A, SEL_SCIF0_0),
1339 PINMUX_IPSR_MODSEL_DATA(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
1340 PINMUX_IPSR_DATA(IP11_9_7, VI0_CLKENB),
1341 PINMUX_IPSR_MODSEL_DATA(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
1342 PINMUX_IPSR_DATA(IP11_9_7, ET0_ERXD5),
1343
1344 PINMUX_IPSR_MODSEL_DATA(IP11_11_10, RX0_A, SEL_SCIF0_0),
1345 PINMUX_IPSR_MODSEL_DATA(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
1346 PINMUX_IPSR_MODSEL_DATA(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
1347 PINMUX_IPSR_DATA(IP11_11_10, ET0_ERXD6),
1348
1349 PINMUX_IPSR_MODSEL_DATA(IP11_12, TX0_A, SEL_SCIF0_0),
1350 PINMUX_IPSR_MODSEL_DATA(IP11_12, HSPI_TX_A, SEL_HSPI_0),
1351
1352 PINMUX_IPSR_DATA(IP11_15_13, PENC1),
1353 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, TX3_D, SEL_SCIF3_3),
1354 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1),
1355 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, TX5_D, SEL_SCIF5_3),
1356 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, IETX_B, SEL_IEBUS_1),
1357
1358 PINMUX_IPSR_DATA(IP11_18_16, USB_OVC1),
1359 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, RX3_D, SEL_SCIF3_3),
1360 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
1361 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, RX5_D, SEL_SCIF5_3),
1362 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, IERX_B, SEL_IEBUS_1),
1363
1364 PINMUX_IPSR_DATA(IP11_20_19, DREQ0),
1365 PINMUX_IPSR_MODSEL_DATA(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
1366 PINMUX_IPSR_DATA(IP11_20_19, ET0_TX_EN),
1367
1368 PINMUX_IPSR_DATA(IP11_22_21, DACK0),
1369 PINMUX_IPSR_MODSEL_DATA(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
1370 PINMUX_IPSR_DATA(IP11_22_21, ET0_TX_ER),
1371
1372 PINMUX_IPSR_DATA(IP11_25_23, DREQ1),
1373 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
1374 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, RX4_B, SEL_SCIF4_1),
1375 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
1376 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
1377
1378 PINMUX_IPSR_DATA(IP11_27_26, DACK1),
1379 PINMUX_IPSR_MODSEL_DATA(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
1380 PINMUX_IPSR_MODSEL_DATA(IP11_27_26, TX4_B, SEL_SCIF3_1),
1381 PINMUX_IPSR_MODSEL_DATA(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
1382
1383 PINMUX_IPSR_DATA(IP11_28, PRESETOUT),
1384 PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
1385};
1386
1387static struct pinmux_gpio pinmux_gpios[] = {
1388 PINMUX_GPIO_GP_ALL(),
1389
1390 GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
1391 GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
1392 GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
1393 GPIO_FN(IRQ2_B), GPIO_FN(IRQ3_B),
1394
1395 /* IPSR0 */
1396 GPIO_FN(A0), GPIO_FN(ST0_CLKIN), GPIO_FN(LCD_DATA0_A),
1397 GPIO_FN(TCLKA_C),
1398 GPIO_FN(A1), GPIO_FN(ST0_REQ), GPIO_FN(LCD_DATA1_A),
1399 GPIO_FN(TCLKB_C),
1400 GPIO_FN(A2), GPIO_FN(ST0_SYC), GPIO_FN(LCD_DATA2_A),
1401 GPIO_FN(TCLKC_C),
1402 GPIO_FN(A3), GPIO_FN(ST0_VLD), GPIO_FN(LCD_DATA3_A),
1403 GPIO_FN(TCLKD_C),
1404 GPIO_FN(A4), GPIO_FN(ST0_D0), GPIO_FN(LCD_DATA4_A),
1405 GPIO_FN(TIOC0A_C),
1406 GPIO_FN(A5), GPIO_FN(ST0_D1), GPIO_FN(LCD_DATA5_A),
1407 GPIO_FN(TIOC0B_C),
1408 GPIO_FN(A6), GPIO_FN(ST0_D2), GPIO_FN(LCD_DATA6_A),
1409 GPIO_FN(TIOC0C_C),
1410 GPIO_FN(A7), GPIO_FN(ST0_D3), GPIO_FN(LCD_DATA7_A),
1411 GPIO_FN(TIOC0D_C),
1412 GPIO_FN(A8), GPIO_FN(ST0_D4), GPIO_FN(LCD_DATA8_A),
1413 GPIO_FN(TIOC1A_C),
1414 GPIO_FN(A9), GPIO_FN(ST0_D5), GPIO_FN(LCD_DATA9_A),
1415 GPIO_FN(TIOC1B_C),
1416 GPIO_FN(A10), GPIO_FN(ST0_D6), GPIO_FN(LCD_DATA10_A),
1417 GPIO_FN(TIOC2A_C),
1418 GPIO_FN(A11), GPIO_FN(ST0_D7), GPIO_FN(LCD_DATA11_A),
1419 GPIO_FN(TIOC2B_C),
1420 GPIO_FN(A12), GPIO_FN(LCD_DATA12_A), GPIO_FN(TIOC3A_C),
1421 GPIO_FN(A13), GPIO_FN(LCD_DATA13_A), GPIO_FN(TIOC3B_C),
1422 GPIO_FN(A14), GPIO_FN(LCD_DATA14_A), GPIO_FN(TIOC3C_C),
1423 GPIO_FN(A15), GPIO_FN(ST0_VCO_CLKIN), GPIO_FN(LCD_DATA15_A),
1424 GPIO_FN(TIOC3D_C),
1425
1426 /* IPSR1 */
1427 GPIO_FN(A16), GPIO_FN(ST0_PWM), GPIO_FN(LCD_DON_A),
1428 GPIO_FN(TIOC4A_C),
1429 GPIO_FN(A17), GPIO_FN(ST1_VCO_CLKIN), GPIO_FN(LCD_CL1_A),
1430 GPIO_FN(TIOC4B_C),
1431 GPIO_FN(A18), GPIO_FN(ST1_PWM), GPIO_FN(LCD_CL2_A),
1432 GPIO_FN(TIOC4C_C),
1433 GPIO_FN(A19), GPIO_FN(ST1_CLKIN), GPIO_FN(LCD_CLK_A),
1434 GPIO_FN(TIOC4D_C),
1435 GPIO_FN(A20), GPIO_FN(ST1_REQ), GPIO_FN(LCD_FLM_A),
1436 GPIO_FN(A21), GPIO_FN(ST1_SYC), GPIO_FN(LCD_VCPWC_A),
1437 GPIO_FN(A22), GPIO_FN(ST1_VLD), GPIO_FN(LCD_VEPWC_A),
1438 GPIO_FN(A23), GPIO_FN(ST1_D0), GPIO_FN(LCD_M_DISP_A),
1439 GPIO_FN(A24), GPIO_FN(RX2_D), GPIO_FN(ST1_D1),
1440 GPIO_FN(A25), GPIO_FN(TX2_D), GPIO_FN(ST1_D2),
1441 GPIO_FN(D0), GPIO_FN(SD0_DAT0_A), GPIO_FN(MMC_D0_A),
1442 GPIO_FN(ST1_D3), GPIO_FN(FD0_A),
1443 GPIO_FN(D1), GPIO_FN(SD0_DAT1_A), GPIO_FN(MMC_D1_A),
1444 GPIO_FN(ST1_D4), GPIO_FN(FD1_A),
1445 GPIO_FN(D2), GPIO_FN(SD0_DAT2_A), GPIO_FN(MMC_D2_A),
1446 GPIO_FN(ST1_D5), GPIO_FN(FD2_A),
1447 GPIO_FN(D3), GPIO_FN(SD0_DAT3_A), GPIO_FN(MMC_D3_A),
1448 GPIO_FN(ST1_D6), GPIO_FN(FD3_A),
1449
1450 /* IPSR2 */
1451 GPIO_FN(D4), GPIO_FN(SD0_CD_A), GPIO_FN(MMC_D4_A), GPIO_FN(ST1_D7),
1452 GPIO_FN(FD4_A),
1453 GPIO_FN(D5), GPIO_FN(SD0_WP_A), GPIO_FN(MMC_D5_A), GPIO_FN(FD5_A),
1454 GPIO_FN(D6), GPIO_FN(RSPI_RSPCK_A), GPIO_FN(MMC_D6_A),
1455 GPIO_FN(QSPCLK_A),
1456 GPIO_FN(FD6_A),
1457 GPIO_FN(D7), GPIO_FN(RSPI_SSL_A), GPIO_FN(MMC_D7_A), GPIO_FN(QSSL_A),
1458 GPIO_FN(FD7_A),
1459 GPIO_FN(D8), GPIO_FN(SD0_CLK_A), GPIO_FN(MMC_CLK_A), GPIO_FN(QIO2_A),
1460 GPIO_FN(FCE_A), GPIO_FN(ET0_GTX_CLK_B),
1461 GPIO_FN(D9), GPIO_FN(SD0_CMD_A), GPIO_FN(MMC_CMD_A), GPIO_FN(QIO3_A),
1462 GPIO_FN(FCLE_A), GPIO_FN(ET0_ETXD1_B),
1463 GPIO_FN(D10), GPIO_FN(RSPI_MOSI_A), GPIO_FN(QMO_QIO0_A),
1464 GPIO_FN(FALE_A), GPIO_FN(ET0_ETXD2_B),
1465 GPIO_FN(D11), GPIO_FN(RSPI_MISO_A), GPIO_FN(QMI_QIO1_A), GPIO_FN(FRE_A),
1466 GPIO_FN(ET0_ETXD3_B),
1467 GPIO_FN(D12), GPIO_FN(FWE_A), GPIO_FN(ET0_ETXD5_B),
1468 GPIO_FN(D13), GPIO_FN(RX2_B), GPIO_FN(FRB_A), GPIO_FN(ET0_ETXD6_B),
1469 GPIO_FN(D14), GPIO_FN(TX2_B), GPIO_FN(FSE_A), GPIO_FN(ET0_TX_CLK_B),
1470
1471 /* IPSR3 */
1472 GPIO_FN(D15), GPIO_FN(SCK2_B),
1473 GPIO_FN(CS1_A26), GPIO_FN(QIO3_B),
1474 GPIO_FN(EX_CS1), GPIO_FN(RX3_B), GPIO_FN(ATACS0), GPIO_FN(QIO2_B),
1475 GPIO_FN(ET0_ETXD0),
1476 GPIO_FN(EX_CS2), GPIO_FN(TX3_B), GPIO_FN(ATACS1), GPIO_FN(QSPCLK_B),
1477 GPIO_FN(ET0_GTX_CLK_A),
1478 GPIO_FN(EX_CS3), GPIO_FN(SD1_CD_A), GPIO_FN(ATARD), GPIO_FN(QMO_QIO0_B),
1479 GPIO_FN(ET0_ETXD1_A),
1480 GPIO_FN(EX_CS4), GPIO_FN(SD1_WP_A), GPIO_FN(ATAWR), GPIO_FN(QMI_QIO1_B),
1481 GPIO_FN(ET0_ETXD2_A),
1482 GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
1483 GPIO_FN(ET0_ETXD3_A),
1484 GPIO_FN(RD_WR), GPIO_FN(TCLK1_B),
1485 GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
1486 GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
1487 GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
1488 GPIO_FN(EX_WAIT2), GPIO_FN(SD1_DAT1_A), GPIO_FN(DACK2),
1489 GPIO_FN(CAN1_RX_C), GPIO_FN(ET0_MAGIC_C), GPIO_FN(ET0_ETXD6_A),
1490 GPIO_FN(DRACK0), GPIO_FN(SD1_DAT2_A), GPIO_FN(ATAG), GPIO_FN(TCLK1_A),
1491 GPIO_FN(ET0_ETXD7),
1492
1493 /* IPSR4 */
1494 GPIO_FN(HCTS0_A), GPIO_FN(CTS1_A), GPIO_FN(VI0_FIELD),
1495 GPIO_FN(RMII0_RXD1_A), GPIO_FN(ET0_ERXD7),
1496 GPIO_FN(HRTS0_A), GPIO_FN(RTS1_A), GPIO_FN(VI0_HSYNC),
1497 GPIO_FN(RMII0_TXD_EN_A), GPIO_FN(ET0_RX_DV),
1498 GPIO_FN(HSCK0_A), GPIO_FN(SCK1_A), GPIO_FN(VI0_VSYNC),
1499 GPIO_FN(RMII0_RX_ER_A), GPIO_FN(ET0_RX_ER),
1500 GPIO_FN(HRX0_A), GPIO_FN(RX1_A), GPIO_FN(VI0_DATA0_VI0_B0),
1501 GPIO_FN(RMII0_CRS_DV_A), GPIO_FN(ET0_CRS),
1502 GPIO_FN(HTX0_A), GPIO_FN(TX1_A), GPIO_FN(VI0_DATA1_VI0_B1),
1503 GPIO_FN(RMII0_MDC_A), GPIO_FN(ET0_COL),
1504 GPIO_FN(CTS0_B), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(RMII0_MDIO_A),
1505 GPIO_FN(ET0_MDC),
1506 GPIO_FN(RTS0_B), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ET0_MDIO_A),
1507 GPIO_FN(SCK1_B), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ET0_LINK_A),
1508 GPIO_FN(RX1_B), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(ET0_MAGIC_A),
1509 GPIO_FN(TX1_B), GPIO_FN(VI0_DATA6_VI0_G0), GPIO_FN(ET0_PHY_INT_A),
1510 GPIO_FN(CTS1_B), GPIO_FN(VI0_DATA7_VI0_G1),
1511 GPIO_FN(RTS1_B), GPIO_FN(VI0_G2),
1512 GPIO_FN(SCK2_A), GPIO_FN(VI0_G3),
1513
1514 /* IPSR5 */
1515 GPIO_FN(REF50CK), GPIO_FN(CTS1_E), GPIO_FN(HCTS0_D),
1516 GPIO_FN(REF125CK), GPIO_FN(ADTRG), GPIO_FN(RX5_C),
1517 GPIO_FN(SD2_WP_A), GPIO_FN(TX5_A), GPIO_FN(VI0_R5),
1518 GPIO_FN(SD2_CD_A), GPIO_FN(RX5_A), GPIO_FN(VI0_R4),
1519 GPIO_FN(ET0_PHY_INT_B),
1520 GPIO_FN(SD2_DAT3_A), GPIO_FN(TX4_A), GPIO_FN(VI0_R3),
1521 GPIO_FN(ET0_MAGIC_B),
1522 GPIO_FN(SD2_DAT2_A), GPIO_FN(RX4_A), GPIO_FN(VI0_R2),
1523 GPIO_FN(ET0_LINK_B),
1524 GPIO_FN(SD2_DAT1_A), GPIO_FN(TX3_A), GPIO_FN(VI0_R1),
1525 GPIO_FN(ET0_MDIO_B),
1526 GPIO_FN(SD2_DAT0_A), GPIO_FN(RX3_A), GPIO_FN(VI0_R0),
1527 GPIO_FN(ET0_ERXD3_B),
1528 GPIO_FN(SD2_CMD_A), GPIO_FN(TX2_A), GPIO_FN(VI0_G5),
1529 GPIO_FN(ET0_ERXD2_B),
1530 GPIO_FN(SD2_CLK_A), GPIO_FN(RX2_A), GPIO_FN(VI0_G4),
1531 GPIO_FN(ET0_RX_CLK_B),
1532
1533 /* IPSR6 */
1534 GPIO_FN(DU0_DG1), GPIO_FN(CTS1_C), GPIO_FN(HRTS0_D),
1535 GPIO_FN(TIOC1B_A), GPIO_FN(HIFD09),
1536 GPIO_FN(DU0_DG0), GPIO_FN(TX1_C), GPIO_FN(HSCK0_D),
1537 GPIO_FN(IECLK_A), GPIO_FN(TIOC1A_A), GPIO_FN(HIFD08),
1538 GPIO_FN(DU0_DR7), GPIO_FN(RX1_C), GPIO_FN(TIOC0D_A),
1539 GPIO_FN(HIFD07),
1540 GPIO_FN(DU0_DR6), GPIO_FN(SCK1_C), GPIO_FN(TIOC0C_A),
1541 GPIO_FN(HIFD06),
1542 GPIO_FN(DU0_DR5), GPIO_FN(RTS0_C), GPIO_FN(TIOC0B_A),
1543 GPIO_FN(HIFD05),
1544 GPIO_FN(DU0_DR4), GPIO_FN(CTS0_C), GPIO_FN(TIOC0A_A),
1545 GPIO_FN(HIFD04),
1546 GPIO_FN(DU0_DR3), GPIO_FN(TX0_B), GPIO_FN(TCLKD_A), GPIO_FN(HIFD03),
1547 GPIO_FN(DU0_DR2), GPIO_FN(RX0_B), GPIO_FN(TCLKC_A), GPIO_FN(HIFD02),
1548 GPIO_FN(DU0_DR1), GPIO_FN(SCK0_B), GPIO_FN(HTX0_D),
1549 GPIO_FN(IERX_A), GPIO_FN(TCLKB_A), GPIO_FN(HIFD01),
1550 GPIO_FN(DU0_DR0), GPIO_FN(SCIF_CLK_B), GPIO_FN(HRX0_D),
1551 GPIO_FN(IETX_A), GPIO_FN(TCLKA_A), GPIO_FN(HIFD00),
1552
1553 /* IPSR7 */
1554 GPIO_FN(DU0_DB4), GPIO_FN(HIFINT),
1555 GPIO_FN(DU0_DB3), GPIO_FN(TX5_B), GPIO_FN(TIOC4D_A), GPIO_FN(HIFRD),
1556 GPIO_FN(DU0_DB2), GPIO_FN(RX5_B), GPIO_FN(RMII0_TXD1_B),
1557 GPIO_FN(TIOC4C_A), GPIO_FN(HIFWR),
1558 GPIO_FN(DU0_DB1), GPIO_FN(TX4_C), GPIO_FN(RMII0_TXD0_B),
1559 GPIO_FN(TIOC4B_A), GPIO_FN(HIFRS),
1560 GPIO_FN(DU0_DB0), GPIO_FN(RX4_C), GPIO_FN(RMII0_TXD_EN_B),
1561 GPIO_FN(TIOC4A_A), GPIO_FN(HIFCS),
1562 GPIO_FN(DU0_DG7), GPIO_FN(TX3_C), GPIO_FN(RMII0_RXD1_B),
1563 GPIO_FN(TIOC3D_A), GPIO_FN(HIFD15),
1564 GPIO_FN(DU0_DG6), GPIO_FN(RX3_C), GPIO_FN(RMII0_RXD0_B),
1565 GPIO_FN(TIOC3C_A), GPIO_FN(HIFD14),
1566 GPIO_FN(DU0_DG5), GPIO_FN(TX2_C), GPIO_FN(RMII0_RX_ER_B),
1567 GPIO_FN(TIOC3B_A), GPIO_FN(HIFD13),
1568 GPIO_FN(DU0_DG4), GPIO_FN(RX2_C), GPIO_FN(RMII0_CRS_DV_B),
1569 GPIO_FN(TIOC3A_A), GPIO_FN(HIFD12),
1570 GPIO_FN(DU0_DG3), GPIO_FN(SCK2_C), GPIO_FN(RMII0_MDIO_B),
1571 GPIO_FN(TIOC2B_A), GPIO_FN(HIFD11),
1572 GPIO_FN(DU0_DG2), GPIO_FN(RTS1_C), GPIO_FN(RMII0_MDC_B),
1573 GPIO_FN(TIOC2A_A), GPIO_FN(HIFD10),
1574
1575 /* IPSR8 */
1576 GPIO_FN(IRQ3_A), GPIO_FN(RTS0_A), GPIO_FN(HRTS0_B),
1577 GPIO_FN(ET0_ERXD3_A),
1578 GPIO_FN(IRQ2_A), GPIO_FN(CTS0_A), GPIO_FN(HCTS0_B),
1579 GPIO_FN(ET0_ERXD2_A),
1580 GPIO_FN(IRQ1_A), GPIO_FN(HSPI_RX_B), GPIO_FN(TX3_E),
1581 GPIO_FN(ET0_ERXD1),
1582 GPIO_FN(IRQ0_A), GPIO_FN(HSPI_TX_B), GPIO_FN(RX3_E),
1583 GPIO_FN(ET0_ERXD0),
1584 GPIO_FN(DU0_CDE), GPIO_FN(HTX0_B), GPIO_FN(AUDIO_CLKB_B),
1585 GPIO_FN(LCD_VCPWC_B),
1586 GPIO_FN(DU0_DISP), GPIO_FN(CAN0_TX_B), GPIO_FN(HRX0_B),
1587 GPIO_FN(AUDIO_CLKA_B),
1588 GPIO_FN(DU0_EXODDF_DU0_ODDF), GPIO_FN(CAN0_RX_B), GPIO_FN(HSCK0_B),
1589 GPIO_FN(SSI_SDATA1_B),
1590 GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(HSPI_RX0_C),
1591 GPIO_FN(SSI_WS1_B),
1592 GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(HSPI_TX0_C),
1593 GPIO_FN(SSI_SCK1_B),
1594 GPIO_FN(DU0_DOTCLKOUT), GPIO_FN(HSPI_CLK0_C),
1595 GPIO_FN(SSI_SDATA0_B),
1596 GPIO_FN(DU0_DOTCLKIN), GPIO_FN(HSPI_CS0_C),
1597 GPIO_FN(SSI_WS0_B),
1598 GPIO_FN(DU0_DB7), GPIO_FN(SSI_SCK0_B), GPIO_FN(HIFEBL_B),
1599 GPIO_FN(DU0_DB6), GPIO_FN(HIFRDY),
1600 GPIO_FN(DU0_DB5), GPIO_FN(HIFDREQ),
1601
1602 /* IPSR9 */
1603 GPIO_FN(SSI_SDATA1_A), GPIO_FN(VI1_3_B), GPIO_FN(LCD_DATA14_B),
1604 GPIO_FN(SSI_WS1_A), GPIO_FN(VI1_2_B), GPIO_FN(LCD_DATA13_B),
1605 GPIO_FN(SSI_SCK1_A), GPIO_FN(VI1_1_B), GPIO_FN(TIOC2B_B),
1606 GPIO_FN(LCD_DATA12_B),
1607 GPIO_FN(SSI_SDATA0_A), GPIO_FN(VI1_0_B), GPIO_FN(TIOC2A_B),
1608 GPIO_FN(LCD_DATA11_B),
1609 GPIO_FN(SSI_WS0_A), GPIO_FN(TIOC1B_B), GPIO_FN(LCD_DATA10_B),
1610 GPIO_FN(SSI_SCK0_A), GPIO_FN(TIOC1A_B), GPIO_FN(LCD_DATA9_B),
1611 GPIO_FN(VI1_7_A), GPIO_FN(FCE_B), GPIO_FN(LCD_DATA8_B),
1612 GPIO_FN(VI1_6_A), GPIO_FN(FD7_B), GPIO_FN(LCD_DATA7_B),
1613 GPIO_FN(VI1_5_A), GPIO_FN(FD6_B), GPIO_FN(LCD_DATA6_B),
1614 GPIO_FN(VI1_4_A), GPIO_FN(FD5_B), GPIO_FN(LCD_DATA5_B),
1615 GPIO_FN(VI1_3_A), GPIO_FN(FD4_B), GPIO_FN(LCD_DATA4_B),
1616 GPIO_FN(VI1_2_A), GPIO_FN(FD3_B), GPIO_FN(LCD_DATA3_B),
1617 GPIO_FN(VI1_1_A), GPIO_FN(FD2_B), GPIO_FN(LCD_DATA2_B),
1618 GPIO_FN(VI1_0_A), GPIO_FN(FD1_B), GPIO_FN(LCD_DATA1_B),
1619 GPIO_FN(VI1_CLK_A), GPIO_FN(FD0_B), GPIO_FN(LCD_DATA0_B),
1620
1621 /* IPSR10 */
1622 GPIO_FN(CAN1_TX_A), GPIO_FN(TX5_C), GPIO_FN(MLB_DAT),
1623 GPIO_FN(CAN0_RX_A), GPIO_FN(IRQ0_B), GPIO_FN(MLB_SIG),
1624 GPIO_FN(CAN1_RX_A), GPIO_FN(IRQ1_B),
1625 GPIO_FN(CAN0_TX_A), GPIO_FN(TX4_D), GPIO_FN(MLB_CLK),
1626 GPIO_FN(CAN_CLK_A), GPIO_FN(RX4_D),
1627 GPIO_FN(AUDIO_CLKOUT), GPIO_FN(TX1_E), GPIO_FN(HRTS0_C),
1628 GPIO_FN(FSE_B), GPIO_FN(LCD_M_DISP_B),
1629 GPIO_FN(AUDIO_CLKC), GPIO_FN(SCK1_E), GPIO_FN(HCTS0_C),
1630 GPIO_FN(FRB_B), GPIO_FN(LCD_VEPWC_B),
1631 GPIO_FN(AUDIO_CLKB_A), GPIO_FN(LCD_CLK_B),
1632 GPIO_FN(AUDIO_CLKA_A), GPIO_FN(VI1_CLK_B), GPIO_FN(SCK1_D),
1633 GPIO_FN(IECLK_B), GPIO_FN(LCD_FLM_B),
1634 GPIO_FN(SSI_SDATA3), GPIO_FN(VI1_7_B), GPIO_FN(HTX0_C),
1635 GPIO_FN(FWE_B), GPIO_FN(LCD_CL2_B),
1636 GPIO_FN(SSI_SDATA2), GPIO_FN(VI1_6_B), GPIO_FN(HRX0_C),
1637 GPIO_FN(FRE_B), GPIO_FN(LCD_CL1_B),
1638 GPIO_FN(SSI_WS23), GPIO_FN(VI1_5_B), GPIO_FN(TX1_D),
1639 GPIO_FN(HSCK0_C), GPIO_FN(FALE_B), GPIO_FN(LCD_DON_B),
1640 GPIO_FN(SSI_SCK23), GPIO_FN(VI1_4_B), GPIO_FN(RX1_D),
1641 GPIO_FN(FCLE_B), GPIO_FN(LCD_DATA15_B),
1642
1643 /* IPSR11 */
1644 GPIO_FN(PRESETOUT), GPIO_FN(ST_CLKOUT),
1645 GPIO_FN(DACK1), GPIO_FN(HSPI_CS_B), GPIO_FN(TX4_B),
1646 GPIO_FN(ET0_RX_CLK_A),
1647 GPIO_FN(DREQ1), GPIO_FN(HSPI_CLK_B), GPIO_FN(RX4_B),
1648 GPIO_FN(ET0_PHY_INT_C), GPIO_FN(ET0_TX_CLK_A),
1649 GPIO_FN(DACK0), GPIO_FN(SD1_DAT3_A), GPIO_FN(ET0_TX_ER),
1650 GPIO_FN(DREQ0), GPIO_FN(SD1_CLK_A), GPIO_FN(ET0_TX_EN),
1651 GPIO_FN(USB_OVC1), GPIO_FN(RX3_D), GPIO_FN(CAN1_RX_B),
1652 GPIO_FN(RX5_D), GPIO_FN(IERX_B),
1653 GPIO_FN(PENC1), GPIO_FN(TX3_D), GPIO_FN(CAN1_TX_B),
1654 GPIO_FN(TX5_D), GPIO_FN(IETX_B),
1655 GPIO_FN(TX0_A), GPIO_FN(HSPI_TX_A),
1656 GPIO_FN(RX0_A), GPIO_FN(HSPI_RX_A), GPIO_FN(RMII0_RXD0_A),
1657 GPIO_FN(ET0_ERXD6),
1658 GPIO_FN(SCK0_A), GPIO_FN(HSPI_CS_A), GPIO_FN(VI0_CLKENB),
1659 GPIO_FN(RMII0_TXD1_A), GPIO_FN(ET0_ERXD5),
1660 GPIO_FN(SCIF_CLK_A), GPIO_FN(HSPI_CLK_A), GPIO_FN(VI0_CLK),
1661 GPIO_FN(RMII0_TXD0_A), GPIO_FN(ET0_ERXD4),
1662 GPIO_FN(SDSELF), GPIO_FN(RTS1_E),
1663 GPIO_FN(SDA0), GPIO_FN(HIFEBL_A),
1664 GPIO_FN(SDA1), GPIO_FN(RX1_E),
1665 GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
1666};
1667
1668static struct pinmux_cfg_reg pinmux_config_regs[] = {
1669 { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) {
1670 GP_0_31_FN, FN_IP2_2_0,
1671 GP_0_30_FN, FN_IP1_31_29,
1672 GP_0_29_FN, FN_IP1_28_26,
1673 GP_0_28_FN, FN_IP1_25_23,
1674 GP_0_27_FN, FN_IP1_22_20,
1675 GP_0_26_FN, FN_IP1_19_18,
1676 GP_0_25_FN, FN_IP1_17_16,
1677 GP_0_24_FN, FN_IP0_5_4,
1678 GP_0_23_FN, FN_IP0_3_2,
1679 GP_0_22_FN, FN_IP0_1_0,
1680 GP_0_21_FN, FN_IP11_28,
1681 GP_0_20_FN, FN_IP1_7_6,
1682 GP_0_19_FN, FN_IP1_5_4,
1683 GP_0_18_FN, FN_IP1_3_2,
1684 GP_0_17_FN, FN_IP1_1_0,
1685 GP_0_16_FN, FN_IP0_31_30,
1686 GP_0_15_FN, FN_IP0_29_28,
1687 GP_0_14_FN, FN_IP0_27_26,
1688 GP_0_13_FN, FN_IP0_25_24,
1689 GP_0_12_FN, FN_IP0_23_22,
1690 GP_0_11_FN, FN_IP0_21_20,
1691 GP_0_10_FN, FN_IP0_19_18,
1692 GP_0_9_FN, FN_IP0_17_16,
1693 GP_0_8_FN, FN_IP0_15_14,
1694 GP_0_7_FN, FN_IP0_13_12,
1695 GP_0_6_FN, FN_IP0_11_10,
1696 GP_0_5_FN, FN_IP0_9_8,
1697 GP_0_4_FN, FN_IP0_7_6,
1698 GP_0_3_FN, FN_IP1_15_14,
1699 GP_0_2_FN, FN_IP1_13_12,
1700 GP_0_1_FN, FN_IP1_11_10,
1701 GP_0_0_FN, FN_IP1_9_8 }
1702 },
1703 { PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1) {
1704 GP_1_31_FN, FN_IP11_25_23,
1705 GP_1_30_FN, FN_IP2_13_11,
1706 GP_1_29_FN, FN_IP2_10_8,
1707 GP_1_28_FN, FN_IP2_7_5,
1708 GP_1_27_FN, FN_IP3_26_24,
1709 GP_1_26_FN, FN_IP3_23_21,
1710 GP_1_25_FN, FN_IP2_4_3,
1711 GP_1_24_FN, FN_WE1,
1712 GP_1_23_FN, FN_WE0,
1713 GP_1_22_FN, FN_IP3_19_18,
1714 GP_1_21_FN, FN_RD,
1715 GP_1_20_FN, FN_IP3_17_15,
1716 GP_1_19_FN, FN_IP3_14_12,
1717 GP_1_18_FN, FN_IP3_11_9,
1718 GP_1_17_FN, FN_IP3_8_6,
1719 GP_1_16_FN, FN_IP3_5_3,
1720 GP_1_15_FN, FN_EX_CS0,
1721 GP_1_14_FN, FN_IP3_2,
1722 GP_1_13_FN, FN_CS0,
1723 GP_1_12_FN, FN_BS,
1724 GP_1_11_FN, FN_CLKOUT,
1725 GP_1_10_FN, FN_IP3_1_0,
1726 GP_1_9_FN, FN_IP2_30_28,
1727 GP_1_8_FN, FN_IP2_27_25,
1728 GP_1_7_FN, FN_IP2_24_23,
1729 GP_1_6_FN, FN_IP2_22_20,
1730 GP_1_5_FN, FN_IP2_19_17,
1731 GP_1_4_FN, FN_IP2_16_14,
1732 GP_1_3_FN, FN_IP11_22_21,
1733 GP_1_2_FN, FN_IP11_20_19,
1734 GP_1_1_FN, FN_IP3_29_27,
1735 GP_1_0_FN, FN_IP3_20 }
1736 },
1737 { PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1) {
1738 GP_2_31_FN, FN_IP4_31_30,
1739 GP_2_30_FN, FN_IP5_2_0,
1740 GP_2_29_FN, FN_IP5_5_3,
1741 GP_2_28_FN, FN_IP5_8_6,
1742 GP_2_27_FN, FN_IP5_11_9,
1743 GP_2_26_FN, FN_IP5_14_12,
1744 GP_2_25_FN, FN_IP5_17_15,
1745 GP_2_24_FN, FN_IP5_20_18,
1746 GP_2_23_FN, FN_IP5_22_21,
1747 GP_2_22_FN, FN_IP5_24_23,
1748 GP_2_21_FN, FN_IP5_26_25,
1749 GP_2_20_FN, FN_IP4_29_28,
1750 GP_2_19_FN, FN_IP4_27_26,
1751 GP_2_18_FN, FN_IP4_25_24,
1752 GP_2_17_FN, FN_IP4_23_22,
1753 GP_2_16_FN, FN_IP4_21_20,
1754 GP_2_15_FN, FN_IP4_19_18,
1755 GP_2_14_FN, FN_IP4_17_15,
1756 GP_2_13_FN, FN_IP4_14_12,
1757 GP_2_12_FN, FN_IP4_11_9,
1758 GP_2_11_FN, FN_IP4_8_6,
1759 GP_2_10_FN, FN_IP4_5_3,
1760 GP_2_9_FN, FN_IP8_27_26,
1761 GP_2_8_FN, FN_IP11_12,
1762 GP_2_7_FN, FN_IP8_25_23,
1763 GP_2_6_FN, FN_IP8_22_20,
1764 GP_2_5_FN, FN_IP11_27_26,
1765 GP_2_4_FN, FN_IP8_29_28,
1766 GP_2_3_FN, FN_IP4_2_0,
1767 GP_2_2_FN, FN_IP11_11_10,
1768 GP_2_1_FN, FN_IP11_9_7,
1769 GP_2_0_FN, FN_IP11_6_4 }
1770 },
1771 { PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1) {
1772 GP_3_31_FN, FN_IP9_1_0,
1773 GP_3_30_FN, FN_IP8_19_18,
1774 GP_3_29_FN, FN_IP8_17_16,
1775 GP_3_28_FN, FN_IP8_15_14,
1776 GP_3_27_FN, FN_IP8_13_12,
1777 GP_3_26_FN, FN_IP8_11_10,
1778 GP_3_25_FN, FN_IP8_9_8,
1779 GP_3_24_FN, FN_IP8_7_6,
1780 GP_3_23_FN, FN_IP8_5_4,
1781 GP_3_22_FN, FN_IP8_3_2,
1782 GP_3_21_FN, FN_IP8_1_0,
1783 GP_3_20_FN, FN_IP7_30_29,
1784 GP_3_19_FN, FN_IP7_28_27,
1785 GP_3_18_FN, FN_IP7_26_24,
1786 GP_3_17_FN, FN_IP7_23_21,
1787 GP_3_16_FN, FN_IP7_20_18,
1788 GP_3_15_FN, FN_IP7_17_15,
1789 GP_3_14_FN, FN_IP7_14_12,
1790 GP_3_13_FN, FN_IP7_11_9,
1791 GP_3_12_FN, FN_IP7_8_6,
1792 GP_3_11_FN, FN_IP7_5_3,
1793 GP_3_10_FN, FN_IP7_2_0,
1794 GP_3_9_FN, FN_IP6_23_21,
1795 GP_3_8_FN, FN_IP6_20_18,
1796 GP_3_7_FN, FN_IP6_17_16,
1797 GP_3_6_FN, FN_IP6_15_14,
1798 GP_3_5_FN, FN_IP6_13_12,
1799 GP_3_4_FN, FN_IP6_11_10,
1800 GP_3_3_FN, FN_IP6_9_8,
1801 GP_3_2_FN, FN_IP6_7_6,
1802 GP_3_1_FN, FN_IP6_5_3,
1803 GP_3_0_FN, FN_IP6_2_0 }
1804 },
1805
1806 { PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1) {
1807 GP_4_31_FN, FN_IP10_24_23,
1808 GP_4_30_FN, FN_IP10_22,
1809 GP_4_29_FN, FN_IP11_18_16,
1810 GP_4_28_FN, FN_USB_OVC0,
1811 GP_4_27_FN, FN_IP11_15_13,
1812 GP_4_26_FN, FN_PENC0,
1813 GP_4_25_FN, FN_IP11_2,
1814 GP_4_24_FN, FN_SCL0,
1815 GP_4_23_FN, FN_IP11_1,
1816 GP_4_22_FN, FN_IP11_0,
1817 GP_4_21_FN, FN_IP10_21_19,
1818 GP_4_20_FN, FN_IP10_18_16,
1819 GP_4_19_FN, FN_IP10_15,
1820 GP_4_18_FN, FN_IP10_14_12,
1821 GP_4_17_FN, FN_IP10_11_9,
1822 GP_4_16_FN, FN_IP10_8_6,
1823 GP_4_15_FN, FN_IP10_5_3,
1824 GP_4_14_FN, FN_IP10_2_0,
1825 GP_4_13_FN, FN_IP9_29_28,
1826 GP_4_12_FN, FN_IP9_27_26,
1827 GP_4_11_FN, FN_IP9_9_8,
1828 GP_4_10_FN, FN_IP9_7_6,
1829 GP_4_9_FN, FN_IP9_5_4,
1830 GP_4_8_FN, FN_IP9_3_2,
1831 GP_4_7_FN, FN_IP9_17_16,
1832 GP_4_6_FN, FN_IP9_15_14,
1833 GP_4_5_FN, FN_IP9_13_12,
1834 GP_4_4_FN, FN_IP9_11_10,
1835 GP_4_3_FN, FN_IP9_25_24,
1836 GP_4_2_FN, FN_IP9_23_22,
1837 GP_4_1_FN, FN_IP9_21_20,
1838 GP_4_0_FN, FN_IP9_19_18 }
1839 },
1840 { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1) {
1841 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */
1842 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */
1843 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */
1844 0, 0, 0, 0, 0, 0, 0, 0, /* 19 - 16 */
1845 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
1846 GP_5_11_FN, FN_IP10_29_28,
1847 GP_5_10_FN, FN_IP10_27_26,
1848 0, 0, 0, 0, 0, 0, 0, 0, /* 9 - 6 */
1849 0, 0, 0, 0, /* 5, 4 */
1850 GP_5_3_FN, FN_IRQ3_B,
1851 GP_5_2_FN, FN_IRQ2_B,
1852 GP_5_1_FN, FN_IP11_3,
1853 GP_5_0_FN, FN_IP10_25 }
1854 },
1855
1856 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1857 2, 2, 2, 2, 2, 2, 2, 2,
1858 2, 2, 2, 2, 2, 2, 2, 2) {
1859 /* IP0_31_30 [2] */
1860 FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A,
1861 FN_TIOC3D_C,
1862 /* IP0_29_28 [2] */
1863 FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C, 0,
1864 /* IP0_27_26 [2] */
1865 FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C, 0,
1866 /* IP0_25_24 [2] */
1867 FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C, 0,
1868 /* IP0_23_22 [2] */
1869 FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
1870 /* IP0_21_20 [2] */
1871 FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
1872 /* IP0_19_18 [2] */
1873 FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
1874 /* IP0_17_16 [2] */
1875 FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
1876 /* IP0_15_14 [2] */
1877 FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
1878 /* IP0_13_12 [2] */
1879 FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
1880 /* IP0_11_10 [2] */
1881 FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
1882 /* IP0_9_8 [2] */
1883 FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
1884 /* IP0_7_6 [2] */
1885 FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
1886 /* IP0_5_4 [2] */
1887 FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
1888 /* IP0_3_2 [2] */
1889 FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
1890 /* IP0_1_0 [2] */
1891 FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C }
1892 },
1893 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1894 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
1895 /* IP1_31_29 [3] */
1896 FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6,
1897 FN_FD3_A, 0, 0, 0,
1898 /* IP1_28_26 [3] */
1899 FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5,
1900 FN_FD2_A, 0, 0, 0,
1901 /* IP1_25_23 [3] */
1902 FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4,
1903 FN_FD1_A, 0, 0, 0,
1904 /* IP1_22_20 [3] */
1905 FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3,
1906 FN_FD0_A, 0, 0, 0,
1907 /* IP1_19_18 [2] */
1908 FN_A25, FN_TX2_D, FN_ST1_D2, 0,
1909 /* IP1_17_16 [2] */
1910 FN_A24, FN_RX2_D, FN_ST1_D1, 0,
1911 /* IP1_15_14 [2] */
1912 FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A, 0,
1913 /* IP1_13_12 [2] */
1914 FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A, 0,
1915 /* IP1_11_10 [2] */
1916 FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A, 0,
1917 /* IP1_9_8 [2] */
1918 FN_A20, FN_ST1_REQ, FN_LCD_FLM_A, 0,
1919 /* IP1_7_6 [2] */
1920 FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C,
1921 /* IP1_5_4 [2] */
1922 FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
1923 /* IP1_3_2 [2] */
1924 FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
1925 /* IP1_1_0 [2] */
1926 FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C }
1927 },
1928 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1929 1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3) {
1930 /* IP2_31 [1] */
1931 0, 0,
1932 /* IP2_30_28 [3] */
1933 FN_D14, FN_TX2_B, 0, FN_FSE_A,
1934 FN_ET0_TX_CLK_B, 0, 0, 0,
1935 /* IP2_27_25 [3] */
1936 FN_D13, FN_RX2_B, 0, FN_FRB_A,
1937 FN_ET0_ETXD6_B, 0, 0, 0,
1938 /* IP2_24_23 [2] */
1939 FN_D12, 0, FN_FWE_A, FN_ET0_ETXD5_B,
1940 /* IP2_22_20 [3] */
1941 FN_D11, FN_RSPI_MISO_A, 0, FN_QMI_QIO1_A,
1942 FN_FRE_A, FN_ET0_ETXD3_B, 0, 0,
1943 /* IP2_19_17 [3] */
1944 FN_D10, FN_RSPI_MOSI_A, 0, FN_QMO_QIO0_A,
1945 FN_FALE_A, FN_ET0_ETXD2_B, 0, 0,
1946 /* IP2_16_14 [3] */
1947 FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A,
1948 FN_FCLE_A, FN_ET0_ETXD1_B, 0, 0,
1949 /* IP2_13_11 [3] */
1950 FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A,
1951 FN_FCE_A, FN_ET0_GTX_CLK_B, 0, 0,
1952 /* IP2_10_8 [3] */
1953 FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A,
1954 FN_FD7_A, 0, 0, 0,
1955 /* IP2_7_5 [3] */
1956 FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A,
1957 FN_FD6_A, 0, 0, 0,
1958 /* IP2_4_3 [2] */
1959 FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
1960 /* IP2_2_0 [3] */
1961 FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7,
1962 FN_FD4_A, 0, 0, 0 }
1963 },
1964 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1965 2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2) {
1966 /* IP3_31_30 [2] */
1967 0, 0, 0, 0,
1968 /* IP3_29_27 [3] */
1969 FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A,
1970 FN_ET0_ETXD7, 0, 0, 0,
1971 /* IP3_26_24 [3] */
1972 FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
1973 FN_ET0_MAGIC_C, FN_ET0_ETXD6_A, 0, 0,
1974 /* IP3_23_21 [3] */
1975 FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
1976 FN_ET0_LINK_C, FN_ET0_ETXD5_A, 0, 0,
1977 /* IP3_20 [1] */
1978 FN_EX_WAIT0, FN_TCLK1_B,
1979 /* IP3_19_18 [2] */
1980 FN_RD_WR, FN_TCLK1_B, 0, 0,
1981 /* IP3_17_15 [3] */
1982 FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
1983 FN_ET0_ETXD3_A, 0, 0, 0,
1984 /* IP3_14_12 [3] */
1985 FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B,
1986 FN_ET0_ETXD2_A, 0, 0, 0,
1987 /* IP3_11_9 [3] */
1988 FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B,
1989 FN_ET0_ETXD1_A, 0, 0, 0,
1990 /* IP3_8_6 [3] */
1991 FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B,
1992 FN_ET0_GTX_CLK_A, 0, 0, 0,
1993 /* IP3_5_3 [3] */
1994 FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B,
1995 FN_ET0_ETXD0, 0, 0, 0,
1996 /* IP3_2 [1] */
1997 FN_CS1_A26, FN_QIO3_B,
1998 /* IP3_1_0 [2] */
1999 FN_D15, FN_SCK2_B, 0, 0 }
2000 },
2001 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
2002 2, 2, 2, 2, 2, 2 , 2, 3, 3, 3, 3, 3, 3) {
2003 /* IP4_31_30 [2] */
2004 0, FN_SCK2_A, FN_VI0_G3, 0,
2005 /* IP4_29_28 [2] */
2006 0, FN_RTS1_B, FN_VI0_G2, 0,
2007 /* IP4_27_26 [2] */
2008 0, FN_CTS1_B, FN_VI0_DATA7_VI0_G1, 0,
2009 /* IP4_25_24 [2] */
2010 0, FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
2011 /* IP4_23_22 [2] */
2012 0, FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
2013 /* IP4_21_20 [2] */
2014 0, FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
2015 /* IP4_19_18 [2] */
2016 0, FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
2017 /* IP4_17_15 [3] */
2018 0, FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A,
2019 FN_ET0_MDC, 0, 0, 0,
2020 /* IP4_14_12 [3] */
2021 FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A,
2022 FN_ET0_COL, 0, 0, 0,
2023 /* IP4_11_9 [3] */
2024 FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A,
2025 FN_ET0_CRS, 0, 0, 0,
2026 /* IP4_8_6 [3] */
2027 FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A,
2028 FN_ET0_RX_ER, 0, 0, 0,
2029 /* IP4_5_3 [3] */
2030 FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A,
2031 FN_ET0_RX_DV, 0, 0, 0,
2032 /* IP4_2_0 [3] */
2033 FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A,
2034 FN_ET0_ERXD7, 0, 0, 0 }
2035 },
2036 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2037 1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3) {
2038 /* IP5_31 [1] */
2039 0, 0,
2040 /* IP5_30 [1] */
2041 0, 0,
2042 /* IP5_29 [1] */
2043 0, 0,
2044 /* IP5_28 [1] */
2045 0, 0,
2046 /* IP5_27 [1] */
2047 0, 0,
2048 /* IP5_26_25 [2] */
2049 FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 0,
2050 /* IP5_24_23 [2] */
2051 FN_REF125CK, FN_ADTRG, FN_RX5_C, 0,
2052 /* IP5_22_21 [2] */
2053 FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5, 0,
2054 /* IP5_20_18 [3] */
2055 FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, 0,
2056 0, 0, 0, FN_ET0_PHY_INT_B,
2057 /* IP5_17_15 [3] */
2058 FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, 0,
2059 0, 0, 0, FN_ET0_MAGIC_B,
2060 /* IP5_14_12 [3] */
2061 FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, 0,
2062 0, 0, 0, FN_ET0_LINK_B,
2063 /* IP5_11_9 [3] */
2064 FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, 0,
2065 0, 0, 0, FN_ET0_MDIO_B,
2066 /* IP5_8_6 [3] */
2067 FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, 0,
2068 0, 0, 0, FN_ET0_ERXD3_B,
2069 /* IP5_5_3 [3] */
2070 FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, 0,
2071 0, 0, 0, FN_ET0_ERXD2_B,
2072 /* IP5_2_0 [3] */
2073 FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0,
2074 FN_ET0_RX_CLK_B, 0, 0, 0 }
2075 },
2076 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2077 1, 1, 1, 1, 1, 1, 1, 1,
2078 3, 3, 2, 2, 2, 2, 2, 2, 3, 3) {
2079 /* IP5_31 [1] */
2080 0, 0,
2081 /* IP6_30 [1] */
2082 0, 0,
2083 /* IP6_29 [1] */
2084 0, 0,
2085 /* IP6_28 [1] */
2086 0, 0,
2087 /* IP6_27 [1] */
2088 0, 0,
2089 /* IP6_26 [1] */
2090 0, 0,
2091 /* IP6_25 [1] */
2092 0, 0,
2093 /* IP6_24 [1] */
2094 0, 0,
2095 /* IP6_23_21 [3] */
2096 FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A,
2097 FN_HIFD09, 0, 0, 0,
2098 /* IP6_20_18 [3] */
2099 FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A,
2100 FN_TIOC1A_A, FN_HIFD08, 0, 0,
2101 /* IP6_17_16 [2] */
2102 FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
2103 /* IP6_15_14 [2] */
2104 FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
2105 /* IP6_13_12 [2] */
2106 FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
2107 /* IP6_11_10 [2] */
2108 FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
2109 /* IP6_9_8 [2] */
2110 FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
2111 /* IP6_7_6 [2] */
2112 FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
2113 /* IP6_5_3 [3] */
2114 FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A,
2115 FN_TCLKB_A, FN_HIFD01, 0, 0,
2116 /* IP6_2_0 [3] */
2117 FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A,
2118 FN_TCLKA_A, FN_HIFD00, 0, 0 }
2119 },
2120 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2121 1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
2122 /* IP7_31 [1] */
2123 0, 0,
2124 /* IP7_30_29 [2] */
2125 FN_DU0_DB4, 0, FN_HIFINT, 0,
2126 /* IP7_28_27 [2] */
2127 FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
2128 /* IP7_26_24 [3] */
2129 FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A,
2130 FN_HIFWR, 0, 0, 0,
2131 /* IP7_23_21 [3] */
2132 FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A,
2133 FN_HIFRS, 0, 0, 0,
2134 /* IP7_20_18 [3] */
2135 FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A,
2136 FN_HIFCS, 0, 0, 0,
2137 /* IP7_17_15 [3] */
2138 FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A,
2139 FN_HIFD15, 0, 0, 0,
2140 /* IP7_14_12 [3] */
2141 FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A,
2142 FN_HIFD14, 0, 0, 0,
2143 /* IP7_11_9 [3] */
2144 FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A,
2145 FN_HIFD13, 0, 0, 0,
2146 /* IP7_8_6 [3] */
2147 FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A,
2148 FN_HIFD12, 0, 0, 0,
2149 /* IP7_5_3 [3] */
2150 FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A,
2151 FN_HIFD11, 0, 0, 0,
2152 /* IP7_2_0 [3] */
2153 FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A,
2154 FN_HIFD10, 0, 0, 0 }
2155 },
2156 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2157 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
2158 /* IP9_31_30 [2] */
2159 0, 0, 0, 0,
2160 /* IP8_29_28 [2] */
2161 FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
2162 /* IP8_27_26 [2] */
2163 FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
2164 /* IP8_25_23 [3] */
2165 FN_IRQ1_A, 0, FN_HSPI_RX_B, FN_TX3_E,
2166 FN_ET0_ERXD1, 0, 0, 0,
2167 /* IP8_22_20 [3] */
2168 FN_IRQ0_A, 0, FN_HSPI_TX_B, FN_RX3_E,
2169 FN_ET0_ERXD0, 0, 0, 0,
2170 /* IP8_19_18 [2] */
2171 FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
2172 /* IP8_17_16 [2] */
2173 FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
2174 /* IP8_15_14 [2] */
2175 FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B,
2176 FN_SSI_SDATA1_B,
2177 /* IP8_13_12 [2] */
2178 FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_HSPI_RX0_C, FN_SSI_WS1_B,
2179 /* IP8_11_10 [2] */
2180 FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
2181 /* IP8_9_8 [2] */
2182 FN_DU0_DOTCLKOUT, 0, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
2183 /* IP8_7_6 [2] */
2184 FN_DU0_DOTCLKIN, 0, FN_HSPI_CS0_C, FN_SSI_WS0_B,
2185 /* IP8_5_4 [2] */
2186 FN_DU0_DB7, 0, FN_SSI_SCK0_B, FN_HIFEBL_B,
2187 /* IP8_3_2 [2] */
2188 FN_DU0_DB6, 0, FN_HIFRDY, 0,
2189 /* IP8_1_0 [2] */
2190 FN_DU0_DB5, 0, FN_HIFDREQ, 0 }
2191 },
2192 { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
2193 2, 2, 2, 2, 2, 2, 2, 2,
2194 2, 2, 2, 2, 2, 2, 2, 2) {
2195 /* IP9_31_30 [2] */
2196 0, 0, 0, 0,
2197 /* IP9_29_28 [2] */
2198 FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 0,
2199 /* IP9_27_26 [2] */
2200 FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B, 0,
2201 /* IP9_25_24 [2] */
2202 FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
2203 /* IP9_23_22 [2] */
2204 FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
2205 /* IP9_21_20 [2] */
2206 FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B, 0,
2207 /* IP9_19_18 [2] */
2208 FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B, 0,
2209 /* IP9_17_16 [2] */
2210 FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B, 0,
2211 /* IP9_15_14 [2] */
2212 FN_VI1_6_A, 0, FN_FD7_B, FN_LCD_DATA7_B,
2213 /* IP9_13_12 [2] */
2214 FN_VI1_5_A, 0, FN_FD6_B, FN_LCD_DATA6_B,
2215 /* IP9_11_10 [2] */
2216 FN_VI1_4_A, 0, FN_FD5_B, FN_LCD_DATA5_B,
2217 /* IP9_9_8 [2] */
2218 FN_VI1_3_A, 0, FN_FD4_B, FN_LCD_DATA4_B,
2219 /* IP9_7_6 [2] */
2220 FN_VI1_2_A, 0, FN_FD3_B, FN_LCD_DATA3_B,
2221 /* IP9_5_4 [2] */
2222 FN_VI1_1_A, 0, FN_FD2_B, FN_LCD_DATA2_B,
2223 /* IP9_3_2 [2] */
2224 FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B,
2225 /* IP9_1_0 [2] */
2226 FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B }
2227 },
2228 { PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32,
2229 2, 2, 2, 1, 2, 1, 3,
2230 3, 1, 3, 3, 3, 3, 3) {
2231 /* IP9_31_30 [2] */
2232 0, 0, 0, 0,
2233 /* IP10_29_28 [2] */
2234 FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 0,
2235 /* IP10_27_26 [2] */
2236 FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG, 0,
2237 /* IP10_25 [1] */
2238 FN_CAN1_RX_A, FN_IRQ1_B,
2239 /* IP10_24_23 [2] */
2240 FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK, 0,
2241 /* IP10_22 [1] */
2242 FN_CAN_CLK_A, FN_RX4_D,
2243 /* IP10_21_19 [3] */
2244 FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B,
2245 FN_LCD_M_DISP_B, 0, 0, 0,
2246 /* IP10_18_16 [3] */
2247 FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B,
2248 FN_LCD_VEPWC_B, 0, 0, 0,
2249 /* IP10_15 [1] */
2250 FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
2251 /* IP10_14_12 [3] */
2252 FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B,
2253 FN_LCD_FLM_B, 0, 0, 0,
2254 /* IP10_11_9 [3] */
2255 FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B,
2256 FN_LCD_CL2_B, 0, 0, 0,
2257 /* IP10_8_6 [3] */
2258 FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B,
2259 FN_LCD_CL1_B, 0, 0, 0,
2260 /* IP10_5_3 [3] */
2261 FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B,
2262 FN_LCD_DON_B, 0, 0, 0,
2263 /* IP10_2_0 [3] */
2264 FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B,
2265 FN_LCD_DATA15_B, 0, 0, 0 }
2266 },
2267 { PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
2268 3, 1, 2, 2, 2, 3, 3, 1, 2, 3, 3, 1, 1, 1, 1) {
2269 /* IP11_31_29 [3] */
2270 0, 0, 0, 0, 0, 0, 0, 0,
2271 /* IP11_28 [1] */
2272 FN_PRESETOUT, FN_ST_CLKOUT,
2273 /* IP11_27_26 [2] */
2274 FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
2275 /* IP11_25_23 [3] */
2276 FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C,
2277 FN_ET0_TX_CLK_A, 0, 0, 0,
2278 /* IP11_22_21 [2] */
2279 FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER, 0,
2280 /* IP11_20_19 [2] */
2281 FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN, 0,
2282 /* IP11_18_16 [3] */
2283 FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D,
2284 FN_IERX_B, 0, 0, 0,
2285 /* IP11_15_13 [3] */
2286 FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D,
2287 FN_IETX_B, 0, 0, 0,
2288 /* IP11_12 [1] */
2289 FN_TX0_A, FN_HSPI_TX_A,
2290 /* IP11_11_10 [2] */
2291 FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
2292 /* IP11_9_7 [3] */
2293 FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A,
2294 FN_ET0_ERXD5, 0, 0, 0,
2295 /* IP11_6_4 [3] */
2296 FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A,
2297 FN_ET0_ERXD4, 0, 0, 0,
2298 /* IP11_3 [1] */
2299 FN_SDSELF, FN_RTS1_E,
2300 /* IP11_2 [1] */
2301 FN_SDA0, FN_HIFEBL_A,
2302 /* IP11_1 [1] */
2303 FN_SDA1, FN_RX1_E,
2304 /* IP11_0 [1] */
2305 FN_SCL1, FN_SCIF_CLK_C }
2306 },
2307 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32,
2308 3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2, 2,
2309 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
2310 /* SEL1_31_29 [3] */
2311 0, 0, 0, 0, 0, 0, 0, 0,
2312 /* SEL1_28 [1] */
2313 FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
2314 /* SEL1_27 [1] */
2315 FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
2316 /* SEL1_26 [1] */
2317 FN_SEL_VIN1_0, FN_SEL_VIN1_1,
2318 /* SEL1_25 [1] */
2319 FN_SEL_HIF_0, FN_SEL_HIF_1,
2320 /* SEL1_24 [1] */
2321 FN_SEL_RSPI_0, FN_SEL_RSPI_1,
2322 /* SEL1_23 [1] */
2323 FN_SEL_LCDC_0, FN_SEL_LCDC_1,
2324 /* SEL1_22_21 [2] */
2325 FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2, 0,
2326 /* SEL1_20 [1] */
2327 FN_SEL_ET0_0, FN_SEL_ET0_1,
2328 /* SEL1_19 [1] */
2329 FN_SEL_RMII_0, FN_SEL_RMII_1,
2330 /* SEL1_18 [1] */
2331 FN_SEL_TMU_0, FN_SEL_TMU_1,
2332 /* SEL1_17_16 [2] */
2333 FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2, 0,
2334 /* SEL1_15_14 [2] */
2335 FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
2336 /* SEL1_13 [1] */
2337 FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
2338 /* SEL1_12_11 [2] */
2339 FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2, 0,
2340 /* SEL1_10 [1] */
2341 FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
2342 /* SEL1_9 [1] */
2343 FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
2344 /* SEL1_8 [1] */
2345 FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
2346 /* SEL1_7 [1] */
2347 FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
2348 /* SEL1_6 [1] */
2349 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
2350 /* SEL1_5 [1] */
2351 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
2352 /* SEL1_4 [1] */
2353 FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
2354 /* SEL1_3 [1] */
2355 FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
2356 /* SEL1_2 [1] */
2357 FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
2358 /* SEL1_1 [1] */
2359 FN_SEL_MMC_0, FN_SEL_MMC_1,
2360 /* SEL1_0 [1] */
2361 FN_SEL_INTC_0, FN_SEL_INTC_1 }
2362 },
2363 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32,
2364 1, 1, 1, 1, 1, 1, 1, 1,
2365 1, 1, 1, 2, 2, 1, 2, 2, 3, 2, 3, 2, 2) {
2366 /* SEL2_31 [1] */
2367 0, 0,
2368 /* SEL2_30 [1] */
2369 0, 0,
2370 /* SEL2_29 [1] */
2371 0, 0,
2372 /* SEL2_28 [1] */
2373 0, 0,
2374 /* SEL2_27 [1] */
2375 0, 0,
2376 /* SEL2_26 [1] */
2377 0, 0,
2378 /* SEL2_25 [1] */
2379 0, 0,
2380 /* SEL2_24 [1] */
2381 0, 0,
2382 /* SEL2_23 [1] */
2383 FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
2384 /* SEL2_22 [1] */
2385 FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
2386 /* SEL2_21 [1] */
2387 FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
2388 /* SEL2_20_19 [2] */
2389 FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2, 0,
2390 /* SEL2_18_17 [2] */
2391 FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2, 0,
2392 /* SEL2_16 [1] */
2393 FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
2394 /* SEL2_15_14 [2] */
2395 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
2396 /* SEL2_13_12 [2] */
2397 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
2398 /* SEL2_11_9 [3] */
2399 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
2400 FN_SEL_SCIF3_4, 0, 0, 0,
2401 /* SEL2_8_7 [2] */
2402 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
2403 /* SEL2_6_4 [3] */
2404 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
2405 FN_SEL_SCIF1_4, 0, 0, 0,
2406 /* SEL2_3_2 [2] */
2407 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0,
2408 /* SEL2_1_0 [2] */
2409 FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0 }
2410 },
2411 /* GPIO 0 - 5*/
2412 { PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1) { GP_INOUTSEL(0) } },
2413 { PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1) { GP_INOUTSEL(1) } },
2414 { PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1) { GP_INOUTSEL(2) } },
2415 { PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1) { GP_INOUTSEL(3) } },
2416 { PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1) { GP_INOUTSEL(4) } },
2417 { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) {
2418 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */
2419 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */
2420 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
2421 GP_5_11_IN, GP_5_11_OUT,
2422 GP_5_10_IN, GP_5_10_OUT,
2423 GP_5_9_IN, GP_5_9_OUT,
2424 GP_5_8_IN, GP_5_8_OUT,
2425 GP_5_7_IN, GP_5_7_OUT,
2426 GP_5_6_IN, GP_5_6_OUT,
2427 GP_5_5_IN, GP_5_5_OUT,
2428 GP_5_4_IN, GP_5_4_OUT,
2429 GP_5_3_IN, GP_5_3_OUT,
2430 GP_5_2_IN, GP_5_2_OUT,
2431 GP_5_1_IN, GP_5_1_OUT,
2432 GP_5_0_IN, GP_5_0_OUT }
2433 },
2434 { },
2435};
2436
2437static struct pinmux_data_reg pinmux_data_regs[] = {
2438 /* GPIO 0 - 5*/
2439 { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } },
2440 { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } },
2441 { PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32) { GP_INDT(2) } },
2442 { PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32) { GP_INDT(3) } },
2443 { PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32) { GP_INDT(4) } },
2444 { PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32) {
2445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2446 0, 0, 0, 0,
2447 GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
2448 GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
2449 GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
2450 },
2451 { },
2452};
2453
2454static struct resource sh7734_pfc_resources[] = {
2455 [0] = { /* PFC */
2456 .start = 0xFFFC0000,
2457 .end = 0xFFFC011C,
2458 .flags = IORESOURCE_MEM,
2459 },
2460 [1] = { /* GPIO */
2461 .start = 0xFFC40000,
2462 .end = 0xFFC4502B,
2463 .flags = IORESOURCE_MEM,
2464 }
2465};
2466
2467static struct pinmux_info sh7734_pinmux_info = {
2468 .name = "sh7734_pfc",
2469
2470 .resource = sh7734_pfc_resources,
2471 .num_resources = ARRAY_SIZE(sh7734_pfc_resources),
2472
2473 .unlock_reg = 0xFFFC0000,
2474
2475 .reserved_id = PINMUX_RESERVED,
2476 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2477 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2478 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2479 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2480 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2481
2482 .first_gpio = GPIO_GP_0_0,
2483 .last_gpio = GPIO_FN_ST_CLKOUT,
2484
2485 .gpios = pinmux_gpios,
2486 .cfg_regs = pinmux_config_regs,
2487 .data_regs = pinmux_data_regs,
2488
2489 .gpio_data = pinmux_data,
2490 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2491};
2492
2493static int __init plat_pinmux_setup(void)
2494{
2495 return register_pinmux(&sh7734_pinmux_info);
2496}
2497arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 1b8848317e9..476f4747df9 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -22,7 +22,7 @@ static struct plat_sci_port scif0_platform_data = {
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
23 .scbrr_algo_id = SCBRR_ALGO_2, 23 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 24 .type = PORT_SCIF,
25 .irqs = { 80, 80, 80, 80 }, 25 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)),
26}; 26};
27 27
28static struct platform_device scif0_device = { 28static struct platform_device scif0_device = {
@@ -39,7 +39,7 @@ static struct plat_sci_port scif1_platform_data = {
39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
40 .scbrr_algo_id = SCBRR_ALGO_2, 40 .scbrr_algo_id = SCBRR_ALGO_2,
41 .type = PORT_SCIF, 41 .type = PORT_SCIF,
42 .irqs = { 81, 81, 81, 81 }, 42 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)),
43}; 43};
44 44
45static struct platform_device scif1_device = { 45static struct platform_device scif1_device = {
@@ -56,7 +56,7 @@ static struct plat_sci_port scif2_platform_data = {
56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
57 .scbrr_algo_id = SCBRR_ALGO_2, 57 .scbrr_algo_id = SCBRR_ALGO_2,
58 .type = PORT_SCIF, 58 .type = PORT_SCIF,
59 .irqs = { 82, 82, 82, 82 }, 59 .irq = SCIx_IRQ_MUXED(evt2irq(0xC40)),
60}; 60};
61 61
62static struct platform_device scif2_device = { 62static struct platform_device scif2_device = {
@@ -73,7 +73,7 @@ static struct plat_sci_port scif3_platform_data = {
73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
74 .scbrr_algo_id = SCBRR_ALGO_2, 74 .scbrr_algo_id = SCBRR_ALGO_2,
75 .type = PORT_SCIF, 75 .type = PORT_SCIF,
76 .irqs = { 83, 83, 83, 83 }, 76 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC60)),
77}; 77};
78 78
79static struct platform_device scif3_device = { 79static struct platform_device scif3_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 87773869a2f..20f9e366a81 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -25,7 +25,7 @@ static struct plat_sci_port scif0_platform_data = {
25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
26 .scbrr_algo_id = SCBRR_ALGO_2, 26 .scbrr_algo_id = SCBRR_ALGO_2,
27 .type = PORT_SCIF, 27 .type = PORT_SCIF,
28 .irqs = { 80, 80, 80, 80 }, 28 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)),
29}; 29};
30 30
31static struct platform_device scif0_device = { 31static struct platform_device scif0_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 8420d4bc8bf..34b2ee5805d 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -182,7 +182,7 @@ static struct plat_sci_port scif0_platform_data = {
182 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 182 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
183 .scbrr_algo_id = SCBRR_ALGO_2, 183 .scbrr_algo_id = SCBRR_ALGO_2,
184 .type = PORT_SCIF, 184 .type = PORT_SCIF,
185 .irqs = { 80, 80, 80, 80 }, 185 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)),
186 .ops = &sh7722_sci_port_ops, 186 .ops = &sh7722_sci_port_ops,
187 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 187 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
188}; 188};
@@ -201,7 +201,7 @@ static struct plat_sci_port scif1_platform_data = {
201 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 201 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
202 .scbrr_algo_id = SCBRR_ALGO_2, 202 .scbrr_algo_id = SCBRR_ALGO_2,
203 .type = PORT_SCIF, 203 .type = PORT_SCIF,
204 .irqs = { 81, 81, 81, 81 }, 204 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)),
205 .ops = &sh7722_sci_port_ops, 205 .ops = &sh7722_sci_port_ops,
206 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 206 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
207}; 207};
@@ -220,7 +220,7 @@ static struct plat_sci_port scif2_platform_data = {
220 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 220 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
221 .scbrr_algo_id = SCBRR_ALGO_2, 221 .scbrr_algo_id = SCBRR_ALGO_2,
222 .type = PORT_SCIF, 222 .type = PORT_SCIF,
223 .irqs = { 82, 82, 82, 82 }, 223 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC40)),
224 .ops = &sh7722_sci_port_ops, 224 .ops = &sh7722_sci_port_ops,
225 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 225 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
226}; 226};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index a188c9ea439..3c1da7e3067 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -28,7 +28,7 @@ static struct plat_sci_port scif0_platform_data = {
28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
29 .scbrr_algo_id = SCBRR_ALGO_2, 29 .scbrr_algo_id = SCBRR_ALGO_2,
30 .type = PORT_SCIF, 30 .type = PORT_SCIF,
31 .irqs = { 80, 80, 80, 80 }, 31 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)),
32 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 32 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
33}; 33};
34 34
@@ -47,7 +47,7 @@ static struct plat_sci_port scif1_platform_data = {
47 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 47 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
48 .scbrr_algo_id = SCBRR_ALGO_2, 48 .scbrr_algo_id = SCBRR_ALGO_2,
49 .type = PORT_SCIF, 49 .type = PORT_SCIF,
50 .irqs = { 81, 81, 81, 81 }, 50 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)),
51 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 51 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
52}; 52};
53 53
@@ -66,7 +66,7 @@ static struct plat_sci_port scif2_platform_data = {
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2, 67 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF, 68 .type = PORT_SCIF,
69 .irqs = { 82, 82, 82, 82 }, 69 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC40)),
70 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 70 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
71}; 71};
72 72
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 4c671cfe68a..20623baeb1c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -295,7 +295,7 @@ static struct plat_sci_port scif0_platform_data = {
295 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 295 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
296 .scbrr_algo_id = SCBRR_ALGO_2, 296 .scbrr_algo_id = SCBRR_ALGO_2,
297 .type = PORT_SCIF, 297 .type = PORT_SCIF,
298 .irqs = { 80, 80, 80, 80 }, 298 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)),
299 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 299 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
300}; 300};
301 301
@@ -314,7 +314,7 @@ static struct plat_sci_port scif1_platform_data = {
314 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 314 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
315 .scbrr_algo_id = SCBRR_ALGO_2, 315 .scbrr_algo_id = SCBRR_ALGO_2,
316 .type = PORT_SCIF, 316 .type = PORT_SCIF,
317 .irqs = { 81, 81, 81, 81 }, 317 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)),
318 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 318 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
319}; 319};
320 320
@@ -333,7 +333,7 @@ static struct plat_sci_port scif2_platform_data = {
333 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 333 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
334 .scbrr_algo_id = SCBRR_ALGO_2, 334 .scbrr_algo_id = SCBRR_ALGO_2,
335 .type = PORT_SCIF, 335 .type = PORT_SCIF,
336 .irqs = { 82, 82, 82, 82 }, 336 .irqs = SCIx_IRQ_MUXED(evt2irq(0xC40)),
337 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 337 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
338}; 338};
339 339
@@ -352,7 +352,7 @@ static struct plat_sci_port scif3_platform_data = {
352 .scscr = SCSCR_RE | SCSCR_TE, 352 .scscr = SCSCR_RE | SCSCR_TE,
353 .scbrr_algo_id = SCBRR_ALGO_3, 353 .scbrr_algo_id = SCBRR_ALGO_3,
354 .type = PORT_SCIFA, 354 .type = PORT_SCIFA,
355 .irqs = { 56, 56, 56, 56 }, 355 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
356}; 356};
357 357
358static struct platform_device scif3_device = { 358static struct platform_device scif3_device = {
@@ -370,7 +370,7 @@ static struct plat_sci_port scif4_platform_data = {
370 .scscr = SCSCR_RE | SCSCR_TE, 370 .scscr = SCSCR_RE | SCSCR_TE,
371 .scbrr_algo_id = SCBRR_ALGO_3, 371 .scbrr_algo_id = SCBRR_ALGO_3,
372 .type = PORT_SCIFA, 372 .type = PORT_SCIFA,
373 .irqs = { 88, 88, 88, 88 }, 373 .irqs = SCIx_IRQ_MUXED(evt2irq(0xD00)),
374}; 374};
375 375
376static struct platform_device scif4_device = { 376static struct platform_device scif4_device = {
@@ -388,7 +388,7 @@ static struct plat_sci_port scif5_platform_data = {
388 .scscr = SCSCR_RE | SCSCR_TE, 388 .scscr = SCSCR_RE | SCSCR_TE,
389 .scbrr_algo_id = SCBRR_ALGO_3, 389 .scbrr_algo_id = SCBRR_ALGO_3,
390 .type = PORT_SCIFA, 390 .type = PORT_SCIFA,
391 .irqs = { 109, 109, 109, 109 }, 391 .irqs = SCIx_IRQ_MUXED(evt2irq(0xFA0)),
392}; 392};
393 393
394static struct platform_device scif5_device = { 394static struct platform_device scif5_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
new file mode 100644
index 00000000000..f799971d453
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
@@ -0,0 +1,800 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/setup-sh7734.c
3
4 * SH7734 Setup
5 *
6 * Copyright (C) 2011,2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * Copyright (C) 2011,2012 Renesas Solutions Corp.
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#include <linux/platform_device.h>
15#include <linux/init.h>
16#include <linux/serial.h>
17#include <linux/mm.h>
18#include <linux/dma-mapping.h>
19#include <linux/serial_sci.h>
20#include <linux/sh_timer.h>
21#include <linux/io.h>
22#include <asm/clock.h>
23#include <asm/irq.h>
24#include <cpu/sh7734.h>
25
26/* SCIF */
27static struct plat_sci_port scif0_platform_data = {
28 .mapbase = 0xFFE40000,
29 .flags = UPF_BOOT_AUTOCONF,
30 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
31 .scbrr_algo_id = SCBRR_ALGO_2,
32 .type = PORT_SCIF,
33 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8C0)),
34 .regtype = SCIx_SH4_SCIF_REGTYPE,
35};
36
37static struct platform_device scif0_device = {
38 .name = "sh-sci",
39 .id = 0,
40 .dev = {
41 .platform_data = &scif0_platform_data,
42 },
43};
44
45static struct plat_sci_port scif1_platform_data = {
46 .mapbase = 0xFFE41000,
47 .flags = UPF_BOOT_AUTOCONF,
48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
49 .scbrr_algo_id = SCBRR_ALGO_2,
50 .type = PORT_SCIF,
51 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8E0)),
52 .regtype = SCIx_SH4_SCIF_REGTYPE,
53};
54
55static struct platform_device scif1_device = {
56 .name = "sh-sci",
57 .id = 1,
58 .dev = {
59 .platform_data = &scif1_platform_data,
60 },
61};
62
63static struct plat_sci_port scif2_platform_data = {
64 .mapbase = 0xFFE42000,
65 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF,
69 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
70 .regtype = SCIx_SH4_SCIF_REGTYPE,
71};
72
73static struct platform_device scif2_device = {
74 .name = "sh-sci",
75 .id = 2,
76 .dev = {
77 .platform_data = &scif2_platform_data,
78 },
79};
80
81static struct plat_sci_port scif3_platform_data = {
82 .mapbase = 0xFFE43000,
83 .flags = UPF_BOOT_AUTOCONF,
84 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
85 .scbrr_algo_id = SCBRR_ALGO_2,
86 .type = PORT_SCIF,
87 .irqs = SCIx_IRQ_MUXED(evt2irq(0x920)),
88 .regtype = SCIx_SH4_SCIF_REGTYPE,
89};
90
91static struct platform_device scif3_device = {
92 .name = "sh-sci",
93 .id = 3,
94 .dev = {
95 .platform_data = &scif3_platform_data,
96 },
97};
98
99static struct plat_sci_port scif4_platform_data = {
100 .mapbase = 0xFFE44000,
101 .flags = UPF_BOOT_AUTOCONF,
102 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
103 .scbrr_algo_id = SCBRR_ALGO_2,
104 .type = PORT_SCIF,
105 .irqs = SCIx_IRQ_MUXED(evt2irq(0x940)),
106 .regtype = SCIx_SH4_SCIF_REGTYPE,
107};
108
109static struct platform_device scif4_device = {
110 .name = "sh-sci",
111 .id = 4,
112 .dev = {
113 .platform_data = &scif4_platform_data,
114 },
115};
116
117static struct plat_sci_port scif5_platform_data = {
118 .mapbase = 0xFFE43000,
119 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
121 .scbrr_algo_id = SCBRR_ALGO_2,
122 .type = PORT_SCIF,
123 .irqs = SCIx_IRQ_MUXED(evt2irq(0x960)),
124 .regtype = SCIx_SH4_SCIF_REGTYPE,
125};
126
127static struct platform_device scif5_device = {
128 .name = "sh-sci",
129 .id = 5,
130 .dev = {
131 .platform_data = &scif5_platform_data,
132 },
133};
134
135/* RTC */
136static struct resource rtc_resources[] = {
137 [0] = {
138 .name = "rtc",
139 .start = 0xFFFC5000,
140 .end = 0xFFFC5000 + 0x26 - 1,
141 .flags = IORESOURCE_IO,
142 },
143 [1] = {
144 .start = evt2irq(0xC00),
145 .flags = IORESOURCE_IRQ,
146 },
147};
148
149static struct platform_device rtc_device = {
150 .name = "sh-rtc",
151 .id = -1,
152 .num_resources = ARRAY_SIZE(rtc_resources),
153 .resource = rtc_resources,
154};
155
156/* I2C 0 */
157static struct resource i2c0_resources[] = {
158 [0] = {
159 .name = "IIC0",
160 .start = 0xFFC70000,
161 .end = 0xFFC7000A - 1,
162 .flags = IORESOURCE_MEM,
163 },
164 [1] = {
165 .start = evt2irq(0x860),
166 .flags = IORESOURCE_IRQ,
167 },
168};
169
170static struct platform_device i2c0_device = {
171 .name = "i2c-sh7734",
172 .id = 0,
173 .num_resources = ARRAY_SIZE(i2c0_resources),
174 .resource = i2c0_resources,
175};
176
177/* TMU */
178static struct sh_timer_config tmu0_platform_data = {
179 .channel_offset = 0x04,
180 .timer_bit = 0,
181 .clockevent_rating = 200,
182};
183
184static struct resource tmu0_resources[] = {
185 [0] = {
186 .start = 0xFFD80008,
187 .end = 0xFFD80014 - 1,
188 .flags = IORESOURCE_MEM,
189 },
190 [1] = {
191 .start = evt2irq(0x400),
192 .flags = IORESOURCE_IRQ,
193 },
194};
195
196static struct platform_device tmu0_device = {
197 .name = "sh_tmu",
198 .id = 0,
199 .dev = {
200 .platform_data = &tmu0_platform_data,
201 },
202 .resource = tmu0_resources,
203 .num_resources = ARRAY_SIZE(tmu0_resources),
204};
205
206static struct sh_timer_config tmu1_platform_data = {
207 .channel_offset = 0x10,
208 .timer_bit = 1,
209 .clocksource_rating = 200,
210};
211
212static struct resource tmu1_resources[] = {
213 [0] = {
214 .start = 0xFFD80014,
215 .end = 0xFFD80020 - 1,
216 .flags = IORESOURCE_MEM,
217 },
218 [1] = {
219 .start = evt2irq(0x420),
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224static struct platform_device tmu1_device = {
225 .name = "sh_tmu",
226 .id = 1,
227 .dev = {
228 .platform_data = &tmu1_platform_data,
229 },
230 .resource = tmu1_resources,
231 .num_resources = ARRAY_SIZE(tmu1_resources),
232};
233
234static struct sh_timer_config tmu2_platform_data = {
235 .channel_offset = 0x1c,
236 .timer_bit = 2,
237};
238
239static struct resource tmu2_resources[] = {
240 [0] = {
241 .start = 0xFFD80020,
242 .end = 0xFFD80030 - 1,
243 .flags = IORESOURCE_MEM,
244 },
245 [1] = {
246 .start = evt2irq(0x440),
247 .flags = IORESOURCE_IRQ,
248 },
249};
250
251static struct platform_device tmu2_device = {
252 .name = "sh_tmu",
253 .id = 2,
254 .dev = {
255 .platform_data = &tmu2_platform_data,
256 },
257 .resource = tmu2_resources,
258 .num_resources = ARRAY_SIZE(tmu2_resources),
259};
260
261
262static struct sh_timer_config tmu3_platform_data = {
263 .channel_offset = 0x04,
264 .timer_bit = 0,
265};
266
267static struct resource tmu3_resources[] = {
268 [0] = {
269 .start = 0xFFD81008,
270 .end = 0xFFD81014 - 1,
271 .flags = IORESOURCE_MEM,
272 },
273 [1] = {
274 .start = evt2irq(0x480),
275 .flags = IORESOURCE_IRQ,
276 },
277};
278
279static struct platform_device tmu3_device = {
280 .name = "sh_tmu",
281 .id = 3,
282 .dev = {
283 .platform_data = &tmu3_platform_data,
284 },
285 .resource = tmu3_resources,
286 .num_resources = ARRAY_SIZE(tmu3_resources),
287};
288
289static struct sh_timer_config tmu4_platform_data = {
290 .channel_offset = 0x10,
291 .timer_bit = 1,
292};
293
294static struct resource tmu4_resources[] = {
295 [0] = {
296 .start = 0xFFD81014,
297 .end = 0xFFD81020 - 1,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = evt2irq(0x4A0),
302 .flags = IORESOURCE_IRQ,
303 },
304};
305
306static struct platform_device tmu4_device = {
307 .name = "sh_tmu",
308 .id = 4,
309 .dev = {
310 .platform_data = &tmu4_platform_data,
311 },
312 .resource = tmu4_resources,
313 .num_resources = ARRAY_SIZE(tmu4_resources),
314};
315
316static struct sh_timer_config tmu5_platform_data = {
317 .channel_offset = 0x1c,
318 .timer_bit = 2,
319};
320
321static struct resource tmu5_resources[] = {
322 [0] = {
323 .start = 0xFFD81020,
324 .end = 0xFFD81030 - 1,
325 .flags = IORESOURCE_MEM,
326 },
327 [1] = {
328 .start = evt2irq(0x4C0),
329 .flags = IORESOURCE_IRQ,
330 },
331};
332
333static struct platform_device tmu5_device = {
334 .name = "sh_tmu",
335 .id = 5,
336 .dev = {
337 .platform_data = &tmu5_platform_data,
338 },
339 .resource = tmu5_resources,
340 .num_resources = ARRAY_SIZE(tmu5_resources),
341};
342
343static struct sh_timer_config tmu6_platform_data = {
344 .channel_offset = 0x4,
345 .timer_bit = 0,
346};
347
348static struct resource tmu6_resources[] = {
349 [0] = {
350 .start = 0xFFD82008,
351 .end = 0xFFD82014 - 1,
352 .flags = IORESOURCE_MEM,
353 },
354 [1] = {
355 .start = evt2irq(0x500),
356 .flags = IORESOURCE_IRQ,
357 },
358};
359
360static struct platform_device tmu6_device = {
361 .name = "sh_tmu",
362 .id = 6,
363 .dev = {
364 .platform_data = &tmu6_platform_data,
365 },
366 .resource = tmu6_resources,
367 .num_resources = ARRAY_SIZE(tmu6_resources),
368};
369
370static struct sh_timer_config tmu7_platform_data = {
371 .channel_offset = 0x10,
372 .timer_bit = 1,
373};
374
375static struct resource tmu7_resources[] = {
376 [0] = {
377 .start = 0xFFD82014,
378 .end = 0xFFD82020 - 1,
379 .flags = IORESOURCE_MEM,
380 },
381 [1] = {
382 .start = evt2irq(0x520),
383 .flags = IORESOURCE_IRQ,
384 },
385};
386
387static struct platform_device tmu7_device = {
388 .name = "sh_tmu",
389 .id = 7,
390 .dev = {
391 .platform_data = &tmu7_platform_data,
392 },
393 .resource = tmu7_resources,
394 .num_resources = ARRAY_SIZE(tmu7_resources),
395};
396
397static struct sh_timer_config tmu8_platform_data = {
398 .channel_offset = 0x1c,
399 .timer_bit = 2,
400};
401
402static struct resource tmu8_resources[] = {
403 [0] = {
404 .start = 0xFFD82020,
405 .end = 0xFFD82030 - 1,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = evt2irq(0x540),
410 .flags = IORESOURCE_IRQ,
411 },
412};
413
414static struct platform_device tmu8_device = {
415 .name = "sh_tmu",
416 .id = 8,
417 .dev = {
418 .platform_data = &tmu8_platform_data,
419 },
420 .resource = tmu8_resources,
421 .num_resources = ARRAY_SIZE(tmu8_resources),
422};
423
424static struct platform_device *sh7734_devices[] __initdata = {
425 &scif0_device,
426 &scif1_device,
427 &scif2_device,
428 &scif3_device,
429 &scif4_device,
430 &scif5_device,
431 &tmu0_device,
432 &tmu1_device,
433 &tmu2_device,
434 &tmu3_device,
435 &tmu4_device,
436 &tmu5_device,
437 &tmu6_device,
438 &tmu7_device,
439 &tmu8_device,
440 &rtc_device,
441};
442
443static struct platform_device *sh7734_early_devices[] __initdata = {
444 &scif0_device,
445 &scif1_device,
446 &scif2_device,
447 &scif3_device,
448 &scif4_device,
449 &scif5_device,
450 &tmu0_device,
451 &tmu1_device,
452 &tmu2_device,
453 &tmu3_device,
454 &tmu4_device,
455 &tmu5_device,
456 &tmu6_device,
457 &tmu7_device,
458 &tmu8_device,
459};
460
461void __init plat_early_device_setup(void)
462{
463 early_platform_add_devices(sh7734_early_devices,
464 ARRAY_SIZE(sh7734_early_devices));
465}
466
467#define GROUP 0
468enum {
469 UNUSED = 0,
470
471 /* interrupt sources */
472
473 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
474 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
475 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
476 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
477
478 IRQ0, IRQ1, IRQ2, IRQ3,
479 DU,
480 TMU00, TMU10, TMU20, TMU21,
481 TMU30, TMU40, TMU50, TMU51,
482 TMU60, TMU70, TMU80,
483 RESET_WDT,
484 USB,
485 HUDI,
486 SHDMAC,
487 SSI0, SSI1, SSI2, SSI3,
488 VIN0,
489 RGPVG,
490 _2DG,
491 MMC,
492 HSPI,
493 LBSCATA,
494 I2C0,
495 RCAN0,
496 MIMLB,
497 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5,
498 LBSCDMAC0, LBSCDMAC1, LBSCDMAC2,
499 RCAN1,
500 SDHI0, SDHI1,
501 IEBUS,
502 HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22, HPBDMAC23_25_27_28,
503 RTC,
504 VIN1,
505 LCDC,
506 SRC0, SRC1,
507 GETHER,
508 SDHI2,
509 GPIO0_3, GPIO4_5,
510 STIF0, STIF1,
511 ADMAC,
512 HIF,
513 FLCTL,
514 ADC,
515 MTU2,
516 RSPI,
517 QSPI,
518 HSCIF,
519 VEU3F_VE3,
520
521 /* Group */
522 /* Mask */
523 STIF_M,
524 GPIO_M,
525 HPBDMAC_M,
526 LBSCDMAC_M,
527 RCAN_M,
528 SRC_M,
529 SCIF_M,
530 LCDC_M,
531 _2DG_M,
532 VIN_M,
533 TMU_3_M,
534 TMU_0_M,
535
536 /* Priority */
537 RCAN_P,
538 LBSCDMAC_P,
539
540 /* Common */
541 SDHI,
542 SSI,
543 SPI,
544};
545
546static struct intc_vect vectors[] __initdata = {
547 INTC_VECT(DU, 0x3E0),
548 INTC_VECT(TMU00, 0x400),
549 INTC_VECT(TMU10, 0x420),
550 INTC_VECT(TMU20, 0x440),
551 INTC_VECT(TMU30, 0x480),
552 INTC_VECT(TMU40, 0x4A0),
553 INTC_VECT(TMU50, 0x4C0),
554 INTC_VECT(TMU51, 0x4E0),
555 INTC_VECT(TMU60, 0x500),
556 INTC_VECT(TMU70, 0x520),
557 INTC_VECT(TMU80, 0x540),
558 INTC_VECT(RESET_WDT, 0x560),
559 INTC_VECT(USB, 0x580),
560 INTC_VECT(HUDI, 0x600),
561 INTC_VECT(SHDMAC, 0x620),
562 INTC_VECT(SSI0, 0x6C0),
563 INTC_VECT(SSI1, 0x6E0),
564 INTC_VECT(SSI2, 0x700),
565 INTC_VECT(SSI3, 0x720),
566 INTC_VECT(VIN0, 0x740),
567 INTC_VECT(RGPVG, 0x760),
568 INTC_VECT(_2DG, 0x780),
569 INTC_VECT(MMC, 0x7A0),
570 INTC_VECT(HSPI, 0x7E0),
571 INTC_VECT(LBSCATA, 0x840),
572 INTC_VECT(I2C0, 0x860),
573 INTC_VECT(RCAN0, 0x880),
574 INTC_VECT(SCIF0, 0x8A0),
575 INTC_VECT(SCIF1, 0x8C0),
576 INTC_VECT(SCIF2, 0x900),
577 INTC_VECT(SCIF3, 0x920),
578 INTC_VECT(SCIF4, 0x940),
579 INTC_VECT(SCIF5, 0x960),
580 INTC_VECT(LBSCDMAC0, 0x9E0),
581 INTC_VECT(LBSCDMAC1, 0xA00),
582 INTC_VECT(LBSCDMAC2, 0xA20),
583 INTC_VECT(RCAN1, 0xA60),
584 INTC_VECT(SDHI0, 0xAE0),
585 INTC_VECT(SDHI1, 0xB00),
586 INTC_VECT(IEBUS, 0xB20),
587 INTC_VECT(HPBDMAC0_3, 0xB60),
588 INTC_VECT(HPBDMAC4_10, 0xB80),
589 INTC_VECT(HPBDMAC11_18, 0xBA0),
590 INTC_VECT(HPBDMAC19_22, 0xBC0),
591 INTC_VECT(HPBDMAC23_25_27_28, 0xBE0),
592 INTC_VECT(RTC, 0xC00),
593 INTC_VECT(VIN1, 0xC20),
594 INTC_VECT(LCDC, 0xC40),
595 INTC_VECT(SRC0, 0xC60),
596 INTC_VECT(SRC1, 0xC80),
597 INTC_VECT(GETHER, 0xCA0),
598 INTC_VECT(SDHI2, 0xCC0),
599 INTC_VECT(GPIO0_3, 0xCE0),
600 INTC_VECT(GPIO4_5, 0xD00),
601 INTC_VECT(STIF0, 0xD20),
602 INTC_VECT(STIF1, 0xD40),
603 INTC_VECT(ADMAC, 0xDA0),
604 INTC_VECT(HIF, 0xDC0),
605 INTC_VECT(FLCTL, 0xDE0),
606 INTC_VECT(ADC, 0xE00),
607 INTC_VECT(MTU2, 0xE20),
608 INTC_VECT(RSPI, 0xE40),
609 INTC_VECT(QSPI, 0xE60),
610 INTC_VECT(HSCIF, 0xFC0),
611 INTC_VECT(VEU3F_VE3, 0xF40),
612};
613
614static struct intc_group groups[] __initdata = {
615 /* Common */
616 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2),
617 INTC_GROUP(SPI, HSPI, RSPI, QSPI),
618 INTC_GROUP(SSI, SSI0, SSI1, SSI2, SSI3),
619
620 /* Mask group */
621 INTC_GROUP(STIF_M, STIF0, STIF1), /* 22 */
622 INTC_GROUP(GPIO_M, GPIO0_3, GPIO4_5), /* 21 */
623 INTC_GROUP(HPBDMAC_M, HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18,
624 HPBDMAC19_22, HPBDMAC23_25_27_28), /* 19 */
625 INTC_GROUP(LBSCDMAC_M, LBSCDMAC0, LBSCDMAC1, LBSCDMAC2), /* 18 */
626 INTC_GROUP(RCAN_M, RCAN0, RCAN1, IEBUS), /* 17 */
627 INTC_GROUP(SRC_M, SRC0, SRC1), /* 16 */
628 INTC_GROUP(SCIF_M, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5,
629 HSCIF), /* 14 */
630 INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */
631 INTC_GROUP(_2DG_M, _2DG, RGPVG), /* 12 */
632 INTC_GROUP(VIN_M, VIN0, VIN1), /* 10 */
633 INTC_GROUP(TMU_3_M, TMU30, TMU40, TMU50, TMU51,
634 TMU60, TMU60, TMU70, TMU80), /* 2 */
635 INTC_GROUP(TMU_0_M, TMU00, TMU10, TMU20, TMU21), /* 1 */
636
637 /* Priority group*/
638 INTC_GROUP(RCAN_P, RCAN0, RCAN1), /* INT2PRI5 */
639 INTC_GROUP(LBSCDMAC_P, LBSCDMAC0, LBSCDMAC1), /* INT2PRI5 */
640};
641
642static struct intc_mask_reg mask_registers[] __initdata = {
643 { 0xFF804040, 0xFF804044, 32, /* INT2MSKRG / INT2MSKCR */
644 { 0,
645 VEU3F_VE3,
646 SDHI, /* SDHI 0-2 */
647 ADMAC,
648 FLCTL,
649 RESET_WDT,
650 HIF,
651 ADC,
652 MTU2,
653 STIF_M, /* STIF 0,1 */
654 GPIO_M, /* GPIO 0-5*/
655 GETHER,
656 HPBDMAC_M, /* HPBDMAC 0_3 - 23_25_27_28 */
657 LBSCDMAC_M, /* LBSCDMAC 0 - 2 */
658 RCAN_M, /* RCAN, IEBUS */
659 SRC_M, /* SRC 0,1 */
660 LBSCATA,
661 SCIF_M, /* SCIF 0-5, HSCIF */
662 LCDC_M, /* LCDC, MIMLB */
663 _2DG_M, /* 2DG, RGPVG */
664 SPI, /* HSPI, RSPI, QSPI */
665 VIN_M, /* VIN0, 1 */
666 SSI, /* SSI 0-3 */
667 USB,
668 SHDMAC,
669 HUDI,
670 MMC,
671 RTC,
672 I2C0, /* I2C */ /* I2C 0, 1*/
673 TMU_3_M, /* TMU30 - TMU80 */
674 TMU_0_M, /* TMU00 - TMU21 */
675 DU } },
676};
677
678static struct intc_prio_reg prio_registers[] __initdata = {
679 { 0xFF804000, 0, 32, 8, /* INT2PRI0 */
680 { DU, TMU00, TMU10, TMU20 } },
681 { 0xFF804004, 0, 32, 8, /* INT2PRI1 */
682 { TMU30, TMU60, RTC, SDHI } },
683 { 0xFF804008, 0, 32, 8, /* INT2PRI2 */
684 { HUDI, SHDMAC, USB, SSI } },
685 { 0xFF80400C, 0, 32, 8, /* INT2PRI3 */
686 { VIN0, SPI, _2DG, LBSCATA } },
687 { 0xFF804010, 0, 32, 8, /* INT2PRI4 */
688 { SCIF0, SCIF3, HSCIF, LCDC } },
689 { 0xFF804014, 0, 32, 8, /* INT2PRI5 */
690 { RCAN_P, LBSCDMAC_P, LBSCDMAC2, MMC } },
691 { 0xFF804018, 0, 32, 8, /* INT2PRI6 */
692 { HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22 } },
693 { 0xFF80401C, 0, 32, 8, /* INT2PRI7 */
694 { HPBDMAC23_25_27_28, I2C0, SRC0, SRC1 } },
695 { 0xFF804020, 0, 32, 8, /* INT2PRI8 */
696 { 0 /* ADIF */, VIN1, RESET_WDT, HIF } },
697 { 0xFF804024, 0, 32, 8, /* INT2PRI9 */
698 { ADMAC, FLCTL, GPIO0_3, GPIO4_5 } },
699 { 0xFF804028, 0, 32, 8, /* INT2PRI10 */
700 { STIF0, STIF1, VEU3F_VE3, GETHER } },
701 { 0xFF80402C, 0, 32, 8, /* INT2PRI11 */
702 { MTU2, RGPVG, MIMLB, IEBUS } },
703};
704
705static DECLARE_INTC_DESC(intc_desc, "sh7734", vectors, groups,
706 mask_registers, prio_registers, NULL);
707
708/* Support for external interrupt pins in IRQ mode */
709
710static struct intc_vect irq3210_vectors[] __initdata = {
711 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
712 INTC_VECT(IRQ2, 0x2C0), INTC_VECT(IRQ3, 0x300),
713};
714
715static struct intc_sense_reg irq3210_sense_registers[] __initdata = {
716 { 0xFF80201C, 32, 2, /* ICR1 */
717 { IRQ0, IRQ1, IRQ2, IRQ3, } },
718};
719
720static struct intc_mask_reg irq3210_ack_registers[] __initdata = {
721 { 0xFF802024, 0, 32, /* INTREQ */
722 { IRQ0, IRQ1, IRQ2, IRQ3, } },
723};
724
725static struct intc_mask_reg irq3210_mask_registers[] __initdata = {
726 { 0xFF802044, 0xFF802064, 32, /* INTMSK0 / INTMSKCLR0 */
727 { IRQ0, IRQ1, IRQ2, IRQ3, } },
728};
729
730static struct intc_prio_reg irq3210_prio_registers[] __initdata = {
731 { 0xFF802010, 0, 32, 4, /* INTPRI */
732 { IRQ0, IRQ1, IRQ2, IRQ3, } },
733};
734
735static DECLARE_INTC_DESC_ACK(intc_desc_irq3210, "sh7734-irq3210",
736 irq3210_vectors, NULL,
737 irq3210_mask_registers, irq3210_prio_registers,
738 irq3210_sense_registers, irq3210_ack_registers);
739
740/* External interrupt pins in IRL mode */
741
742static struct intc_vect vectors_irl3210[] __initdata = {
743 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
744 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
745 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
746 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
747 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
748 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
749 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
750 INTC_VECT(IRL0_HHHL, 0x3c0),
751};
752
753static DECLARE_INTC_DESC(intc_desc_irl3210, "sh7734-irl3210",
754 vectors_irl3210, NULL, mask_registers, NULL, NULL);
755
756#define INTC_ICR0 0xFF802000
757#define INTC_INTMSK0 0xFF802044
758#define INTC_INTMSK1 0xFF802048
759#define INTC_INTMSKCLR0 0xFF802064
760#define INTC_INTMSKCLR1 0xFF802068
761
762void __init plat_irq_setup(void)
763{
764 /* disable IRQ3-0 */
765 __raw_writel(0xF0000000, INTC_INTMSK0);
766
767 /* disable IRL3-0 */
768 __raw_writel(0x80000000, INTC_INTMSK1);
769
770 /* select IRL mode for IRL3-0 */
771 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0);
772
773 /* disable holding function, ie enable "SH-4 Mode (LVLMODE)" */
774 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
775
776 register_intc_controller(&intc_desc);
777}
778
779void __init plat_irq_setup_pins(int mode)
780{
781 switch (mode) {
782 case IRQ_MODE_IRQ3210:
783 /* select IRQ mode for IRL3-0 */
784 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
785 register_intc_controller(&intc_desc_irq3210);
786 break;
787 case IRQ_MODE_IRL3210:
788 /* enable IRL0-3 but don't provide any masking */
789 __raw_writel(0x80000000, INTC_INTMSKCLR1);
790 __raw_writel(0xf0000000, INTC_INTMSKCLR0);
791 break;
792 case IRQ_MODE_IRL3210_MASK:
793 /* enable IRL0-3 and mask using cpu intc controller */
794 __raw_writel(0x80000000, INTC_INTMSKCLR0);
795 register_intc_controller(&intc_desc_irl3210);
796 break;
797 default:
798 BUG();
799 }
800}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index c8836cffa21..fe45e4cb183 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -28,7 +28,7 @@ static struct plat_sci_port scif2_platform_data = {
28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
29 .scbrr_algo_id = SCBRR_ALGO_2, 29 .scbrr_algo_id = SCBRR_ALGO_2,
30 .type = PORT_SCIF, 30 .type = PORT_SCIF,
31 .irqs = { 40, 40, 40, 40 }, 31 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
32}; 32};
33 33
34static struct platform_device scif2_device = { 34static struct platform_device scif2_device = {
@@ -45,7 +45,7 @@ static struct plat_sci_port scif3_platform_data = {
45 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 45 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
46 .scbrr_algo_id = SCBRR_ALGO_2, 46 .scbrr_algo_id = SCBRR_ALGO_2,
47 .type = PORT_SCIF, 47 .type = PORT_SCIF,
48 .irqs = { 76, 76, 76, 76 }, 48 .irqs = SCIx_IRQ_MUXED(evt2irq(0xB80)),
49}; 49};
50 50
51static struct platform_device scif3_device = { 51static struct platform_device scif3_device = {
@@ -62,7 +62,7 @@ static struct plat_sci_port scif4_platform_data = {
62 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 62 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
63 .scbrr_algo_id = SCBRR_ALGO_2, 63 .scbrr_algo_id = SCBRR_ALGO_2,
64 .type = PORT_SCIF, 64 .type = PORT_SCIF,
65 .irqs = { 104, 104, 104, 104 }, 65 .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)),
66}; 66};
67 67
68static struct platform_device scif4_device = { 68static struct platform_device scif4_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 00113515f23..197e4c9a4a0 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -22,7 +22,7 @@ static struct plat_sci_port scif0_platform_data = {
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2, 23 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 24 .type = PORT_SCIF,
25 .irqs = { 40, 40, 40, 40 }, 25 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
27}; 27};
28 28
@@ -40,7 +40,7 @@ static struct plat_sci_port scif1_platform_data = {
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
41 .scbrr_algo_id = SCBRR_ALGO_2, 41 .scbrr_algo_id = SCBRR_ALGO_2,
42 .type = PORT_SCIF, 42 .type = PORT_SCIF,
43 .irqs = { 76, 76, 76, 76 }, 43 .irqs = SCIx_IRQ_MUXED(evt2irq(0xB80)),
44 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 44 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
45}; 45};
46 46
@@ -58,7 +58,7 @@ static struct plat_sci_port scif2_platform_data = {
58 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 58 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
59 .scbrr_algo_id = SCBRR_ALGO_2, 59 .scbrr_algo_id = SCBRR_ALGO_2,
60 .type = PORT_SCIF, 60 .type = PORT_SCIF,
61 .irqs = { 104, 104, 104, 104 }, 61 .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)),
62 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 62 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
63}; 63};
64 64
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 2c6aa22cf5f..46ea8703d18 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -20,7 +20,7 @@ static struct plat_sci_port scif0_platform_data = {
20 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 20 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
21 .scbrr_algo_id = SCBRR_ALGO_2, 21 .scbrr_algo_id = SCBRR_ALGO_2,
22 .type = PORT_SCIF, 22 .type = PORT_SCIF,
23 .irqs = { 61, 61, 61, 61 }, 23 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9A0)),
24}; 24};
25 25
26static struct platform_device scif0_device = { 26static struct platform_device scif0_device = {
@@ -37,7 +37,7 @@ static struct plat_sci_port scif1_platform_data = {
37 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 37 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
38 .scbrr_algo_id = SCBRR_ALGO_2, 38 .scbrr_algo_id = SCBRR_ALGO_2,
39 .type = PORT_SCIF, 39 .type = PORT_SCIF,
40 .irqs = { 62, 62, 62, 62 }, 40 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9C0)),
41}; 41};
42 42
43static struct platform_device scif1_device = { 43static struct platform_device scif1_device = {
@@ -54,7 +54,7 @@ static struct plat_sci_port scif2_platform_data = {
54 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 54 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
55 .scbrr_algo_id = SCBRR_ALGO_2, 55 .scbrr_algo_id = SCBRR_ALGO_2,
56 .type = PORT_SCIF, 56 .type = PORT_SCIF,
57 .irqs = { 63, 63, 63, 63 }, 57 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9E0)),
58}; 58};
59 59
60static struct platform_device scif2_device = { 60static struct platform_device scif2_device = {
@@ -71,7 +71,7 @@ static struct plat_sci_port scif3_platform_data = {
71 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 71 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
72 .scbrr_algo_id = SCBRR_ALGO_2, 72 .scbrr_algo_id = SCBRR_ALGO_2,
73 .type = PORT_SCIF, 73 .type = PORT_SCIF,
74 .irqs = { 64, 64, 64, 64 }, 74 .irqs = SCIx_IRQ_MUXED(evt2irq(0xA00)),
75}; 75};
76 76
77static struct platform_device scif3_device = { 77static struct platform_device scif3_device = {
@@ -88,7 +88,7 @@ static struct plat_sci_port scif4_platform_data = {
88 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 88 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
89 .scbrr_algo_id = SCBRR_ALGO_2, 89 .scbrr_algo_id = SCBRR_ALGO_2,
90 .type = PORT_SCIF, 90 .type = PORT_SCIF,
91 .irqs = { 65, 65, 65, 65 }, 91 .irqs = SCIx_IRQ_MUXED(evt2irq(0xA20)),
92}; 92};
93 93
94static struct platform_device scif4_device = { 94static struct platform_device scif4_device = {
@@ -105,7 +105,7 @@ static struct plat_sci_port scif5_platform_data = {
105 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 105 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
106 .scbrr_algo_id = SCBRR_ALGO_2, 106 .scbrr_algo_id = SCBRR_ALGO_2,
107 .type = PORT_SCIF, 107 .type = PORT_SCIF,
108 .irqs = { 66, 66, 66, 66 }, 108 .irqs = SCIx_IRQ_MUXED(evt2irq(0xA40)),
109}; 109};
110 110
111static struct platform_device scif5_device = { 111static struct platform_device scif5_device = {
@@ -122,7 +122,7 @@ static struct plat_sci_port scif6_platform_data = {
122 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 122 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
123 .scbrr_algo_id = SCBRR_ALGO_2, 123 .scbrr_algo_id = SCBRR_ALGO_2,
124 .type = PORT_SCIF, 124 .type = PORT_SCIF,
125 .irqs = { 67, 67, 67, 67 }, 125 .irqs = SCIx_IRQ_MUXED(evt2irq(0xA60)),
126}; 126};
127 127
128static struct platform_device scif6_device = { 128static struct platform_device scif6_device = {
@@ -139,7 +139,7 @@ static struct plat_sci_port scif7_platform_data = {
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
140 .scbrr_algo_id = SCBRR_ALGO_2, 140 .scbrr_algo_id = SCBRR_ALGO_2,
141 .type = PORT_SCIF, 141 .type = PORT_SCIF,
142 .irqs = { 68, 68, 68, 68 }, 142 .irqs = SCIx_IRQ_MUXED(evt2irq(0xA80)),
143}; 143};
144 144
145static struct platform_device scif7_device = { 145static struct platform_device scif7_device = {
@@ -156,7 +156,7 @@ static struct plat_sci_port scif8_platform_data = {
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
157 .scbrr_algo_id = SCBRR_ALGO_2, 157 .scbrr_algo_id = SCBRR_ALGO_2,
158 .type = PORT_SCIF, 158 .type = PORT_SCIF,
159 .irqs = { 69, 69, 69, 69 }, 159 .irqs = SCIx_IRQ_MUXED(evt2irq(0xAA0)),
160}; 160};
161 161
162static struct platform_device scif8_device = { 162static struct platform_device scif8_device = {
@@ -173,7 +173,7 @@ static struct plat_sci_port scif9_platform_data = {
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
174 .scbrr_algo_id = SCBRR_ALGO_2, 174 .scbrr_algo_id = SCBRR_ALGO_2,
175 .type = PORT_SCIF, 175 .type = PORT_SCIF,
176 .irqs = { 70, 70, 70, 70 }, 176 .irqs = SCIx_IRQ_MUXED(evt2irq(0xAC0)),
177}; 177};
178 178
179static struct platform_device scif9_device = { 179static struct platform_device scif9_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 81588ef15a6..304339fe7a2 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -24,7 +24,7 @@ static struct plat_sci_port scif0_platform_data = {
24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
25 .scbrr_algo_id = SCBRR_ALGO_1, 25 .scbrr_algo_id = SCBRR_ALGO_1,
26 .type = PORT_SCIF, 26 .type = PORT_SCIF,
27 .irqs = { 40, 40, 40, 40 }, 27 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
28 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 28 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
29}; 29};
30 30
@@ -42,7 +42,7 @@ static struct plat_sci_port scif1_platform_data = {
42 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 42 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
43 .scbrr_algo_id = SCBRR_ALGO_1, 43 .scbrr_algo_id = SCBRR_ALGO_1,
44 .type = PORT_SCIF, 44 .type = PORT_SCIF,
45 .irqs = { 44, 44, 44, 44 }, 45 .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)),
46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
47}; 47};
48 48
@@ -60,7 +60,7 @@ static struct plat_sci_port scif2_platform_data = {
60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
61 .scbrr_algo_id = SCBRR_ALGO_1, 61 .scbrr_algo_id = SCBRR_ALGO_1,
62 .type = PORT_SCIF, 62 .type = PORT_SCIF,
63 .irqs = { 60, 60, 60, 60 }, 63 .irqs = SCIx_IRQ_MUXED(evt2irq(0x980)),
64 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 64 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
65}; 65};
66 66
@@ -78,7 +78,7 @@ static struct plat_sci_port scif3_platform_data = {
78 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 78 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
79 .scbrr_algo_id = SCBRR_ALGO_1, 79 .scbrr_algo_id = SCBRR_ALGO_1,
80 .type = PORT_SCIF, 80 .type = PORT_SCIF,
81 .irqs = { 61, 61, 61, 61 }, 81 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9A0)),
82 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 82 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
83}; 83};
84 84
@@ -96,7 +96,7 @@ static struct plat_sci_port scif4_platform_data = {
96 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 96 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
97 .scbrr_algo_id = SCBRR_ALGO_1, 97 .scbrr_algo_id = SCBRR_ALGO_1,
98 .type = PORT_SCIF, 98 .type = PORT_SCIF,
99 .irqs = { 62, 62, 62, 62 }, 99 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9C0)),
100 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 100 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
101}; 101};
102 102
@@ -114,7 +114,7 @@ static struct plat_sci_port scif5_platform_data = {
114 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 114 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
115 .scbrr_algo_id = SCBRR_ALGO_1, 115 .scbrr_algo_id = SCBRR_ALGO_1,
116 .type = PORT_SCIF, 116 .type = PORT_SCIF,
117 .irqs = { 63, 63, 63, 63 }, 117 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9E0)),
118 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 118 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
119}; 119};
120 120
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 599022d73b2..9befe2dcf45 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -53,7 +53,7 @@ static struct plat_sci_port scif1_platform_data = {
53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
54 .scbrr_algo_id = SCBRR_ALGO_1, 54 .scbrr_algo_id = SCBRR_ALGO_1,
55 .type = PORT_SCIF, 55 .type = PORT_SCIF,
56 .irqs = { 44, 44, 44, 44 }, 56 .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)),
57 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 57 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
58}; 58};
59 59
@@ -71,7 +71,7 @@ static struct plat_sci_port scif2_platform_data = {
71 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 71 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
72 .scbrr_algo_id = SCBRR_ALGO_1, 72 .scbrr_algo_id = SCBRR_ALGO_1,
73 .type = PORT_SCIF, 73 .type = PORT_SCIF,
74 .irqs = { 50, 50, 50, 50 }, 74 .irqs = SCIx_IRQ_MUXED(evt2irq(0x840)),
75 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 75 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
76}; 76};
77 77
@@ -89,7 +89,7 @@ static struct plat_sci_port scif3_platform_data = {
89 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 89 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
90 .scbrr_algo_id = SCBRR_ALGO_1, 90 .scbrr_algo_id = SCBRR_ALGO_1,
91 .type = PORT_SCIF, 91 .type = PORT_SCIF,
92 .irqs = { 51, 51, 51, 51 }, 92 .irqs = SCIx_IRQ_MUXED(evt2irq(0x860)),
93 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 93 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
94}; 94};
95 95
@@ -107,7 +107,7 @@ static struct plat_sci_port scif4_platform_data = {
107 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 107 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
108 .scbrr_algo_id = SCBRR_ALGO_1, 108 .scbrr_algo_id = SCBRR_ALGO_1,
109 .type = PORT_SCIF, 109 .type = PORT_SCIF,
110 .irqs = { 52, 52, 52, 52 }, 110 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
111 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 111 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
112}; 112};
113 113
@@ -125,7 +125,7 @@ static struct plat_sci_port scif5_platform_data = {
125 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 125 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
126 .scbrr_algo_id = SCBRR_ALGO_1, 126 .scbrr_algo_id = SCBRR_ALGO_1,
127 .type = PORT_SCIF, 127 .type = PORT_SCIF,
128 .irqs = { 53, 53, 53, 53 }, 128 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8A0)),
129 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 129 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
130}; 130};
131 131
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index 324eef93c90..98e88a6112b 100644
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -129,6 +129,8 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
129 int si_code; 129 int si_code;
130 int fault; 130 int fault;
131 siginfo_t info; 131 siginfo_t info;
132 unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
133 (writeaccess ? FAULT_FLAG_WRITE : 0));
132 134
133 tsk = current; 135 tsk = current;
134 mm = tsk->mm; 136 mm = tsk->mm;
@@ -169,6 +171,7 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
169 if (in_atomic() || !mm) 171 if (in_atomic() || !mm)
170 goto no_context; 172 goto no_context;
171 173
174retry:
172 down_read(&mm->mmap_sem); 175 down_read(&mm->mmap_sem);
173 176
174 vma = find_vma(mm, address); 177 vma = find_vma(mm, address);
@@ -200,7 +203,11 @@ good_area:
200 * make sure we exit gracefully rather than endlessly redo 203 * make sure we exit gracefully rather than endlessly redo
201 * the fault. 204 * the fault.
202 */ 205 */
203 fault = handle_mm_fault(mm, vma, address, writeaccess ? FAULT_FLAG_WRITE : 0); 206 fault = handle_mm_fault(mm, vma, address, flags);
207
208 if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
209 return;
210
204 if (unlikely(fault & VM_FAULT_ERROR)) { 211 if (unlikely(fault & VM_FAULT_ERROR)) {
205 if (fault & VM_FAULT_OOM) 212 if (fault & VM_FAULT_OOM)
206 goto out_of_memory; 213 goto out_of_memory;
@@ -208,14 +215,27 @@ good_area:
208 goto do_sigbus; 215 goto do_sigbus;
209 BUG(); 216 BUG();
210 } 217 }
211 if (fault & VM_FAULT_MAJOR) { 218
212 tsk->maj_flt++; 219 if (flags & FAULT_FLAG_ALLOW_RETRY) {
213 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 220 if (fault & VM_FAULT_MAJOR) {
214 regs, address); 221 tsk->maj_flt++;
215 } else { 222 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
216 tsk->min_flt++; 223 regs, address);
217 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 224 } else {
218 regs, address); 225 tsk->min_flt++;
226 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1,
227 regs, address);
228 }
229 if (fault & VM_FAULT_RETRY) {
230 flags &= ~FAULT_FLAG_ALLOW_RETRY;
231
232 /*
233 * No need to up_read(&mm->mmap_sem) as we would
234 * have already released it in __lock_page_or_retry
235 * in mm/filemap.c.
236 */
237 goto retry;
238 }
219 } 239 }
220 240
221 up_read(&mm->mmap_sem); 241 up_read(&mm->mmap_sem);
diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c
index 11c5a18f10e..605dc65dc66 100644
--- a/arch/sh/mm/tlbflush_64.c
+++ b/arch/sh/mm/tlbflush_64.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2000, 2001 Paolo Alberelli 4 * Copyright (C) 2000, 2001 Paolo Alberelli
5 * Copyright (C) 2003 Richard Curnow (/proc/tlb, bug fixes) 5 * Copyright (C) 2003 Richard Curnow (/proc/tlb, bug fixes)
6 * Copyright (C) 2003 - 2009 Paul Mundt 6 * Copyright (C) 2003 - 2012 Paul Mundt
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -28,33 +28,6 @@
28#include <asm/pgalloc.h> 28#include <asm/pgalloc.h>
29#include <asm/mmu_context.h> 29#include <asm/mmu_context.h>
30 30
31extern void die(const char *,struct pt_regs *,long);
32
33#define PFLAG(val,flag) (( (val) & (flag) ) ? #flag : "" )
34#define PPROT(flag) PFLAG(pgprot_val(prot),flag)
35
36static inline void print_prots(pgprot_t prot)
37{
38 printk("prot is 0x%016llx\n",pgprot_val(prot));
39
40 printk("%s %s %s %s %s\n",PPROT(_PAGE_SHARED),PPROT(_PAGE_READ),
41 PPROT(_PAGE_EXECUTE),PPROT(_PAGE_WRITE),PPROT(_PAGE_USER));
42}
43
44static inline void print_vma(struct vm_area_struct *vma)
45{
46 printk("vma start 0x%08lx\n", vma->vm_start);
47 printk("vma end 0x%08lx\n", vma->vm_end);
48
49 print_prots(vma->vm_page_prot);
50 printk("vm_flags 0x%08lx\n", vma->vm_flags);
51}
52
53static inline void print_task(struct task_struct *tsk)
54{
55 printk("Task pid %d\n", task_pid_nr(tsk));
56}
57
58static pte_t *lookup_pte(struct mm_struct *mm, unsigned long address) 31static pte_t *lookup_pte(struct mm_struct *mm, unsigned long address)
59{ 32{
60 pgd_t *dir; 33 pgd_t *dir;
@@ -95,6 +68,8 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long writeaccess,
95 struct mm_struct *mm; 68 struct mm_struct *mm;
96 struct vm_area_struct * vma; 69 struct vm_area_struct * vma;
97 const struct exception_table_entry *fixup; 70 const struct exception_table_entry *fixup;
71 unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
72 (writeaccess ? FAULT_FLAG_WRITE : 0));
98 pte_t *pte; 73 pte_t *pte;
99 int fault; 74 int fault;
100 75
@@ -124,47 +99,20 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long writeaccess,
124 if (in_atomic() || !mm) 99 if (in_atomic() || !mm)
125 goto no_context; 100 goto no_context;
126 101
102retry:
127 /* TLB misses upon some cache flushes get done under cli() */ 103 /* TLB misses upon some cache flushes get done under cli() */
128 down_read(&mm->mmap_sem); 104 down_read(&mm->mmap_sem);
129 105
130 vma = find_vma(mm, address); 106 vma = find_vma(mm, address);
131 107 if (!vma)
132 if (!vma) {
133#ifdef DEBUG_FAULT
134 print_task(tsk);
135 printk("%s:%d fault, address is 0x%08x PC %016Lx textaccess %d writeaccess %d\n",
136 __func__, __LINE__,
137 address,regs->pc,textaccess,writeaccess);
138 show_regs(regs);
139#endif
140 goto bad_area; 108 goto bad_area;
141 } 109 if (vma->vm_start <= address)
142 if (vma->vm_start <= address) {
143 goto good_area; 110 goto good_area;
144 } 111 if (!(vma->vm_flags & VM_GROWSDOWN))
145
146 if (!(vma->vm_flags & VM_GROWSDOWN)) {
147#ifdef DEBUG_FAULT
148 print_task(tsk);
149 printk("%s:%d fault, address is 0x%08x PC %016Lx textaccess %d writeaccess %d\n",
150 __func__, __LINE__,
151 address,regs->pc,textaccess,writeaccess);
152 show_regs(regs);
153
154 print_vma(vma);
155#endif
156 goto bad_area; 112 goto bad_area;
157 } 113 if (expand_stack(vma, address))
158 if (expand_stack(vma, address)) {
159#ifdef DEBUG_FAULT
160 print_task(tsk);
161 printk("%s:%d fault, address is 0x%08x PC %016Lx textaccess %d writeaccess %d\n",
162 __func__, __LINE__,
163 address,regs->pc,textaccess,writeaccess);
164 show_regs(regs);
165#endif
166 goto bad_area; 114 goto bad_area;
167 } 115
168/* 116/*
169 * Ok, we have a good vm_area for this memory access, so 117 * Ok, we have a good vm_area for this memory access, so
170 * we can handle it.. 118 * we can handle it..
@@ -188,7 +136,11 @@ good_area:
188 * make sure we exit gracefully rather than endlessly redo 136 * make sure we exit gracefully rather than endlessly redo
189 * the fault. 137 * the fault.
190 */ 138 */
191 fault = handle_mm_fault(mm, vma, address, writeaccess ? FAULT_FLAG_WRITE : 0); 139 fault = handle_mm_fault(mm, vma, address, flags);
140
141 if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
142 return;
143
192 if (unlikely(fault & VM_FAULT_ERROR)) { 144 if (unlikely(fault & VM_FAULT_ERROR)) {
193 if (fault & VM_FAULT_OOM) 145 if (fault & VM_FAULT_OOM)
194 goto out_of_memory; 146 goto out_of_memory;
@@ -197,14 +149,27 @@ good_area:
197 BUG(); 149 BUG();
198 } 150 }
199 151
200 if (fault & VM_FAULT_MAJOR) { 152 if (flags & FAULT_FLAG_ALLOW_RETRY) {
201 tsk->maj_flt++; 153 if (fault & VM_FAULT_MAJOR) {
202 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 154 tsk->maj_flt++;
203 regs, address); 155 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
204 } else { 156 regs, address);
205 tsk->min_flt++; 157 } else {
206 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 158 tsk->min_flt++;
207 regs, address); 159 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1,
160 regs, address);
161 }
162
163 if (fault & VM_FAULT_RETRY) {
164 flags &= ~FAULT_FLAG_ALLOW_RETRY;
165
166 /*
167 * No need to up_read(&mm->mmap_sem) as we would
168 * have already released it in __lock_page_or_retry
169 * in mm/filemap.c.
170 */
171 goto retry;
172 }
208 } 173 }
209 174
210 /* If we get here, the page fault has been handled. Do the TLB refill 175 /* If we get here, the page fault has been handled. Do the TLB refill
@@ -231,9 +196,6 @@ no_pte:
231 * Fix it, but check if it's kernel or user first.. 196 * Fix it, but check if it's kernel or user first..
232 */ 197 */
233bad_area: 198bad_area:
234#ifdef DEBUG_FAULT
235 printk("fault:bad area\n");
236#endif
237 up_read(&mm->mmap_sem); 199 up_read(&mm->mmap_sem);
238 200
239 if (user_mode(regs)) { 201 if (user_mode(regs)) {
@@ -246,9 +208,6 @@ bad_area:
246 printk("user mode bad_area address=%08lx pid=%d (%s) pc=%08lx\n", 208 printk("user mode bad_area address=%08lx pid=%d (%s) pc=%08lx\n",
247 address, task_pid_nr(current), current->comm, 209 address, task_pid_nr(current), current->comm,
248 (unsigned long) regs->pc); 210 (unsigned long) regs->pc);
249#if 0
250 show_regs(regs);
251#endif
252 } 211 }
253 if (is_global_init(tsk)) { 212 if (is_global_init(tsk)) {
254 panic("INIT had user mode bad_area\n"); 213 panic("INIT had user mode bad_area\n");
@@ -263,9 +222,6 @@ bad_area:
263 } 222 }
264 223
265no_context: 224no_context:
266#ifdef DEBUG_FAULT
267 printk("fault:No context\n");
268#endif
269 /* Are we prepared to handle this kernel fault? */ 225 /* Are we prepared to handle this kernel fault? */
270 fixup = search_exception_tables(regs->pc); 226 fixup = search_exception_tables(regs->pc);
271 if (fixup) { 227 if (fixup) {
diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c
index aba6b958b2a..19f56058742 100644
--- a/arch/sparc/kernel/leon_pci.c
+++ b/arch/sparc/kernel/leon_pci.c
@@ -45,7 +45,6 @@ void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
45 45
46void __devinit pcibios_fixup_bus(struct pci_bus *pbus) 46void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
47{ 47{
48 struct leon_pci_info *info = pbus->sysdata;
49 struct pci_dev *dev; 48 struct pci_dev *dev;
50 int i, has_io, has_mem; 49 int i, has_io, has_mem;
51 u16 cmd; 50 u16 cmd;
@@ -111,18 +110,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
111 return pci_enable_resources(dev, mask); 110 return pci_enable_resources(dev, mask);
112} 111}
113 112
114struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
115{
116 /*
117 * Currently the OpenBoot nodes are not connected with the PCI device,
118 * this is because the LEON PROM does not create PCI nodes. Eventually
119 * this will change and the same approach as pcic.c can be used to
120 * match PROM nodes with pci devices.
121 */
122 return NULL;
123}
124EXPORT_SYMBOL(pci_device_to_OF_node);
125
126void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) 113void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
127{ 114{
128#ifdef CONFIG_PCI_DEBUG 115#ifdef CONFIG_PCI_DEBUG
diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c
index 7705c6731e2..df3155a1799 100644
--- a/arch/sparc/mm/fault_32.c
+++ b/arch/sparc/mm/fault_32.c
@@ -225,6 +225,8 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write,
225 unsigned long g2; 225 unsigned long g2;
226 int from_user = !(regs->psr & PSR_PS); 226 int from_user = !(regs->psr & PSR_PS);
227 int fault, code; 227 int fault, code;
228 unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
229 (write ? FAULT_FLAG_WRITE : 0));
228 230
229 if(text_fault) 231 if(text_fault)
230 address = regs->pc; 232 address = regs->pc;
@@ -251,6 +253,7 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write,
251 253
252 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address); 254 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
253 255
256retry:
254 down_read(&mm->mmap_sem); 257 down_read(&mm->mmap_sem);
255 258
256 /* 259 /*
@@ -289,7 +292,11 @@ good_area:
289 * make sure we exit gracefully rather than endlessly redo 292 * make sure we exit gracefully rather than endlessly redo
290 * the fault. 293 * the fault.
291 */ 294 */
292 fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0); 295 fault = handle_mm_fault(mm, vma, address, flags);
296
297 if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
298 return;
299
293 if (unlikely(fault & VM_FAULT_ERROR)) { 300 if (unlikely(fault & VM_FAULT_ERROR)) {
294 if (fault & VM_FAULT_OOM) 301 if (fault & VM_FAULT_OOM)
295 goto out_of_memory; 302 goto out_of_memory;
@@ -297,13 +304,29 @@ good_area:
297 goto do_sigbus; 304 goto do_sigbus;
298 BUG(); 305 BUG();
299 } 306 }
300 if (fault & VM_FAULT_MAJOR) { 307
301 current->maj_flt++; 308 if (flags & FAULT_FLAG_ALLOW_RETRY) {
302 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, address); 309 if (fault & VM_FAULT_MAJOR) {
303 } else { 310 current->maj_flt++;
304 current->min_flt++; 311 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ,
305 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, address); 312 1, regs, address);
313 } else {
314 current->min_flt++;
315 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN,
316 1, regs, address);
317 }
318 if (fault & VM_FAULT_RETRY) {
319 flags &= ~FAULT_FLAG_ALLOW_RETRY;
320
321 /* No need to up_read(&mm->mmap_sem) as we would
322 * have already released it in __lock_page_or_retry
323 * in mm/filemap.c.
324 */
325
326 goto retry;
327 }
306 } 328 }
329
307 up_read(&mm->mmap_sem); 330 up_read(&mm->mmap_sem);
308 return; 331 return;
309 332
diff --git a/arch/sparc/mm/fault_64.c b/arch/sparc/mm/fault_64.c
index 504c0622f72..1fe0429b631 100644
--- a/arch/sparc/mm/fault_64.c
+++ b/arch/sparc/mm/fault_64.c
@@ -279,6 +279,7 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs)
279 unsigned int insn = 0; 279 unsigned int insn = 0;
280 int si_code, fault_code, fault; 280 int si_code, fault_code, fault;
281 unsigned long address, mm_rss; 281 unsigned long address, mm_rss;
282 unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
282 283
283 fault_code = get_thread_fault_code(); 284 fault_code = get_thread_fault_code();
284 285
@@ -333,6 +334,8 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs)
333 insn = get_fault_insn(regs, insn); 334 insn = get_fault_insn(regs, insn);
334 goto handle_kernel_fault; 335 goto handle_kernel_fault;
335 } 336 }
337
338retry:
336 down_read(&mm->mmap_sem); 339 down_read(&mm->mmap_sem);
337 } 340 }
338 341
@@ -423,7 +426,12 @@ good_area:
423 goto bad_area; 426 goto bad_area;
424 } 427 }
425 428
426 fault = handle_mm_fault(mm, vma, address, (fault_code & FAULT_CODE_WRITE) ? FAULT_FLAG_WRITE : 0); 429 flags |= ((fault_code & FAULT_CODE_WRITE) ? FAULT_FLAG_WRITE : 0);
430 fault = handle_mm_fault(mm, vma, address, flags);
431
432 if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
433 return;
434
427 if (unlikely(fault & VM_FAULT_ERROR)) { 435 if (unlikely(fault & VM_FAULT_ERROR)) {
428 if (fault & VM_FAULT_OOM) 436 if (fault & VM_FAULT_OOM)
429 goto out_of_memory; 437 goto out_of_memory;
@@ -431,12 +439,27 @@ good_area:
431 goto do_sigbus; 439 goto do_sigbus;
432 BUG(); 440 BUG();
433 } 441 }
434 if (fault & VM_FAULT_MAJOR) { 442
435 current->maj_flt++; 443 if (flags & FAULT_FLAG_ALLOW_RETRY) {
436 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, address); 444 if (fault & VM_FAULT_MAJOR) {
437 } else { 445 current->maj_flt++;
438 current->min_flt++; 446 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ,
439 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, address); 447 1, regs, address);
448 } else {
449 current->min_flt++;
450 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN,
451 1, regs, address);
452 }
453 if (fault & VM_FAULT_RETRY) {
454 flags &= ~FAULT_FLAG_ALLOW_RETRY;
455
456 /* No need to up_read(&mm->mmap_sem) as we would
457 * have already released it in __lock_page_or_retry
458 * in mm/filemap.c.
459 */
460
461 goto retry;
462 }
440 } 463 }
441 up_read(&mm->mmap_sem); 464 up_read(&mm->mmap_sem);
442 465
diff --git a/arch/um/drivers/cow.h b/arch/um/drivers/cow.h
index dc36b222100..6673508f342 100644
--- a/arch/um/drivers/cow.h
+++ b/arch/um/drivers/cow.h
@@ -3,41 +3,6 @@
3 3
4#include <asm/types.h> 4#include <asm/types.h>
5 5
6#if defined(__KERNEL__)
7
8# include <asm/byteorder.h>
9
10# if defined(__BIG_ENDIAN)
11# define ntohll(x) (x)
12# define htonll(x) (x)
13# elif defined(__LITTLE_ENDIAN)
14# define ntohll(x) be64_to_cpu(x)
15# define htonll(x) cpu_to_be64(x)
16# else
17# error "Could not determine byte order"
18# endif
19
20#else
21/* For the definition of ntohl, htonl and __BYTE_ORDER */
22#include <endian.h>
23#include <netinet/in.h>
24#if defined(__BYTE_ORDER)
25
26# if __BYTE_ORDER == __BIG_ENDIAN
27# define ntohll(x) (x)
28# define htonll(x) (x)
29# elif __BYTE_ORDER == __LITTLE_ENDIAN
30# define ntohll(x) bswap_64(x)
31# define htonll(x) bswap_64(x)
32# else
33# error "Could not determine byte order: __BYTE_ORDER uncorrectly defined"
34# endif
35
36#else /* ! defined(__BYTE_ORDER) */
37# error "Could not determine byte order: __BYTE_ORDER not defined"
38#endif
39#endif /* ! defined(__KERNEL__) */
40
41extern int init_cow_file(int fd, char *cow_file, char *backing_file, 6extern int init_cow_file(int fd, char *cow_file, char *backing_file,
42 int sectorsize, int alignment, int *bitmap_offset_out, 7 int sectorsize, int alignment, int *bitmap_offset_out,
43 unsigned long *bitmap_len_out, int *data_offset_out); 8 unsigned long *bitmap_len_out, int *data_offset_out);
diff --git a/arch/um/drivers/cow_user.c b/arch/um/drivers/cow_user.c
index 9cbb426c0b9..0ee9cc6cc4c 100644
--- a/arch/um/drivers/cow_user.c
+++ b/arch/um/drivers/cow_user.c
@@ -8,11 +8,10 @@
8 * that. 8 * that.
9 */ 9 */
10#include <unistd.h> 10#include <unistd.h>
11#include <byteswap.h>
12#include <errno.h> 11#include <errno.h>
13#include <string.h> 12#include <string.h>
14#include <arpa/inet.h> 13#include <arpa/inet.h>
15#include <asm/types.h> 14#include <endian.h>
16#include "cow.h" 15#include "cow.h"
17#include "cow_sys.h" 16#include "cow_sys.h"
18 17
@@ -214,8 +213,8 @@ int write_cow_header(char *cow_file, int fd, char *backing_file,
214 "header\n"); 213 "header\n");
215 goto out; 214 goto out;
216 } 215 }
217 header->magic = htonl(COW_MAGIC); 216 header->magic = htobe32(COW_MAGIC);
218 header->version = htonl(COW_VERSION); 217 header->version = htobe32(COW_VERSION);
219 218
220 err = -EINVAL; 219 err = -EINVAL;
221 if (strlen(backing_file) > sizeof(header->backing_file) - 1) { 220 if (strlen(backing_file) > sizeof(header->backing_file) - 1) {
@@ -246,10 +245,10 @@ int write_cow_header(char *cow_file, int fd, char *backing_file,
246 goto out_free; 245 goto out_free;
247 } 246 }
248 247
249 header->mtime = htonl(modtime); 248 header->mtime = htobe32(modtime);
250 header->size = htonll(*size); 249 header->size = htobe64(*size);
251 header->sectorsize = htonl(sectorsize); 250 header->sectorsize = htobe32(sectorsize);
252 header->alignment = htonl(alignment); 251 header->alignment = htobe32(alignment);
253 header->cow_format = COW_BITMAP; 252 header->cow_format = COW_BITMAP;
254 253
255 err = cow_write_file(fd, header, sizeof(*header)); 254 err = cow_write_file(fd, header, sizeof(*header));
@@ -301,8 +300,8 @@ int read_cow_header(int (*reader)(__u64, char *, int, void *), void *arg,
301 magic = header->v1.magic; 300 magic = header->v1.magic;
302 if (magic == COW_MAGIC) 301 if (magic == COW_MAGIC)
303 version = header->v1.version; 302 version = header->v1.version;
304 else if (magic == ntohl(COW_MAGIC)) 303 else if (magic == be32toh(COW_MAGIC))
305 version = ntohl(header->v1.version); 304 version = be32toh(header->v1.version);
306 /* No error printed because the non-COW case comes through here */ 305 /* No error printed because the non-COW case comes through here */
307 else goto out; 306 else goto out;
308 307
@@ -327,9 +326,9 @@ int read_cow_header(int (*reader)(__u64, char *, int, void *), void *arg,
327 "header\n"); 326 "header\n");
328 goto out; 327 goto out;
329 } 328 }
330 *mtime_out = ntohl(header->v2.mtime); 329 *mtime_out = be32toh(header->v2.mtime);
331 *size_out = ntohll(header->v2.size); 330 *size_out = be64toh(header->v2.size);
332 *sectorsize_out = ntohl(header->v2.sectorsize); 331 *sectorsize_out = be32toh(header->v2.sectorsize);
333 *bitmap_offset_out = sizeof(header->v2); 332 *bitmap_offset_out = sizeof(header->v2);
334 *align_out = *sectorsize_out; 333 *align_out = *sectorsize_out;
335 file = header->v2.backing_file; 334 file = header->v2.backing_file;
@@ -341,10 +340,10 @@ int read_cow_header(int (*reader)(__u64, char *, int, void *), void *arg,
341 "header\n"); 340 "header\n");
342 goto out; 341 goto out;
343 } 342 }
344 *mtime_out = ntohl(header->v3.mtime); 343 *mtime_out = be32toh(header->v3.mtime);
345 *size_out = ntohll(header->v3.size); 344 *size_out = be64toh(header->v3.size);
346 *sectorsize_out = ntohl(header->v3.sectorsize); 345 *sectorsize_out = be32toh(header->v3.sectorsize);
347 *align_out = ntohl(header->v3.alignment); 346 *align_out = be32toh(header->v3.alignment);
348 if (*align_out == 0) { 347 if (*align_out == 0) {
349 cow_printf("read_cow_header - invalid COW header, " 348 cow_printf("read_cow_header - invalid COW header, "
350 "align == 0\n"); 349 "align == 0\n");
@@ -366,16 +365,16 @@ int read_cow_header(int (*reader)(__u64, char *, int, void *), void *arg,
366 * this was used until Dec2005 - 64bits are needed to represent 365 * this was used until Dec2005 - 64bits are needed to represent
367 * 2038+. I.e. we can safely do this truncating cast. 366 * 2038+. I.e. we can safely do this truncating cast.
368 * 367 *
369 * Additionally, we must use ntohl() instead of ntohll(), since 368 * Additionally, we must use be32toh() instead of be64toh(), since
370 * the program used to use the former (tested - I got mtime 369 * the program used to use the former (tested - I got mtime
371 * mismatch "0 vs whatever"). 370 * mismatch "0 vs whatever").
372 * 371 *
373 * Ever heard about bug-to-bug-compatibility ? ;-) */ 372 * Ever heard about bug-to-bug-compatibility ? ;-) */
374 *mtime_out = (time32_t) ntohl(header->v3_b.mtime); 373 *mtime_out = (time32_t) be32toh(header->v3_b.mtime);
375 374
376 *size_out = ntohll(header->v3_b.size); 375 *size_out = be64toh(header->v3_b.size);
377 *sectorsize_out = ntohl(header->v3_b.sectorsize); 376 *sectorsize_out = be32toh(header->v3_b.sectorsize);
378 *align_out = ntohl(header->v3_b.alignment); 377 *align_out = be32toh(header->v3_b.alignment);
379 if (*align_out == 0) { 378 if (*align_out == 0) {
380 cow_printf("read_cow_header - invalid COW header, " 379 cow_printf("read_cow_header - invalid COW header, "
381 "align == 0\n"); 380 "align == 0\n");
diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c
index e672bd6d43e..43b39d61b53 100644
--- a/arch/um/drivers/mconsole_kern.c
+++ b/arch/um/drivers/mconsole_kern.c
@@ -22,6 +22,7 @@
22#include <linux/workqueue.h> 22#include <linux/workqueue.h>
23#include <linux/mutex.h> 23#include <linux/mutex.h>
24#include <asm/uaccess.h> 24#include <asm/uaccess.h>
25#include <asm/switch_to.h>
25 26
26#include "init.h" 27#include "init.h"
27#include "irq_kern.h" 28#include "irq_kern.h"
diff --git a/arch/um/include/asm/Kbuild b/arch/um/include/asm/Kbuild
index 8419f5cf2ac..fff24352255 100644
--- a/arch/um/include/asm/Kbuild
+++ b/arch/um/include/asm/Kbuild
@@ -1,3 +1,4 @@
1generic-y += bug.h cputime.h device.h emergency-restart.h futex.h hardirq.h 1generic-y += bug.h cputime.h device.h emergency-restart.h futex.h hardirq.h
2generic-y += hw_irq.h irq_regs.h kdebug.h percpu.h sections.h topology.h xor.h 2generic-y += hw_irq.h irq_regs.h kdebug.h percpu.h sections.h topology.h xor.h
3generic-y += ftrace.h pci.h io.h param.h delay.h mutex.h current.h 3generic-y += ftrace.h pci.h io.h param.h delay.h mutex.h current.h exec.h
4generic-y += switch_to.h
diff --git a/arch/um/kernel/Makefile b/arch/um/kernel/Makefile
index 492bc4c1b62..65a1c3d690e 100644
--- a/arch/um/kernel/Makefile
+++ b/arch/um/kernel/Makefile
@@ -3,9 +3,10 @@
3# Licensed under the GPL 3# Licensed under the GPL
4# 4#
5 5
6CPPFLAGS_vmlinux.lds := -DSTART=$(LDS_START) \ 6CPPFLAGS_vmlinux.lds := -DSTART=$(LDS_START) \
7 -DELF_ARCH=$(LDS_ELF_ARCH) \ 7 -DELF_ARCH=$(LDS_ELF_ARCH) \
8 -DELF_FORMAT=$(LDS_ELF_FORMAT) 8 -DELF_FORMAT=$(LDS_ELF_FORMAT) \
9 $(LDS_EXTRA)
9extra-y := vmlinux.lds 10extra-y := vmlinux.lds
10clean-files := 11clean-files :=
11 12
diff --git a/arch/um/kernel/process.c b/arch/um/kernel/process.c
index f386d04a84a..2b73dedb44c 100644
--- a/arch/um/kernel/process.c
+++ b/arch/um/kernel/process.c
@@ -88,11 +88,8 @@ static inline void set_current(struct task_struct *task)
88 88
89extern void arch_switch_to(struct task_struct *to); 89extern void arch_switch_to(struct task_struct *to);
90 90
91void *_switch_to(void *prev, void *next, void *last) 91void *__switch_to(struct task_struct *from, struct task_struct *to)
92{ 92{
93 struct task_struct *from = prev;
94 struct task_struct *to = next;
95
96 to->thread.prev_sched = from; 93 to->thread.prev_sched = from;
97 set_current(to); 94 set_current(to);
98 95
@@ -111,7 +108,6 @@ void *_switch_to(void *prev, void *next, void *last)
111 } while (current->thread.saved_task); 108 } while (current->thread.saved_task);
112 109
113 return current->thread.prev_sched; 110 return current->thread.prev_sched;
114
115} 111}
116 112
117void interrupt_end(void) 113void interrupt_end(void)
diff --git a/arch/um/kernel/skas/mmu.c b/arch/um/kernel/skas/mmu.c
index 4947b319f53..0a49ef0c2bf 100644
--- a/arch/um/kernel/skas/mmu.c
+++ b/arch/um/kernel/skas/mmu.c
@@ -103,7 +103,6 @@ int init_new_context(struct task_struct *task, struct mm_struct *mm)
103 103
104void uml_setup_stubs(struct mm_struct *mm) 104void uml_setup_stubs(struct mm_struct *mm)
105{ 105{
106 struct page **pages;
107 int err, ret; 106 int err, ret;
108 107
109 if (!skas_needs_stub) 108 if (!skas_needs_stub)
diff --git a/arch/x86/Makefile.um b/arch/x86/Makefile.um
index 4be406abeef..36b62bc5263 100644
--- a/arch/x86/Makefile.um
+++ b/arch/x86/Makefile.um
@@ -14,6 +14,9 @@ LINK-y += $(call cc-option,-m32)
14 14
15export LDFLAGS 15export LDFLAGS
16 16
17LDS_EXTRA := -Ui386
18export LDS_EXTRA
19
17# First of all, tune CFLAGS for the specific CPU. This actually sets cflags-y. 20# First of all, tune CFLAGS for the specific CPU. This actually sets cflags-y.
18include $(srctree)/arch/x86/Makefile_32.cpu 21include $(srctree)/arch/x86/Makefile_32.cpu
19 22
diff --git a/arch/x86/um/asm/barrier.h b/arch/x86/um/asm/barrier.h
new file mode 100644
index 00000000000..7d01b8c56c0
--- /dev/null
+++ b/arch/x86/um/asm/barrier.h
@@ -0,0 +1,75 @@
1#ifndef _ASM_UM_BARRIER_H_
2#define _ASM_UM_BARRIER_H_
3
4#include <asm/asm.h>
5#include <asm/segment.h>
6#include <asm/cpufeature.h>
7#include <asm/cmpxchg.h>
8#include <asm/nops.h>
9
10#include <linux/kernel.h>
11#include <linux/irqflags.h>
12
13/*
14 * Force strict CPU ordering.
15 * And yes, this is required on UP too when we're talking
16 * to devices.
17 */
18#ifdef CONFIG_X86_32
19
20#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
21#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
22#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
23
24#else /* CONFIG_X86_32 */
25
26#define mb() asm volatile("mfence" : : : "memory")
27#define rmb() asm volatile("lfence" : : : "memory")
28#define wmb() asm volatile("sfence" : : : "memory")
29
30#endif /* CONFIG_X86_32 */
31
32#define read_barrier_depends() do { } while (0)
33
34#ifdef CONFIG_SMP
35
36#define smp_mb() mb()
37#ifdef CONFIG_X86_PPRO_FENCE
38#define smp_rmb() rmb()
39#else /* CONFIG_X86_PPRO_FENCE */
40#define smp_rmb() barrier()
41#endif /* CONFIG_X86_PPRO_FENCE */
42
43#ifdef CONFIG_X86_OOSTORE
44#define smp_wmb() wmb()
45#else /* CONFIG_X86_OOSTORE */
46#define smp_wmb() barrier()
47#endif /* CONFIG_X86_OOSTORE */
48
49#define smp_read_barrier_depends() read_barrier_depends()
50#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
51
52#else /* CONFIG_SMP */
53
54#define smp_mb() barrier()
55#define smp_rmb() barrier()
56#define smp_wmb() barrier()
57#define smp_read_barrier_depends() do { } while (0)
58#define set_mb(var, value) do { var = value; barrier(); } while (0)
59
60#endif /* CONFIG_SMP */
61
62/*
63 * Stop RDTSC speculation. This is needed when you need to use RDTSC
64 * (or get_cycles or vread that possibly accesses the TSC) in a defined
65 * code region.
66 *
67 * (Could use an alternative three way for this if there was one.)
68 */
69static inline void rdtsc_barrier(void)
70{
71 alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
72 alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
73}
74
75#endif
diff --git a/arch/x86/um/asm/system.h b/arch/x86/um/asm/system.h
deleted file mode 100644
index a459fd9b759..00000000000
--- a/arch/x86/um/asm/system.h
+++ /dev/null
@@ -1,135 +0,0 @@
1#ifndef _ASM_X86_SYSTEM_H_
2#define _ASM_X86_SYSTEM_H_
3
4#include <asm/asm.h>
5#include <asm/segment.h>
6#include <asm/cpufeature.h>
7#include <asm/cmpxchg.h>
8#include <asm/nops.h>
9
10#include <linux/kernel.h>
11#include <linux/irqflags.h>
12
13/* entries in ARCH_DLINFO: */
14#ifdef CONFIG_IA32_EMULATION
15# define AT_VECTOR_SIZE_ARCH 2
16#else
17# define AT_VECTOR_SIZE_ARCH 1
18#endif
19
20extern unsigned long arch_align_stack(unsigned long sp);
21
22void default_idle(void);
23
24/*
25 * Force strict CPU ordering.
26 * And yes, this is required on UP too when we're talking
27 * to devices.
28 */
29#ifdef CONFIG_X86_32
30/*
31 * Some non-Intel clones support out of order store. wmb() ceases to be a
32 * nop for these.
33 */
34#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
35#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
36#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
37#else
38#define mb() asm volatile("mfence":::"memory")
39#define rmb() asm volatile("lfence":::"memory")
40#define wmb() asm volatile("sfence" ::: "memory")
41#endif
42
43/**
44 * read_barrier_depends - Flush all pending reads that subsequents reads
45 * depend on.
46 *
47 * No data-dependent reads from memory-like regions are ever reordered
48 * over this barrier. All reads preceding this primitive are guaranteed
49 * to access memory (but not necessarily other CPUs' caches) before any
50 * reads following this primitive that depend on the data return by
51 * any of the preceding reads. This primitive is much lighter weight than
52 * rmb() on most CPUs, and is never heavier weight than is
53 * rmb().
54 *
55 * These ordering constraints are respected by both the local CPU
56 * and the compiler.
57 *
58 * Ordering is not guaranteed by anything other than these primitives,
59 * not even by data dependencies. See the documentation for
60 * memory_barrier() for examples and URLs to more information.
61 *
62 * For example, the following code would force ordering (the initial
63 * value of "a" is zero, "b" is one, and "p" is "&a"):
64 *
65 * <programlisting>
66 * CPU 0 CPU 1
67 *
68 * b = 2;
69 * memory_barrier();
70 * p = &b; q = p;
71 * read_barrier_depends();
72 * d = *q;
73 * </programlisting>
74 *
75 * because the read of "*q" depends on the read of "p" and these
76 * two reads are separated by a read_barrier_depends(). However,
77 * the following code, with the same initial values for "a" and "b":
78 *
79 * <programlisting>
80 * CPU 0 CPU 1
81 *
82 * a = 2;
83 * memory_barrier();
84 * b = 3; y = b;
85 * read_barrier_depends();
86 * x = a;
87 * </programlisting>
88 *
89 * does not enforce ordering, since there is no data dependency between
90 * the read of "a" and the read of "b". Therefore, on some CPUs, such
91 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
92 * in cases like this where there are no data dependencies.
93 **/
94
95#define read_barrier_depends() do { } while (0)
96
97#ifdef CONFIG_SMP
98#define smp_mb() mb()
99#ifdef CONFIG_X86_PPRO_FENCE
100# define smp_rmb() rmb()
101#else
102# define smp_rmb() barrier()
103#endif
104#ifdef CONFIG_X86_OOSTORE
105# define smp_wmb() wmb()
106#else
107# define smp_wmb() barrier()
108#endif
109#define smp_read_barrier_depends() read_barrier_depends()
110#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
111#else
112#define smp_mb() barrier()
113#define smp_rmb() barrier()
114#define smp_wmb() barrier()
115#define smp_read_barrier_depends() do { } while (0)
116#define set_mb(var, value) do { var = value; barrier(); } while (0)
117#endif
118
119/*
120 * Stop RDTSC speculation. This is needed when you need to use RDTSC
121 * (or get_cycles or vread that possibly accesses the TSC) in a defined
122 * code region.
123 *
124 * (Could use an alternative three way for this if there was one.)
125 */
126static inline void rdtsc_barrier(void)
127{
128 alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
129 alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
130}
131
132extern void *_switch_to(void *prev, void *next, void *last);
133#define switch_to(prev, next, last) prev = _switch_to(prev, next, last)
134
135#endif
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 21ff9d01543..8e84225c096 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -627,7 +627,7 @@ config CRYPTO_BLOWFISH_COMMON
627 627
628config CRYPTO_BLOWFISH_X86_64 628config CRYPTO_BLOWFISH_X86_64
629 tristate "Blowfish cipher algorithm (x86_64)" 629 tristate "Blowfish cipher algorithm (x86_64)"
630 depends on (X86 || UML_X86) && 64BIT 630 depends on X86 && 64BIT
631 select CRYPTO_ALGAPI 631 select CRYPTO_ALGAPI
632 select CRYPTO_BLOWFISH_COMMON 632 select CRYPTO_BLOWFISH_COMMON
633 help 633 help
@@ -657,7 +657,7 @@ config CRYPTO_CAMELLIA
657 657
658config CRYPTO_CAMELLIA_X86_64 658config CRYPTO_CAMELLIA_X86_64
659 tristate "Camellia cipher algorithm (x86_64)" 659 tristate "Camellia cipher algorithm (x86_64)"
660 depends on (X86 || UML_X86) && 64BIT 660 depends on X86 && 64BIT
661 depends on CRYPTO 661 depends on CRYPTO
662 select CRYPTO_ALGAPI 662 select CRYPTO_ALGAPI
663 select CRYPTO_LRW 663 select CRYPTO_LRW
@@ -893,7 +893,7 @@ config CRYPTO_TWOFISH_X86_64
893 893
894config CRYPTO_TWOFISH_X86_64_3WAY 894config CRYPTO_TWOFISH_X86_64_3WAY
895 tristate "Twofish cipher algorithm (x86_64, 3-way parallel)" 895 tristate "Twofish cipher algorithm (x86_64, 3-way parallel)"
896 depends on (X86 || UML_X86) && 64BIT 896 depends on X86 && 64BIT
897 select CRYPTO_ALGAPI 897 select CRYPTO_ALGAPI
898 select CRYPTO_TWOFISH_COMMON 898 select CRYPTO_TWOFISH_COMMON
899 select CRYPTO_TWOFISH_X86_64 899 select CRYPTO_TWOFISH_X86_64
diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 37f42113af3..00e8f213f56 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -182,7 +182,6 @@ static int i2c_dw_pci_resume(struct device *dev)
182 pci_restore_state(pdev); 182 pci_restore_state(pdev);
183 183
184 i2c_dw_init(i2c); 184 i2c_dw_init(i2c);
185 i2c_dw_enable(i2c);
186 return 0; 185 return 0;
187} 186}
188 187
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
index 53969af1755..81fd606e47b 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -214,7 +214,7 @@ static struct of_device_id __devinitdata of_anatop_regulator_match_tbl[] = {
214 { /* end */ } 214 { /* end */ }
215}; 215};
216 216
217static struct platform_driver anatop_regulator = { 217static struct platform_driver anatop_regulator_driver = {
218 .driver = { 218 .driver = {
219 .name = "anatop_regulator", 219 .name = "anatop_regulator",
220 .owner = THIS_MODULE, 220 .owner = THIS_MODULE,
@@ -226,13 +226,13 @@ static struct platform_driver anatop_regulator = {
226 226
227static int __init anatop_regulator_init(void) 227static int __init anatop_regulator_init(void)
228{ 228{
229 return platform_driver_register(&anatop_regulator); 229 return platform_driver_register(&anatop_regulator_driver);
230} 230}
231postcore_initcall(anatop_regulator_init); 231postcore_initcall(anatop_regulator_init);
232 232
233static void __exit anatop_regulator_exit(void) 233static void __exit anatop_regulator_exit(void)
234{ 234{
235 platform_driver_unregister(&anatop_regulator); 235 platform_driver_unregister(&anatop_regulator_driver);
236} 236}
237module_exit(anatop_regulator_exit); 237module_exit(anatop_regulator_exit);
238 238
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index 91b6d52f74e..f0d015dd0fe 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -2,6 +2,7 @@
2 * Helper routines for SuperH Clock Pulse Generator blocks (CPG). 2 * Helper routines for SuperH Clock Pulse Generator blocks (CPG).
3 * 3 *
4 * Copyright (C) 2010 Magnus Damm 4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2010 - 2012 Paul Mundt
5 * 6 *
6 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
@@ -13,26 +14,44 @@
13#include <linux/io.h> 14#include <linux/io.h>
14#include <linux/sh_clk.h> 15#include <linux/sh_clk.h>
15 16
16static int sh_clk_mstp32_enable(struct clk *clk) 17static unsigned int sh_clk_read(struct clk *clk)
17{ 18{
18 iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit), 19 if (clk->flags & CLK_ENABLE_REG_8BIT)
19 clk->mapped_reg); 20 return ioread8(clk->mapped_reg);
21 else if (clk->flags & CLK_ENABLE_REG_16BIT)
22 return ioread16(clk->mapped_reg);
23
24 return ioread32(clk->mapped_reg);
25}
26
27static void sh_clk_write(int value, struct clk *clk)
28{
29 if (clk->flags & CLK_ENABLE_REG_8BIT)
30 iowrite8(value, clk->mapped_reg);
31 else if (clk->flags & CLK_ENABLE_REG_16BIT)
32 iowrite16(value, clk->mapped_reg);
33 else
34 iowrite32(value, clk->mapped_reg);
35}
36
37static int sh_clk_mstp_enable(struct clk *clk)
38{
39 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);
20 return 0; 40 return 0;
21} 41}
22 42
23static void sh_clk_mstp32_disable(struct clk *clk) 43static void sh_clk_mstp_disable(struct clk *clk)
24{ 44{
25 iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit), 45 sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk);
26 clk->mapped_reg);
27} 46}
28 47
29static struct sh_clk_ops sh_clk_mstp32_clk_ops = { 48static struct sh_clk_ops sh_clk_mstp_clk_ops = {
30 .enable = sh_clk_mstp32_enable, 49 .enable = sh_clk_mstp_enable,
31 .disable = sh_clk_mstp32_disable, 50 .disable = sh_clk_mstp_disable,
32 .recalc = followparent_recalc, 51 .recalc = followparent_recalc,
33}; 52};
34 53
35int __init sh_clk_mstp32_register(struct clk *clks, int nr) 54int __init sh_clk_mstp_register(struct clk *clks, int nr)
36{ 55{
37 struct clk *clkp; 56 struct clk *clkp;
38 int ret = 0; 57 int ret = 0;
@@ -40,7 +59,7 @@ int __init sh_clk_mstp32_register(struct clk *clks, int nr)
40 59
41 for (k = 0; !ret && (k < nr); k++) { 60 for (k = 0; !ret && (k < nr); k++) {
42 clkp = clks + k; 61 clkp = clks + k;
43 clkp->ops = &sh_clk_mstp32_clk_ops; 62 clkp->ops = &sh_clk_mstp_clk_ops;
44 ret |= clk_register(clkp); 63 ret |= clk_register(clkp);
45 } 64 }
46 65
@@ -72,7 +91,7 @@ static unsigned long sh_clk_div6_recalc(struct clk *clk)
72 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 91 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
73 table, NULL); 92 table, NULL);
74 93
75 idx = ioread32(clk->mapped_reg) & 0x003f; 94 idx = sh_clk_read(clk) & 0x003f;
76 95
77 return clk->freq_table[idx].frequency; 96 return clk->freq_table[idx].frequency;
78} 97}
@@ -98,10 +117,10 @@ static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
98 if (ret < 0) 117 if (ret < 0)
99 return ret; 118 return ret;
100 119
101 value = ioread32(clk->mapped_reg) & 120 value = sh_clk_read(clk) &
102 ~(((1 << clk->src_width) - 1) << clk->src_shift); 121 ~(((1 << clk->src_width) - 1) << clk->src_shift);
103 122
104 iowrite32(value | (i << clk->src_shift), clk->mapped_reg); 123 sh_clk_write(value | (i << clk->src_shift), clk);
105 124
106 /* Rebuild the frequency table */ 125 /* Rebuild the frequency table */
107 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 126 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
@@ -119,10 +138,10 @@ static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
119 if (idx < 0) 138 if (idx < 0)
120 return idx; 139 return idx;
121 140
122 value = ioread32(clk->mapped_reg); 141 value = sh_clk_read(clk);
123 value &= ~0x3f; 142 value &= ~0x3f;
124 value |= idx; 143 value |= idx;
125 iowrite32(value, clk->mapped_reg); 144 sh_clk_write(value, clk);
126 return 0; 145 return 0;
127} 146}
128 147
@@ -133,9 +152,9 @@ static int sh_clk_div6_enable(struct clk *clk)
133 152
134 ret = sh_clk_div6_set_rate(clk, clk->rate); 153 ret = sh_clk_div6_set_rate(clk, clk->rate);
135 if (ret == 0) { 154 if (ret == 0) {
136 value = ioread32(clk->mapped_reg); 155 value = sh_clk_read(clk);
137 value &= ~0x100; /* clear stop bit to enable clock */ 156 value &= ~0x100; /* clear stop bit to enable clock */
138 iowrite32(value, clk->mapped_reg); 157 sh_clk_write(value, clk);
139 } 158 }
140 return ret; 159 return ret;
141} 160}
@@ -144,10 +163,10 @@ static void sh_clk_div6_disable(struct clk *clk)
144{ 163{
145 unsigned long value; 164 unsigned long value;
146 165
147 value = ioread32(clk->mapped_reg); 166 value = sh_clk_read(clk);
148 value |= 0x100; /* stop clock */ 167 value |= 0x100; /* stop clock */
149 value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */ 168 value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
150 iowrite32(value, clk->mapped_reg); 169 sh_clk_write(value, clk);
151} 170}
152 171
153static struct sh_clk_ops sh_clk_div6_clk_ops = { 172static struct sh_clk_ops sh_clk_div6_clk_ops = {
@@ -182,7 +201,7 @@ static int __init sh_clk_init_parent(struct clk *clk)
182 return -EINVAL; 201 return -EINVAL;
183 } 202 }
184 203
185 val = (ioread32(clk->mapped_reg) >> clk->src_shift); 204 val = (sh_clk_read(clk) >> clk->src_shift);
186 val &= (1 << clk->src_width) - 1; 205 val &= (1 << clk->src_width) - 1;
187 206
188 if (val >= clk->parent_num) { 207 if (val >= clk->parent_num) {
@@ -252,7 +271,7 @@ static unsigned long sh_clk_div4_recalc(struct clk *clk)
252 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 271 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
253 table, &clk->arch_flags); 272 table, &clk->arch_flags);
254 273
255 idx = (ioread32(clk->mapped_reg) >> clk->enable_bit) & 0x000f; 274 idx = (sh_clk_read(clk) >> clk->enable_bit) & 0x000f;
256 275
257 return clk->freq_table[idx].frequency; 276 return clk->freq_table[idx].frequency;
258} 277}
@@ -270,15 +289,15 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
270 */ 289 */
271 290
272 if (parent->flags & CLK_ENABLE_ON_INIT) 291 if (parent->flags & CLK_ENABLE_ON_INIT)
273 value = ioread32(clk->mapped_reg) & ~(1 << 7); 292 value = sh_clk_read(clk) & ~(1 << 7);
274 else 293 else
275 value = ioread32(clk->mapped_reg) | (1 << 7); 294 value = sh_clk_read(clk) | (1 << 7);
276 295
277 ret = clk_reparent(clk, parent); 296 ret = clk_reparent(clk, parent);
278 if (ret < 0) 297 if (ret < 0)
279 return ret; 298 return ret;
280 299
281 iowrite32(value, clk->mapped_reg); 300 sh_clk_write(value, clk);
282 301
283 /* Rebiuld the frequency table */ 302 /* Rebiuld the frequency table */
284 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 303 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
@@ -295,10 +314,10 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
295 if (idx < 0) 314 if (idx < 0)
296 return idx; 315 return idx;
297 316
298 value = ioread32(clk->mapped_reg); 317 value = sh_clk_read(clk);
299 value &= ~(0xf << clk->enable_bit); 318 value &= ~(0xf << clk->enable_bit);
300 value |= (idx << clk->enable_bit); 319 value |= (idx << clk->enable_bit);
301 iowrite32(value, clk->mapped_reg); 320 sh_clk_write(value, clk);
302 321
303 if (d4t->kick) 322 if (d4t->kick)
304 d4t->kick(clk); 323 d4t->kick(clk);
@@ -308,13 +327,13 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
308 327
309static int sh_clk_div4_enable(struct clk *clk) 328static int sh_clk_div4_enable(struct clk *clk)
310{ 329{
311 iowrite32(ioread32(clk->mapped_reg) & ~(1 << 8), clk->mapped_reg); 330 sh_clk_write(sh_clk_read(clk) & ~(1 << 8), clk);
312 return 0; 331 return 0;
313} 332}
314 333
315static void sh_clk_div4_disable(struct clk *clk) 334static void sh_clk_div4_disable(struct clk *clk)
316{ 335{
317 iowrite32(ioread32(clk->mapped_reg) | (1 << 8), clk->mapped_reg); 336 sh_clk_write(sh_clk_read(clk) | (1 << 8), clk);
318} 337}
319 338
320static struct sh_clk_ops sh_clk_div4_clk_ops = { 339static struct sh_clk_ops sh_clk_div4_clk_ops = {
diff --git a/drivers/staging/android/lowmemorykiller.c b/drivers/staging/android/lowmemorykiller.c
index 052b43e4e50..b91e4bc332a 100644
--- a/drivers/staging/android/lowmemorykiller.c
+++ b/drivers/staging/android/lowmemorykiller.c
@@ -55,7 +55,6 @@ static int lowmem_minfree[6] = {
55}; 55};
56static int lowmem_minfree_size = 4; 56static int lowmem_minfree_size = 4;
57 57
58static struct task_struct *lowmem_deathpending;
59static unsigned long lowmem_deathpending_timeout; 58static unsigned long lowmem_deathpending_timeout;
60 59
61#define lowmem_print(level, x...) \ 60#define lowmem_print(level, x...) \
@@ -64,24 +63,6 @@ static unsigned long lowmem_deathpending_timeout;
64 printk(x); \ 63 printk(x); \
65 } while (0) 64 } while (0)
66 65
67static int
68task_notify_func(struct notifier_block *self, unsigned long val, void *data);
69
70static struct notifier_block task_nb = {
71 .notifier_call = task_notify_func,
72};
73
74static int
75task_notify_func(struct notifier_block *self, unsigned long val, void *data)
76{
77 struct task_struct *task = data;
78
79 if (task == lowmem_deathpending)
80 lowmem_deathpending = NULL;
81
82 return NOTIFY_OK;
83}
84
85static int lowmem_shrink(struct shrinker *s, struct shrink_control *sc) 66static int lowmem_shrink(struct shrinker *s, struct shrink_control *sc)
86{ 67{
87 struct task_struct *tsk; 68 struct task_struct *tsk;
@@ -97,19 +78,6 @@ static int lowmem_shrink(struct shrinker *s, struct shrink_control *sc)
97 int other_file = global_page_state(NR_FILE_PAGES) - 78 int other_file = global_page_state(NR_FILE_PAGES) -
98 global_page_state(NR_SHMEM); 79 global_page_state(NR_SHMEM);
99 80
100 /*
101 * If we already have a death outstanding, then
102 * bail out right away; indicating to vmscan
103 * that we have nothing further to offer on
104 * this pass.
105 *
106 * Note: Currently you need CONFIG_PROFILING
107 * for this to work correctly.
108 */
109 if (lowmem_deathpending &&
110 time_before_eq(jiffies, lowmem_deathpending_timeout))
111 return 0;
112
113 if (lowmem_adj_size < array_size) 81 if (lowmem_adj_size < array_size)
114 array_size = lowmem_adj_size; 82 array_size = lowmem_adj_size;
115 if (lowmem_minfree_size < array_size) 83 if (lowmem_minfree_size < array_size)
@@ -148,6 +116,12 @@ static int lowmem_shrink(struct shrinker *s, struct shrink_control *sc)
148 if (!p) 116 if (!p)
149 continue; 117 continue;
150 118
119 if (test_tsk_thread_flag(p, TIF_MEMDIE) &&
120 time_before_eq(jiffies, lowmem_deathpending_timeout)) {
121 task_unlock(p);
122 rcu_read_unlock();
123 return 0;
124 }
151 oom_score_adj = p->signal->oom_score_adj; 125 oom_score_adj = p->signal->oom_score_adj;
152 if (oom_score_adj < min_score_adj) { 126 if (oom_score_adj < min_score_adj) {
153 task_unlock(p); 127 task_unlock(p);
@@ -174,15 +148,9 @@ static int lowmem_shrink(struct shrinker *s, struct shrink_control *sc)
174 lowmem_print(1, "send sigkill to %d (%s), adj %d, size %d\n", 148 lowmem_print(1, "send sigkill to %d (%s), adj %d, size %d\n",
175 selected->pid, selected->comm, 149 selected->pid, selected->comm,
176 selected_oom_score_adj, selected_tasksize); 150 selected_oom_score_adj, selected_tasksize);
177 /*
178 * If CONFIG_PROFILING is off, then we don't want to stall
179 * the killer by setting lowmem_deathpending.
180 */
181#ifdef CONFIG_PROFILING
182 lowmem_deathpending = selected;
183 lowmem_deathpending_timeout = jiffies + HZ; 151 lowmem_deathpending_timeout = jiffies + HZ;
184#endif
185 send_sig(SIGKILL, selected, 0); 152 send_sig(SIGKILL, selected, 0);
153 set_tsk_thread_flag(selected, TIF_MEMDIE);
186 rem -= selected_tasksize; 154 rem -= selected_tasksize;
187 } 155 }
188 lowmem_print(4, "lowmem_shrink %lu, %x, return %d\n", 156 lowmem_print(4, "lowmem_shrink %lu, %x, return %d\n",
@@ -198,7 +166,6 @@ static struct shrinker lowmem_shrinker = {
198 166
199static int __init lowmem_init(void) 167static int __init lowmem_init(void)
200{ 168{
201 task_handoff_register(&task_nb);
202 register_shrinker(&lowmem_shrinker); 169 register_shrinker(&lowmem_shrinker);
203 return 0; 170 return 0;
204} 171}
@@ -206,7 +173,6 @@ static int __init lowmem_init(void)
206static void __exit lowmem_exit(void) 173static void __exit lowmem_exit(void)
207{ 174{
208 unregister_shrinker(&lowmem_shrinker); 175 unregister_shrinker(&lowmem_shrinker);
209 task_handoff_unregister(&task_nb);
210} 176}
211 177
212module_param_named(cost, lowmem_shrinker.seeks, int, S_IRUGO | S_IWUSR); 178module_param_named(cost, lowmem_shrinker.seeks, int, S_IRUGO | S_IWUSR);
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 3158e17b665..be31d85a50e 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1564,10 +1564,32 @@ static void sci_enable_ms(struct uart_port *port)
1564 1564
1565static void sci_break_ctl(struct uart_port *port, int break_state) 1565static void sci_break_ctl(struct uart_port *port, int break_state)
1566{ 1566{
1567 /* 1567 struct sci_port *s = to_sci_port(port);
1568 * Not supported by hardware. Most parts couple break and rx 1568 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1569 * interrupts together, with break detection always enabled. 1569 unsigned short scscr, scsptr;
1570 */ 1570
1571 /* check wheter the port has SCSPTR */
1572 if (!reg->size) {
1573 /*
1574 * Not supported by hardware. Most parts couple break and rx
1575 * interrupts together, with break detection always enabled.
1576 */
1577 return;
1578 }
1579
1580 scsptr = serial_port_in(port, SCSPTR);
1581 scscr = serial_port_in(port, SCSCR);
1582
1583 if (break_state == -1) {
1584 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1585 scscr &= ~SCSCR_TE;
1586 } else {
1587 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1588 scscr |= SCSCR_TE;
1589 }
1590
1591 serial_port_out(port, SCSPTR, scsptr);
1592 serial_port_out(port, SCSCR, scscr);
1571} 1593}
1572 1594
1573#ifdef CONFIG_SERIAL_SH_SCI_DMA 1595#ifdef CONFIG_SERIAL_SH_SCI_DMA
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index 78779074f6e..eb763adf981 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -52,6 +52,8 @@ enum {
52/* SCSPTR, optional */ 52/* SCSPTR, optional */
53#define SCSPTR_RTSIO (1 << 7) 53#define SCSPTR_RTSIO (1 << 7)
54#define SCSPTR_CTSIO (1 << 5) 54#define SCSPTR_CTSIO (1 << 5)
55#define SCSPTR_SPB2IO (1 << 1)
56#define SCSPTR_SPB2DT (1 << 0)
55 57
56/* Offsets into the sci_port->irqs array */ 58/* Offsets into the sci_port->irqs array */
57enum { 59enum {
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h
index 0a9d8f2ac51..c513b73cd7c 100644
--- a/include/linux/sh_clk.h
+++ b/include/linux/sh_clk.h
@@ -59,7 +59,15 @@ struct clk {
59 unsigned int nr_freqs; 59 unsigned int nr_freqs;
60}; 60};
61 61
62#define CLK_ENABLE_ON_INIT (1 << 0) 62#define CLK_ENABLE_ON_INIT BIT(0)
63
64#define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */
65#define CLK_ENABLE_REG_16BIT BIT(2)
66#define CLK_ENABLE_REG_8BIT BIT(3)
67
68#define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \
69 CLK_ENABLE_REG_16BIT | \
70 CLK_ENABLE_REG_8BIT)
63 71
64/* drivers/sh/clk.c */ 72/* drivers/sh/clk.c */
65unsigned long followparent_recalc(struct clk *); 73unsigned long followparent_recalc(struct clk *);
@@ -102,7 +110,7 @@ long clk_round_parent(struct clk *clk, unsigned long target,
102 unsigned long *best_freq, unsigned long *parent_freq, 110 unsigned long *best_freq, unsigned long *parent_freq,
103 unsigned int div_min, unsigned int div_max); 111 unsigned int div_min, unsigned int div_max);
104 112
105#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \ 113#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \
106{ \ 114{ \
107 .parent = _parent, \ 115 .parent = _parent, \
108 .enable_reg = (void __iomem *)_enable_reg, \ 116 .enable_reg = (void __iomem *)_enable_reg, \
@@ -110,7 +118,27 @@ long clk_round_parent(struct clk *clk, unsigned long target,
110 .flags = _flags, \ 118 .flags = _flags, \
111} 119}
112 120
113int sh_clk_mstp32_register(struct clk *clks, int nr); 121#define SH_CLK_MSTP32(_p, _r, _b, _f) \
122 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT)
123
124#define SH_CLK_MSTP16(_p, _r, _b, _f) \
125 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT)
126
127#define SH_CLK_MSTP8(_p, _r, _b, _f) \
128 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT)
129
130int sh_clk_mstp_register(struct clk *clks, int nr);
131
132/*
133 * MSTP registration never really cared about access size, despite the
134 * original enable/disable pairs assuming a 32-bit access. Clocks are
135 * responsible for defining their access sizes either directly or via the
136 * clock definition wrappers.
137 */
138static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
139{
140 return sh_clk_mstp_register(clks, nr);
141}
114 142
115#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ 143#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
116{ \ 144{ \
diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c
index 3f01fd90873..c4e7d1510f9 100644
--- a/scripts/mod/modpost.c
+++ b/scripts/mod/modpost.c
@@ -132,8 +132,10 @@ static struct module *new_module(char *modname)
132 /* strip trailing .o */ 132 /* strip trailing .o */
133 s = strrchr(p, '.'); 133 s = strrchr(p, '.');
134 if (s != NULL) 134 if (s != NULL)
135 if (strcmp(s, ".o") == 0) 135 if (strcmp(s, ".o") == 0) {
136 *s = '\0'; 136 *s = '\0';
137 mod->is_dot_o = 1;
138 }
137 139
138 /* add to list */ 140 /* add to list */
139 mod->name = p; 141 mod->name = p;
@@ -587,7 +589,8 @@ static void handle_modversions(struct module *mod, struct elf_info *info,
587 unsigned int crc; 589 unsigned int crc;
588 enum export export; 590 enum export export;
589 591
590 if (!is_vmlinux(mod->name) && strncmp(symname, "__ksymtab", 9) == 0) 592 if ((!is_vmlinux(mod->name) || mod->is_dot_o) &&
593 strncmp(symname, "__ksymtab", 9) == 0)
591 export = export_from_secname(info, get_secindex(info, sym)); 594 export = export_from_secname(info, get_secindex(info, sym));
592 else 595 else
593 export = export_from_sec(info, get_secindex(info, sym)); 596 export = export_from_sec(info, get_secindex(info, sym));
diff --git a/scripts/mod/modpost.h b/scripts/mod/modpost.h
index 2031119080d..51207e4d5f8 100644
--- a/scripts/mod/modpost.h
+++ b/scripts/mod/modpost.h
@@ -113,6 +113,7 @@ struct module {
113 int has_cleanup; 113 int has_cleanup;
114 struct buffer dev_table_buf; 114 struct buffer dev_table_buf;
115 char srcversion[25]; 115 char srcversion[25];
116 int is_dot_o;
116}; 117};
117 118
118struct elf_info { 119struct elf_info {
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-13 01:09:57 -0400