3 files changed, 65 insertions, 17 deletions

diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 8fda331f8a8..29f76204ce1 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -14,7 +14,9 @@
 #define flush_cache_dup_mm(mm)                  do { } while (0)
 #define flush_cache_range(vma, start, end)      __flush_cache_all()
 #define flush_cache_page(vma, vmaddr)           do { } while (0)
+#ifndef flush_dcache_range
 #define flush_dcache_range(start,len)           __flush_cache_all()
+#endif
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
 #define flush_dcache_page(page)                 do { } while (0)
 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index da713d22dd0..7d28da4d622 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -40,31 +40,75 @@
 #define ACR_CM          0x00000060      /* Cache mode mask */
 #define ACR_WPROTECT    0x00000004      /* Write protect */
 
+#if defined(CONFIG_M5407)
+
+#define ICACHE_SIZE 0x4000      /* instruction - 16k */
+#define DCACHE_SIZE 0x2000      /* data - 8k */
+
+#elif defined(CONFIG_M548x)
+
+#define ICACHE_SIZE 0x8000      /* instruction - 32k */
+#define DCACHE_SIZE 0x8000      /* data - 32k */
+
+#endif
+
+#define CACHE_LINE_SIZE 0x0010  /* 16 bytes */
+#define CACHE_WAYS 4            /* 4 ways */
+
+/*
+ *      Version 4 cores have a true harvard style separate instruction
+ *      and data cache. Enable data and instruction caches, also enable write
+ *      buffers and branch accelerator.
+ */
+/* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */
+/* use '+' instead of '|' for assembler's sake */
+
+        /* Enable data cache */
+        /* Enable data store buffer */
+        /* outside ACRs : No cache, precise */
+        /* Enable instruction+branch caches */
+#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC)
+
+#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
+
+#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
+
 #ifndef __ASSEMBLY__
 
+#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT)
+#define flush_dcache_range(a, l) do { asm("nop"); } while (0)
+#endif
+
 static inline void __m54xx_flush_cache_all(void)
 {
+        __asm__ __volatile__ (
+#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP)
         /*
          *      Use cpushl to push and invalidate all cache lines.
          *      Gas doesn't seem to know how to generate the ColdFire
          *      cpushl instruction... Oh well, bit stuff it for now.
          */
-        __asm__ __volatile__ (
-                "nop\n\t"
                 "clrl   %%d0\n\t"
                 "1:\n\t"
                 "movel  %%d0,%%a0\n\t"
                 "2:\n\t"
                 ".word  0xf468\n\t"
-                "addl   #0x10,%%a0\n\t"
-                "cmpl   #0x00000800,%%a0\n\t"
+                "addl   %0,%%a0\n\t"
+                "cmpl   %1,%%a0\n\t"
                 "blt    2b\n\t"
                 "addql  #1,%%d0\n\t"
-                "cmpil  #4,%%d0\n\t"
+                "cmpil  %2,%%d0\n\t"
                 "bne    1b\n\t"
-                "movel  #0xb6088500,%%d0\n\t"
+#endif
+                "movel  %3,%%d0\n\t"
                 "movec  %%d0,%%CACR\n\t"
-                : : : "d0", "a0" );
+                "nop\n\t"       /* forces flush of Store Buffer */
+                : /* No output */
+                : "i" (CACHE_LINE_SIZE),
+                  "i" (DCACHE_SIZE / CACHE_WAYS),
+                  "i" (CACHE_WAYS),
+                  "i" (CACHE_MODE|CACR_DCINVA|CACR_BCINVA|CACR_ICINVA)
+                : "d0", "a0" );
 }
 
 #define __flush_cache_all() __m54xx_flush_cache_all()
diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h
index f49dfc09f70..7acb406d601 100644
--- a/arch/m68k/include/asm/mcfcache.h
+++ b/arch/m68k/include/asm/mcfcache.h
@@ -108,28 +108,30 @@
 #endif /* CONFIG_M532x */
 
 #if defined(CONFIG_M5407) || defined(CONFIG_M548x)
-/*
- *      Version 4 cores have a true harvard style separate instruction
- *      and data cache. Invalidate and enable cache, also enable write
- *      buffers and branch accelerator.
- */
+
+#include <asm/m54xxacr.h>
+
 .macro CACHE_ENABLE
-        movel   #0x01040100,%d0         /* invalidate whole cache */
+        /* invalidate whole cache */
+        movel   #(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA),%d0
         movec   %d0,%CACR
         nop
-        movel   #0x000fc000,%d0         /* set SDRAM cached only */
+        /* addresses range for data cache : 0x00000000-0x0fffffff */
+        movel   #(0x000f0000+DATA_CACHE_MODE),%d0       /* set SDRAM cached */
         movec   %d0, %ACR0
         movel   #0x00000000,%d0         /* no other regions cached */
         movec   %d0, %ACR1
-        movel   #0x000fc000,%d0         /* set SDRAM cached only */
+        /* addresses range for instruction cache : 0x00000000-0x0fffffff */
+        movel   #(0x000f0000+INSN_CACHE_MODE),%d0       /* set SDRAM cached */
         movec   %d0, %ACR2
         movel   #0x00000000,%d0         /* no other regions cached */
         movec   %d0, %ACR3
-        movel   #0xb6088400,%d0         /* enable caches */
+        /* enable caches */
+        movel   #(CACHE_MODE),%d0
         movec   %d0,%CACR
         nop
 .endm
-#endif /* CONFIG_M5407 */
+#endif /* CONFIG_M5407 || CONFIG_M548x */
 
 #if defined(CONFIG_M520x)
 .macro CACHE_ENABLE