9 files changed, 280 insertions, 21 deletions

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 343e0f0f84b..63bac584f9c 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -1638,6 +1638,17 @@ and is between 256 and 4096 characters. It is defined in the file
                 nomsi           [MSI] If the PCI_MSI kernel config parameter is
                                 enabled, this kernel boot option can be used to
                                 disable the use of MSI interrupts system-wide.
+                noioapicquirk   [APIC] Disable all boot interrupt quirks.
+                                Safety option to keep boot IRQs enabled. This
+                                should never be necessary.
+                ioapicreroute   [APIC] Enable rerouting of boot IRQs to the
+                                primary IO-APIC for bridges that cannot disable
+                                boot IRQs. This fixes a source of spurious IRQs
+                                when the system masks IRQs.
+                noioapicreroute [APIC] Disable workaround that uses the
+                                boot IRQ equivalent of an IRQ that connects to
+                                a chipset where boot IRQs cannot be disabled.
+                                The opposite of ioapicreroute.
                 biosirq         [X86-32] Use PCI BIOS calls to get the interrupt
                                 routing table. These calls are known to be buggy
                                 on several machines and they hang the machine
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 350bee1d54d..f4ed47db79e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -653,6 +653,30 @@ config X86_VISWS_APIC
         def_bool y
         depends on X86_32 && X86_VISWS
 
+config X86_REROUTE_FOR_BROKEN_BOOT_IRQS
+        bool "Reroute for broken boot IRQs"
+        default n
+        depends on X86_IO_APIC
+        help
+          This option enables a workaround that fixes a source of
+          spurious interrupts. This is recommended when threaded
+          interrupt handling is used on systems where the generation of
+          superfluous "boot interrupts" cannot be disabled.
+
+          Some chipsets generate a legacy INTx "boot IRQ" when the IRQ
+          entry in the chipset's IO-APIC is masked (as, e.g. the RT
+          kernel does during interrupt handling). On chipsets where this
+          boot IRQ generation cannot be disabled, this workaround keeps
+          the original IRQ line masked so that only the equivalent "boot
+          IRQ" is delivered to the CPUs. The workaround also tells the
+          kernel to set up the IRQ handler on the boot IRQ line. In this
+          way only one interrupt is delivered to the kernel. Otherwise
+          the spurious second interrupt may cause the kernel to bring
+          down (vital) interrupt lines.
+
+          Only affects "broken" chipsets. Interrupt sharing may be
+          increased on these systems.
+
 config X86_MCE
         bool "Machine Check Exception"
         depends on !X86_VOYAGER
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index 6afd9933a7d..e475e009ae5 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -156,11 +156,21 @@ extern int sis_apic_bug;
 /* 1 if "noapic" boot option passed */
 extern int skip_ioapic_setup;
 
+/* 1 if "noapic" boot option passed */
+extern int noioapicquirk;
+
+/* -1 if "noapic" boot option passed */
+extern int noioapicreroute;
+
 /* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
 extern int timer_through_8259;
 
 static inline void disable_ioapic_setup(void)
 {
+#ifdef CONFIG_PCI
+        noioapicquirk = 1;
+        noioapicreroute = -1;
+#endif
         skip_ioapic_setup = 1;
 }
 
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 875b38edf19..647781298e7 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -19,6 +19,8 @@ struct pci_sysdata {
 };
 
 extern int pci_routeirq;
+extern int noioapicquirk;
+extern int noioapicreroute;
 
 /* scan a bus after allocating a pci_sysdata for it */
 extern struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops,
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index b67732bbb85..bb1a01f089e 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -23,6 +23,12 @@ unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
 unsigned int pci_early_dump_regs;
 static int pci_bf_sort;
 int pci_routeirq;
+int noioapicquirk;
+#ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
+int noioapicreroute = 0;
+#else
+int noioapicreroute = 1;
+#endif
 int pcibios_last_bus = -1;
 unsigned long pirq_table_addr;
 struct pci_bus *pci_root_bus;
@@ -519,6 +525,17 @@ char * __devinit  pcibios_setup(char *str)
         } else if (!strcmp(str, "skip_isa_align")) {
                 pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
                 return NULL;
+        } else if (!strcmp(str, "noioapicquirk")) {
+                noioapicquirk = 1;
+                return NULL;
+        } else if (!strcmp(str, "ioapicreroute")) {
+                if (noioapicreroute != -1)
+                        noioapicreroute = 0;
+                return NULL;
+        } else if (!strcmp(str, "noioapicreroute")) {
+                if (noioapicreroute != -1)
+                        noioapicreroute = 1;
+                return NULL;
         }
         return str;
 }
diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c
index 11acaee14d6..bf79d83bdfb 100644
--- a/drivers/acpi/pci_irq.c
+++ b/drivers/acpi/pci_irq.c
@@ -384,6 +384,27 @@ acpi_pci_free_irq(struct acpi_prt_entry *entry,
         return irq;
 }
 
+#ifdef CONFIG_X86_IO_APIC
+extern int noioapicquirk;
+
+static int bridge_has_boot_interrupt_variant(struct pci_bus *bus)
+{
+        struct pci_bus *bus_it;
+
+        for (bus_it = bus ; bus_it ; bus_it = bus_it->parent) {
+                if (!bus_it->self)
+                        return 0;
+
+                printk(KERN_INFO "vendor=%04x device=%04x\n", bus_it->self->vendor,
+                                bus_it->self->device);
+
+                if (bus_it->self->irq_reroute_variant)
+                        return bus_it->self->irq_reroute_variant;
+        }
+        return 0;
+}
+#endif /* CONFIG_X86_IO_APIC */
+
 /*
  * acpi_pci_irq_lookup
  * success: return IRQ >= 0
@@ -413,6 +434,41 @@ acpi_pci_irq_lookup(struct pci_bus *bus,
         }
 
         ret = func(entry, triggering, polarity, link);
+
+#ifdef CONFIG_X86_IO_APIC
+        /*
+         * Some chipsets (e.g. intel 6700PXH) generate a legacy INTx when the
+         * IRQ entry in the chipset's IO-APIC is masked (as, e.g. the RT kernel
+         * does during interrupt handling). When this INTx generation cannot be
+         * disabled, we reroute these interrupts to their legacy equivalent to
+         * get rid of spurious interrupts.
+         */
+        if (!noioapicquirk) {
+                switch (bridge_has_boot_interrupt_variant(bus)) {
+                case 0:
+                        /* no rerouting necessary */
+                        break;
+
+                case INTEL_IRQ_REROUTE_VARIANT:
+                        /*
+                         * Remap according to INTx routing table in 6700PXH
+                         * specs, intel order number 302628-002, section
+                         * 2.15.2. Other chipsets (80332, ...) have the same
+                         * mapping and are handled here as well.
+                         */
+                        printk(KERN_INFO "pci irq %d -> rerouted to legacy "
+                                         "irq %d\n", ret, (ret % 4) + 16);
+                        ret = (ret % 4) + 16;
+                        break;
+
+                default:
+                        printk(KERN_INFO "not rerouting irq %d to legacy irq: "
+                                         "unknown mapping\n", ret);
+                        break;
+                }
+        }
+#endif /* CONFIG_X86_IO_APIC */
+
         return ret;
 }
 
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 96cf8ecd04c..0b60ed884d9 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -619,27 +619,6 @@ static void __init quirk_ioapic_rmw(struct pci_dev *dev)
                 sis_apic_bug = 1;
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_ANY_ID,                     quirk_ioapic_rmw);
-
-#define AMD8131_revA0        0x01
-#define AMD8131_revB0        0x11
-#define AMD8131_MISC         0x40
-#define AMD8131_NIOAMODE_BIT 0
-static void quirk_amd_8131_ioapic(struct pci_dev *dev)
-{ 
-        unsigned char tmp;
-        
-        if (nr_ioapics == 0) 
-                return;
-
-        if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
-                dev_info(&dev->dev, "Fixing up AMD8131 IOAPIC mode\n");
-                pci_read_config_byte( dev, AMD8131_MISC, &tmp);
-                tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
-                pci_write_config_byte( dev, AMD8131_MISC, tmp);
-        }
-} 
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
-DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
 #endif /* CONFIG_X86_IO_APIC */
 
 /*
@@ -1436,6 +1415,155 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2609, quirk_intel_pcie_pm);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x260a, quirk_intel_pcie_pm);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x260b, quirk_intel_pcie_pm);
 
+#ifdef CONFIG_X86_IO_APIC
+/*
+ * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
+ * remap the original interrupt in the linux kernel to the boot interrupt, so
+ * that a PCI device's interrupt handler is installed on the boot interrupt
+ * line instead.
+ */
+static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
+{
+        if (noioapicquirk || noioapicreroute)
+                return;
+
+        dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
+
+        printk(KERN_INFO "PCI quirk: reroute interrupts for 0x%04x:0x%04x\n",
+                        dev->vendor, dev->device);
+        return;
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80333_0,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80333_1,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB2_0,     quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_0,      quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_1,      quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHV,       quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80332_0,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80332_1,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80333_0,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80333_1,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB2_0,     quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXH_0,      quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXH_1,      quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXHV,       quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80332_0,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80332_1,    quirk_reroute_to_boot_interrupts_intel);
+
+/*
+ * On some chipsets we can disable the generation of legacy INTx boot
+ * interrupts.
+ */
+
+/*
+ * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
+ * 300641-004US, section 5.7.3.
+ */
+#define INTEL_6300_IOAPIC_ABAR          0x40
+#define INTEL_6300_DISABLE_BOOT_IRQ     (1<<14)
+
+static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
+{
+        u16 pci_config_word;
+
+        if (noioapicquirk)
+                return;
+
+        pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
+        pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
+        pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
+
+        printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n",
+                dev->vendor, dev->device);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,      quirk_disable_intel_boot_interrupt);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,     quirk_disable_intel_boot_interrupt);
+
+/*
+ * disable boot interrupts on HT-1000
+ */
+#define BC_HT1000_FEATURE_REG           0x64
+#define BC_HT1000_PIC_REGS_ENABLE       (1<<0)
+#define BC_HT1000_MAP_IDX               0xC00
+#define BC_HT1000_MAP_DATA              0xC01
+
+static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
+{
+        u32 pci_config_dword;
+        u8 irq;
+
+        if (noioapicquirk)
+                return;
+
+        pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
+        pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
+                        BC_HT1000_PIC_REGS_ENABLE);
+
+        for (irq = 0x10; irq < 0x10 + 32; irq++) {
+                outb(irq, BC_HT1000_MAP_IDX);
+                outb(0x00, BC_HT1000_MAP_DATA);
+        }
+
+        pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
+
+        printk(KERN_INFO "disabled boot interrupts on PCI device"
+                        "0x%04x:0x%04x\n", dev->vendor, dev->device);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,        quirk_disable_broadcom_boot_interrupt);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,       quirk_disable_broadcom_boot_interrupt);
+
+/*
+ * disable boot interrupts on AMD and ATI chipsets
+ */
+/*
+ * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
+ * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
+ * (due to an erratum).
+ */
+#define AMD_813X_MISC                   0x40
+#define AMD_813X_NOIOAMODE              (1<<0)
+
+static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
+{
+        u32 pci_config_dword;
+
+        if (noioapicquirk)
+                return;
+
+        pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
+        pci_config_dword &= ~AMD_813X_NOIOAMODE;
+        pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
+
+        printk(KERN_INFO "disabled boot interrupts on PCI device "
+                        "0x%04x:0x%04x\n", dev->vendor, dev->device);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8131_BRIDGE,     quirk_disable_amd_813x_boot_interrupt);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8132_BRIDGE,    quirk_disable_amd_813x_boot_interrupt);
+
+#define AMD_8111_PCI_IRQ_ROUTING        0x56
+
+static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
+{
+        u16 pci_config_word;
+
+        if (noioapicquirk)
+                return;
+
+        pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
+        if (!pci_config_word) {
+                printk(KERN_INFO "boot interrupts on PCI device 0x%04x:0x%04x "
+                                "already disabled\n",
+                                dev->vendor, dev->device);
+                return;
+        }
+        pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
+        printk(KERN_INFO "disabled boot interrupts on PCI device "
+                        "0x%04x:0x%04x\n", dev->vendor, dev->device);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,      quirk_disable_amd_8111_boot_interrupt);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,     quirk_disable_amd_8111_boot_interrupt);
+#endif /* CONFIG_X86_IO_APIC */
+
 /*
  * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
  * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
diff --git a/include/linux/pci.h b/include/linux/pci.h
index c75b82bda32..9194adf82e2 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -134,6 +134,11 @@ enum pci_dev_flags {
         PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
 };
 
+enum pci_irq_reroute_variant {
+        INTEL_IRQ_REROUTE_VARIANT = 1,
+        MAX_IRQ_REROUTE_VARIANTS = 3
+};
+
 typedef unsigned short __bitwise pci_bus_flags_t;
 enum pci_bus_flags {
         PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
@@ -218,6 +223,7 @@ struct pci_dev {
         unsigned int    no_msi:1;       /* device may not use msi */
         unsigned int    block_ucfg_access:1;    /* userspace config space access is blocked */
         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
+        unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
         unsigned int    msi_enabled:1;
         unsigned int    msix_enabled:1;
         unsigned int    ari_enabled:1;  /* ARI forwarding */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 1800f1d6e40..b6e69445428 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2304,6 +2304,10 @@
 #define PCI_DEVICE_ID_INTEL_PXH_0       0x0329
 #define PCI_DEVICE_ID_INTEL_PXH_1       0x032A
 #define PCI_DEVICE_ID_INTEL_PXHV        0x032C
+#define PCI_DEVICE_ID_INTEL_80332_0     0x0330
+#define PCI_DEVICE_ID_INTEL_80332_1     0x0332
+#define PCI_DEVICE_ID_INTEL_80333_0     0x0370
+#define PCI_DEVICE_ID_INTEL_80333_1     0x0372
 #define PCI_DEVICE_ID_INTEL_82375       0x0482
 #define PCI_DEVICE_ID_INTEL_82424       0x0483
 #define PCI_DEVICE_ID_INTEL_82378       0x0484
@@ -2376,6 +2380,7 @@
 #define PCI_DEVICE_ID_INTEL_ESB_4       0x25a4
 #define PCI_DEVICE_ID_INTEL_ESB_5       0x25a6
 #define PCI_DEVICE_ID_INTEL_ESB_9       0x25ab
+#define PCI_DEVICE_ID_INTEL_ESB_10      0x25ac
 #define PCI_DEVICE_ID_INTEL_82820_HB    0x2500
 #define PCI_DEVICE_ID_INTEL_82820_UP_HB 0x2501
 #define PCI_DEVICE_ID_INTEL_82850_HB    0x2530