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-rw-r--r--drivers/pci/pcie/aspm.c11
-rw-r--r--include/uapi/linux/pci_regs.h2
2 files changed, 8 insertions, 5 deletions
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 213753b283a..c2faf9d0ffd 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -427,7 +427,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
427 427
428static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) 428static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
429{ 429{
430 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, 0x3, val); 430 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
431 PCI_EXP_LNKCTL_ASPMC, val);
431} 432}
432 433
433static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) 434static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
@@ -442,12 +443,12 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
442 return; 443 return;
443 /* Convert ASPM state to upstream/downstream ASPM register state */ 444 /* Convert ASPM state to upstream/downstream ASPM register state */
444 if (state & ASPM_STATE_L0S_UP) 445 if (state & ASPM_STATE_L0S_UP)
445 dwstream |= PCIE_LINK_STATE_L0S; 446 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
446 if (state & ASPM_STATE_L0S_DW) 447 if (state & ASPM_STATE_L0S_DW)
447 upstream |= PCIE_LINK_STATE_L0S; 448 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
448 if (state & ASPM_STATE_L1) { 449 if (state & ASPM_STATE_L1) {
449 upstream |= PCIE_LINK_STATE_L1; 450 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
450 dwstream |= PCIE_LINK_STATE_L1; 451 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
451 } 452 }
452 /* 453 /*
453 * Spec 2.0 suggests all functions should be configured the 454 * Spec 2.0 suggests all functions should be configured the
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 4cca834f9ab..0b6dbe49dc1 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -469,6 +469,8 @@
469#define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ 469#define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
470#define PCI_EXP_LNKCTL 16 /* Link Control */ 470#define PCI_EXP_LNKCTL 16 /* Link Control */
471#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ 471#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
472#define PCI_EXP_LNKCTL_ASPM_L0S 0x01 /* L0s Enable */
473#define PCI_EXP_LNKCTL_ASPM_L1 0x02 /* L1 Enable */
472#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ 474#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
473#define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ 475#define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */
474#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ 476#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */