diff options
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 2 |
2 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3ae2c7c00ef..583e8c7569f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -3502,7 +3502,11 @@ | |||
3502 | #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) | 3502 | #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) |
3503 | #define GEN6_RP_CONTROL 0xA024 | 3503 | #define GEN6_RP_CONTROL 0xA024 |
3504 | #define GEN6_RP_MEDIA_TURBO (1<<11) | 3504 | #define GEN6_RP_MEDIA_TURBO (1<<11) |
3505 | #define GEN6_RP_USE_NORMAL_FREQ (1<<9) | 3505 | #define GEN6_RP_MEDIA_MODE_MASK (3<<9) |
3506 | #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) | ||
3507 | #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) | ||
3508 | #define GEN6_RP_MEDIA_HW_MODE (1<<9) | ||
3509 | #define GEN6_RP_MEDIA_SW_MODE (0<<9) | ||
3506 | #define GEN6_RP_MEDIA_IS_GFX (1<<8) | 3510 | #define GEN6_RP_MEDIA_IS_GFX (1<<8) |
3507 | #define GEN6_RP_ENABLE (1<<7) | 3511 | #define GEN6_RP_ENABLE (1<<7) |
3508 | #define GEN6_RP_UP_IDLE_MIN (0x1<<3) | 3512 | #define GEN6_RP_UP_IDLE_MIN (0x1<<3) |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 55a5b4c4edf..cb21d5bbecc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -8043,7 +8043,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) | |||
8043 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | 8043 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
8044 | I915_WRITE(GEN6_RP_CONTROL, | 8044 | I915_WRITE(GEN6_RP_CONTROL, |
8045 | GEN6_RP_MEDIA_TURBO | | 8045 | GEN6_RP_MEDIA_TURBO | |
8046 | GEN6_RP_USE_NORMAL_FREQ | | 8046 | GEN6_RP_MEDIA_HW_MODE | |
8047 | GEN6_RP_MEDIA_IS_GFX | | 8047 | GEN6_RP_MEDIA_IS_GFX | |
8048 | GEN6_RP_ENABLE | | 8048 | GEN6_RP_ENABLE | |
8049 | GEN6_RP_UP_BUSY_AVG | | 8049 | GEN6_RP_UP_BUSY_AVG | |