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-rw-r--r--arch/arm/mach-omap2/Makefile11
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c2
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_dpllcore.c2
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_osc.c2
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_sys.c2
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c2
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c1
-rw-r--r--arch/arm/mach-omap2/clock.c4
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c4
-rw-r--r--arch/arm/mach-omap2/clock2430.c2
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c4
-rw-r--r--arch/arm/mach-omap2/clock34xx.c2
-rw-r--r--arch/arm/mach-omap2/clock3517.c2
-rw-r--r--arch/arm/mach-omap2/clock3xxx.c4
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c4
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c6
-rw-r--r--arch/arm/mach-omap2/clockdomain.c5
-rw-r--r--arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c4
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h2
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h2
-rw-r--r--arch/arm/mach-omap2/cm-regbits-44xx.h3
-rw-r--r--arch/arm/mach-omap2/cm.h134
-rw-r--r--arch/arm/mach-omap2/cm2xxx_3xxx.c (renamed from arch/arm/mach-omap2/cm.c)39
-rw-r--r--arch/arm/mach-omap2/cm2xxx_3xxx.h131
-rw-r--r--arch/arm/mach-omap2/cm44xx.h1
-rw-r--r--arch/arm/mach-omap2/cm4xxx.c2
-rw-r--r--arch/arm/mach-omap2/control.c4
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c4
-rw-r--r--arch/arm/mach-omap2/dsp.c11
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c5
-rw-r--r--arch/arm/mach-omap2/pm-debug.c4
-rw-r--r--arch/arm/mach-omap2/pm24xx.c4
-rw-r--r--arch/arm/mach-omap2/pm34xx.c4
-rw-r--r--arch/arm/mach-omap2/powerdomain.c3
-rw-r--r--arch/arm/mach-omap2/powerdomain44xx.c1
-rw-r--r--arch/arm/mach-omap2/powerdomains2xxx_data.c4
-rw-r--r--arch/arm/mach-omap2/powerdomains3xxx_data.c4
-rw-r--r--arch/arm/mach-omap2/powerdomains44xx_data.c1
-rw-r--r--arch/arm/mach-omap2/prcm-common.h6
-rw-r--r--arch/arm/mach-omap2/prcm.c88
-rw-r--r--arch/arm/mach-omap2/prm-regbits-24xx.h2
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h8
-rw-r--r--arch/arm/mach-omap2/prm-regbits-44xx.h2
-rw-r--r--arch/arm/mach-omap2/prm.h352
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.c51
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.h367
-rw-r--r--arch/arm/mach-omap2/prm44xx.h1
-rw-r--r--arch/arm/mach-omap2/sdrc.c2
-rw-r--r--arch/arm/mach-omap2/sdrc2xxx.c2
-rw-r--r--arch/arm/mach-omap2/serial.c4
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S4
-rw-r--r--arch/arm/mach-omap2/sram242x.S4
-rw-r--r--arch/arm/mach-omap2/sram243x.S4
-rw-r--r--arch/arm/mach-omap2/sram34xx.S2
-rw-r--r--arch/arm/plat-omap/include/plat/common.h2
-rw-r--r--arch/arm/plat-omap/include/plat/prcm.h7
-rw-r--r--arch/arm/plat-omap/mcbsp.c2
-rw-r--r--arch/arm/plat-omap/sram.c5
-rw-r--r--drivers/staging/tidspbridge/core/_tiomap.h6
60 files changed, 699 insertions, 650 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 2006deef018..b2e4f7bcfa3 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -6,7 +6,7 @@
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \ 6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
7 common.o gpio.o dma.o wd_timer.o 7 common.o gpio.o dma.o wd_timer.o
8 8
9omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o 9omap-2-3-common = irq.o sdrc.o
10hwmod-common = omap_hwmod.o \ 10hwmod-common = omap_hwmod.o \
11 omap_hwmod_common_data.o 11 omap_hwmod_common_data.o
12clock-common = clock.o clock_common_data.o \ 12clock-common = clock.o clock_common_data.o \
@@ -72,9 +72,12 @@ endif
72endif 72endif
73 73
74# PRCM 74# PRCM
75obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm.o 75obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
76obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm.o 76obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
77obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm4xxx.o 77# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
78# will be removed once the OMAP4 part of the codebase is converted to
79# use OMAP4-specific PRCM functions.
80obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cm4xxx.o
78 81
79# OMAP powerdomain framework 82# OMAP powerdomain framework
80powerdomain-common += powerdomain.o powerdomain-common.o 83powerdomain-common += powerdomain.o powerdomain-common.o
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index 66e01acfd58..954d11f3754 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -26,7 +26,7 @@
26 26
27#include "clock.h" 27#include "clock.h"
28#include "clock2xxx.h" 28#include "clock2xxx.h"
29#include "cm.h" 29#include "cm2xxx_3xxx.h"
30#include "cm-regbits-24xx.h" 30#include "cm-regbits-24xx.h"
31 31
32/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ 32/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 019048434f1..530a76bc4a6 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -32,7 +32,7 @@
32#include "clock.h" 32#include "clock.h"
33#include "clock2xxx.h" 33#include "clock2xxx.h"
34#include "opp2xxx.h" 34#include "opp2xxx.h"
35#include "cm.h" 35#include "cm2xxx_3xxx.h"
36#include "cm-regbits-24xx.h" 36#include "cm-regbits-24xx.h"
37 37
38/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ 38/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index 2167be84a5b..df7b8050648 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -27,7 +27,7 @@
27 27
28#include "clock.h" 28#include "clock.h"
29#include "clock2xxx.h" 29#include "clock2xxx.h"
30#include "prm.h" 30#include "prm2xxx_3xxx.h"
31#include "prm-regbits-24xx.h" 31#include "prm-regbits-24xx.h"
32 32
33static int omap2_enable_osc_ck(struct clk *clk) 33static int omap2_enable_osc_ck(struct clk *clk)
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
index 822b5a79f45..8693cfdac49 100644
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ b/arch/arm/mach-omap2/clkt2xxx_sys.c
@@ -26,7 +26,7 @@
26 26
27#include "clock.h" 27#include "clock.h"
28#include "clock2xxx.h" 28#include "clock2xxx.h"
29#include "prm.h" 29#include "prm2xxx_3xxx.h"
30#include "prm-regbits-24xx.h" 30#include "prm-regbits-24xx.h"
31 31
32void __iomem *prcm_clksrc_ctrl; 32void __iomem *prcm_clksrc_ctrl;
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index aef62918aaf..f49f47d7457 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -40,7 +40,7 @@
40#include "clock.h" 40#include "clock.h"
41#include "clock2xxx.h" 41#include "clock2xxx.h"
42#include "opp2xxx.h" 42#include "opp2xxx.h"
43#include "cm.h" 43#include "cm2xxx_3xxx.h"
44#include "cm-regbits-24xx.h" 44#include "cm-regbits-24xx.h"
45 45
46const struct prcm_config *curr_prcm_set; 46const struct prcm_config *curr_prcm_set;
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 6ce512e902c..337392c3f54 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -24,7 +24,6 @@
24#include <plat/clock.h> 24#include <plat/clock.h>
25 25
26#include "clock.h" 26#include "clock.h"
27#include "cm.h"
28#include "cm-regbits-24xx.h" 27#include "cm-regbits-24xx.h"
29#include "cm-regbits-34xx.h" 28#include "cm-regbits-34xx.h"
30 29
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index b5babf5440e..cda2f1da2e1 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -29,9 +29,7 @@
29#include <plat/prcm.h> 29#include <plat/prcm.h>
30 30
31#include "clock.h" 31#include "clock.h"
32#include "prm.h" 32#include "cm2xxx_3xxx.h"
33#include "prm-regbits-24xx.h"
34#include "cm.h"
35#include "cm-regbits-24xx.h" 33#include "cm-regbits-24xx.h"
36#include "cm-regbits-34xx.h" 34#include "cm-regbits-34xx.h"
37 35
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index ed61ac2c6f7..0b2471add7d 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -22,8 +22,8 @@
22#include "clock.h" 22#include "clock.h"
23#include "clock2xxx.h" 23#include "clock2xxx.h"
24#include "opp2xxx.h" 24#include "opp2xxx.h"
25#include "prm.h" 25#include "cm2xxx_3xxx.h"
26#include "cm.h" 26#include "prm2xxx_3xxx.h"
27#include "prm-regbits-24xx.h" 27#include "prm-regbits-24xx.h"
28#include "cm-regbits-24xx.h" 28#include "cm-regbits-24xx.h"
29#include "sdrc.h" 29#include "sdrc.h"
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
index 44d0cccc51a..d87bc9cb2a3 100644
--- a/arch/arm/mach-omap2/clock2430.c
+++ b/arch/arm/mach-omap2/clock2430.c
@@ -25,7 +25,7 @@
25 25
26#include "clock.h" 26#include "clock.h"
27#include "clock2xxx.h" 27#include "clock2xxx.h"
28#include "cm.h" 28#include "cm2xxx_3xxx.h"
29#include "cm-regbits-24xx.h" 29#include "cm-regbits-24xx.h"
30 30
31/** 31/**
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 1bded4e0748..570c26d8146 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -22,8 +22,8 @@
22#include "clock.h" 22#include "clock.h"
23#include "clock2xxx.h" 23#include "clock2xxx.h"
24#include "opp2xxx.h" 24#include "opp2xxx.h"
25#include "prm.h" 25#include "cm2xxx_3xxx.h"
26#include "cm.h" 26#include "prm2xxx_3xxx.h"
27#include "prm-regbits-24xx.h" 27#include "prm-regbits-24xx.h"
28#include "cm-regbits-24xx.h" 28#include "cm-regbits-24xx.h"
29#include "sdrc.h" 29#include "sdrc.h"
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6febd5f11e8..287abc48092 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -25,7 +25,7 @@
25 25
26#include "clock.h" 26#include "clock.h"
27#include "clock34xx.h" 27#include "clock34xx.h"
28#include "cm.h" 28#include "cm2xxx_3xxx.h"
29#include "cm-regbits-34xx.h" 29#include "cm-regbits-34xx.h"
30 30
31/** 31/**
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
index b496a9305e1..74116a3cf09 100644
--- a/arch/arm/mach-omap2/clock3517.c
+++ b/arch/arm/mach-omap2/clock3517.c
@@ -25,7 +25,7 @@
25 25
26#include "clock.h" 26#include "clock.h"
27#include "clock3517.h" 27#include "clock3517.h"
28#include "cm.h" 28#include "cm2xxx_3xxx.h"
29#include "cm-regbits-34xx.h" 29#include "cm-regbits-34xx.h"
30 30
31/* 31/*
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index a447c4d2c28..81f5fdb256d 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -25,9 +25,9 @@
25 25
26#include "clock.h" 26#include "clock.h"
27#include "clock3xxx.h" 27#include "clock3xxx.h"
28#include "prm.h" 28#include "prm2xxx_3xxx.h"
29#include "prm-regbits-34xx.h" 29#include "prm-regbits-34xx.h"
30#include "cm.h" 30#include "cm2xxx_3xxx.h"
31#include "cm-regbits-34xx.h" 31#include "cm-regbits-34xx.h"
32 32
33/* 33/*
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index ee8aa39269f..a179edb03c1 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -28,9 +28,9 @@
28#include "clock36xx.h" 28#include "clock36xx.h"
29#include "clock3517.h" 29#include "clock3517.h"
30 30
31#include "cm.h" 31#include "cm2xxx_3xxx.h"
32#include "cm-regbits-34xx.h" 32#include "cm-regbits-34xx.h"
33#include "prm.h" 33#include "prm2xxx_3xxx.h"
34#include "prm-regbits-34xx.h" 34#include "prm-regbits-34xx.h"
35#include "control.h" 35#include "control.h"
36 36
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 254f341e4bd..91ab6f223b8 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -33,11 +33,15 @@
33#include "cm1_44xx.h" 33#include "cm1_44xx.h"
34#include "cm2_44xx.h" 34#include "cm2_44xx.h"
35#include "cm-regbits-44xx.h" 35#include "cm-regbits-44xx.h"
36#include "prm.h" 36#include "prm44xx.h"
37#include "prm44xx.h" 37#include "prm44xx.h"
38#include "prm-regbits-44xx.h" 38#include "prm-regbits-44xx.h"
39#include "control.h" 39#include "control.h"
40 40
41/* OMAP4 modulemode control */
42#define OMAP4430_MODULEMODE_HWCTRL 0
43#define OMAP4430_MODULEMODE_SWCTRL 1
44
41/* Root clocks */ 45/* Root clocks */
42 46
43static struct clk extalt_clkin_ck = { 47static struct clk extalt_clkin_ck = {
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 6fb61b1a0d4..a2142e0f1ef 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -27,9 +27,10 @@
27 27
28#include <linux/bitops.h> 28#include <linux/bitops.h>
29 29
30#include "prm.h" 30#include "prm2xxx_3xxx.h"
31#include "prm-regbits-24xx.h" 31#include "prm-regbits-24xx.h"
32#include "cm.h" 32#include "cm2xxx_3xxx.h"
33#include "cm2xxx_3xxx.h"
33 34
34#include <plat/clock.h> 35#include <plat/clock.h>
35#include <plat/powerdomain.h> 36#include <plat/powerdomain.h>
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 8dadf754ff1..de1d3b759ae 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -36,8 +36,8 @@
36#include <linux/io.h> 36#include <linux/io.h>
37 37
38#include <plat/clockdomain.h> 38#include <plat/clockdomain.h>
39#include "cm.h" 39#include "prm2xxx_3xxx.h"
40#include "prm.h" 40#include "cm2xxx_3xxx.h"
41#include "cm-regbits-24xx.h" 41#include "cm-regbits-24xx.h"
42#include "cm-regbits-34xx.h" 42#include "cm-regbits-34xx.h"
43#include "cm-regbits-44xx.h" 43#include "cm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index d4a52060347..7fc81f651b5 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -27,6 +27,8 @@
27#include <linux/io.h> 27#include <linux/io.h>
28 28
29#include <plat/clockdomain.h> 29#include <plat/clockdomain.h>
30#include "cm1_44xx.h"
31#include "cm2_44xx.h"
30 32
31#include "cm1_44xx.h" 33#include "cm1_44xx.h"
32#include "cm2_44xx.h" 34#include "cm2_44xx.h"
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 9a106c04c4a..0856f2bcee5 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -14,8 +14,6 @@
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 16
17#include "cm.h"
18
19/* Bits shared between registers */ 17/* Bits shared between registers */
20 18
21/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 19/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 4f959a7d881..cd9ff8b6a10 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -14,8 +14,6 @@
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 16
17#include "cm.h"
18
19/* Bits shared between registers */ 17/* Bits shared between registers */
20 18
21/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 19/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 0b72be43377..9d47a05b17b 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -22,9 +22,6 @@
22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
24 24
25#include "cm.h"
26
27
28/* 25/*
29 * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, 26 * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
30 * CM_TESLA_DYNAMICDEP 27 * CM_TESLA_DYNAMICDEP
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index bf21375eee7..a7bc096bd40 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -1,8 +1,5 @@
1#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
2#define __ARCH_ASM_MACH_OMAP2_CM_H
3
4/* 1/*
5 * OMAP2/3 Clock Management (CM) register definitions 2 * OMAP2+ Clock Management prototypes
6 * 3 *
7 * Copyright (C) 2007-2009 Texas Instruments, Inc. 4 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 * Copyright (C) 2007-2009 Nokia Corporation 5 * Copyright (C) 2007-2009 Nokia Corporation
@@ -13,133 +10,8 @@
13 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
15 */ 12 */
16 13#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
17#include "prcm-common.h" 14#define __ARCH_ASM_MACH_OMAP2_CM_H
18
19#define OMAP2420_CM_REGADDR(module, reg) \
20 OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
21#define OMAP2430_CM_REGADDR(module, reg) \
22 OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
23#define OMAP34XX_CM_REGADDR(module, reg) \
24 OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
25
26
27#include "cm44xx.h"
28
29/*
30 * Architecture-specific global CM registers
31 * Use cm_{read,write}_reg() with these registers.
32 * These registers appear once per CM module.
33 */
34
35#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
36#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
37#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
38
39#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
40#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
41
42/*
43 * Module specific CM registers from CM_BASE + domain offset
44 * Use cm_{read,write}_mod_reg() with these registers.
45 * These register offsets generally appear in more than one PRCM submodule.
46 */
47
48/* Common between 24xx and 34xx */
49
50#define CM_FCLKEN 0x0000
51#define CM_FCLKEN1 CM_FCLKEN
52#define CM_CLKEN CM_FCLKEN
53#define CM_ICLKEN 0x0010
54#define CM_ICLKEN1 CM_ICLKEN
55#define CM_ICLKEN2 0x0014
56#define CM_ICLKEN3 0x0018
57#define CM_IDLEST 0x0020
58#define CM_IDLEST1 CM_IDLEST
59#define CM_IDLEST2 0x0024
60#define CM_AUTOIDLE 0x0030
61#define CM_AUTOIDLE1 CM_AUTOIDLE
62#define CM_AUTOIDLE2 0x0034
63#define CM_AUTOIDLE3 0x0038
64#define CM_CLKSEL 0x0040
65#define CM_CLKSEL1 CM_CLKSEL
66#define CM_CLKSEL2 0x0044
67#define OMAP2_CM_CLKSTCTRL 0x0048
68#define OMAP4_CM_CLKSTCTRL 0x0000
69
70
71/* Architecture-specific registers */
72
73#define OMAP24XX_CM_FCLKEN2 0x0004
74#define OMAP24XX_CM_ICLKEN4 0x001c
75#define OMAP24XX_CM_AUTOIDLE4 0x003c
76
77#define OMAP2430_CM_IDLEST3 0x0028
78
79#define OMAP3430_CM_CLKEN_PLL 0x0004
80#define OMAP3430ES2_CM_CLKEN2 0x0004
81#define OMAP3430ES2_CM_FCLKEN3 0x0008
82#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
83#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
84#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2
85#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
86#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
87#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
88#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
89#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL
90#define OMAP3430_CM_CLKSTST 0x004c
91#define OMAP3430ES2_CM_CLKSEL4 0x004c
92#define OMAP3430ES2_CM_CLKSEL5 0x0050
93#define OMAP3430_CM_CLKSEL2_EMU 0x0050
94#define OMAP3430_CM_CLKSEL3_EMU 0x0054
95
96/* CM2.CEFUSE_CM2 register offsets */
97
98/* OMAP4 modulemode control */
99#define OMAP4430_MODULEMODE_HWCTRL 0
100#define OMAP4430_MODULEMODE_SWCTRL 1
101
102/* Clock management domain register get/set */
103
104#ifndef __ASSEMBLER__
105
106extern u32 cm_read_mod_reg(s16 module, u16 idx);
107extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
108extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
109
110extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
111 u8 idlest_shift);
112extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
113
114static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
115{
116 return cm_rmw_mod_reg_bits(bits, bits, module, idx);
117}
118
119static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
120{
121 return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
122}
123
124#endif
125
126/* CM register bits shared between 24XX and 3430 */
127
128/* CM_CLKSEL_GFX */
129#define OMAP_CLKSEL_GFX_SHIFT 0
130#define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
131
132/* CM_ICLKEN_GFX */
133#define OMAP_EN_GFX_SHIFT 0
134#define OMAP_EN_GFX_MASK (1 << 0)
135
136/* CM_IDLEST_GFX */
137#define OMAP_ST_GFX_MASK (1 << 0)
138
139
140/* CM_IDLEST indicator */
141#define OMAP24XX_CM_IDLEST_VAL 0
142#define OMAP34XX_CM_IDLEST_VAL 1
143 15
144/* 16/*
145 * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the 17 * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 721c3b66740..5978ce426ec 100644
--- a/arch/arm/mach-omap2/cm.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -10,7 +10,6 @@
10 */ 10 */
11 11
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/types.h> 13#include <linux/types.h>
15#include <linux/delay.h> 14#include <linux/delay.h>
16#include <linux/spinlock.h> 15#include <linux/spinlock.h>
@@ -19,11 +18,10 @@
19#include <linux/err.h> 18#include <linux/err.h>
20#include <linux/io.h> 19#include <linux/io.h>
21 20
22#include <asm/atomic.h>
23
24#include <plat/common.h> 21#include <plat/common.h>
25 22
26#include "cm.h" 23#include "cm.h"
24#include "cm2xxx_3xxx.h"
27#include "cm-regbits-24xx.h" 25#include "cm-regbits-24xx.h"
28#include "cm-regbits-34xx.h" 26#include "cm-regbits-34xx.h"
29 27
@@ -31,6 +29,40 @@ static const u8 cm_idlest_offs[] = {
31 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 29 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
32}; 30};
33 31
32
33u32 cm_read_mod_reg(s16 module, u16 idx)
34{
35 return __raw_readl(cm_base + module + idx);
36}
37
38void cm_write_mod_reg(u32 val, s16 module, u16 idx)
39{
40 __raw_writel(val, cm_base + module + idx);
41}
42
43/* Read-modify-write a register in a CM module. Caller must lock */
44u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
45{
46 u32 v;
47
48 v = cm_read_mod_reg(module, idx);
49 v &= ~mask;
50 v |= bits;
51 cm_write_mod_reg(v, module, idx);
52
53 return v;
54}
55
56u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
57{
58 return cm_rmw_mod_reg_bits(bits, bits, module, idx);
59}
60
61u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
62{
63 return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
64}
65
34/** 66/**
35 * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby 67 * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
36 * @prcm_mod: PRCM module offset 68 * @prcm_mod: PRCM module offset
@@ -59,7 +91,6 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
59 else 91 else
60 BUG(); 92 BUG();
61 93
62 /* XXX should be OMAP2 CM */
63 omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), 94 omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
64 MAX_MODULE_READY_TIME, i); 95 MAX_MODULE_READY_TIME, i);
65 96
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
new file mode 100644
index 00000000000..5e572112be0
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -0,0 +1,131 @@
1/*
2 * OMAP2/3 Clock Management (CM) register definitions
3 *
4 * Copyright (C) 2007-2009 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The CM hardware modules on the OMAP2/3 are quite similar to each
13 * other. The CM modules/instances on OMAP4 are quite different, so
14 * they are handled in a separate file.
15 */
16#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
17#define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
18
19#include "prcm-common.h"
20
21#define OMAP2420_CM_REGADDR(module, reg) \
22 OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
23#define OMAP2430_CM_REGADDR(module, reg) \
24 OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
25#define OMAP34XX_CM_REGADDR(module, reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
27
28
29/*
30 * OMAP3-specific global CM registers
31 * Use cm_{read,write}_reg() with these registers.
32 * These registers appear once per CM module.
33 */
34
35#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
36#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
37#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
38
39#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
40#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
41
42/*
43 * Module specific CM register offsets from CM_BASE + domain offset
44 * Use cm_{read,write}_mod_reg() with these registers.
45 * These register offsets generally appear in more than one PRCM submodule.
46 */
47
48/* Common between OMAP2 and OMAP3 */
49
50#define CM_FCLKEN 0x0000
51#define CM_FCLKEN1 CM_FCLKEN
52#define CM_CLKEN CM_FCLKEN
53#define CM_ICLKEN 0x0010
54#define CM_ICLKEN1 CM_ICLKEN
55#define CM_ICLKEN2 0x0014
56#define CM_ICLKEN3 0x0018
57#define CM_IDLEST 0x0020
58#define CM_IDLEST1 CM_IDLEST
59#define CM_IDLEST2 0x0024
60#define CM_AUTOIDLE 0x0030
61#define CM_AUTOIDLE1 CM_AUTOIDLE
62#define CM_AUTOIDLE2 0x0034
63#define CM_AUTOIDLE3 0x0038
64#define CM_CLKSEL 0x0040
65#define CM_CLKSEL1 CM_CLKSEL
66#define CM_CLKSEL2 0x0044
67#define OMAP2_CM_CLKSTCTRL 0x0048
68
69/* OMAP2-specific register offsets */
70
71#define OMAP24XX_CM_FCLKEN2 0x0004
72#define OMAP24XX_CM_ICLKEN4 0x001c
73#define OMAP24XX_CM_AUTOIDLE4 0x003c
74
75#define OMAP2430_CM_IDLEST3 0x0028
76
77/* OMAP3-specific register offsets */
78
79#define OMAP3430_CM_CLKEN_PLL 0x0004
80#define OMAP3430ES2_CM_CLKEN2 0x0004
81#define OMAP3430ES2_CM_FCLKEN3 0x0008
82#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
83#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
84#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2
85#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
86#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
87#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
88#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
89#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL
90#define OMAP3430_CM_CLKSTST 0x004c
91#define OMAP3430ES2_CM_CLKSEL4 0x004c
92#define OMAP3430ES2_CM_CLKSEL5 0x0050
93#define OMAP3430_CM_CLKSEL2_EMU 0x0050
94#define OMAP3430_CM_CLKSEL3_EMU 0x0054
95
96
97/* CM_IDLEST bit field values to indicate deasserted IdleReq */
98
99#define OMAP24XX_CM_IDLEST_VAL 0
100#define OMAP34XX_CM_IDLEST_VAL 1
101
102
103/* Clock management domain register get/set */
104
105#ifndef __ASSEMBLER__
106
107extern u32 cm_read_mod_reg(s16 module, u16 idx);
108extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
109extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
110
111extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
112 u8 idlest_shift);
113extern u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
114extern u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
115
116#endif
117
118/* CM register bits shared between 24XX and 3430 */
119
120/* CM_CLKSEL_GFX */
121#define OMAP_CLKSEL_GFX_SHIFT 0
122#define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
123
124/* CM_ICLKEN_GFX */
125#define OMAP_EN_GFX_SHIFT 0
126#define OMAP_EN_GFX_MASK (1 << 0)
127
128/* CM_IDLEST_GFX */
129#define OMAP_ST_GFX_MASK (1 << 0)
130
131#endif
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index d3905263e03..48fc3f426fb 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -18,6 +18,7 @@
18 18
19 19
20#include "prcm-common.h" 20#include "prcm-common.h"
21#include "cm.h"
21 22
22#define OMAP4_CM_CLKSTCTRL 0x0000 23#define OMAP4_CM_CLKSTCTRL 0x0000
23 24
diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c
index f8a660a1a4a..25d2b3e4c6f 100644
--- a/arch/arm/mach-omap2/cm4xxx.c
+++ b/arch/arm/mach-omap2/cm4xxx.c
@@ -23,7 +23,7 @@
23 23
24#include <plat/common.h> 24#include <plat/common.h>
25 25
26#include "cm.h" 26#include "cm44xx.h"
27#include "cm-regbits-44xx.h" 27#include "cm-regbits-44xx.h"
28 28
29/** 29/**
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index b066c6e110a..2506edfc4ac 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -20,8 +20,8 @@
20 20
21#include "cm-regbits-34xx.h" 21#include "cm-regbits-34xx.h"
22#include "prm-regbits-34xx.h" 22#include "prm-regbits-34xx.h"
23#include "cm.h" 23#include "prm2xxx_3xxx.h"
24#include "prm.h" 24#include "cm2xxx_3xxx.h"
25#include "sdrc.h" 25#include "sdrc.h"
26#include "pm.h" 26#include "pm.h"
27#include "control.h" 27#include "control.h"
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index ed8d330522f..cb535ee4e8f 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -32,9 +32,7 @@
32#include <asm/clkdev.h> 32#include <asm/clkdev.h>
33 33
34#include "clock.h" 34#include "clock.h"
35#include "prm.h" 35#include "cm2xxx_3xxx.h"
36#include "prm-regbits-34xx.h"
37#include "cm.h"
38#include "cm-regbits-34xx.h" 36#include "cm-regbits-34xx.h"
39 37
40/* CM_AUTOIDLE_PLL*.AUTO_* bit values */ 38/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 6feeeae6c21..cf5f3331af2 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -11,9 +11,16 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14/*
15 * XXX The function pointers to the PRM/CM functions are incorrect and
16 * should be removed. No device driver should be changing PRM/CM bits
17 * directly; that's a layering violation -- those bits are the responsibility
18 * of the OMAP PM core code.
19 */
20
14#include <linux/platform_device.h> 21#include <linux/platform_device.h>
15#include "prm.h" 22#include "cm2xxx_3xxx.h"
16#include "cm.h" 23#include "prm2xxx_3xxx.h"
17#ifdef CONFIG_BRIDGE_DVFS 24#ifdef CONFIG_BRIDGE_DVFS
18#include <plat/omap-pm.h> 25#include <plat/omap-pm.h>
19#endif 26#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 2b660e57a30..1312ce2913a 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -145,8 +145,9 @@
145#include <plat/omap_hwmod.h> 145#include <plat/omap_hwmod.h>
146#include <plat/prcm.h> 146#include <plat/prcm.h>
147 147
148#include "cm.h" 148#include "cm2xxx_3xxx.h"
149#include "prm.h" 149#include "cm44xx.h"
150#include "prm2xxx_3xxx.h"
150#include "prm44xx.h" 151#include "prm44xx.h"
151 152
152/* Maximum microseconds to wait for OMAP module to softreset */ 153/* Maximum microseconds to wait for OMAP module to softreset */
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index a8afb610c7d..1f5d68beabf 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -33,8 +33,8 @@
33#include <plat/clockdomain.h> 33#include <plat/clockdomain.h>
34#include <plat/dmtimer.h> 34#include <plat/dmtimer.h>
35 35
36#include "prm.h" 36#include "cm2xxx_3xxx.h"
37#include "cm.h" 37#include "prm2xxx_3xxx.h"
38#include "pm.h" 38#include "pm.h"
39 39
40int omap2_pm_debug; 40int omap2_pm_debug;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index aea7ced9a2f..8ea49dcaae4 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -42,9 +42,9 @@
42#include <plat/dma.h> 42#include <plat/dma.h>
43#include <plat/board.h> 43#include <plat/board.h>
44 44
45#include "prm.h" 45#include "prm2xxx_3xxx.h"
46#include "prm-regbits-24xx.h" 46#include "prm-regbits-24xx.h"
47#include "cm.h" 47#include "cm2xxx_3xxx.h"
48#include "cm-regbits-24xx.h" 48#include "cm-regbits-24xx.h"
49#include "sdrc.h" 49#include "sdrc.h"
50#include "pm.h" 50#include "pm.h"
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c45b4fa1dee..7e500d89280 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -41,11 +41,11 @@
41 41
42#include <asm/tlbflush.h> 42#include <asm/tlbflush.h>
43 43
44#include "cm.h" 44#include "cm2xxx_3xxx.h"
45#include "cm-regbits-34xx.h" 45#include "cm-regbits-34xx.h"
46#include "prm-regbits-34xx.h" 46#include "prm-regbits-34xx.h"
47 47
48#include "prm.h" 48#include "prm2xxx_3xxx.h"
49#include "pm.h" 49#include "pm.h"
50#include "sdrc.h" 50#include "sdrc.h"
51#include "control.h" 51#include "control.h"
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 77f42b96df4..8a0dcd05afe 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -19,6 +19,9 @@
19#include <linux/list.h> 19#include <linux/list.h>
20#include <linux/errno.h> 20#include <linux/errno.h>
21#include <linux/string.h> 21#include <linux/string.h>
22#include "cm2xxx_3xxx.h"
23#include "cm44xx.h"
24#include "prm2xxx_3xxx.h"
22#include "prm44xx.h" 25#include "prm44xx.h"
23 26
24#include <plat/cpu.h> 27#include <plat/cpu.h>
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
index 7efdf682d7f..dae767bf195 100644
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -18,6 +18,7 @@
18 18
19#include <plat/powerdomain.h> 19#include <plat/powerdomain.h>
20#include <plat/prcm.h> 20#include <plat/prcm.h>
21#include "prm2xxx_3xxx.h"
21#include "prm44xx.h" 22#include "prm44xx.h"
22#include "prm-regbits-44xx.h" 23#include "prm-regbits-44xx.h"
23#include "powerdomains.h" 24#include "powerdomains.h"
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index adc85d35928..e136895e0a3 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -19,10 +19,8 @@
19#include "powerdomains.h" 19#include "powerdomains.h"
20 20
21#include "prcm-common.h" 21#include "prcm-common.h"
22#include "prm.h" 22#include "prm2xxx_3xxx.h"
23#include "prm-regbits-24xx.h" 23#include "prm-regbits-24xx.h"
24#include "cm.h"
25#include "cm-regbits-24xx.h"
26 24
27/* 24XX powerdomains and dependencies */ 25/* 24XX powerdomains and dependencies */
28 26
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 1ddc040d7bc..1830c63ae67 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -19,9 +19,9 @@
19#include "powerdomains.h" 19#include "powerdomains.h"
20 20
21#include "prcm-common.h" 21#include "prcm-common.h"
22#include "prm.h" 22#include "prm2xxx_3xxx.h"
23#include "prm-regbits-34xx.h" 23#include "prm-regbits-34xx.h"
24#include "cm.h" 24#include "cm2xxx_3xxx.h"
25#include "cm-regbits-34xx.h" 25#include "cm-regbits-34xx.h"
26 26
27/* 27/*
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index cf6adfcf035..069a21d5491 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -26,7 +26,6 @@
26#include "powerdomains.h" 26#include "powerdomains.h"
27 27
28#include "prcm-common.h" 28#include "prcm-common.h"
29#include "prm.h"
30#include "prm-regbits-44xx.h" 29#include "prm-regbits-44xx.h"
31#include "prm44xx.h" 30#include "prm44xx.h"
32#include "prcm_mpu44xx.h" 31#include "prcm_mpu44xx.h"
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 427ab612f0d..87486f55978 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -396,5 +396,11 @@
396 */ 396 */
397#define MAX_MODULE_HARDRESET_WAIT 10000 397#define MAX_MODULE_HARDRESET_WAIT 10000
398 398
399# ifndef __ASSEMBLER__
400extern void __iomem *prm_base;
401extern void __iomem *cm_base;
402extern void __iomem *cm2_base;
403# endif
404
399#endif 405#endif
400 406
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index aac8070fadc..171c710c822 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -29,16 +29,17 @@
29 29
30#include "clock.h" 30#include "clock.h"
31#include "clock2xxx.h" 31#include "clock2xxx.h"
32#include "cm.h" 32#include "cm2xxx_3xxx.h"
33#include "prm.h" 33#include "cm44xx.h"
34#include "prm2xxx_3xxx.h"
34#include "prm44xx.h" 35#include "prm44xx.h"
35#include "prm-regbits-24xx.h" 36#include "prm-regbits-24xx.h"
36#include "prm-regbits-44xx.h" 37#include "prm-regbits-44xx.h"
37#include "control.h" 38#include "control.h"
38 39
39static void __iomem *prm_base; 40void __iomem *prm_base;
40static void __iomem *cm_base; 41void __iomem *cm_base;
41static void __iomem *cm2_base; 42void __iomem *cm2_base;
42 43
43#define MAX_MODULE_ENABLE_WAIT 100000 44#define MAX_MODULE_ENABLE_WAIT 100000
44 45
@@ -158,56 +159,6 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
158 prcm_offs, OMAP4_RM_RSTCTRL); 159 prcm_offs, OMAP4_RM_RSTCTRL);
159} 160}
160 161
161static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
162{
163 BUG_ON(!base);
164 return __raw_readl(base + module + reg);
165}
166
167static inline void __omap_prcm_write(u32 value, void __iomem *base,
168 s16 module, u16 reg)
169{
170 BUG_ON(!base);
171 __raw_writel(value, base + module + reg);
172}
173
174/* Read a register in a PRM module */
175u32 prm_read_mod_reg(s16 module, u16 idx)
176{
177 return __omap_prcm_read(prm_base, module, idx);
178}
179
180/* Write into a register in a PRM module */
181void prm_write_mod_reg(u32 val, s16 module, u16 idx)
182{
183 __omap_prcm_write(val, prm_base, module, idx);
184}
185
186/* Read-modify-write a register in a PRM module. Caller must lock */
187u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
188{
189 u32 v;
190
191 v = prm_read_mod_reg(module, idx);
192 v &= ~mask;
193 v |= bits;
194 prm_write_mod_reg(v, module, idx);
195
196 return v;
197}
198
199/* Read a PRM register, AND it, and shift the result down to bit 0 */
200u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
201{
202 u32 v;
203
204 v = prm_read_mod_reg(domain, idx);
205 v &= mask;
206 v >>= __ffs(mask);
207
208 return v;
209}
210
211/* Read a PRM register, AND it, and shift the result down to bit 0 */ 162/* Read a PRM register, AND it, and shift the result down to bit 0 */
212u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask) 163u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
213{ 164{
@@ -232,30 +183,6 @@ u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
232 183
233 return v; 184 return v;
234} 185}
235/* Read a register in a CM module */
236u32 cm_read_mod_reg(s16 module, u16 idx)
237{
238 return __omap_prcm_read(cm_base, module, idx);
239}
240
241/* Write into a register in a CM module */
242void cm_write_mod_reg(u32 val, s16 module, u16 idx)
243{
244 __omap_prcm_write(val, cm_base, module, idx);
245}
246
247/* Read-modify-write a register in a CM module. Caller must lock */
248u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
249{
250 u32 v;
251
252 v = cm_read_mod_reg(module, idx);
253 v &= ~mask;
254 v |= bits;
255 cm_write_mod_reg(v, module, idx);
256
257 return v;
258}
259 186
260/** 187/**
261 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness 188 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
@@ -266,6 +193,9 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
266 * 193 *
267 * Returns 1 if the module indicated readiness in time, or 0 if it 194 * Returns 1 if the module indicated readiness in time, or 0 if it
268 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. 195 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
196 *
197 * XXX This function is deprecated. It should be removed once the
198 * hwmod conversion is complete.
269 */ 199 */
270int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, 200int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
271 const char *name) 201 const char *name)
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 0b188ffa710..6ac966103f3 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -14,7 +14,7 @@
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 16
17#include "prm.h" 17#include "prm2xxx_3xxx.h"
18 18
19/* Bits shared between registers */ 19/* Bits shared between registers */
20 20
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index ec1a710db9c..64c087af6a8 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -1,6 +1,3 @@
1#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
2#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
3
4/* 1/*
5 * OMAP3430 Power/Reset Management register bits 2 * OMAP3430 Power/Reset Management register bits
6 * 3 *
@@ -13,8 +10,11 @@
13 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
15 */ 12 */
13#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
14#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
15
16 16
17#include "prm.h" 17#include "prm2xxx_3xxx.h"
18 18
19/* Shared register bits */ 19/* Shared register bits */
20 20
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 25b19b61017..6d2776f6fc0 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -22,8 +22,6 @@
22#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 22#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 23#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
24 24
25#include "prm.h"
26
27 25
28/* 26/*
29 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 27 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 10a24ca3f40..39d562169d1 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -1,304 +1,20 @@
1#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
2#define __ARCH_ARM_MACH_OMAP2_PRM_H
3
4/* 1/*
5 * OMAP2/3 Power/Reset Management (PRM) register definitions 2 * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
6 * 3 *
7 * Copyright (C) 2007-2009 Texas Instruments, Inc. 4 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 * Copyright (C) 2010 Nokia Corporation 5 * Copyright (C) 2010 Nokia Corporation
9 * 6 *
10 * Written by Paul Walmsley 7 * Paul Walmsley
11 * 8 *
12 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
15 */ 12 */
13#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
14#define __ARCH_ARM_MACH_OMAP2_PRM_H
16 15
17#include "prcm-common.h" 16#include "prcm-common.h"
18 17
19#define OMAP2420_PRM_REGADDR(module, reg) \
20 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
21#define OMAP2430_PRM_REGADDR(module, reg) \
22 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
23#define OMAP34XX_PRM_REGADDR(module, reg) \
24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
25
26/*
27 * Architecture-specific global PRM registers
28 * Use __raw_{read,write}l() with these registers.
29 *
30 * With a few exceptions, these are the register names beginning with
31 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
32 * IRQSTATUS and IRQENABLE bits.)
33 *
34 */
35
36#define OMAP2_PRCM_REVISION_OFFSET 0x0000
37#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
38#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
39#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
40
41#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
42#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
43#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
44#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
45
46#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
47#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
48#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
49#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
50#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
51#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
52#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
53#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
54#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
55#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
56#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
57#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
58#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
59#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
60#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
61#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
62#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
63#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
64#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
65#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
66
67#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
68#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
69
70#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
71#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
72
73#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
74#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
75#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
76#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
77#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
78#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
79#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
80#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
81#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
82#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
83
84#define OMAP3_PRM_REVISION_OFFSET 0x0004
85#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
86#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
87#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
88
89#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
90#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
91#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
92#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
93
94
95#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
96#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
97#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
98#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
99#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
100#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
101#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
102#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
103#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
104#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
105#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
106#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
107#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
108#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
109#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
110#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
111#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
112#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
113#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
114#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
115#define OMAP3_PRM_RSTST_OFFSET 0x0058
116#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
117#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
118#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
119#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
120#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
121#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
122#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
123#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
124#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
125#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
126#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
127#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
128#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
129#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
130#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
131#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
132#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
133#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
134#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
135#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
136#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
137#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
138#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
139#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
140#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
141#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
142#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
143#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
144#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
145#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
146#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
147#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
148#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
149#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
150#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
151#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
152#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
153#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
154#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
155#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
156#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
157
158#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
159#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
160#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
161#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
162
163/*
164 * Module specific PRM registers from PRM_BASE + domain offset
165 *
166 * Use prm_{read,write}_mod_reg() with these registers.
167 *
168 * With a few exceptions, these are the register names beginning with
169 * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
170 * and IRQENABLE bits.)
171 *
172 */
173
174/* Registers appearing on both 24xx and 34xx */
175
176#define OMAP2_RM_RSTCTRL 0x0050
177#define OMAP2_RM_RSTTIME 0x0054
178#define OMAP2_RM_RSTST 0x0058
179#define OMAP2_PM_PWSTCTRL 0x00e0
180#define OMAP2_PM_PWSTST 0x00e4
181
182#define PM_WKEN 0x00a0
183#define PM_WKEN1 PM_WKEN
184#define PM_WKST 0x00b0
185#define PM_WKST1 PM_WKST
186#define PM_WKDEP 0x00c8
187#define PM_EVGENCTRL 0x00d4
188#define PM_EVGENONTIM 0x00d8
189#define PM_EVGENOFFTIM 0x00dc
190
191/* Omap2 specific registers */
192#define OMAP24XX_PM_WKEN2 0x00a4
193#define OMAP24XX_PM_WKST2 0x00b4
194
195#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
196#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
197#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
198#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
199
200/* Omap3 specific registers */
201#define OMAP3430ES2_PM_WKEN3 0x00f0
202#define OMAP3430ES2_PM_WKST3 0x00b8
203
204#define OMAP3430_PM_MPUGRPSEL 0x00a4
205#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
206#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
207
208#define OMAP3430_PM_IVAGRPSEL 0x00a8
209#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
210#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
211
212#define OMAP3430_PM_PREPWSTST 0x00e8
213
214#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
215#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
216
217
218#ifndef __ASSEMBLER__
219
220/* Power/reset management domain register get/set */
221extern u32 prm_read_mod_reg(s16 module, u16 idx);
222extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
223extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
224
225/* Read-modify-write bits in a PRM register (by domain) */
226static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
227{
228 return prm_rmw_mod_reg_bits(bits, bits, module, idx);
229}
230
231static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
232{
233 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
234}
235
236/* These omap2_ PRM functions apply to both OMAP2 and 3 */
237int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
238int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
239int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
240
241#endif
242
243/*
244 * Bits common to specific registers
245 *
246 * The 3430 register and bit names are generally used,
247 * since they tend to make more sense
248 */
249
250/* PM_EVGENONTIM_MPU */
251/* Named PM_EVEGENONTIM_MPU on the 24XX */
252#define OMAP_ONTIMEVAL_SHIFT 0
253#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
254
255/* PM_EVGENOFFTIM_MPU */
256/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
257#define OMAP_OFFTIMEVAL_SHIFT 0
258#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
259
260/* PRM_CLKSETUP and PRCM_VOLTSETUP */
261/* Named PRCM_CLKSSETUP on the 24XX */
262#define OMAP_SETUP_TIME_SHIFT 0
263#define OMAP_SETUP_TIME_MASK (0xffff << 0)
264
265/* PRM_CLKSRC_CTRL */
266/* Named PRCM_CLKSRC_CTRL on the 24XX */
267#define OMAP_SYSCLKDIV_SHIFT 6
268#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
269#define OMAP_AUTOEXTCLKMODE_SHIFT 3
270#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
271#define OMAP_SYSCLKSEL_SHIFT 0
272#define OMAP_SYSCLKSEL_MASK (0x3 << 0)
273
274/* PM_EVGENCTRL_MPU */
275#define OMAP_OFFLOADMODE_SHIFT 3
276#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
277#define OMAP_ONLOADMODE_SHIFT 1
278#define OMAP_ONLOADMODE_MASK (0x3 << 1)
279#define OMAP_ENABLE_MASK (1 << 0)
280
281/* PRM_RSTTIME */
282/* Named RM_RSTTIME_WKUP on the 24xx */
283#define OMAP_RSTTIME2_SHIFT 8
284#define OMAP_RSTTIME2_MASK (0x1f << 8)
285#define OMAP_RSTTIME1_SHIFT 0
286#define OMAP_RSTTIME1_MASK (0xff << 0)
287
288/* PRM_RSTCTRL */
289/* Named RM_RSTCTRL_WKUP on the 24xx */
290/* 2420 calls RST_DPLL3 'RST_DPLL' */
291#define OMAP_RST_DPLL3_MASK (1 << 2)
292#define OMAP_RST_GS_MASK (1 << 1)
293
294
295/*
296 * Bits common to module-shared registers
297 *
298 * Not all registers of a particular type support all of these bits -
299 * check TRM if you are unsure
300 */
301
302/* 18/*
303 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP 19 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
304 * 20 *
@@ -324,59 +40,6 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
324#define OMAP_POWERSTATEST_MASK (0x3 << 0) 40#define OMAP_POWERSTATEST_MASK (0x3 << 0)
325 41
326/* 42/*
327 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
328 * called 'COREWKUP_RST'
329 *
330 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
331 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
332 */
333#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3)
334
335/*
336 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
337 *
338 * 2430: RM_RSTST_MDM
339 *
340 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
341 */
342#define OMAP_DOMAINWKUP_RST_MASK (1 << 2)
343
344/*
345 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
346 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
347 *
348 * 2430: RM_RSTST_MDM
349 *
350 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
351 */
352#define OMAP_GLOBALWARM_RST_MASK (1 << 1)
353#define OMAP_GLOBALCOLD_RST_MASK (1 << 0)
354
355/*
356 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
357 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
358 *
359 * 2430: PM_WKDEP_MDM
360 *
361 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
362 * PM_WKDEP_PER
363 */
364#define OMAP_EN_WKUP_SHIFT 4
365#define OMAP_EN_WKUP_MASK (1 << 4)
366
367/*
368 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
369 * PM_PWSTCTRL_DSP
370 *
371 * 2430: PM_PWSTCTRL_MDM
372 *
373 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
374 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
375 * PM_PWSTCTRL_NEON
376 */
377#define OMAP_LOGICRETSTATE_MASK (1 << 2)
378
379/*
380 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 43 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
381 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU 44 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
382 * 45 *
@@ -390,11 +53,4 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
390#define OMAP_POWERSTATE_MASK (0x3 << 0) 53#define OMAP_POWERSTATE_MASK (0x3 << 0)
391 54
392 55
393/*
394 * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
395 * submodule to exit hardreset
396 */
397#define MAX_MODULE_HARDRESET_WAIT 10000
398
399
400#endif 56#endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 421771eee45..064b52a3e20 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -12,18 +12,65 @@
12 */ 12 */
13 13
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/delay.h>
16#include <linux/errno.h> 15#include <linux/errno.h>
17#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/io.h>
18 18
19#include <plat/common.h> 19#include <plat/common.h>
20#include <plat/cpu.h> 20#include <plat/cpu.h>
21#include <plat/prcm.h> 21#include <plat/prcm.h>
22 22
23#include "prm.h" 23#include "prm2xxx_3xxx.h"
24#include "cm2xxx_3xxx.h"
24#include "prm-regbits-24xx.h" 25#include "prm-regbits-24xx.h"
25#include "prm-regbits-34xx.h" 26#include "prm-regbits-34xx.h"
26 27
28u32 prm_read_mod_reg(s16 module, u16 idx)
29{
30 return __raw_readl(prm_base + module + idx);
31}
32
33void prm_write_mod_reg(u32 val, s16 module, u16 idx)
34{
35 __raw_writel(val, prm_base + module + idx);
36}
37
38/* Read-modify-write a register in a PRM module. Caller must lock */
39u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
40{
41 u32 v;
42
43 v = prm_read_mod_reg(module, idx);
44 v &= ~mask;
45 v |= bits;
46 prm_write_mod_reg(v, module, idx);
47
48 return v;
49}
50
51/* Read a PRM register, AND it, and shift the result down to bit 0 */
52u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
53{
54 u32 v;
55
56 v = prm_read_mod_reg(domain, idx);
57 v &= mask;
58 v >>= __ffs(mask);
59
60 return v;
61}
62
63u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
64{
65 return prm_rmw_mod_reg_bits(bits, bits, module, idx);
66}
67
68u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
69{
70 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
71}
72
73
27/** 74/**
28 * omap2_prm_is_hardreset_asserted - read the HW reset line state of 75 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
29 * submodules contained in the hwmod module 76 * submodules contained in the hwmod module
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
new file mode 100644
index 00000000000..ab28517c82c
--- /dev/null
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -0,0 +1,367 @@
1/*
2 * OMAP2/3 Power/Reset Management (PRM) register definitions
3 *
4 * Copyright (C) 2007-2009 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The PRM hardware modules on the OMAP2/3 are quite similar to each
13 * other. The PRM on OMAP4 has a new register layout, and is handled
14 * in a separate file.
15 */
16#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
17#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
18
19#include "prcm-common.h"
20#include "prm.h"
21
22#define OMAP2420_PRM_REGADDR(module, reg) \
23 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
24#define OMAP2430_PRM_REGADDR(module, reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
26#define OMAP34XX_PRM_REGADDR(module, reg) \
27 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
28
29
30/*
31 * OMAP2-specific global PRM registers
32 * Use __raw_{read,write}l() with these registers.
33 *
34 * With a few exceptions, these are the register names beginning with
35 * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
36 * bits.)
37 *
38 */
39
40#define OMAP2_PRCM_REVISION_OFFSET 0x0000
41#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
42#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
43#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
44
45#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
46#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
47#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
48#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
49
50#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
51#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
52#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
53#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
54#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
55#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
56#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
57#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
58#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
59#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
60#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
61#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
62#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
63#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
64#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
65#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
66#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
67#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
68#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
69#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
70
71#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
72#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
73
74#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
75#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
76
77#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
78#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
79#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
80#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
81#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
82#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
83#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
84#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
85#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
86#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
87
88/*
89 * OMAP3-specific global PRM registers
90 * Use __raw_{read,write}l() with these registers.
91 *
92 * With a few exceptions, these are the register names beginning with
93 * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE
94 * bits.)
95 */
96
97#define OMAP3_PRM_REVISION_OFFSET 0x0004
98#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
99#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
100#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
101
102#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
103#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
104#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
105#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
106
107
108#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
109#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
110#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
111#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
112#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
113#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
114#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
115#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
116#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
117#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
118#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
119#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
120#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
121#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
122#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
123#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
124#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
125#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
126#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
127#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
128#define OMAP3_PRM_RSTST_OFFSET 0x0058
129#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
130#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
131#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
132#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
133#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
134#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
135#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
136#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
137#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
138#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
139#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
140#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
141#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
142#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
143#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
144#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
145#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
146#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
147#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
148#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
149#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
150#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
151#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
152#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
153#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
154#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
155#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
156#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
157#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
158#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
159#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
160#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
161#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
162#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
163#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
164#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
165#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
166#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
167#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
168#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
169#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
170
171#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
172#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
173#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
174#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
175
176/*
177 * Module specific PRM register offsets from PRM_BASE + domain offset
178 *
179 * Use prm_{read,write}_mod_reg() with these registers.
180 *
181 * With a few exceptions, these are the register names beginning with
182 * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the
183 * IRQSTATUS and IRQENABLE bits.)
184 */
185
186/* Register offsets appearing on both OMAP2 and OMAP3 */
187
188#define OMAP2_RM_RSTCTRL 0x0050
189#define OMAP2_RM_RSTTIME 0x0054
190#define OMAP2_RM_RSTST 0x0058
191#define OMAP2_PM_PWSTCTRL 0x00e0
192#define OMAP2_PM_PWSTST 0x00e4
193
194#define PM_WKEN 0x00a0
195#define PM_WKEN1 PM_WKEN
196#define PM_WKST 0x00b0
197#define PM_WKST1 PM_WKST
198#define PM_WKDEP 0x00c8
199#define PM_EVGENCTRL 0x00d4
200#define PM_EVGENONTIM 0x00d8
201#define PM_EVGENOFFTIM 0x00dc
202
203/* OMAP2xxx specific register offsets */
204#define OMAP24XX_PM_WKEN2 0x00a4
205#define OMAP24XX_PM_WKST2 0x00b4
206
207#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
208#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
209#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
210#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
211
212/* OMAP3 specific register offsets */
213#define OMAP3430ES2_PM_WKEN3 0x00f0
214#define OMAP3430ES2_PM_WKST3 0x00b8
215
216#define OMAP3430_PM_MPUGRPSEL 0x00a4
217#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
218#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
219
220#define OMAP3430_PM_IVAGRPSEL 0x00a8
221#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
222#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
223
224#define OMAP3430_PM_PREPWSTST 0x00e8
225
226#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
227#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
228
229
230#ifndef __ASSEMBLER__
231
232/* Power/reset management domain register get/set */
233extern u32 prm_read_mod_reg(s16 module, u16 idx);
234extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
235extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
236extern u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
237extern u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
238extern u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
239
240/* These omap2_ PRM functions apply to both OMAP2 and 3 */
241extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
242extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
243extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
244
245#endif
246
247/*
248 * Bits common to specific registers
249 *
250 * The 3430 register and bit names are generally used,
251 * since they tend to make more sense
252 */
253
254/* PM_EVGENONTIM_MPU */
255/* Named PM_EVEGENONTIM_MPU on the 24XX */
256#define OMAP_ONTIMEVAL_SHIFT 0
257#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
258
259/* PM_EVGENOFFTIM_MPU */
260/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
261#define OMAP_OFFTIMEVAL_SHIFT 0
262#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
263
264/* PRM_CLKSETUP and PRCM_VOLTSETUP */
265/* Named PRCM_CLKSSETUP on the 24XX */
266#define OMAP_SETUP_TIME_SHIFT 0
267#define OMAP_SETUP_TIME_MASK (0xffff << 0)
268
269/* PRM_CLKSRC_CTRL */
270/* Named PRCM_CLKSRC_CTRL on the 24XX */
271#define OMAP_SYSCLKDIV_SHIFT 6
272#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
273#define OMAP_AUTOEXTCLKMODE_SHIFT 3
274#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
275#define OMAP_SYSCLKSEL_SHIFT 0
276#define OMAP_SYSCLKSEL_MASK (0x3 << 0)
277
278/* PM_EVGENCTRL_MPU */
279#define OMAP_OFFLOADMODE_SHIFT 3
280#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
281#define OMAP_ONLOADMODE_SHIFT 1
282#define OMAP_ONLOADMODE_MASK (0x3 << 1)
283#define OMAP_ENABLE_MASK (1 << 0)
284
285/* PRM_RSTTIME */
286/* Named RM_RSTTIME_WKUP on the 24xx */
287#define OMAP_RSTTIME2_SHIFT 8
288#define OMAP_RSTTIME2_MASK (0x1f << 8)
289#define OMAP_RSTTIME1_SHIFT 0
290#define OMAP_RSTTIME1_MASK (0xff << 0)
291
292/* PRM_RSTCTRL */
293/* Named RM_RSTCTRL_WKUP on the 24xx */
294/* 2420 calls RST_DPLL3 'RST_DPLL' */
295#define OMAP_RST_DPLL3_MASK (1 << 2)
296#define OMAP_RST_GS_MASK (1 << 1)
297
298
299/*
300 * Bits common to module-shared registers
301 *
302 * Not all registers of a particular type support all of these bits -
303 * check TRM if you are unsure
304 */
305
306/*
307 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
308 * called 'COREWKUP_RST'
309 *
310 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
311 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
312 */
313#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3)
314
315/*
316 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
317 *
318 * 2430: RM_RSTST_MDM
319 *
320 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
321 */
322#define OMAP_DOMAINWKUP_RST_MASK (1 << 2)
323
324/*
325 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
326 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
327 *
328 * 2430: RM_RSTST_MDM
329 *
330 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
331 */
332#define OMAP_GLOBALWARM_RST_MASK (1 << 1)
333#define OMAP_GLOBALCOLD_RST_MASK (1 << 0)
334
335/*
336 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
337 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
338 *
339 * 2430: PM_WKDEP_MDM
340 *
341 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
342 * PM_WKDEP_PER
343 */
344#define OMAP_EN_WKUP_SHIFT 4
345#define OMAP_EN_WKUP_MASK (1 << 4)
346
347/*
348 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
349 * PM_PWSTCTRL_DSP
350 *
351 * 2430: PM_PWSTCTRL_MDM
352 *
353 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
354 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
355 * PM_PWSTCTRL_NEON
356 */
357#define OMAP_LOGICRETSTATE_MASK (1 << 2)
358
359
360/*
361 * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
362 * submodule to exit hardreset
363 */
364#define MAX_MODULE_HARDRESET_WAIT 10000
365
366
367#endif
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 0d444a5c939..3d361497ca7 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -26,6 +26,7 @@
26#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H 26#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
27 27
28#include "prcm-common.h" 28#include "prcm-common.h"
29#include "prm.h"
29 30
30#define OMAP4430_PRM_BASE 0x4a306000 31#define OMAP4430_PRM_BASE 0x4a306000
31 32
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 4c65f5628b3..da6f3a63b5d 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -27,8 +27,6 @@
27#include <plat/clock.h> 27#include <plat/clock.h>
28#include <plat/sram.h> 28#include <plat/sram.h>
29 29
30#include "prm.h"
31
32#include <plat/sdrc.h> 30#include <plat/sdrc.h>
33#include "sdrc.h" 31#include "sdrc.h"
34 32
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 0f4d27aef44..64778b6240c 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -28,7 +28,7 @@
28#include <plat/clock.h> 28#include <plat/clock.h>
29#include <plat/sram.h> 29#include <plat/sram.h>
30 30
31#include "prm.h" 31#include "prm2xxx_3xxx.h"
32#include "clock.h" 32#include "clock.h"
33#include <plat/sdrc.h> 33#include <plat/sdrc.h>
34#include "sdrc.h" 34#include "sdrc.h"
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 0548bbd4340..26770d80419 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -40,9 +40,9 @@
40#include <plat/omap_hwmod.h> 40#include <plat/omap_hwmod.h>
41#include <plat/omap_device.h> 41#include <plat/omap_device.h>
42 42
43#include "prm.h" 43#include "prm2xxx_3xxx.h"
44#include "pm.h" 44#include "pm.h"
45#include "cm.h" 45#include "cm2xxx_3xxx.h"
46#include "prm-regbits-34xx.h" 46#include "prm-regbits-34xx.h"
47#include "control.h" 47#include "control.h"
48 48
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index e3b5cd76c54..98d8232808b 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -27,8 +27,8 @@
27#include <plat/sram.h> 27#include <plat/sram.h>
28#include <mach/io.h> 28#include <mach/io.h>
29 29
30#include "cm.h" 30#include "cm2xxx_3xxx.h"
31#include "prm.h" 31#include "prm2xxx_3xxx.h"
32#include "sdrc.h" 32#include "sdrc.h"
33#include "control.h" 33#include "control.h"
34 34
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index 92e6e1a12af..8e7e6fef09e 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -27,8 +27,8 @@
27#include <mach/io.h> 27#include <mach/io.h>
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29 29
30#include "prm.h" 30#include "prm2xxx_3xxx.h"
31#include "cm.h" 31#include "cm2xxx_3xxx.h"
32#include "sdrc.h" 32#include "sdrc.h"
33 33
34 .text 34 .text
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index ab4973695c7..9ea87f68524 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -27,8 +27,8 @@
27#include <mach/io.h> 27#include <mach/io.h>
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29 29
30#include "prm.h" 30#include "prm2xxx_3xxx.h"
31#include "cm.h" 31#include "cm2xxx_3xxx.h"
32#include "sdrc.h" 32#include "sdrc.h"
33 33
34 .text 34 .text
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 3637274af5b..b7aba60f832 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -32,7 +32,7 @@
32#include <mach/io.h> 32#include <mach/io.h>
33 33
34#include "sdrc.h" 34#include "sdrc.h"
35#include "cm.h" 35#include "cm2xxx_3xxx.h"
36 36
37 .text 37 .text
38 38
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index a9d69a09920..6b8088ec74a 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -27,6 +27,8 @@
27#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H 27#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
28#define __ARCH_ARM_MACH_OMAP_COMMON_H 28#define __ARCH_ARM_MACH_OMAP_COMMON_H
29 29
30#include <linux/delay.h>
31
30#include <plat/i2c.h> 32#include <plat/i2c.h>
31 33
32struct sys_timer; 34struct sys_timer;
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index ab77442e42a..3769fc6eca2 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -34,15 +34,8 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
34void omap3_prcm_save_context(void); 34void omap3_prcm_save_context(void);
35void omap3_prcm_restore_context(void); 35void omap3_prcm_restore_context(void);
36 36
37u32 prm_read_mod_reg(s16 module, u16 idx);
38void prm_write_mod_reg(u32 val, s16 module, u16 idx);
39u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
40u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
41u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); 37u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
42u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); 38u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
43u32 cm_read_mod_reg(s16 module, u16 idx);
44void cm_write_mod_reg(u32 val, s16 module, u16 idx);
45u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
46 39
47#endif 40#endif
48 41
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index fdecd339d4f..95449b90074 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -28,6 +28,8 @@
28#include <plat/dma.h> 28#include <plat/dma.h>
29#include <plat/mcbsp.h> 29#include <plat/mcbsp.h>
30 30
31/* XXX These "sideways" includes are a sign that something is wrong */
32#include "../mach-omap2/cm2xxx_3xxx.h"
31#include "../mach-omap2/cm-regbits-34xx.h" 33#include "../mach-omap2/cm-regbits-34xx.h"
32 34
33struct omap_mcbsp **mcbsp_ptr; 35struct omap_mcbsp **mcbsp_ptr;
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 1a686c89d8d..e26e50487d6 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -33,9 +33,10 @@
33 33
34#include "sram.h" 34#include "sram.h"
35#include "fb.h" 35#include "fb.h"
36
37/* XXX These "sideways" includes are a sign that something is wrong */
36#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 38#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
37# include "../mach-omap2/prm.h" 39# include "../mach-omap2/prm2xxx_3xxx.h"
38# include "../mach-omap2/cm.h"
39# include "../mach-omap2/sdrc.h" 40# include "../mach-omap2/sdrc.h"
40#endif 41#endif
41 42
diff --git a/drivers/staging/tidspbridge/core/_tiomap.h b/drivers/staging/tidspbridge/core/_tiomap.h
index 1c1f157e167..7fac488f7f4 100644
--- a/drivers/staging/tidspbridge/core/_tiomap.h
+++ b/drivers/staging/tidspbridge/core/_tiomap.h
@@ -21,6 +21,12 @@
21 21
22#include <plat/powerdomain.h> 22#include <plat/powerdomain.h>
23#include <plat/clockdomain.h> 23#include <plat/clockdomain.h>
24/*
25 * XXX These mach-omap2/ includes are wrong and should be removed. No
26 * driver should read or write to PRM/CM registers directly; they
27 * should rely on OMAP core code to do this.
28 */
29#include <mach-omap2/cm2xxx_3xxx.h>
24#include <mach-omap2/prm-regbits-34xx.h> 30#include <mach-omap2/prm-regbits-34xx.h>
25#include <mach-omap2/cm-regbits-34xx.h> 31#include <mach-omap2/cm-regbits-34xx.h>
26#include <dspbridge/devdefs.h> 32#include <dspbridge/devdefs.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 04:34:59 -0400