diff options
-rw-r--r-- | arch/mips/ar7/platform.c | 2 | ||||
-rw-r--r-- | arch/mips/ar7/setup.c | 2 | ||||
-rw-r--r-- | arch/mips/ath79/setup.c | 2 | ||||
-rw-r--r-- | arch/mips/bcm47xx/setup.c | 4 | ||||
-rw-r--r-- | arch/mips/cavium-octeon/setup.c | 6 | ||||
-rw-r--r-- | arch/mips/cavium-octeon/smp.c | 2 | ||||
-rw-r--r-- | arch/mips/include/asm/pgtable-32.h | 7 | ||||
-rw-r--r-- | arch/mips/include/asm/tlbmisc.h | 10 | ||||
-rw-r--r-- | arch/mips/jazz/irq.c | 1 | ||||
-rw-r--r-- | arch/mips/jazz/setup.c | 1 | ||||
-rw-r--r-- | arch/mips/jz4740/board-qi_lb60.c | 2 | ||||
-rw-r--r-- | arch/mips/kernel/smtc.c | 4 | ||||
-rw-r--r-- | arch/mips/kernel/traps.c | 4 | ||||
-rw-r--r-- | arch/mips/lantiq/clk.c | 4 | ||||
-rw-r--r-- | arch/mips/lantiq/irq.c | 12 | ||||
-rw-r--r-- | arch/mips/lantiq/xway/dma.c | 6 | ||||
-rw-r--r-- | arch/mips/lantiq/xway/ebu.c | 6 | ||||
-rw-r--r-- | arch/mips/lantiq/xway/pmu.c | 8 | ||||
-rw-r--r-- | arch/mips/lantiq/xway/reset.c | 6 | ||||
-rw-r--r-- | arch/mips/mm/c-octeon.c | 2 | ||||
-rw-r--r-- | arch/mips/mm/tlb-r3k.c | 1 | ||||
-rw-r--r-- | arch/mips/mm/tlb-r4k.c | 1 | ||||
-rw-r--r-- | arch/mips/pci/msi-octeon.c | 2 | ||||
-rw-r--r-- | arch/mips/pci/pci-alchemy.c | 138 | ||||
-rw-r--r-- | arch/mips/pmc-sierra/msp71xx/msp_setup.c | 2 | ||||
-rw-r--r-- | arch/mips/sgi-ip27/ip27-irq.c | 4 |
26 files changed, 123 insertions, 116 deletions
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index 33ffecf6a6d..60102392af0 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c | |||
@@ -536,7 +536,7 @@ static int __init ar7_register_uarts(void) | |||
536 | 536 | ||
537 | bus_clk = clk_get(NULL, "bus"); | 537 | bus_clk = clk_get(NULL, "bus"); |
538 | if (IS_ERR(bus_clk)) | 538 | if (IS_ERR(bus_clk)) |
539 | panic("unable to get bus clk\n"); | 539 | panic("unable to get bus clk"); |
540 | 540 | ||
541 | uart_port.type = PORT_AR7; | 541 | uart_port.type = PORT_AR7; |
542 | uart_port.uartclk = clk_get_rate(bus_clk) / 2; | 542 | uart_port.uartclk = clk_get_rate(bus_clk) / 2; |
diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c index f20b53e597c..9a357fffcfb 100644 --- a/arch/mips/ar7/setup.c +++ b/arch/mips/ar7/setup.c | |||
@@ -96,7 +96,7 @@ void __init plat_mem_setup(void) | |||
96 | 96 | ||
97 | io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000); | 97 | io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000); |
98 | if (!io_base) | 98 | if (!io_base) |
99 | panic("Can't remap IO base!\n"); | 99 | panic("Can't remap IO base!"); |
100 | set_io_port_base(io_base); | 100 | set_io_port_base(io_base); |
101 | 101 | ||
102 | prom_meminit(); | 102 | prom_meminit(); |
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 159b42f106b..1cf60e1d9dd 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c | |||
@@ -134,7 +134,7 @@ static void __init ath79_detect_sys_type(void) | |||
134 | break; | 134 | break; |
135 | 135 | ||
136 | default: | 136 | default: |
137 | panic("ath79: unknown SoC, id:0x%08x\n", id); | 137 | panic("ath79: unknown SoC, id:0x%08x", id); |
138 | } | 138 | } |
139 | 139 | ||
140 | sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); | 140 | sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); |
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 1cfdda03546..aab6b0c40a7 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c | |||
@@ -289,7 +289,7 @@ static void __init bcm47xx_register_ssb(void) | |||
289 | err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE, | 289 | err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE, |
290 | bcm47xx_get_invariants); | 290 | bcm47xx_get_invariants); |
291 | if (err) | 291 | if (err) |
292 | panic("Failed to initialize SSB bus (err %d)\n", err); | 292 | panic("Failed to initialize SSB bus (err %d)", err); |
293 | 293 | ||
294 | mcore = &bcm47xx_bus.ssb.mipscore; | 294 | mcore = &bcm47xx_bus.ssb.mipscore; |
295 | if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) { | 295 | if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) { |
@@ -314,7 +314,7 @@ static void __init bcm47xx_register_bcma(void) | |||
314 | 314 | ||
315 | err = bcma_host_soc_register(&bcm47xx_bus.bcma); | 315 | err = bcma_host_soc_register(&bcm47xx_bus.bcma); |
316 | if (err) | 316 | if (err) |
317 | panic("Failed to initialize BCMA bus (err %d)\n", err); | 317 | panic("Failed to initialize BCMA bus (err %d)", err); |
318 | } | 318 | } |
319 | #endif | 319 | #endif |
320 | 320 | ||
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index b394552e5ca..260b2736734 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c | |||
@@ -759,11 +759,11 @@ void prom_free_prom_memory(void) | |||
759 | : "=r" (insn) : : "$31", "memory"); | 759 | : "=r" (insn) : : "$31", "memory"); |
760 | 760 | ||
761 | if ((insn >> 26) != 0x33) | 761 | if ((insn >> 26) != 0x33) |
762 | panic("No PREF instruction at Core-14449 probe point.\n"); | 762 | panic("No PREF instruction at Core-14449 probe point."); |
763 | 763 | ||
764 | if (((insn >> 16) & 0x1f) != 28) | 764 | if (((insn >> 16) & 0x1f) != 28) |
765 | panic("Core-14449 WAR not in place (%04x).\n" | 765 | panic("Core-14449 WAR not in place (%04x).\n" |
766 | "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn); | 766 | "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn); |
767 | } | 767 | } |
768 | #ifdef CONFIG_CAVIUM_DECODE_RSL | 768 | #ifdef CONFIG_CAVIUM_DECODE_RSL |
769 | cvmx_interrupt_rsl_enable(); | 769 | cvmx_interrupt_rsl_enable(); |
@@ -771,7 +771,7 @@ void prom_free_prom_memory(void) | |||
771 | /* Add an interrupt handler for general failures. */ | 771 | /* Add an interrupt handler for general failures. */ |
772 | if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, | 772 | if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, |
773 | "RML/RSL", octeon_rlm_interrupt)) { | 773 | "RML/RSL", octeon_rlm_interrupt)) { |
774 | panic("Unable to request_irq(OCTEON_IRQ_RML)\n"); | 774 | panic("Unable to request_irq(OCTEON_IRQ_RML)"); |
775 | } | 775 | } |
776 | #endif | 776 | #endif |
777 | } | 777 | } |
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index efcfff4d462..b1535fe409d 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c | |||
@@ -210,7 +210,7 @@ void octeon_prepare_cpus(unsigned int max_cpus) | |||
210 | if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, | 210 | if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, |
211 | IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI", | 211 | IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI", |
212 | mailbox_interrupt)) { | 212 | mailbox_interrupt)) { |
213 | panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); | 213 | panic("Cannot request_irq(OCTEON_IRQ_MBOX0)"); |
214 | } | 214 | } |
215 | } | 215 | } |
216 | 216 | ||
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index d169c07c38e..5d56bb23034 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h | |||
@@ -19,12 +19,7 @@ | |||
19 | #include <asm-generic/pgtable-nopmd.h> | 19 | #include <asm-generic/pgtable-nopmd.h> |
20 | 20 | ||
21 | /* | 21 | /* |
22 | * - add_wired_entry() add a fixed TLB entry, and move wired register | 22 | * Basically we have the same two-level (which is the logical three level |
23 | */ | ||
24 | extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, | ||
25 | unsigned long entryhi, unsigned long pagemask); | ||
26 | |||
27 | /* Basically we have the same two-level (which is the logical three level | ||
28 | * Linux page table layout folded) page tables as the i386. Some day | 23 | * Linux page table layout folded) page tables as the i386. Some day |
29 | * when we have proper page coloring support we can have a 1% quicker | 24 | * when we have proper page coloring support we can have a 1% quicker |
30 | * tlb refill handling mechanism, but for now it is a bit slower but | 25 | * tlb refill handling mechanism, but for now it is a bit slower but |
diff --git a/arch/mips/include/asm/tlbmisc.h b/arch/mips/include/asm/tlbmisc.h new file mode 100644 index 00000000000..3a452282cba --- /dev/null +++ b/arch/mips/include/asm/tlbmisc.h | |||
@@ -0,0 +1,10 @@ | |||
1 | #ifndef __ASM_TLBMISC_H | ||
2 | #define __ASM_TLBMISC_H | ||
3 | |||
4 | /* | ||
5 | * - add_wired_entry() add a fixed TLB entry, and move wired register | ||
6 | */ | ||
7 | extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, | ||
8 | unsigned long entryhi, unsigned long pagemask); | ||
9 | |||
10 | #endif /* __ASM_TLBMISC_H */ | ||
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 0f4a14752a7..f21868b28b2 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <asm/io.h> | 20 | #include <asm/io.h> |
21 | #include <asm/jazz.h> | 21 | #include <asm/jazz.h> |
22 | #include <asm/pgtable.h> | 22 | #include <asm/pgtable.h> |
23 | #include <asm/tlbmisc.h> | ||
23 | 24 | ||
24 | static DEFINE_RAW_SPINLOCK(r4030_lock); | 25 | static DEFINE_RAW_SPINLOCK(r4030_lock); |
25 | 26 | ||
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index 0d0f054a02f..820e926dacb 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include <asm/jazzdma.h> | 21 | #include <asm/jazzdma.h> |
22 | #include <asm/reboot.h> | 22 | #include <asm/reboot.h> |
23 | #include <asm/pgtable.h> | 23 | #include <asm/pgtable.h> |
24 | #include <asm/tlbmisc.h> | ||
24 | 25 | ||
25 | extern asmlinkage void jazz_handle_int(void); | 26 | extern asmlinkage void jazz_handle_int(void); |
26 | 27 | ||
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index c3b04be3fb2..639e3ce6c26 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c | |||
@@ -488,7 +488,7 @@ static int __init qi_lb60_board_setup(void) | |||
488 | board_gpio_setup(); | 488 | board_gpio_setup(); |
489 | 489 | ||
490 | if (qi_lb60_init_platform_devices()) | 490 | if (qi_lb60_init_platform_devices()) |
491 | panic("Failed to initialize platform devices\n"); | 491 | panic("Failed to initialize platform devices"); |
492 | 492 | ||
493 | return 0; | 493 | return 0; |
494 | } | 494 | } |
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 17c9412b5f4..0a42ff3ff6a 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c | |||
@@ -559,7 +559,7 @@ void smtc_prepare_cpus(int cpus) | |||
559 | 559 | ||
560 | pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL); | 560 | pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL); |
561 | if (pipi == NULL) | 561 | if (pipi == NULL) |
562 | panic("kmalloc of IPI message buffers failed\n"); | 562 | panic("kmalloc of IPI message buffers failed"); |
563 | else | 563 | else |
564 | printk("IPI buffer pool of %d buffers\n", nipi); | 564 | printk("IPI buffer pool of %d buffers\n", nipi); |
565 | for (i = 0; i < nipi; i++) { | 565 | for (i = 0; i < nipi; i++) { |
@@ -813,7 +813,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) | |||
813 | if (pipi == NULL) { | 813 | if (pipi == NULL) { |
814 | bust_spinlocks(1); | 814 | bust_spinlocks(1); |
815 | mips_mt_regdump(dvpe()); | 815 | mips_mt_regdump(dvpe()); |
816 | panic("IPI Msg. Buffers Depleted\n"); | 816 | panic("IPI Msg. Buffers Depleted"); |
817 | } | 817 | } |
818 | pipi->type = type; | 818 | pipi->type = type; |
819 | pipi->arg = (void *)action; | 819 | pipi->arg = (void *)action; |
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 5c8a49d5505..363c4764b81 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
@@ -400,7 +400,7 @@ void __noreturn die(const char *str, struct pt_regs *regs) | |||
400 | panic("Fatal exception in interrupt"); | 400 | panic("Fatal exception in interrupt"); |
401 | 401 | ||
402 | if (panic_on_oops) { | 402 | if (panic_on_oops) { |
403 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); | 403 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); |
404 | ssleep(5); | 404 | ssleep(5); |
405 | panic("Fatal exception"); | 405 | panic("Fatal exception"); |
406 | } | 406 | } |
@@ -1150,7 +1150,7 @@ asmlinkage void do_mt(struct pt_regs *regs) | |||
1150 | asmlinkage void do_dsp(struct pt_regs *regs) | 1150 | asmlinkage void do_dsp(struct pt_regs *regs) |
1151 | { | 1151 | { |
1152 | if (cpu_has_dsp) | 1152 | if (cpu_has_dsp) |
1153 | panic("Unexpected DSP exception\n"); | 1153 | panic("Unexpected DSP exception"); |
1154 | 1154 | ||
1155 | force_sig(SIGILL, current); | 1155 | force_sig(SIGILL, current); |
1156 | } | 1156 | } |
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c index 77ed70fc2fe..412814fdd3e 100644 --- a/arch/mips/lantiq/clk.c +++ b/arch/mips/lantiq/clk.c | |||
@@ -134,11 +134,11 @@ void __init plat_time_init(void) | |||
134 | struct clk *clk; | 134 | struct clk *clk; |
135 | 135 | ||
136 | if (insert_resource(&iomem_resource, <q_cgu_resource) < 0) | 136 | if (insert_resource(&iomem_resource, <q_cgu_resource) < 0) |
137 | panic("Failed to insert cgu memory\n"); | 137 | panic("Failed to insert cgu memory"); |
138 | 138 | ||
139 | if (request_mem_region(ltq_cgu_resource.start, | 139 | if (request_mem_region(ltq_cgu_resource.start, |
140 | resource_size(<q_cgu_resource), "cgu") < 0) | 140 | resource_size(<q_cgu_resource), "cgu") < 0) |
141 | panic("Failed to request cgu memory\n"); | 141 | panic("Failed to request cgu memory"); |
142 | 142 | ||
143 | ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start, | 143 | ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start, |
144 | resource_size(<q_cgu_resource)); | 144 | resource_size(<q_cgu_resource)); |
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 3c56179b4ca..d673731c538 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c | |||
@@ -248,28 +248,28 @@ void __init arch_init_irq(void) | |||
248 | int i; | 248 | int i; |
249 | 249 | ||
250 | if (insert_resource(&iomem_resource, <q_icu_resource) < 0) | 250 | if (insert_resource(&iomem_resource, <q_icu_resource) < 0) |
251 | panic("Failed to insert icu memory\n"); | 251 | panic("Failed to insert icu memory"); |
252 | 252 | ||
253 | if (request_mem_region(ltq_icu_resource.start, | 253 | if (request_mem_region(ltq_icu_resource.start, |
254 | resource_size(<q_icu_resource), "icu") < 0) | 254 | resource_size(<q_icu_resource), "icu") < 0) |
255 | panic("Failed to request icu memory\n"); | 255 | panic("Failed to request icu memory"); |
256 | 256 | ||
257 | ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start, | 257 | ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start, |
258 | resource_size(<q_icu_resource)); | 258 | resource_size(<q_icu_resource)); |
259 | if (!ltq_icu_membase) | 259 | if (!ltq_icu_membase) |
260 | panic("Failed to remap icu memory\n"); | 260 | panic("Failed to remap icu memory"); |
261 | 261 | ||
262 | if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) | 262 | if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) |
263 | panic("Failed to insert eiu memory\n"); | 263 | panic("Failed to insert eiu memory"); |
264 | 264 | ||
265 | if (request_mem_region(ltq_eiu_resource.start, | 265 | if (request_mem_region(ltq_eiu_resource.start, |
266 | resource_size(<q_eiu_resource), "eiu") < 0) | 266 | resource_size(<q_eiu_resource), "eiu") < 0) |
267 | panic("Failed to request eiu memory\n"); | 267 | panic("Failed to request eiu memory"); |
268 | 268 | ||
269 | ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, | 269 | ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, |
270 | resource_size(<q_eiu_resource)); | 270 | resource_size(<q_eiu_resource)); |
271 | if (!ltq_eiu_membase) | 271 | if (!ltq_eiu_membase) |
272 | panic("Failed to remap eiu memory\n"); | 272 | panic("Failed to remap eiu memory"); |
273 | 273 | ||
274 | /* make sure all irqs are turned off by default */ | 274 | /* make sure all irqs are turned off by default */ |
275 | for (i = 0; i < 5; i++) | 275 | for (i = 0; i < 5; i++) |
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c index cbb6ae5747b..b210e936c7c 100644 --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c | |||
@@ -222,17 +222,17 @@ ltq_dma_init(void) | |||
222 | 222 | ||
223 | /* insert and request the memory region */ | 223 | /* insert and request the memory region */ |
224 | if (insert_resource(&iomem_resource, <q_dma_resource) < 0) | 224 | if (insert_resource(&iomem_resource, <q_dma_resource) < 0) |
225 | panic("Failed to insert dma memory\n"); | 225 | panic("Failed to insert dma memory"); |
226 | 226 | ||
227 | if (request_mem_region(ltq_dma_resource.start, | 227 | if (request_mem_region(ltq_dma_resource.start, |
228 | resource_size(<q_dma_resource), "dma") < 0) | 228 | resource_size(<q_dma_resource), "dma") < 0) |
229 | panic("Failed to request dma memory\n"); | 229 | panic("Failed to request dma memory"); |
230 | 230 | ||
231 | /* remap dma register range */ | 231 | /* remap dma register range */ |
232 | ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, | 232 | ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, |
233 | resource_size(<q_dma_resource)); | 233 | resource_size(<q_dma_resource)); |
234 | if (!ltq_dma_membase) | 234 | if (!ltq_dma_membase) |
235 | panic("Failed to remap dma memory\n"); | 235 | panic("Failed to remap dma memory"); |
236 | 236 | ||
237 | /* power up and reset the dma engine */ | 237 | /* power up and reset the dma engine */ |
238 | ltq_pmu_enable(PMU_DMA); | 238 | ltq_pmu_enable(PMU_DMA); |
diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c index 033b3184c7a..862e3e83068 100644 --- a/arch/mips/lantiq/xway/ebu.c +++ b/arch/mips/lantiq/xway/ebu.c | |||
@@ -32,17 +32,17 @@ static int __init lantiq_ebu_init(void) | |||
32 | { | 32 | { |
33 | /* insert and request the memory region */ | 33 | /* insert and request the memory region */ |
34 | if (insert_resource(&iomem_resource, <q_ebu_resource) < 0) | 34 | if (insert_resource(&iomem_resource, <q_ebu_resource) < 0) |
35 | panic("Failed to insert ebu memory\n"); | 35 | panic("Failed to insert ebu memory"); |
36 | 36 | ||
37 | if (request_mem_region(ltq_ebu_resource.start, | 37 | if (request_mem_region(ltq_ebu_resource.start, |
38 | resource_size(<q_ebu_resource), "ebu") < 0) | 38 | resource_size(<q_ebu_resource), "ebu") < 0) |
39 | panic("Failed to request ebu memory\n"); | 39 | panic("Failed to request ebu memory"); |
40 | 40 | ||
41 | /* remap ebu register range */ | 41 | /* remap ebu register range */ |
42 | ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start, | 42 | ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start, |
43 | resource_size(<q_ebu_resource)); | 43 | resource_size(<q_ebu_resource)); |
44 | if (!ltq_ebu_membase) | 44 | if (!ltq_ebu_membase) |
45 | panic("Failed to remap ebu memory\n"); | 45 | panic("Failed to remap ebu memory"); |
46 | 46 | ||
47 | /* make sure to unprotect the memory region where flash is located */ | 47 | /* make sure to unprotect the memory region where flash is located */ |
48 | ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); | 48 | ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); |
diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c index 39f0d2641cb..fe85361e032 100644 --- a/arch/mips/lantiq/xway/pmu.c +++ b/arch/mips/lantiq/xway/pmu.c | |||
@@ -40,7 +40,7 @@ void ltq_pmu_enable(unsigned int module) | |||
40 | do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); | 40 | do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); |
41 | 41 | ||
42 | if (!err) | 42 | if (!err) |
43 | panic("activating PMU module failed!\n"); | 43 | panic("activating PMU module failed!"); |
44 | } | 44 | } |
45 | EXPORT_SYMBOL(ltq_pmu_enable); | 45 | EXPORT_SYMBOL(ltq_pmu_enable); |
46 | 46 | ||
@@ -53,16 +53,16 @@ EXPORT_SYMBOL(ltq_pmu_disable); | |||
53 | int __init ltq_pmu_init(void) | 53 | int __init ltq_pmu_init(void) |
54 | { | 54 | { |
55 | if (insert_resource(&iomem_resource, <q_pmu_resource) < 0) | 55 | if (insert_resource(&iomem_resource, <q_pmu_resource) < 0) |
56 | panic("Failed to insert pmu memory\n"); | 56 | panic("Failed to insert pmu memory"); |
57 | 57 | ||
58 | if (request_mem_region(ltq_pmu_resource.start, | 58 | if (request_mem_region(ltq_pmu_resource.start, |
59 | resource_size(<q_pmu_resource), "pmu") < 0) | 59 | resource_size(<q_pmu_resource), "pmu") < 0) |
60 | panic("Failed to request pmu memory\n"); | 60 | panic("Failed to request pmu memory"); |
61 | 61 | ||
62 | ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start, | 62 | ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start, |
63 | resource_size(<q_pmu_resource)); | 63 | resource_size(<q_pmu_resource)); |
64 | if (!ltq_pmu_membase) | 64 | if (!ltq_pmu_membase) |
65 | panic("Failed to remap pmu memory\n"); | 65 | panic("Failed to remap pmu memory"); |
66 | return 0; | 66 | return 0; |
67 | } | 67 | } |
68 | 68 | ||
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c index 3d41f0bb5bf..8b66bd87f0c 100644 --- a/arch/mips/lantiq/xway/reset.c +++ b/arch/mips/lantiq/xway/reset.c | |||
@@ -69,17 +69,17 @@ static int __init mips_reboot_setup(void) | |||
69 | { | 69 | { |
70 | /* insert and request the memory region */ | 70 | /* insert and request the memory region */ |
71 | if (insert_resource(&iomem_resource, <q_rcu_resource) < 0) | 71 | if (insert_resource(&iomem_resource, <q_rcu_resource) < 0) |
72 | panic("Failed to insert rcu memory\n"); | 72 | panic("Failed to insert rcu memory"); |
73 | 73 | ||
74 | if (request_mem_region(ltq_rcu_resource.start, | 74 | if (request_mem_region(ltq_rcu_resource.start, |
75 | resource_size(<q_rcu_resource), "rcu") < 0) | 75 | resource_size(<q_rcu_resource), "rcu") < 0) |
76 | panic("Failed to request rcu memory\n"); | 76 | panic("Failed to request rcu memory"); |
77 | 77 | ||
78 | /* remap rcu register range */ | 78 | /* remap rcu register range */ |
79 | ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start, | 79 | ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start, |
80 | resource_size(<q_rcu_resource)); | 80 | resource_size(<q_rcu_resource)); |
81 | if (!ltq_rcu_membase) | 81 | if (!ltq_rcu_membase) |
82 | panic("Failed to remap rcu memory\n"); | 82 | panic("Failed to remap rcu memory"); |
83 | 83 | ||
84 | _machine_restart = ltq_machine_restart; | 84 | _machine_restart = ltq_machine_restart; |
85 | _machine_halt = ltq_machine_halt; | 85 | _machine_halt = ltq_machine_halt; |
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index daa81f7284a..cf7895db073 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c | |||
@@ -223,7 +223,7 @@ static void __cpuinit probe_octeon(void) | |||
223 | break; | 223 | break; |
224 | 224 | ||
225 | default: | 225 | default: |
226 | panic("Unsupported Cavium Networks CPU type\n"); | 226 | panic("Unsupported Cavium Networks CPU type"); |
227 | break; | 227 | break; |
228 | } | 228 | } |
229 | 229 | ||
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c index 87bb85d8d53..ed1fa460f84 100644 --- a/arch/mips/mm/tlb-r3k.c +++ b/arch/mips/mm/tlb-r3k.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <asm/pgtable.h> | 20 | #include <asm/pgtable.h> |
21 | #include <asm/mmu_context.h> | 21 | #include <asm/mmu_context.h> |
22 | #include <asm/system.h> | 22 | #include <asm/system.h> |
23 | #include <asm/tlbmisc.h> | ||
23 | #include <asm/isadep.h> | 24 | #include <asm/isadep.h> |
24 | #include <asm/io.h> | 25 | #include <asm/io.h> |
25 | #include <asm/bootinfo.h> | 26 | #include <asm/bootinfo.h> |
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 74d67c88574..2dc625346c4 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <asm/mmu_context.h> | 19 | #include <asm/mmu_context.h> |
20 | #include <asm/pgtable.h> | 20 | #include <asm/pgtable.h> |
21 | #include <asm/system.h> | 21 | #include <asm/system.h> |
22 | #include <asm/tlbmisc.h> | ||
22 | 23 | ||
23 | extern void build_tlb_refill_handler(void); | 24 | extern void build_tlb_refill_handler(void); |
24 | 25 | ||
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index 5d530f89d87..d37be36dc65 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c | |||
@@ -162,7 +162,7 @@ msi_irq_allocated: | |||
162 | msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32; | 162 | msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32; |
163 | break; | 163 | break; |
164 | default: | 164 | default: |
165 | panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n"); | 165 | panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type"); |
166 | } | 166 | } |
167 | msg.data = irq - OCTEON_IRQ_MSI_BIT0; | 167 | msg.data = irq - OCTEON_IRQ_MSI_BIT0; |
168 | 168 | ||
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c index b5ce041cdaf..ec125bed721 100644 --- a/arch/mips/pci/pci-alchemy.c +++ b/arch/mips/pci/pci-alchemy.c | |||
@@ -13,9 +13,11 @@ | |||
13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
16 | #include <linux/syscore_ops.h> | ||
16 | #include <linux/vmalloc.h> | 17 | #include <linux/vmalloc.h> |
17 | 18 | ||
18 | #include <asm/mach-au1x00/au1000.h> | 19 | #include <asm/mach-au1x00/au1000.h> |
20 | #include <asm/tlbmisc.h> | ||
19 | 21 | ||
20 | #ifdef CONFIG_DEBUG_PCI | 22 | #ifdef CONFIG_DEBUG_PCI |
21 | #define DBG(x...) printk(KERN_DEBUG x) | 23 | #define DBG(x...) printk(KERN_DEBUG x) |
@@ -41,6 +43,12 @@ struct alchemy_pci_context { | |||
41 | int (*board_pci_idsel)(unsigned int devsel, int assert); | 43 | int (*board_pci_idsel)(unsigned int devsel, int assert); |
42 | }; | 44 | }; |
43 | 45 | ||
46 | /* for syscore_ops. There's only one PCI controller on Alchemy chips, so this | ||
47 | * should suffice for now. | ||
48 | */ | ||
49 | static struct alchemy_pci_context *__alchemy_pci_ctx; | ||
50 | |||
51 | |||
44 | /* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr | 52 | /* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr |
45 | * in arch/mips/alchemy/common/setup.c | 53 | * in arch/mips/alchemy/common/setup.c |
46 | */ | 54 | */ |
@@ -99,18 +107,6 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, | |||
99 | return -1; | 107 | return -1; |
100 | } | 108 | } |
101 | 109 | ||
102 | /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired | ||
103 | * on resume, clearing our wired entry. Unfortunately the ->resume() | ||
104 | * callback is called way way way too late (and ->suspend() too early) | ||
105 | * to have them destroy and recreate it. Instead just test if c0_wired | ||
106 | * is now lower than the index we retrieved before suspending and then | ||
107 | * recreate the entry if necessary. Of course this is totally bonkers | ||
108 | * and breaks as soon as someone else adds another wired entry somewhere | ||
109 | * else. Anyone have any ideas how to handle this better? | ||
110 | */ | ||
111 | if (unlikely(read_c0_wired() < ctx->wired_entry)) | ||
112 | alchemy_pci_wired_entry(ctx); | ||
113 | |||
114 | local_irq_save(flags); | 110 | local_irq_save(flags); |
115 | r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; | 111 | r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; |
116 | r |= PCI_STATCMD_STATUS(0x2000); | 112 | r |= PCI_STATCMD_STATUS(0x2000); |
@@ -304,6 +300,62 @@ static int alchemy_pci_def_idsel(unsigned int devsel, int assert) | |||
304 | return 1; /* success */ | 300 | return 1; /* success */ |
305 | } | 301 | } |
306 | 302 | ||
303 | /* save PCI controller register contents. */ | ||
304 | static int alchemy_pci_suspend(void) | ||
305 | { | ||
306 | struct alchemy_pci_context *ctx = __alchemy_pci_ctx; | ||
307 | if (!ctx) | ||
308 | return 0; | ||
309 | |||
310 | ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); | ||
311 | ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; | ||
312 | ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); | ||
313 | ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); | ||
314 | ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); | ||
315 | ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); | ||
316 | ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); | ||
317 | ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); | ||
318 | ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); | ||
319 | ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); | ||
320 | ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); | ||
321 | ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); | ||
322 | |||
323 | return 0; | ||
324 | } | ||
325 | |||
326 | static void alchemy_pci_resume(void) | ||
327 | { | ||
328 | struct alchemy_pci_context *ctx = __alchemy_pci_ctx; | ||
329 | if (!ctx) | ||
330 | return; | ||
331 | |||
332 | __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); | ||
333 | __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); | ||
334 | __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); | ||
335 | __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); | ||
336 | __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); | ||
337 | __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); | ||
338 | __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); | ||
339 | __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); | ||
340 | __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); | ||
341 | __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); | ||
342 | __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); | ||
343 | wmb(); | ||
344 | __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); | ||
345 | wmb(); | ||
346 | |||
347 | /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired | ||
348 | * on resume, making it necessary to recreate it as soon as possible. | ||
349 | */ | ||
350 | ctx->wired_entry = 8191; /* impossibly high value */ | ||
351 | alchemy_pci_wired_entry(ctx); /* install it */ | ||
352 | } | ||
353 | |||
354 | static struct syscore_ops alchemy_pci_pmops = { | ||
355 | .suspend = alchemy_pci_suspend, | ||
356 | .resume = alchemy_pci_resume, | ||
357 | }; | ||
358 | |||
307 | static int __devinit alchemy_pci_probe(struct platform_device *pdev) | 359 | static int __devinit alchemy_pci_probe(struct platform_device *pdev) |
308 | { | 360 | { |
309 | struct alchemy_pci_platdata *pd = pdev->dev.platform_data; | 361 | struct alchemy_pci_platdata *pd = pdev->dev.platform_data; |
@@ -396,7 +448,8 @@ static int __devinit alchemy_pci_probe(struct platform_device *pdev) | |||
396 | ret = -ENOMEM; | 448 | ret = -ENOMEM; |
397 | goto out4; | 449 | goto out4; |
398 | } | 450 | } |
399 | ctx->wired_entry = 8192; /* impossibly high value */ | 451 | ctx->wired_entry = 8191; /* impossibly high value */ |
452 | alchemy_pci_wired_entry(ctx); /* install it */ | ||
400 | 453 | ||
401 | set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base); | 454 | set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base); |
402 | 455 | ||
@@ -408,7 +461,9 @@ static int __devinit alchemy_pci_probe(struct platform_device *pdev) | |||
408 | __raw_writel(val, ctx->regs + PCI_REG_CONFIG); | 461 | __raw_writel(val, ctx->regs + PCI_REG_CONFIG); |
409 | wmb(); | 462 | wmb(); |
410 | 463 | ||
464 | __alchemy_pci_ctx = ctx; | ||
411 | platform_set_drvdata(pdev, ctx); | 465 | platform_set_drvdata(pdev, ctx); |
466 | register_syscore_ops(&alchemy_pci_pmops); | ||
412 | register_pci_controller(&ctx->alchemy_pci_ctrl); | 467 | register_pci_controller(&ctx->alchemy_pci_ctrl); |
413 | 468 | ||
414 | return 0; | 469 | return 0; |
@@ -425,68 +480,11 @@ out: | |||
425 | return ret; | 480 | return ret; |
426 | } | 481 | } |
427 | 482 | ||
428 | |||
429 | #ifdef CONFIG_PM | ||
430 | /* save PCI controller register contents. */ | ||
431 | static int alchemy_pci_suspend(struct device *dev) | ||
432 | { | ||
433 | struct alchemy_pci_context *ctx = dev_get_drvdata(dev); | ||
434 | |||
435 | ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); | ||
436 | ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; | ||
437 | ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); | ||
438 | ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); | ||
439 | ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); | ||
440 | ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); | ||
441 | ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); | ||
442 | ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); | ||
443 | ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); | ||
444 | ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); | ||
445 | ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); | ||
446 | ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); | ||
447 | |||
448 | return 0; | ||
449 | } | ||
450 | |||
451 | static int alchemy_pci_resume(struct device *dev) | ||
452 | { | ||
453 | struct alchemy_pci_context *ctx = dev_get_drvdata(dev); | ||
454 | |||
455 | __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); | ||
456 | __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); | ||
457 | __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); | ||
458 | __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); | ||
459 | __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); | ||
460 | __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); | ||
461 | __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); | ||
462 | __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); | ||
463 | __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); | ||
464 | __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); | ||
465 | __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); | ||
466 | wmb(); | ||
467 | __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); | ||
468 | wmb(); | ||
469 | |||
470 | return 0; | ||
471 | } | ||
472 | |||
473 | static const struct dev_pm_ops alchemy_pci_pmops = { | ||
474 | .suspend = alchemy_pci_suspend, | ||
475 | .resume = alchemy_pci_resume, | ||
476 | }; | ||
477 | |||
478 | #define ALCHEMY_PCICTL_PM (&alchemy_pci_pmops) | ||
479 | |||
480 | #else | ||
481 | #define ALCHEMY_PCICTL_PM NULL | ||
482 | #endif | ||
483 | |||
484 | static struct platform_driver alchemy_pcictl_driver = { | 483 | static struct platform_driver alchemy_pcictl_driver = { |
485 | .probe = alchemy_pci_probe, | 484 | .probe = alchemy_pci_probe, |
486 | .driver = { | 485 | .driver = { |
487 | .name = "alchemy-pci", | 486 | .name = "alchemy-pci", |
488 | .owner = THIS_MODULE, | 487 | .owner = THIS_MODULE, |
489 | .pm = ALCHEMY_PCICTL_PM, | ||
490 | }, | 488 | }, |
491 | }; | 489 | }; |
492 | 490 | ||
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index 655308a4e1c..7a834b2f8a5 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c | |||
@@ -209,7 +209,7 @@ void __init prom_init(void) | |||
209 | default: | 209 | default: |
210 | /* we don't recognize the machine */ | 210 | /* we don't recognize the machine */ |
211 | mips_machtype = MACH_UNKNOWN; | 211 | mips_machtype = MACH_UNKNOWN; |
212 | panic("***Bogosity factor five***, exiting\n"); | 212 | panic("***Bogosity factor five***, exiting"); |
213 | break; | 213 | break; |
214 | } | 214 | } |
215 | 215 | ||
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 888eac1b831..23642238c68 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c | |||
@@ -73,7 +73,7 @@ static inline int alloc_level(int cpu, int irq) | |||
73 | 73 | ||
74 | level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); | 74 | level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); |
75 | if (level >= LEVELS_PER_SLICE) | 75 | if (level >= LEVELS_PER_SLICE) |
76 | panic("Cpu %d flooded with devices\n", cpu); | 76 | panic("Cpu %d flooded with devices", cpu); |
77 | 77 | ||
78 | __set_bit(level, hub->irq_alloc_mask); | 78 | __set_bit(level, hub->irq_alloc_mask); |
79 | si->level_to_irq[level] = irq; | 79 | si->level_to_irq[level] = irq; |
@@ -96,7 +96,7 @@ static inline int find_level(cpuid_t *cpunum, int irq) | |||
96 | } | 96 | } |
97 | } | 97 | } |
98 | 98 | ||
99 | panic("Could not identify cpu/level for irq %d\n", irq); | 99 | panic("Could not identify cpu/level for irq %d", irq); |
100 | } | 100 | } |
101 | 101 | ||
102 | /* | 102 | /* |