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-rw-r--r--Documentation/arm/SPEAr/overview.txt13
-rw-r--r--Documentation/devicetree/bindings/arm/spear.txt18
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt108
-rw-r--r--Documentation/driver-model/devres.txt4
-rw-r--r--MAINTAINERS23
-rw-r--r--arch/arm/boot/dts/spear300-evb.dts221
-rw-r--r--arch/arm/boot/dts/spear300.dtsi77
-rw-r--r--arch/arm/boot/dts/spear310-evb.dts172
-rw-r--r--arch/arm/boot/dts/spear310.dtsi80
-rw-r--r--arch/arm/boot/dts/spear320-evb.dts173
-rw-r--r--arch/arm/boot/dts/spear320.dtsi95
-rw-r--r--arch/arm/boot/dts/spear3xx.dtsi144
-rw-r--r--arch/arm/boot/dts/spear600-evb.dts4
-rw-r--r--arch/arm/boot/dts/spear600.dtsi8
-rw-r--r--arch/arm/configs/spear3xx_defconfig52
-rw-r--r--arch/arm/configs/spear6xx_defconfig41
-rw-r--r--arch/arm/mach-spear3xx/Kconfig37
-rw-r--r--arch/arm/mach-spear3xx/Makefile13
-rw-r--r--arch/arm/mach-spear3xx/Makefile.boot4
-rw-r--r--arch/arm/mach-spear3xx/clock.c182
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h153
-rw-r--r--arch/arm/mach-spear3xx/include/mach/hardware.h3
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h9
-rw-r--r--arch/arm/mach-spear3xx/spear300.c613
-rw-r--r--arch/arm/mach-spear3xx/spear300_evb.c75
-rw-r--r--arch/arm/mach-spear3xx/spear310.c416
-rw-r--r--arch/arm/mach-spear3xx/spear310_evb.c81
-rw-r--r--arch/arm/mach-spear3xx/spear320.c663
-rw-r--r--arch/arm/mach-spear3xx/spear320_evb.c79
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c541
-rw-r--r--arch/arm/mach-spear6xx/Makefile.boot2
-rw-r--r--arch/arm/mach-spear6xx/clock.c80
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c372
-rw-r--r--arch/arm/plat-spear/Kconfig4
-rw-r--r--arch/arm/plat-spear/Makefile4
-rw-r--r--arch/arm/plat-spear/include/plat/padmux.h92
-rw-r--r--arch/arm/plat-spear/include/plat/pl080.h21
-rw-r--r--arch/arm/plat-spear/padmux.c164
-rw-r--r--arch/arm/plat-spear/pl080.c79
-rw-r--r--drivers/clk/clkdev.c142
-rw-r--r--drivers/pinctrl/Kconfig2
-rw-r--r--drivers/pinctrl/Makefile2
-rw-r--r--drivers/pinctrl/spear/Kconfig34
-rw-r--r--drivers/pinctrl/spear/Makefile7
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.c354
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.h142
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear300.c708
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear310.c431
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear320.c3468
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear3xx.c588
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear3xx.h92
-rw-r--r--include/linux/clk.h32
-rw-r--r--include/linux/clkdev.h3
53 files changed, 8678 insertions, 2247 deletions
diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 253a35c6f78..28a9af953b9 100644
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -17,14 +17,14 @@ Introduction
17 SPEAr (Platform) 17 SPEAr (Platform)
18 - SPEAr3XX (3XX SOC series, based on ARM9) 18 - SPEAr3XX (3XX SOC series, based on ARM9)
19 - SPEAr300 (SOC) 19 - SPEAr300 (SOC)
20 - SPEAr300_EVB (Evaluation Board) 20 - SPEAr300 Evaluation Board
21 - SPEAr310 (SOC) 21 - SPEAr310 (SOC)
22 - SPEAr310_EVB (Evaluation Board) 22 - SPEAr310 Evaluation Board
23 - SPEAr320 (SOC) 23 - SPEAr320 (SOC)
24 - SPEAr320_EVB (Evaluation Board) 24 - SPEAr320 Evaluation Board
25 - SPEAr6XX (6XX SOC series, based on ARM9) 25 - SPEAr6XX (6XX SOC series, based on ARM9)
26 - SPEAr600 (SOC) 26 - SPEAr600 (SOC)
27 - SPEAr600_EVB (Evaluation Board) 27 - SPEAr600 Evaluation Board
28 - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9) 28 - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
29 - SPEAr1300 (SOC) 29 - SPEAr1300 (SOC)
30 30
@@ -51,10 +51,11 @@ Introduction
51 Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for 51 Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
52 spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine 52 spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
53 specific files, like spear300.c, spear310.c, spear320.c and spear600.c. 53 specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
54 mach-spear* also contains board specific files for each machine type. 54 mach-spear* doesn't contains board specific files as they fully support
55 Flattened Device Tree.
55 56
56 57
57 Document Author 58 Document Author
58 --------------- 59 ---------------
59 60
60 Viresh Kumar, (c) 2010 ST Microelectronics 61 Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics
diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
index f8e54f09232..aa5f355cc94 100644
--- a/Documentation/devicetree/bindings/arm/spear.txt
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -6,3 +6,21 @@ Boards with the ST SPEAr600 SoC shall have the following properties:
6Required root node property: 6Required root node property:
7 7
8compatible = "st,spear600"; 8compatible = "st,spear600";
9
10Boards with the ST SPEAr300 SoC shall have the following properties:
11
12Required root node property:
13
14compatible = "st,spear300";
15
16Boards with the ST SPEAr310 SoC shall have the following properties:
17
18Required root node property:
19
20compatible = "st,spear310";
21
22Boards with the ST SPEAr320 SoC shall have the following properties:
23
24Required root node property:
25
26compatible = "st,spear320";
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
new file mode 100644
index 00000000000..3664d37e679
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
@@ -0,0 +1,108 @@
1ST Microelectronics, SPEAr pinmux controller
2
3Required properties:
4- compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7- reg : Address range of the pinctrl registers
8- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
9 - Its values for SPEAr300:
10 - NAND_MODE : <0>
11 - NOR_MODE : <1>
12 - PHOTO_FRAME_MODE : <2>
13 - LEND_IP_PHONE_MODE : <3>
14 - HEND_IP_PHONE_MODE : <4>
15 - LEND_WIFI_PHONE_MODE : <5>
16 - HEND_WIFI_PHONE_MODE : <6>
17 - ATA_PABX_WI2S_MODE : <7>
18 - ATA_PABX_I2S_MODE : <8>
19 - CAML_LCDW_MODE : <9>
20 - CAMU_LCD_MODE : <10>
21 - CAMU_WLCD_MODE : <11>
22 - CAML_LCD_MODE : <12>
23 - Its values for SPEAr320:
24 - AUTO_NET_SMII_MODE : <0>
25 - AUTO_NET_MII_MODE : <1>
26 - AUTO_EXP_MODE : <2>
27 - SMALL_PRINTERS_MODE : <3>
28 - EXTENDED_MODE : <4>
29
30Please refer to pinctrl-bindings.txt in this directory for details of the common
31pinctrl bindings used by client devices.
32
33SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
34of these subnodes represents muxing for a pin, a group, or a list of pins or
35groups.
36
37The name of each subnode is not important; all subnodes should be enumerated
38and processed purely based on their content.
39
40Required subnode-properties:
41- st,pins : An array of strings. Each string contains the name of a pin or
42 group.
43- st,function: A string containing the name of the function to mux to the pin or
44 group. See the SPEAr's TRM to determine which are valid for each pin or group.
45
46 Valid values for group and function names can be found from looking at the
47 group and function arrays in driver files:
48 drivers/pinctrl/spear/pinctrl-spear3*0.c
49
50Valid values for group names are:
51For All SPEAr3xx machines:
52 "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
53 "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
54 "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
55 "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
56
57For SPEAr300 machines:
58 "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
59 "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
60 "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
61 "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
62
63For SPEAr310 machines:
64 "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
65 "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
66
67For SPEAr320 machines:
68 "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
69 "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
70 "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
71 "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
72 "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
73 "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
74 "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
75 "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
76 "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
77 "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
78 "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
79 "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
80 "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
81 "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
82 "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
83 "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
84 "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
85 "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
86 "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
87 "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
88 "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
89 "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
90 "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
91
92Valid values for function names are:
93For All SPEAr3xx machines:
94 "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
95 "uart0", "timer_0_1", "timer_2_3"
96
97For SPEAr300 machines:
98 "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
99
100For SPEAr310 machines:
101 "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
102 "rs485_1", "tdm"
103
104For SPEAr320 machines:
105 "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
106 "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
107 "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
108 "mii0_1", "i2c1", "i2c2"
diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt
index ef4fa7b423d..950856bd2e3 100644
--- a/Documentation/driver-model/devres.txt
+++ b/Documentation/driver-model/devres.txt
@@ -277,6 +277,10 @@ REGULATOR
277 devm_regulator_put() 277 devm_regulator_put()
278 devm_regulator_bulk_get() 278 devm_regulator_bulk_get()
279 279
280CLOCK
281 devm_clk_get()
282 devm_clk_put()
283
280PINCTRL 284PINCTRL
281 devm_pinctrl_get() 285 devm_pinctrl_get()
282 devm_pinctrl_put() 286 devm_pinctrl_put()
diff --git a/MAINTAINERS b/MAINTAINERS
index b0f1073c40b..cf900fcd074 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5234,6 +5234,14 @@ M: Linus Walleij <linus.walleij@linaro.org>
5234S: Maintained 5234S: Maintained
5235F: drivers/pinctrl/ 5235F: drivers/pinctrl/
5236 5236
5237PIN CONTROLLER - ST SPEAR
5238M: Viresh Kumar <viresh.kumar@st.com>
5239L: spear-devel@list.st.com
5240L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
5241W: http://www.st.com/spear
5242S: Maintained
5243F: driver/pinctrl/spear/
5244
5237PKTCDVD DRIVER 5245PKTCDVD DRIVER
5238M: Peter Osterlund <petero2@telia.com> 5246M: Peter Osterlund <petero2@telia.com>
5239S: Maintained 5247S: Maintained
@@ -6330,21 +6338,6 @@ F: arch/arm/mach-spear*/clock.c
6330F: arch/arm/plat-spear/clock.c 6338F: arch/arm/plat-spear/clock.c
6331F: arch/arm/plat-spear/include/plat/clock.h 6339F: arch/arm/plat-spear/include/plat/clock.h
6332 6340
6333SPEAR PAD MULTIPLEXING SUPPORT
6334M: Viresh Kumar <viresh.kumar@st.com>
6335L: spear-devel@list.st.com
6336L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
6337W: http://www.st.com/spear
6338S: Maintained
6339F: arch/arm/plat-spear/include/plat/padmux.h
6340F: arch/arm/plat-spear/padmux.c
6341F: arch/arm/mach-spear*/spear*xx.c
6342F: arch/arm/mach-spear*/include/mach/generic.h
6343F: arch/arm/mach-spear3xx/spear3*0.c
6344F: arch/arm/mach-spear3xx/spear3*0_evb.c
6345F: arch/arm/mach-spear6xx/spear600.c
6346F: arch/arm/mach-spear6xx/spear600_evb.c
6347
6348SPI SUBSYSTEM 6341SPI SUBSYSTEM
6349M: Grant Likely <grant.likely@secretlab.ca> 6342M: Grant Likely <grant.likely@secretlab.ca>
6350L: spi-devel-general@lists.sourceforge.net 6343L: spi-devel-general@lists.sourceforge.net
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
new file mode 100644
index 00000000000..402ca0d5501
--- /dev/null
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -0,0 +1,221 @@
1/*
2 * DTS file for SPEAr300 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear300.dtsi"
16
17/ {
18 model = "ST SPEAr300 Evaluation Board";
19 compatible = "st,spear300-evb", "st,spear300";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@99000000 {
29 st,pinmux-mode = <2>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 ssp0 {
39 st,pins = "ssp0_grp";
40 st,function = "ssp0";
41 };
42 mii0 {
43 st,pins = "mii0_grp";
44 st,function = "mii0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 clcd {
51 st,pins = "clcd_pfmode_grp";
52 st,function = "clcd";
53 };
54 sdhci {
55 st,pins = "sdhci_4bit_grp";
56 st,function = "sdhci";
57 };
58 gpio1 {
59 st,pins = "gpio1_4_to_7_grp",
60 "gpio1_0_to_3_grp";
61 st,function = "gpio1";
62 };
63 };
64 };
65
66 clcd@60000000 {
67 status = "okay";
68 };
69
70 dma@fc400000 {
71 status = "okay";
72 };
73
74 fsmc: flash@94000000 {
75 status = "okay";
76 };
77
78 gmac: eth@e0800000 {
79 status = "okay";
80 };
81
82 sdhci@70000000 {
83 int-gpio = <&gpio1 0 0>;
84 power-gpio = <&gpio1 2 1>;
85 status = "okay";
86 };
87
88 smi: flash@fc000000 {
89 status = "okay";
90 };
91
92 spi0: spi@d0100000 {
93 status = "okay";
94 };
95
96 ehci@e1800000 {
97 status = "okay";
98 };
99
100 ohci@e1900000 {
101 status = "okay";
102 };
103
104 ohci@e2100000 {
105 status = "okay";
106 };
107
108 apb {
109 gpio0: gpio@fc980000 {
110 status = "okay";
111 };
112
113 gpio1: gpio@a9000000 {
114 status = "okay";
115 };
116
117 i2c0: i2c@d0180000 {
118 status = "okay";
119 };
120
121 kbd@a0000000 {
122 linux,keymap = < 0x00010000
123 0x00020100
124 0x00030200
125 0x00040300
126 0x00050400
127 0x00060500
128 0x00070600
129 0x00080700
130 0x00090800
131 0x000a0001
132 0x000c0101
133 0x000d0201
134 0x000e0301
135 0x000f0401
136 0x00100501
137 0x00110601
138 0x00120701
139 0x00130801
140 0x00140002
141 0x00150102
142 0x00160202
143 0x00170302
144 0x00180402
145 0x00190502
146 0x001a0602
147 0x001b0702
148 0x001c0802
149 0x001d0003
150 0x001e0103
151 0x001f0203
152 0x00200303
153 0x00210403
154 0x00220503
155 0x00230603
156 0x00240703
157 0x00250803
158 0x00260004
159 0x00270104
160 0x00280204
161 0x00290304
162 0x002a0404
163 0x002b0504
164 0x002c0604
165 0x002d0704
166 0x002e0804
167 0x002f0005
168 0x00300105
169 0x00310205
170 0x00320305
171 0x00330405
172 0x00340505
173 0x00350605
174 0x00360705
175 0x00370805
176 0x00380006
177 0x00390106
178 0x003a0206
179 0x003b0306
180 0x003c0406
181 0x003d0506
182 0x003e0606
183 0x003f0706
184 0x00400806
185 0x00410007
186 0x00420107
187 0x00430207
188 0x00440307
189 0x00450407
190 0x00460507
191 0x00470607
192 0x00480707
193 0x00490807
194 0x004a0008
195 0x004b0108
196 0x004c0208
197 0x004d0308
198 0x004e0408
199 0x004f0508
200 0x00500608
201 0x00510708
202 0x00520808 >;
203 autorepeat;
204 st,mode = <0>;
205 status = "okay";
206 };
207
208 rtc@fc900000 {
209 status = "okay";
210 };
211
212 serial@d0000000 {
213 status = "okay";
214 };
215
216 wdt@fc880000 {
217 status = "okay";
218 };
219 };
220 };
221};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
new file mode 100644
index 00000000000..01c5e358fdb
--- /dev/null
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -0,0 +1,77 @@
1/*
2 * DTS file for SPEAr300 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x60000000 0x60000000 0x50000000
22 0xd0000000 0xd0000000 0x30000000>;
23
24 pinmux@99000000 {
25 compatible = "st,spear300-pinmux";
26 reg = <0x99000000 0x1000>;
27 };
28
29 clcd@60000000 {
30 compatible = "arm,clcd-pl110", "arm,primecell";
31 reg = <0x60000000 0x1000>;
32 interrupts = <30>;
33 status = "disabled";
34 };
35
36 fsmc: flash@94000000 {
37 compatible = "st,spear600-fsmc-nand";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x94000000 0x1000 /* FSMC Register */
41 0x80000000 0x0010>; /* NAND Base */
42 reg-names = "fsmc_regs", "nand_data";
43 st,ale-off = <0x20000>;
44 st,cle-off = <0x10000>;
45 status = "disabled";
46 };
47
48 sdhci@70000000 {
49 compatible = "st,sdhci-spear";
50 reg = <0x70000000 0x100>;
51 interrupts = <1>;
52 status = "disabled";
53 };
54
55 apb {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 compatible = "simple-bus";
59 ranges = <0xa0000000 0xa0000000 0x10000000
60 0xd0000000 0xd0000000 0x30000000>;
61
62 gpio1: gpio@a9000000 {
63 #gpio-cells = <2>;
64 compatible = "arm,pl061", "arm,primecell";
65 gpio-controller;
66 reg = <0xa9000000 0x1000>;
67 status = "disabled";
68 };
69
70 kbd@a0000000 {
71 compatible = "st,spear300-kbd";
72 reg = <0xa0000000 0x1000>;
73 status = "disabled";
74 };
75 };
76 };
77};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
new file mode 100644
index 00000000000..6d95317100a
--- /dev/null
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -0,0 +1,172 @@
1/*
2 * DTS file for SPEAr310 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear310.dtsi"
16
17/ {
18 model = "ST SPEAr310 Evaluation Board";
19 compatible = "st,spear310-evb", "st,spear310";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@b4000000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 gpio0 {
34 st,pins = "gpio0_pin0_grp",
35 "gpio0_pin1_grp",
36 "gpio0_pin2_grp",
37 "gpio0_pin3_grp",
38 "gpio0_pin4_grp",
39 "gpio0_pin5_grp";
40 st,function = "gpio0";
41 };
42 i2c0 {
43 st,pins = "i2c0_grp";
44 st,function = "i2c0";
45 };
46 mii0 {
47 st,pins = "mii0_grp";
48 st,function = "mii0";
49 };
50 ssp0 {
51 st,pins = "ssp0_grp";
52 st,function = "ssp0";
53 };
54 uart0 {
55 st,pins = "uart0_grp";
56 st,function = "uart0";
57 };
58 emi {
59 st,pins = "emi_cs_0_to_5_grp";
60 st,function = "emi";
61 };
62 fsmc {
63 st,pins = "fsmc_grp";
64 st,function = "fsmc";
65 };
66 uart1 {
67 st,pins = "uart1_grp";
68 st,function = "uart1";
69 };
70 uart2 {
71 st,pins = "uart2_grp";
72 st,function = "uart2";
73 };
74 uart3 {
75 st,pins = "uart3_grp";
76 st,function = "uart3";
77 };
78 uart4 {
79 st,pins = "uart4_grp";
80 st,function = "uart4";
81 };
82 uart5 {
83 st,pins = "uart5_grp";
84 st,function = "uart5";
85 };
86 };
87 };
88
89 dma@fc400000 {
90 status = "okay";
91 };
92
93 fsmc: flash@44000000 {
94 status = "okay";
95 };
96
97 gmac: eth@e0800000 {
98 status = "okay";
99 };
100
101 smi: flash@fc000000 {
102 status = "okay";
103 clock-rate=<50000000>;
104
105 flash@f8000000 {
106 label = "m25p64";
107 reg = <0xf8000000 0x800000>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 st,smi-fast-mode;
111 };
112 };
113
114 spi0: spi@d0100000 {
115 status = "okay";
116 };
117
118 ehci@e1800000 {
119 status = "okay";
120 };
121
122 ohci@e1900000 {
123 status = "okay";
124 };
125
126 ohci@e2100000 {
127 status = "okay";
128 };
129
130 apb {
131 gpio0: gpio@fc980000 {
132 status = "okay";
133 };
134
135 i2c0: i2c@d0180000 {
136 status = "okay";
137 };
138
139 rtc@fc900000 {
140 status = "okay";
141 };
142
143 serial@d0000000 {
144 status = "okay";
145 };
146
147 serial@b2000000 {
148 status = "okay";
149 };
150
151 serial@b2080000 {
152 status = "okay";
153 };
154
155 serial@b2100000 {
156 status = "okay";
157 };
158
159 serial@b2180000 {
160 status = "okay";
161 };
162
163 serial@b2200000 {
164 status = "okay";
165 };
166
167 wdt@fc880000 {
168 status = "okay";
169 };
170 };
171 };
172};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
new file mode 100644
index 00000000000..e47081c494d
--- /dev/null
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -0,0 +1,80 @@
1/*
2 * DTS file for SPEAr310 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x40000000 0x40000000 0x10000000
22 0xb0000000 0xb0000000 0x10000000
23 0xd0000000 0xd0000000 0x30000000>;
24
25 pinmux@b4000000 {
26 compatible = "st,spear310-pinmux";
27 reg = <0xb4000000 0x1000>;
28 };
29
30 fsmc: flash@44000000 {
31 compatible = "st,spear600-fsmc-nand";
32 #address-cells = <1>;
33 #size-cells = <1>;
34 reg = <0x44000000 0x1000 /* FSMC Register */
35 0x40000000 0x0010>; /* NAND Base */
36 reg-names = "fsmc_regs", "nand_data";
37 st,ale-off = <0x10000>;
38 st,cle-off = <0x20000>;
39 status = "disabled";
40 };
41
42 apb {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 compatible = "simple-bus";
46 ranges = <0xb0000000 0xb0000000 0x10000000
47 0xd0000000 0xd0000000 0x30000000>;
48
49 serial@b2000000 {
50 compatible = "arm,pl011", "arm,primecell";
51 reg = <0xb2000000 0x1000>;
52 status = "disabled";
53 };
54
55 serial@b2080000 {
56 compatible = "arm,pl011", "arm,primecell";
57 reg = <0xb2080000 0x1000>;
58 status = "disabled";
59 };
60
61 serial@b2100000 {
62 compatible = "arm,pl011", "arm,primecell";
63 reg = <0xb2100000 0x1000>;
64 status = "disabled";
65 };
66
67 serial@b2180000 {
68 compatible = "arm,pl011", "arm,primecell";
69 reg = <0xb2180000 0x1000>;
70 status = "disabled";
71 };
72
73 serial@b2200000 {
74 compatible = "arm,pl011", "arm,primecell";
75 reg = <0xb2200000 0x1000>;
76 status = "disabled";
77 };
78 };
79 };
80};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
new file mode 100644
index 00000000000..0c6463b71a3
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -0,0 +1,173 @@
1/*
2 * DTS file for SPEAr320 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear320.dtsi"
16
17/ {
18 model = "ST SPEAr300 Evaluation Board";
19 compatible = "st,spear300-evb", "st,spear300";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@b3000000 {
29 st,pinmux-mode = <3>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 mii0 {
39 st,pins = "mii0_grp";
40 st,function = "mii0";
41 };
42 ssp0 {
43 st,pins = "ssp0_grp";
44 st,function = "ssp0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 sdhci {
51 st,pins = "sdhci_cd_51_grp";
52 st,function = "sdhci";
53 };
54 i2s {
55 st,pins = "i2s_grp";
56 st,function = "i2s";
57 };
58 uart1 {
59 st,pins = "uart1_grp";
60 st,function = "uart1";
61 };
62 uart2 {
63 st,pins = "uart2_grp";
64 st,function = "uart2";
65 };
66 can0 {
67 st,pins = "can0_grp";
68 st,function = "can0";
69 };
70 can1 {
71 st,pins = "can1_grp";
72 st,function = "can1";
73 };
74 mii2 {
75 st,pins = "mii2_grp";
76 st,function = "mii2";
77 };
78 pwm0_1 {
79 st,pins = "pwm0_1_pin_14_15_grp";
80 st,function = "pwm0_1";
81 };
82 pwm2 {
83 st,pins = "pwm2_pin_13_grp";
84 st,function = "pwm2";
85 };
86 };
87 };
88
89 clcd@90000000 {
90 status = "okay";
91 };
92
93 dma@fc400000 {
94 status = "okay";
95 };
96
97 fsmc: flash@4c000000 {
98 status = "okay";
99 };
100
101 gmac: eth@e0800000 {
102 status = "okay";
103 };
104
105 sdhci@70000000 {
106 power-gpio = <&gpio0 2 1>;
107 power_always_enb;
108 status = "okay";
109 };
110
111 smi: flash@fc000000 {
112 status = "okay";
113 };
114
115 spi0: spi@d0100000 {
116 status = "okay";
117 };
118
119 spi1: spi@a5000000 {
120 status = "okay";
121 };
122
123 spi2: spi@a6000000 {
124 status = "okay";
125 };
126
127 ehci@e1800000 {
128 status = "okay";
129 };
130
131 ohci@e1900000 {
132 status = "okay";
133 };
134
135 ohci@e2100000 {
136 status = "okay";
137 };
138
139 apb {
140 gpio0: gpio@fc980000 {
141 status = "okay";
142 };
143
144 i2c0: i2c@d0180000 {
145 status = "okay";
146 };
147
148 i2c1: i2c@a7000000 {
149 status = "okay";
150 };
151
152 rtc@fc900000 {
153 status = "okay";
154 };
155
156 serial@d0000000 {
157 status = "okay";
158 };
159
160 serial@a3000000 {
161 status = "okay";
162 };
163
164 serial@a4000000 {
165 status = "okay";
166 };
167
168 wdt@fc880000 {
169 status = "okay";
170 };
171 };
172 };
173};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
new file mode 100644
index 00000000000..5372ca399b1
--- /dev/null
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -0,0 +1,95 @@
1/*
2 * DTS file for SPEAr320 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x40000000 0x40000000 0x80000000
22 0xd0000000 0xd0000000 0x30000000>;
23
24 pinmux@b3000000 {
25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>;
27 };
28
29 clcd@90000000 {
30 compatible = "arm,clcd-pl110", "arm,primecell";
31 reg = <0x90000000 0x1000>;
32 interrupts = <33>;
33 status = "disabled";
34 };
35
36 fsmc: flash@4c000000 {
37 compatible = "st,spear600-fsmc-nand";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x4c000000 0x1000 /* FSMC Register */
41 0x50000000 0x0010>; /* NAND Base */
42 reg-names = "fsmc_regs", "nand_data";
43 st,ale-off = <0x20000>;
44 st,cle-off = <0x10000>;
45 status = "disabled";
46 };
47
48 sdhci@70000000 {
49 compatible = "st,sdhci-spear";
50 reg = <0x70000000 0x100>;
51 interrupts = <29>;
52 status = "disabled";
53 };
54
55 spi1: spi@a5000000 {
56 compatible = "arm,pl022", "arm,primecell";
57 reg = <0xa5000000 0x1000>;
58 status = "disabled";
59 };
60
61 spi2: spi@a6000000 {
62 compatible = "arm,pl022", "arm,primecell";
63 reg = <0xa6000000 0x1000>;
64 status = "disabled";
65 };
66
67 apb {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 ranges = <0xa0000000 0xa0000000 0x10000000
72 0xd0000000 0xd0000000 0x30000000>;
73
74 i2c1: i2c@a7000000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 compatible = "snps,designware-i2c";
78 reg = <0xa7000000 0x1000>;
79 status = "disabled";
80 };
81
82 serial@a3000000 {
83 compatible = "arm,pl011", "arm,primecell";
84 reg = <0xa3000000 0x1000>;
85 status = "disabled";
86 };
87
88 serial@a4000000 {
89 compatible = "arm,pl011", "arm,primecell";
90 reg = <0xa4000000 0x1000>;
91 status = "disabled";
92 };
93 };
94 };
95};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
new file mode 100644
index 00000000000..0ae7c8e8631
--- /dev/null
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -0,0 +1,144 @@
1/*
2 * DTS file for all SPEAr3xx SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&vic>;
18
19 cpus {
20 cpu@0 {
21 compatible = "arm,arm926ejs";
22 };
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0 0x40000000>;
28 };
29
30 ahb {
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "simple-bus";
34 ranges = <0xd0000000 0xd0000000 0x30000000>;
35
36 vic: interrupt-controller@f1100000 {
37 compatible = "arm,pl190-vic";
38 interrupt-controller;
39 reg = <0xf1100000 0x1000>;
40 #interrupt-cells = <1>;
41 };
42
43 dma@fc400000 {
44 compatible = "arm,pl080", "arm,primecell";
45 reg = <0xfc400000 0x1000>;
46 interrupt-parent = <&vic>;
47 interrupts = <8>;
48 status = "disabled";
49 };
50
51 gmac: eth@e0800000 {
52 compatible = "st,spear600-gmac";
53 reg = <0xe0800000 0x8000>;
54 interrupts = <23 22>;
55 interrupt-names = "macirq", "eth_wake_irq";
56 status = "disabled";
57 };
58
59 smi: flash@fc000000 {
60 compatible = "st,spear600-smi";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 reg = <0xfc000000 0x1000>;
64 interrupts = <9>;
65 status = "disabled";
66 };
67
68 spi0: spi@d0100000 {
69 compatible = "arm,pl022", "arm,primecell";
70 reg = <0xd0100000 0x1000>;
71 interrupts = <20>;
72 status = "disabled";
73 };
74
75 ehci@e1800000 {
76 compatible = "st,spear600-ehci", "usb-ehci";
77 reg = <0xe1800000 0x1000>;
78 interrupts = <26>;
79 status = "disabled";
80 };
81
82 ohci@e1900000 {
83 compatible = "st,spear600-ohci", "usb-ohci";
84 reg = <0xe1900000 0x1000>;
85 interrupts = <25>;
86 status = "disabled";
87 };
88
89 ohci@e2100000 {
90 compatible = "st,spear600-ohci", "usb-ohci";
91 reg = <0xe2100000 0x1000>;
92 interrupts = <27>;
93 status = "disabled";
94 };
95
96 apb {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "simple-bus";
100 ranges = <0xd0000000 0xd0000000 0x30000000>;
101
102 gpio0: gpio@fc980000 {
103 compatible = "arm,pl061", "arm,primecell";
104 reg = <0xfc980000 0x1000>;
105 interrupts = <11>;
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
110 status = "disabled";
111 };
112
113 i2c0: i2c@d0180000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "snps,designware-i2c";
117 reg = <0xd0180000 0x1000>;
118 interrupts = <21>;
119 status = "disabled";
120 };
121
122 rtc@fc900000 {
123 compatible = "st,spear-rtc";
124 reg = <0xfc900000 0x1000>;
125 interrupts = <10>;
126 status = "disabled";
127 };
128
129 serial@d0000000 {
130 compatible = "arm,pl011", "arm,primecell";
131 reg = <0xd0000000 0x1000>;
132 interrupts = <19>;
133 status = "disabled";
134 };
135
136 wdt@fc880000 {
137 compatible = "arm,sp805", "arm,primecell";
138 reg = <0xfc880000 0x1000>;
139 interrupts = <12>;
140 status = "disabled";
141 };
142 };
143 };
144};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 636292e18c9..790a7a8a5cc 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,6 +24,10 @@
24 }; 24 };
25 25
26 ahb { 26 ahb {
27 dma@fc400000 {
28 status = "okay";
29 };
30
27 gmac: ethernet@e0800000 { 31 gmac: ethernet@e0800000 {
28 phy-mode = "gmii"; 32 phy-mode = "gmii";
29 status = "okay"; 33 status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index ebe0885a2b9..d777e3a6f17 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
45 #interrupt-cells = <1>; 45 #interrupt-cells = <1>;
46 }; 46 };
47 47
48 dma@fc400000 {
49 compatible = "arm,pl080", "arm,primecell";
50 reg = <0xfc400000 0x1000>;
51 interrupt-parent = <&vic1>;
52 interrupts = <10>;
53 status = "disabled";
54 };
55
48 gmac: ethernet@e0800000 { 56 gmac: ethernet@e0800000 {
49 compatible = "st,spear600-gmac"; 57 compatible = "st,spear600-gmac";
50 reg = <0xe0800000 0x8000>; 58 reg = <0xe0800000 0x8000>;
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f026a..7ed42912d69 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -2,33 +2,67 @@ CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y 3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_BLK_DEV_INITRD=y 4CONFIG_BLK_DEV_INITRD=y
5CONFIG_KALLSYMS_EXTRA_PASS=y
6CONFIG_MODULES=y 5CONFIG_MODULES=y
7CONFIG_MODULE_UNLOAD=y 6CONFIG_MODULE_UNLOAD=y
8CONFIG_MODVERSIONS=y 7CONFIG_MODVERSIONS=y
8CONFIG_PARTITION_ADVANCED=y
9CONFIG_PLAT_SPEAR=y 9CONFIG_PLAT_SPEAR=y
10CONFIG_BOARD_SPEAR300_EVB=y 10CONFIG_MACH_SPEAR300=y
11CONFIG_BOARD_SPEAR310_EVB=y 11CONFIG_MACH_SPEAR310=y
12CONFIG_BOARD_SPEAR320_EVB=y 12CONFIG_MACH_SPEAR320=y
13CONFIG_BINFMT_MISC=y 13CONFIG_BINFMT_MISC=y
14CONFIG_NET=y
14CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 15CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
16CONFIG_MTD=y
17CONFIG_MTD_NAND=y
18CONFIG_MTD_NAND_FSMC=y
15CONFIG_BLK_DEV_RAM=y 19CONFIG_BLK_DEV_RAM=y
16CONFIG_BLK_DEV_RAM_SIZE=16384 20CONFIG_BLK_DEV_RAM_SIZE=16384
21CONFIG_NETDEVICES=y
22# CONFIG_NET_VENDOR_BROADCOM is not set
23# CONFIG_NET_VENDOR_CIRRUS is not set
24# CONFIG_NET_VENDOR_FARADAY is not set
25# CONFIG_NET_VENDOR_INTEL is not set
26# CONFIG_NET_VENDOR_MICREL is not set
27# CONFIG_NET_VENDOR_NATSEMI is not set
28# CONFIG_NET_VENDOR_SEEQ is not set
29# CONFIG_NET_VENDOR_SMSC is not set
30CONFIG_STMMAC_ETH=y
31# CONFIG_WLAN is not set
17CONFIG_INPUT_FF_MEMLESS=y 32CONFIG_INPUT_FF_MEMLESS=y
18# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 33# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
19# CONFIG_INPUT_KEYBOARD is not set 34# CONFIG_KEYBOARD_ATKBD is not set
35CONFIG_KEYBOARD_SPEAR=y
20# CONFIG_INPUT_MOUSE is not set 36# CONFIG_INPUT_MOUSE is not set
37# CONFIG_LEGACY_PTYS is not set
21CONFIG_SERIAL_AMBA_PL011=y 38CONFIG_SERIAL_AMBA_PL011=y
22CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 39CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
23# CONFIG_LEGACY_PTYS is not set
24# CONFIG_HW_RANDOM is not set 40# CONFIG_HW_RANDOM is not set
25CONFIG_RAW_DRIVER=y 41CONFIG_RAW_DRIVER=y
26CONFIG_MAX_RAW_DEVS=8192 42CONFIG_MAX_RAW_DEVS=8192
43CONFIG_I2C=y
44CONFIG_I2C_DESIGNWARE_PLATFORM=y
45CONFIG_SPI=y
46CONFIG_SPI_PL022=y
27CONFIG_GPIO_SYSFS=y 47CONFIG_GPIO_SYSFS=y
28CONFIG_GPIO_PL061=y 48CONFIG_GPIO_PL061=y
29# CONFIG_HWMON is not set 49# CONFIG_HWMON is not set
50CONFIG_WATCHDOG=y
51CONFIG_ARM_SP805_WATCHDOG=y
52CONFIG_FB=y
53CONFIG_FB_ARMCLCD=y
30# CONFIG_HID_SUPPORT is not set 54# CONFIG_HID_SUPPORT is not set
31# CONFIG_USB_SUPPORT is not set 55CONFIG_USB=y
56# CONFIG_USB_DEVICE_CLASS is not set
57CONFIG_USB_EHCI_HCD=y
58CONFIG_USB_OHCI_HCD=y
59CONFIG_MMC=y
60CONFIG_MMC_SDHCI=y
61CONFIG_MMC_SDHCI_SPEAR=y
62CONFIG_RTC_CLASS=y
63CONFIG_DMADEVICES=y
64CONFIG_AMBA_PL08X=y
65CONFIG_DMATEST=m
32CONFIG_EXT2_FS=y 66CONFIG_EXT2_FS=y
33CONFIG_EXT2_FS_XATTR=y 67CONFIG_EXT2_FS_XATTR=y
34CONFIG_EXT2_FS_SECURITY=y 68CONFIG_EXT2_FS_SECURITY=y
@@ -39,8 +73,6 @@ CONFIG_MSDOS_FS=m
39CONFIG_VFAT_FS=m 73CONFIG_VFAT_FS=m
40CONFIG_FAT_DEFAULT_IOCHARSET="ascii" 74CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
41CONFIG_TMPFS=y 75CONFIG_TMPFS=y
42CONFIG_PARTITION_ADVANCED=y
43CONFIG_NLS=y
44CONFIG_NLS_DEFAULT="utf8" 76CONFIG_NLS_DEFAULT="utf8"
45CONFIG_NLS_CODEPAGE_437=y 77CONFIG_NLS_CODEPAGE_437=y
46CONFIG_NLS_ASCII=m 78CONFIG_NLS_ASCII=m
@@ -48,6 +80,4 @@ CONFIG_MAGIC_SYSRQ=y
48CONFIG_DEBUG_FS=y 80CONFIG_DEBUG_FS=y
49CONFIG_DEBUG_KERNEL=y 81CONFIG_DEBUG_KERNEL=y
50CONFIG_DEBUG_SPINLOCK=y 82CONFIG_DEBUG_SPINLOCK=y
51CONFIG_DEBUG_SPINLOCK_SLEEP=y
52CONFIG_DEBUG_INFO=y 83CONFIG_DEBUG_INFO=y
53# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e836afd..cf94bc73a0e 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -2,29 +2,58 @@ CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y 3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_BLK_DEV_INITRD=y 4CONFIG_BLK_DEV_INITRD=y
5CONFIG_KALLSYMS_EXTRA_PASS=y
6CONFIG_MODULES=y 5CONFIG_MODULES=y
7CONFIG_MODULE_UNLOAD=y 6CONFIG_MODULE_UNLOAD=y
8CONFIG_MODVERSIONS=y 7CONFIG_MODVERSIONS=y
8CONFIG_PARTITION_ADVANCED=y
9CONFIG_PLAT_SPEAR=y 9CONFIG_PLAT_SPEAR=y
10CONFIG_ARCH_SPEAR6XX=y 10CONFIG_ARCH_SPEAR6XX=y
11CONFIG_BOARD_SPEAR600_EVB=y 11CONFIG_BOARD_SPEAR600_DT=y
12CONFIG_BINFMT_MISC=y 12CONFIG_BINFMT_MISC=y
13CONFIG_NET=y
13CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 14CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
15CONFIG_MTD=y
16CONFIG_MTD_NAND=y
17CONFIG_MTD_NAND_FSMC=y
14CONFIG_BLK_DEV_RAM=y 18CONFIG_BLK_DEV_RAM=y
15CONFIG_BLK_DEV_RAM_SIZE=16384 19CONFIG_BLK_DEV_RAM_SIZE=16384
20CONFIG_NETDEVICES=y
21# CONFIG_NET_VENDOR_BROADCOM is not set
22# CONFIG_NET_VENDOR_CIRRUS is not set
23# CONFIG_NET_VENDOR_FARADAY is not set
24# CONFIG_NET_VENDOR_INTEL is not set
25# CONFIG_NET_VENDOR_MICREL is not set
26# CONFIG_NET_VENDOR_NATSEMI is not set
27# CONFIG_NET_VENDOR_SEEQ is not set
28# CONFIG_NET_VENDOR_SMSC is not set
29CONFIG_STMMAC_ETH=y
30# CONFIG_WLAN is not set
16CONFIG_INPUT_FF_MEMLESS=y 31CONFIG_INPUT_FF_MEMLESS=y
17# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 32# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
33# CONFIG_INPUT_KEYBOARD is not set
34# CONFIG_INPUT_MOUSE is not set
35# CONFIG_LEGACY_PTYS is not set
18CONFIG_SERIAL_AMBA_PL011=y 36CONFIG_SERIAL_AMBA_PL011=y
19CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 37CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
20# CONFIG_LEGACY_PTYS is not set
21CONFIG_RAW_DRIVER=y 38CONFIG_RAW_DRIVER=y
22CONFIG_MAX_RAW_DEVS=8192 39CONFIG_MAX_RAW_DEVS=8192
40CONFIG_I2C=y
41CONFIG_I2C_DESIGNWARE_PLATFORM=y
42CONFIG_SPI=y
43CONFIG_SPI_PL022=y
23CONFIG_GPIO_SYSFS=y 44CONFIG_GPIO_SYSFS=y
24CONFIG_GPIO_PL061=y 45CONFIG_GPIO_PL061=y
25# CONFIG_HWMON is not set 46# CONFIG_HWMON is not set
47CONFIG_WATCHDOG=y
48CONFIG_ARM_SP805_WATCHDOG=y
26# CONFIG_HID_SUPPORT is not set 49# CONFIG_HID_SUPPORT is not set
27# CONFIG_USB_SUPPORT is not set 50CONFIG_USB=y
51CONFIG_USB_EHCI_HCD=y
52CONFIG_USB_OHCI_HCD=y
53CONFIG_RTC_CLASS=y
54CONFIG_DMADEVICES=y
55CONFIG_AMBA_PL08X=y
56CONFIG_DMATEST=m
28CONFIG_EXT2_FS=y 57CONFIG_EXT2_FS=y
29CONFIG_EXT2_FS_XATTR=y 58CONFIG_EXT2_FS_XATTR=y
30CONFIG_EXT2_FS_SECURITY=y 59CONFIG_EXT2_FS_SECURITY=y
@@ -35,8 +64,6 @@ CONFIG_MSDOS_FS=m
35CONFIG_VFAT_FS=m 64CONFIG_VFAT_FS=m
36CONFIG_FAT_DEFAULT_IOCHARSET="ascii" 65CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
37CONFIG_TMPFS=y 66CONFIG_TMPFS=y
38CONFIG_PARTITION_ADVANCED=y
39CONFIG_NLS=y
40CONFIG_NLS_DEFAULT="utf8" 67CONFIG_NLS_DEFAULT="utf8"
41CONFIG_NLS_CODEPAGE_437=y 68CONFIG_NLS_CODEPAGE_437=y
42CONFIG_NLS_ASCII=m 69CONFIG_NLS_ASCII=m
@@ -44,6 +71,4 @@ CONFIG_MAGIC_SYSRQ=y
44CONFIG_DEBUG_FS=y 71CONFIG_DEBUG_FS=y
45CONFIG_DEBUG_KERNEL=y 72CONFIG_DEBUG_KERNEL=y
46CONFIG_DEBUG_SPINLOCK=y 73CONFIG_DEBUG_SPINLOCK=y
47CONFIG_DEBUG_SPINLOCK_SLEEP=y
48CONFIG_DEBUG_INFO=y 74CONFIG_DEBUG_INFO=y
49# CONFIG_CRC32 is not set
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0de37..8bd37291fa4 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -5,39 +5,22 @@
5if ARCH_SPEAR3XX 5if ARCH_SPEAR3XX
6 6
7menu "SPEAr3xx Implementations" 7menu "SPEAr3xx Implementations"
8config BOARD_SPEAR300_EVB
9 bool "SPEAr300 Evaluation Board"
10 select MACH_SPEAR300
11 help
12 Supports ST SPEAr300 Evaluation Board
13
14config BOARD_SPEAR310_EVB
15 bool "SPEAr310 Evaluation Board"
16 select MACH_SPEAR310
17 help
18 Supports ST SPEAr310 Evaluation Board
19
20config BOARD_SPEAR320_EVB
21 bool "SPEAr320 Evaluation Board"
22 select MACH_SPEAR320
23 help
24 Supports ST SPEAr320 Evaluation Board
25
26endmenu
27
28config MACH_SPEAR300 8config MACH_SPEAR300
29 bool "SPEAr300" 9 bool "SPEAr300 Machine support with Device Tree"
10 select PINCTRL_SPEAR300
30 help 11 help
31 Supports ST SPEAr300 Machine 12 Supports ST SPEAr300 machine configured via the device-tree
32 13
33config MACH_SPEAR310 14config MACH_SPEAR310
34 bool "SPEAr310" 15 bool "SPEAr310 Machine support with Device Tree"
16 select PINCTRL_SPEAR310
35 help 17 help
36 Supports ST SPEAr310 Machine 18 Supports ST SPEAr310 machine configured via the device-tree
37 19
38config MACH_SPEAR320 20config MACH_SPEAR320
39 bool "SPEAr320" 21 bool "SPEAr320 Machine support with Device Tree"
22 select PINCTRL_SPEAR320
40 help 23 help
41 Supports ST SPEAr320 Machine 24 Supports ST SPEAr320 machine configured via the device-tree
42 25endmenu
43endif #ARCH_SPEAR3XX 26endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b2486248970..17b5d83cf2d 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
3# 3#
4 4
5# common files 5# common files
6obj-y += spear3xx.o clock.o 6obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o clock.o
7 7
8# spear300 specific files 8# spear300 specific files
9obj-$(CONFIG_MACH_SPEAR300) += spear300.o 9obj-$(CONFIG_MACH_SPEAR300) += spear300.o
10 10
11# spear300 boards files
12obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
13
14
15# spear310 specific files 11# spear310 specific files
16obj-$(CONFIG_MACH_SPEAR310) += spear310.o 12obj-$(CONFIG_MACH_SPEAR310) += spear310.o
17 13
18# spear310 boards files
19obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
20
21
22# spear320 specific files 14# spear320 specific files
23obj-$(CONFIG_MACH_SPEAR320) += spear320.o 15obj-$(CONFIG_MACH_SPEAR320) += spear320.o
24
25# spear320 boards files
26obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c221d..d93e2177e6e 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
1zreladdr-y += 0x00008000 1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100 2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000 3initrd_phys-y := 0x00800000
4
5dtb-$(CONFIG_MACH_SPEAR300) += spear300-evb.dtb
6dtb-$(CONFIG_MACH_SPEAR310) += spear310-evb.dtb
7dtb-$(CONFIG_MACH_SPEAR320) += spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 6c4841f5522..eeafe38eab2 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -11,9 +11,11 @@
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/clkdev.h>
14#include <linux/init.h> 15#include <linux/init.h>
15#include <linux/io.h> 16#include <linux/io.h>
16#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/of_platform.h>
17#include <asm/mach-types.h> 19#include <asm/mach-types.h>
18#include <plat/clock.h> 20#include <plat/clock.h>
19#include <mach/misc_regs.h> 21#include <mach/misc_regs.h>
@@ -411,6 +413,21 @@ static struct clk usbd_clk = {
411 .recalc = &follow_parent, 413 .recalc = &follow_parent,
412}; 414};
413 415
416/* clock derived from usbh clk */
417/* usbh0 clock */
418static struct clk usbh0_clk = {
419 .flags = ALWAYS_ENABLED,
420 .pclk = &usbh_clk,
421 .recalc = &follow_parent,
422};
423
424/* usbh1 clock */
425static struct clk usbh1_clk = {
426 .flags = ALWAYS_ENABLED,
427 .pclk = &usbh_clk,
428 .recalc = &follow_parent,
429};
430
414/* clock derived from ahb clk */ 431/* clock derived from ahb clk */
415/* apb masks structure */ 432/* apb masks structure */
416static struct bus_clk_masks apb_masks = { 433static struct bus_clk_masks apb_masks = {
@@ -652,109 +669,126 @@ static struct clk pwm_clk = {
652 669
653/* array of all spear 3xx clock lookups */ 670/* array of all spear 3xx clock lookups */
654static struct clk_lookup spear_clk_lookups[] = { 671static struct clk_lookup spear_clk_lookups[] = {
655 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, 672 CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
656 /* root clks */ 673 /* root clks */
657 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, 674 CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
658 { .con_id = "osc_24m_clk", .clk = &osc_24m_clk}, 675 CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
659 /* clock derived from 32 KHz osc clk */ 676 /* clock derived from 32 KHz osc clk */
660 { .dev_id = "rtc-spear", .clk = &rtc_clk}, 677 CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk),
661 /* clock derived from 24 MHz osc clk */ 678 /* clock derived from 24 MHz osc clk */
662 { .con_id = "pll1_clk", .clk = &pll1_clk}, 679 CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
663 { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, 680 CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
664 { .dev_id = "wdt", .clk = &wdt_clk}, 681 CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk),
665 /* clock derived from pll1 clk */ 682 /* clock derived from pll1 clk */
666 { .con_id = "cpu_clk", .clk = &cpu_clk}, 683 CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
667 { .con_id = "ahb_clk", .clk = &ahb_clk}, 684 CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
668 { .con_id = "uart_synth_clk", .clk = &uart_synth_clk}, 685 CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
669 { .con_id = "firda_synth_clk", .clk = &firda_synth_clk}, 686 CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
670 { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk}, 687 CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
671 { .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk}, 688 CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
672 { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk}, 689 CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
673 { .dev_id = "uart", .clk = &uart_clk}, 690 CLKDEV_INIT("d0000000.serial", NULL, &uart_clk),
674 { .dev_id = "firda", .clk = &firda_clk}, 691 CLKDEV_INIT("firda", NULL, &firda_clk),
675 { .dev_id = "gpt0", .clk = &gpt0_clk}, 692 CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
676 { .dev_id = "gpt1", .clk = &gpt1_clk}, 693 CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
677 { .dev_id = "gpt2", .clk = &gpt2_clk}, 694 CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
678 /* clock derived from pll3 clk */ 695 /* clock derived from pll3 clk */
679 { .dev_id = "designware_udc", .clk = &usbd_clk}, 696 CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
680 { .con_id = "usbh_clk", .clk = &usbh_clk}, 697 CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
698 /* clock derived from usbh clk */
699 CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
700 CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
681 /* clock derived from ahb clk */ 701 /* clock derived from ahb clk */
682 { .con_id = "apb_clk", .clk = &apb_clk}, 702 CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
683 { .dev_id = "i2c_designware.0", .clk = &i2c_clk}, 703 CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
684 { .dev_id = "dma", .clk = &dma_clk}, 704 CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
685 { .dev_id = "jpeg", .clk = &jpeg_clk}, 705 CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
686 { .dev_id = "gmac", .clk = &gmac_clk}, 706 CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk),
687 { .dev_id = "smi", .clk = &smi_clk}, 707 CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
688 { .dev_id = "c3", .clk = &c3_clk}, 708 CLKDEV_INIT("c3", NULL, &c3_clk),
689 /* clock derived from apb clk */ 709 /* clock derived from apb clk */
690 { .dev_id = "adc", .clk = &adc_clk}, 710 CLKDEV_INIT("adc", NULL, &adc_clk),
691 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, 711 CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk),
692 { .dev_id = "gpio", .clk = &gpio_clk}, 712 CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk),
693}; 713};
694 714
695/* array of all spear 300 clock lookups */ 715/* array of all spear 300 clock lookups */
696#ifdef CONFIG_MACH_SPEAR300 716#ifdef CONFIG_MACH_SPEAR300
697static struct clk_lookup spear300_clk_lookups[] = { 717static struct clk_lookup spear300_clk_lookups[] = {
698 { .dev_id = "clcd", .clk = &clcd_clk}, 718 CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk),
699 { .con_id = "fsmc", .clk = &fsmc_clk}, 719 CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk),
700 { .dev_id = "gpio1", .clk = &gpio1_clk}, 720 CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk),
701 { .dev_id = "keyboard", .clk = &kbd_clk}, 721 CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk),
702 { .dev_id = "sdhci", .clk = &sdhci_clk}, 722 CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
703}; 723};
724
725void __init spear300_clk_init(void)
726{
727 int i;
728
729 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
730 clk_register(&spear_clk_lookups[i]);
731
732 for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++)
733 clk_register(&spear300_clk_lookups[i]);
734
735 clk_init();
736}
704#endif 737#endif
705 738
706/* array of all spear 310 clock lookups */ 739/* array of all spear 310 clock lookups */
707#ifdef CONFIG_MACH_SPEAR310 740#ifdef CONFIG_MACH_SPEAR310
708static struct clk_lookup spear310_clk_lookups[] = { 741static struct clk_lookup spear310_clk_lookups[] = {
709 { .con_id = "fsmc", .clk = &fsmc_clk}, 742 CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk),
710 { .con_id = "emi", .clk = &emi_clk}, 743 CLKDEV_INIT(NULL, "emi", &emi_clk),
711 { .dev_id = "uart1", .clk = &uart1_clk}, 744 CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk),
712 { .dev_id = "uart2", .clk = &uart2_clk}, 745 CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk),
713 { .dev_id = "uart3", .clk = &uart3_clk}, 746 CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk),
714 { .dev_id = "uart4", .clk = &uart4_clk}, 747 CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk),
715 { .dev_id = "uart5", .clk = &uart5_clk}, 748 CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk),
716}; 749};
750
751void __init spear310_clk_init(void)
752{
753 int i;
754
755 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
756 clk_register(&spear_clk_lookups[i]);
757
758 for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++)
759 clk_register(&spear310_clk_lookups[i]);
760
761 clk_init();
762}
717#endif 763#endif
718 764
719/* array of all spear 320 clock lookups */ 765/* array of all spear 320 clock lookups */
720#ifdef CONFIG_MACH_SPEAR320 766#ifdef CONFIG_MACH_SPEAR320
721static struct clk_lookup spear320_clk_lookups[] = { 767static struct clk_lookup spear320_clk_lookups[] = {
722 { .dev_id = "clcd", .clk = &clcd_clk}, 768 CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk),
723 { .con_id = "fsmc", .clk = &fsmc_clk}, 769 CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk),
724 { .dev_id = "i2c_designware.1", .clk = &i2c1_clk}, 770 CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk),
725 { .con_id = "emi", .clk = &emi_clk}, 771 CLKDEV_INIT(NULL, "emi", &emi_clk),
726 { .dev_id = "pwm", .clk = &pwm_clk}, 772 CLKDEV_INIT("pwm", NULL, &pwm_clk),
727 { .dev_id = "sdhci", .clk = &sdhci_clk}, 773 CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
728 { .dev_id = "c_can_platform.0", .clk = &can0_clk}, 774 CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
729 { .dev_id = "c_can_platform.1", .clk = &can1_clk}, 775 CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
730 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, 776 CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk),
731 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, 777 CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk),
732 { .dev_id = "uart1", .clk = &uart1_clk}, 778 CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk),
733 { .dev_id = "uart2", .clk = &uart2_clk}, 779 CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk),
734}; 780};
735#endif 781
736 782void __init spear320_clk_init(void)
737void __init spear3xx_clk_init(void)
738{ 783{
739 int i, cnt; 784 int i;
740 struct clk_lookup *lookups;
741
742 if (machine_is_spear300()) {
743 cnt = ARRAY_SIZE(spear300_clk_lookups);
744 lookups = spear300_clk_lookups;
745 } else if (machine_is_spear310()) {
746 cnt = ARRAY_SIZE(spear310_clk_lookups);
747 lookups = spear310_clk_lookups;
748 } else {
749 cnt = ARRAY_SIZE(spear320_clk_lookups);
750 lookups = spear320_clk_lookups;
751 }
752 785
753 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) 786 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
754 clk_register(&spear_clk_lookups[i]); 787 clk_register(&spear_clk_lookups[i]);
755 788
756 for (i = 0; i < cnt; i++) 789 for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++)
757 clk_register(&lookups[i]); 790 clk_register(&spear320_clk_lookups[i]);
758 791
759 clk_init(); 792 clk_init();
760} 793}
794#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5a98d..9603bf4d511 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,12 +14,12 @@
14#ifndef __MACH_GENERIC_H 14#ifndef __MACH_GENERIC_H
15#define __MACH_GENERIC_H 15#define __MACH_GENERIC_H
16 16
17#include <linux/amba/pl08x.h>
17#include <linux/init.h> 18#include <linux/init.h>
18#include <linux/platform_device.h> 19#include <linux/platform_device.h>
19#include <linux/amba/bus.h> 20#include <linux/amba/bus.h>
20#include <asm/mach/time.h> 21#include <asm/mach/time.h>
21#include <asm/mach/map.h> 22#include <asm/mach/map.h>
22#include <plat/padmux.h>
23 23
24/* spear3xx declarations */ 24/* spear3xx declarations */
25/* 25/*
@@ -31,171 +31,32 @@
31#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2 31#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
32 32
33/* Add spear3xx family device structure declarations here */ 33/* Add spear3xx family device structure declarations here */
34extern struct amba_device spear3xx_gpio_device;
35extern struct amba_device spear3xx_uart_device;
36extern struct sys_timer spear3xx_timer; 34extern struct sys_timer spear3xx_timer;
35extern struct pl022_ssp_controller pl022_plat_data;
36extern struct pl08x_platform_data pl080_plat_data;
37 37
38/* Add spear3xx family function declarations here */ 38/* Add spear3xx family function declarations here */
39void __init spear3xx_clk_init(void);
40void __init spear_setup_timer(void); 39void __init spear_setup_timer(void);
41void __init spear3xx_map_io(void); 40void __init spear3xx_map_io(void);
42void __init spear3xx_init_irq(void); 41void __init spear3xx_dt_init_irq(void);
43void __init spear3xx_init(void);
44 42
45void spear_restart(char, const char *); 43void spear_restart(char, const char *);
46 44
47/* pad mux declarations */
48#define PMX_FIRDA_MASK (1 << 14)
49#define PMX_I2C_MASK (1 << 13)
50#define PMX_SSP_CS_MASK (1 << 12)
51#define PMX_SSP_MASK (1 << 11)
52#define PMX_MII_MASK (1 << 10)
53#define PMX_GPIO_PIN0_MASK (1 << 9)
54#define PMX_GPIO_PIN1_MASK (1 << 8)
55#define PMX_GPIO_PIN2_MASK (1 << 7)
56#define PMX_GPIO_PIN3_MASK (1 << 6)
57#define PMX_GPIO_PIN4_MASK (1 << 5)
58#define PMX_GPIO_PIN5_MASK (1 << 4)
59#define PMX_UART0_MODEM_MASK (1 << 3)
60#define PMX_UART0_MASK (1 << 2)
61#define PMX_TIMER_3_4_MASK (1 << 1)
62#define PMX_TIMER_1_2_MASK (1 << 0)
63
64/* pad mux devices */
65extern struct pmx_dev spear3xx_pmx_firda;
66extern struct pmx_dev spear3xx_pmx_i2c;
67extern struct pmx_dev spear3xx_pmx_ssp_cs;
68extern struct pmx_dev spear3xx_pmx_ssp;
69extern struct pmx_dev spear3xx_pmx_mii;
70extern struct pmx_dev spear3xx_pmx_gpio_pin0;
71extern struct pmx_dev spear3xx_pmx_gpio_pin1;
72extern struct pmx_dev spear3xx_pmx_gpio_pin2;
73extern struct pmx_dev spear3xx_pmx_gpio_pin3;
74extern struct pmx_dev spear3xx_pmx_gpio_pin4;
75extern struct pmx_dev spear3xx_pmx_gpio_pin5;
76extern struct pmx_dev spear3xx_pmx_uart0_modem;
77extern struct pmx_dev spear3xx_pmx_uart0;
78extern struct pmx_dev spear3xx_pmx_timer_3_4;
79extern struct pmx_dev spear3xx_pmx_timer_1_2;
80
81#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
82/* padmux plgpio devices */
83extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
84extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
85extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
86extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
87extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
88extern struct pmx_dev spear3xx_pmx_plgpio_28;
89extern struct pmx_dev spear3xx_pmx_plgpio_29;
90extern struct pmx_dev spear3xx_pmx_plgpio_30;
91extern struct pmx_dev spear3xx_pmx_plgpio_31;
92extern struct pmx_dev spear3xx_pmx_plgpio_32;
93extern struct pmx_dev spear3xx_pmx_plgpio_33;
94extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
95extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
96extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
97extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
98#endif
99
100/* spear300 declarations */ 45/* spear300 declarations */
101#ifdef CONFIG_MACH_SPEAR300 46#ifdef CONFIG_MACH_SPEAR300
102/* Add spear300 machine device structure declarations here */ 47void __init spear300_clk_init(void);
103extern struct amba_device spear300_gpio1_device;
104
105/* pad mux modes */
106extern struct pmx_mode spear300_nand_mode;
107extern struct pmx_mode spear300_nor_mode;
108extern struct pmx_mode spear300_photo_frame_mode;
109extern struct pmx_mode spear300_lend_ip_phone_mode;
110extern struct pmx_mode spear300_hend_ip_phone_mode;
111extern struct pmx_mode spear300_lend_wifi_phone_mode;
112extern struct pmx_mode spear300_hend_wifi_phone_mode;
113extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
114extern struct pmx_mode spear300_ata_pabx_i2s_mode;
115extern struct pmx_mode spear300_caml_lcdw_mode;
116extern struct pmx_mode spear300_camu_lcd_mode;
117extern struct pmx_mode spear300_camu_wlcd_mode;
118extern struct pmx_mode spear300_caml_lcd_mode;
119
120/* pad mux devices */
121extern struct pmx_dev spear300_pmx_fsmc_2_chips;
122extern struct pmx_dev spear300_pmx_fsmc_4_chips;
123extern struct pmx_dev spear300_pmx_keyboard;
124extern struct pmx_dev spear300_pmx_clcd;
125extern struct pmx_dev spear300_pmx_telecom_gpio;
126extern struct pmx_dev spear300_pmx_telecom_tdm;
127extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
128extern struct pmx_dev spear300_pmx_telecom_camera;
129extern struct pmx_dev spear300_pmx_telecom_dac;
130extern struct pmx_dev spear300_pmx_telecom_i2s;
131extern struct pmx_dev spear300_pmx_telecom_boot_pins;
132extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
133extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
134extern struct pmx_dev spear300_pmx_gpio1;
135
136/* Add spear300 machine function declarations here */
137void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
138 u8 pmx_dev_count);
139 48
140#endif /* CONFIG_MACH_SPEAR300 */ 49#endif /* CONFIG_MACH_SPEAR300 */
141 50
142/* spear310 declarations */ 51/* spear310 declarations */
143#ifdef CONFIG_MACH_SPEAR310 52#ifdef CONFIG_MACH_SPEAR310
144/* Add spear310 machine device structure declarations here */ 53void __init spear310_clk_init(void);
145
146/* pad mux devices */
147extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
148extern struct pmx_dev spear310_pmx_emi_cs_2_3;
149extern struct pmx_dev spear310_pmx_uart1;
150extern struct pmx_dev spear310_pmx_uart2;
151extern struct pmx_dev spear310_pmx_uart3_4_5;
152extern struct pmx_dev spear310_pmx_fsmc;
153extern struct pmx_dev spear310_pmx_rs485_0_1;
154extern struct pmx_dev spear310_pmx_tdm0;
155
156/* Add spear310 machine function declarations here */
157void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
158 u8 pmx_dev_count);
159 54
160#endif /* CONFIG_MACH_SPEAR310 */ 55#endif /* CONFIG_MACH_SPEAR310 */
161 56
162/* spear320 declarations */ 57/* spear320 declarations */
163#ifdef CONFIG_MACH_SPEAR320 58#ifdef CONFIG_MACH_SPEAR320
164/* Add spear320 machine device structure declarations here */ 59void __init spear320_clk_init(void);
165
166/* pad mux modes */
167extern struct pmx_mode spear320_auto_net_smii_mode;
168extern struct pmx_mode spear320_auto_net_mii_mode;
169extern struct pmx_mode spear320_auto_exp_mode;
170extern struct pmx_mode spear320_small_printers_mode;
171
172/* pad mux devices */
173extern struct pmx_dev spear320_pmx_clcd;
174extern struct pmx_dev spear320_pmx_emi;
175extern struct pmx_dev spear320_pmx_fsmc;
176extern struct pmx_dev spear320_pmx_spp;
177extern struct pmx_dev spear320_pmx_sdhci;
178extern struct pmx_dev spear320_pmx_i2s;
179extern struct pmx_dev spear320_pmx_uart1;
180extern struct pmx_dev spear320_pmx_uart1_modem;
181extern struct pmx_dev spear320_pmx_uart2;
182extern struct pmx_dev spear320_pmx_touchscreen;
183extern struct pmx_dev spear320_pmx_can;
184extern struct pmx_dev spear320_pmx_sdhci_led;
185extern struct pmx_dev spear320_pmx_pwm0;
186extern struct pmx_dev spear320_pmx_pwm1;
187extern struct pmx_dev spear320_pmx_pwm2;
188extern struct pmx_dev spear320_pmx_pwm3;
189extern struct pmx_dev spear320_pmx_ssp1;
190extern struct pmx_dev spear320_pmx_ssp2;
191extern struct pmx_dev spear320_pmx_mii1;
192extern struct pmx_dev spear320_pmx_smii0;
193extern struct pmx_dev spear320_pmx_smii1;
194extern struct pmx_dev spear320_pmx_i2c1;
195
196/* Add spear320 machine function declarations here */
197void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
198 u8 pmx_dev_count);
199 60
200#endif /* CONFIG_MACH_SPEAR320 */ 61#endif /* CONFIG_MACH_SPEAR320 */
201 62
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4660c0d8ec0..defa374f5be 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -17,7 +17,4 @@
17#include <plat/hardware.h> 17#include <plat/hardware.h>
18#include <mach/spear.h> 18#include <mach/spear.h>
19 19
20/* Vitual to physical translation of statically mapped space */
21#define IO_ADDRESS(x) (x | 0xF0000000)
22
23#endif /* __MACH_HARDWARE_H */ 20#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 63fd9835691..8e3900aa0d4 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -25,8 +25,9 @@
25 25
26/* ICM1 - Low speed connection */ 26/* ICM1 - Low speed connection */
27#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) 27#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
28#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
28#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) 29#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
29#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) 30#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
30#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000) 31#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
31#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) 32#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
32#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000) 33#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
@@ -53,11 +54,11 @@
53#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) 54#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
54#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) 55#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000)
55#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) 56#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
56#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
57 57
58/* ICM3 - Basic Subsystem */ 58/* ICM3 - Basic Subsystem */
59#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000) 59#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
60#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 60#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
61#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
61#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) 62#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
62#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) 63#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
63#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000) 64#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
@@ -65,9 +66,9 @@
65#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000) 66#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
66#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000) 67#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
67#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 68#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
68#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) 69#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
69#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) 70#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
70#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) 71#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
71#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000) 72#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
72 73
73/* Debug uart for linux, will be used for debug and uncompress messages */ 74/* Debug uart for linux, will be used for debug and uncompress messages */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db66812ab..2db0bd14e48 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,373 +3,24 @@
3 * 3 *
4 * SPEAr300 machine source file 4 * SPEAr300 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/types.h> 14#define pr_fmt(fmt) "SPEAr300: " fmt
15#include <linux/amba/pl061.h> 15
16#include <linux/ptrace.h> 16#include <linux/amba/pl08x.h>
17#include <asm/irq.h> 17#include <linux/of_platform.h>
18#include <asm/hardware/vic.h>
19#include <asm/mach/arch.h>
18#include <plat/shirq.h> 20#include <plat/shirq.h>
19#include <mach/generic.h> 21#include <mach/generic.h>
20#include <mach/hardware.h> 22#include <mach/hardware.h>
21 23
22/* pad multiplexing support */
23/* muxing registers */
24#define PAD_MUX_CONFIG_REG 0x00
25#define MODE_CONFIG_REG 0x04
26
27/* modes */
28#define NAND_MODE (1 << 0)
29#define NOR_MODE (1 << 1)
30#define PHOTO_FRAME_MODE (1 << 2)
31#define LEND_IP_PHONE_MODE (1 << 3)
32#define HEND_IP_PHONE_MODE (1 << 4)
33#define LEND_WIFI_PHONE_MODE (1 << 5)
34#define HEND_WIFI_PHONE_MODE (1 << 6)
35#define ATA_PABX_WI2S_MODE (1 << 7)
36#define ATA_PABX_I2S_MODE (1 << 8)
37#define CAML_LCDW_MODE (1 << 9)
38#define CAMU_LCD_MODE (1 << 10)
39#define CAMU_WLCD_MODE (1 << 11)
40#define CAML_LCD_MODE (1 << 12)
41#define ALL_MODES 0x1FFF
42
43struct pmx_mode spear300_nand_mode = {
44 .id = NAND_MODE,
45 .name = "nand mode",
46 .mask = 0x00,
47};
48
49struct pmx_mode spear300_nor_mode = {
50 .id = NOR_MODE,
51 .name = "nor mode",
52 .mask = 0x01,
53};
54
55struct pmx_mode spear300_photo_frame_mode = {
56 .id = PHOTO_FRAME_MODE,
57 .name = "photo frame mode",
58 .mask = 0x02,
59};
60
61struct pmx_mode spear300_lend_ip_phone_mode = {
62 .id = LEND_IP_PHONE_MODE,
63 .name = "lend ip phone mode",
64 .mask = 0x03,
65};
66
67struct pmx_mode spear300_hend_ip_phone_mode = {
68 .id = HEND_IP_PHONE_MODE,
69 .name = "hend ip phone mode",
70 .mask = 0x04,
71};
72
73struct pmx_mode spear300_lend_wifi_phone_mode = {
74 .id = LEND_WIFI_PHONE_MODE,
75 .name = "lend wifi phone mode",
76 .mask = 0x05,
77};
78
79struct pmx_mode spear300_hend_wifi_phone_mode = {
80 .id = HEND_WIFI_PHONE_MODE,
81 .name = "hend wifi phone mode",
82 .mask = 0x06,
83};
84
85struct pmx_mode spear300_ata_pabx_wi2s_mode = {
86 .id = ATA_PABX_WI2S_MODE,
87 .name = "ata pabx wi2s mode",
88 .mask = 0x07,
89};
90
91struct pmx_mode spear300_ata_pabx_i2s_mode = {
92 .id = ATA_PABX_I2S_MODE,
93 .name = "ata pabx i2s mode",
94 .mask = 0x08,
95};
96
97struct pmx_mode spear300_caml_lcdw_mode = {
98 .id = CAML_LCDW_MODE,
99 .name = "caml lcdw mode",
100 .mask = 0x0C,
101};
102
103struct pmx_mode spear300_camu_lcd_mode = {
104 .id = CAMU_LCD_MODE,
105 .name = "camu lcd mode",
106 .mask = 0x0D,
107};
108
109struct pmx_mode spear300_camu_wlcd_mode = {
110 .id = CAMU_WLCD_MODE,
111 .name = "camu wlcd mode",
112 .mask = 0x0E,
113};
114
115struct pmx_mode spear300_caml_lcd_mode = {
116 .id = CAML_LCD_MODE,
117 .name = "caml lcd mode",
118 .mask = 0x0F,
119};
120
121/* devices */
122static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
123 {
124 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
125 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
126 .mask = PMX_FIRDA_MASK,
127 },
128};
129
130struct pmx_dev spear300_pmx_fsmc_2_chips = {
131 .name = "fsmc_2_chips",
132 .modes = pmx_fsmc_2_chips_modes,
133 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
134 .enb_on_reset = 1,
135};
136
137static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
138 {
139 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
140 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
141 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
142 },
143};
144
145struct pmx_dev spear300_pmx_fsmc_4_chips = {
146 .name = "fsmc_4_chips",
147 .modes = pmx_fsmc_4_chips_modes,
148 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
149 .enb_on_reset = 1,
150};
151
152static struct pmx_dev_mode pmx_keyboard_modes[] = {
153 {
154 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
155 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
156 CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
157 CAML_LCD_MODE,
158 .mask = 0x0,
159 },
160};
161
162struct pmx_dev spear300_pmx_keyboard = {
163 .name = "keyboard",
164 .modes = pmx_keyboard_modes,
165 .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
166 .enb_on_reset = 1,
167};
168
169static struct pmx_dev_mode pmx_clcd_modes[] = {
170 {
171 .ids = PHOTO_FRAME_MODE,
172 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
173 }, {
174 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
175 CAMU_LCD_MODE | CAML_LCD_MODE,
176 .mask = PMX_TIMER_3_4_MASK,
177 },
178};
179
180struct pmx_dev spear300_pmx_clcd = {
181 .name = "clcd",
182 .modes = pmx_clcd_modes,
183 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
184 .enb_on_reset = 1,
185};
186
187static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
188 {
189 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
190 .mask = PMX_MII_MASK,
191 }, {
192 .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
193 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
194 }, {
195 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
196 .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
197 }, {
198 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
199 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
200 }, {
201 .ids = ATA_PABX_WI2S_MODE,
202 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
203 | PMX_UART0_MODEM_MASK,
204 },
205};
206
207struct pmx_dev spear300_pmx_telecom_gpio = {
208 .name = "telecom_gpio",
209 .modes = pmx_telecom_gpio_modes,
210 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
211 .enb_on_reset = 1,
212};
213
214static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
215 {
216 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
217 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
218 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
219 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
220 | CAMU_WLCD_MODE | CAML_LCD_MODE,
221 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
222 },
223};
224
225struct pmx_dev spear300_pmx_telecom_tdm = {
226 .name = "telecom_tdm",
227 .modes = pmx_telecom_tdm_modes,
228 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
229 .enb_on_reset = 1,
230};
231
232static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
233 {
234 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
235 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
236 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
237 CAML_LCDW_MODE | CAML_LCD_MODE,
238 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
239 },
240};
241
242struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
243 .name = "telecom_spi_cs_i2c_clk",
244 .modes = pmx_telecom_spi_cs_i2c_clk_modes,
245 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
246 .enb_on_reset = 1,
247};
248
249static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
250 {
251 .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
252 .mask = PMX_MII_MASK,
253 }, {
254 .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
255 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
256 },
257};
258
259struct pmx_dev spear300_pmx_telecom_camera = {
260 .name = "telecom_camera",
261 .modes = pmx_telecom_camera_modes,
262 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
263 .enb_on_reset = 1,
264};
265
266static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
267 {
268 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
269 | CAMU_WLCD_MODE | CAML_LCD_MODE,
270 .mask = PMX_TIMER_1_2_MASK,
271 },
272};
273
274struct pmx_dev spear300_pmx_telecom_dac = {
275 .name = "telecom_dac",
276 .modes = pmx_telecom_dac_modes,
277 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
278 .enb_on_reset = 1,
279};
280
281static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
282 {
283 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
284 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
285 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
286 | CAMU_WLCD_MODE | CAML_LCD_MODE,
287 .mask = PMX_UART0_MODEM_MASK,
288 },
289};
290
291struct pmx_dev spear300_pmx_telecom_i2s = {
292 .name = "telecom_i2s",
293 .modes = pmx_telecom_i2s_modes,
294 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
295 .enb_on_reset = 1,
296};
297
298static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
299 {
300 .ids = NAND_MODE | NOR_MODE,
301 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
302 PMX_TIMER_3_4_MASK,
303 },
304};
305
306struct pmx_dev spear300_pmx_telecom_boot_pins = {
307 .name = "telecom_boot_pins",
308 .modes = pmx_telecom_boot_pins_modes,
309 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
310 .enb_on_reset = 1,
311};
312
313static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
314 {
315 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
316 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
317 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
318 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
319 ATA_PABX_I2S_MODE,
320 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
321 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
322 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
323 },
324};
325
326struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
327 .name = "telecom_sdhci_4bit",
328 .modes = pmx_telecom_sdhci_4bit_modes,
329 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
330 .enb_on_reset = 1,
331};
332
333static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
334 {
335 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
336 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
337 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
338 CAMU_WLCD_MODE | CAML_LCD_MODE,
339 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
340 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
341 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
342 },
343};
344
345struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
346 .name = "telecom_sdhci_8bit",
347 .modes = pmx_telecom_sdhci_8bit_modes,
348 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
349 .enb_on_reset = 1,
350};
351
352static struct pmx_dev_mode pmx_gpio1_modes[] = {
353 {
354 .ids = PHOTO_FRAME_MODE,
355 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
356 PMX_TIMER_3_4_MASK,
357 },
358};
359
360struct pmx_dev spear300_pmx_gpio1 = {
361 .name = "arm gpio1",
362 .modes = pmx_gpio1_modes,
363 .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
364 .enb_on_reset = 1,
365};
366
367/* pmx driver structure */
368static struct pmx_driver pmx_driver = {
369 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
370 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
371};
372
373/* spear3xx shared irq */ 24/* spear3xx shared irq */
374static struct shirq_dev_config shirq_ras1_config[] = { 25static struct shirq_dev_config shirq_ras1_config[] = {
375 { 26 {
@@ -423,45 +74,239 @@ static struct spear_shirq shirq_ras1 = {
423 }, 74 },
424}; 75};
425 76
426/* Add spear300 specific devices here */ 77/* DMAC platform data's slave info */
427/* arm gpio1 device registration */ 78struct pl08x_channel_data spear300_dma_info[] = {
428static struct pl061_platform_data gpio1_plat_data = { 79 {
429 .gpio_base = 8, 80 .bus_id = "uart0_rx",
430 .irq_base = SPEAR300_GPIO1_INT_BASE, 81 .min_signal = 2,
82 .max_signal = 2,
83 .muxval = 0,
84 .cctl = 0,
85 .periph_buses = PL08X_AHB1,
86 }, {
87 .bus_id = "uart0_tx",
88 .min_signal = 3,
89 .max_signal = 3,
90 .muxval = 0,
91 .cctl = 0,
92 .periph_buses = PL08X_AHB1,
93 }, {
94 .bus_id = "ssp0_rx",
95 .min_signal = 8,
96 .max_signal = 8,
97 .muxval = 0,
98 .cctl = 0,
99 .periph_buses = PL08X_AHB1,
100 }, {
101 .bus_id = "ssp0_tx",
102 .min_signal = 9,
103 .max_signal = 9,
104 .muxval = 0,
105 .cctl = 0,
106 .periph_buses = PL08X_AHB1,
107 }, {
108 .bus_id = "i2c_rx",
109 .min_signal = 10,
110 .max_signal = 10,
111 .muxval = 0,
112 .cctl = 0,
113 .periph_buses = PL08X_AHB1,
114 }, {
115 .bus_id = "i2c_tx",
116 .min_signal = 11,
117 .max_signal = 11,
118 .muxval = 0,
119 .cctl = 0,
120 .periph_buses = PL08X_AHB1,
121 }, {
122 .bus_id = "irda",
123 .min_signal = 12,
124 .max_signal = 12,
125 .muxval = 0,
126 .cctl = 0,
127 .periph_buses = PL08X_AHB1,
128 }, {
129 .bus_id = "adc",
130 .min_signal = 13,
131 .max_signal = 13,
132 .muxval = 0,
133 .cctl = 0,
134 .periph_buses = PL08X_AHB1,
135 }, {
136 .bus_id = "to_jpeg",
137 .min_signal = 14,
138 .max_signal = 14,
139 .muxval = 0,
140 .cctl = 0,
141 .periph_buses = PL08X_AHB1,
142 }, {
143 .bus_id = "from_jpeg",
144 .min_signal = 15,
145 .max_signal = 15,
146 .muxval = 0,
147 .cctl = 0,
148 .periph_buses = PL08X_AHB1,
149 }, {
150 .bus_id = "ras0_rx",
151 .min_signal = 0,
152 .max_signal = 0,
153 .muxval = 1,
154 .cctl = 0,
155 .periph_buses = PL08X_AHB1,
156 }, {
157 .bus_id = "ras0_tx",
158 .min_signal = 1,
159 .max_signal = 1,
160 .muxval = 1,
161 .cctl = 0,
162 .periph_buses = PL08X_AHB1,
163 }, {
164 .bus_id = "ras1_rx",
165 .min_signal = 2,
166 .max_signal = 2,
167 .muxval = 1,
168 .cctl = 0,
169 .periph_buses = PL08X_AHB1,
170 }, {
171 .bus_id = "ras1_tx",
172 .min_signal = 3,
173 .max_signal = 3,
174 .muxval = 1,
175 .cctl = 0,
176 .periph_buses = PL08X_AHB1,
177 }, {
178 .bus_id = "ras2_rx",
179 .min_signal = 4,
180 .max_signal = 4,
181 .muxval = 1,
182 .cctl = 0,
183 .periph_buses = PL08X_AHB1,
184 }, {
185 .bus_id = "ras2_tx",
186 .min_signal = 5,
187 .max_signal = 5,
188 .muxval = 1,
189 .cctl = 0,
190 .periph_buses = PL08X_AHB1,
191 }, {
192 .bus_id = "ras3_rx",
193 .min_signal = 6,
194 .max_signal = 6,
195 .muxval = 1,
196 .cctl = 0,
197 .periph_buses = PL08X_AHB1,
198 }, {
199 .bus_id = "ras3_tx",
200 .min_signal = 7,
201 .max_signal = 7,
202 .muxval = 1,
203 .cctl = 0,
204 .periph_buses = PL08X_AHB1,
205 }, {
206 .bus_id = "ras4_rx",
207 .min_signal = 8,
208 .max_signal = 8,
209 .muxval = 1,
210 .cctl = 0,
211 .periph_buses = PL08X_AHB1,
212 }, {
213 .bus_id = "ras4_tx",
214 .min_signal = 9,
215 .max_signal = 9,
216 .muxval = 1,
217 .cctl = 0,
218 .periph_buses = PL08X_AHB1,
219 }, {
220 .bus_id = "ras5_rx",
221 .min_signal = 10,
222 .max_signal = 10,
223 .muxval = 1,
224 .cctl = 0,
225 .periph_buses = PL08X_AHB1,
226 }, {
227 .bus_id = "ras5_tx",
228 .min_signal = 11,
229 .max_signal = 11,
230 .muxval = 1,
231 .cctl = 0,
232 .periph_buses = PL08X_AHB1,
233 }, {
234 .bus_id = "ras6_rx",
235 .min_signal = 12,
236 .max_signal = 12,
237 .muxval = 1,
238 .cctl = 0,
239 .periph_buses = PL08X_AHB1,
240 }, {
241 .bus_id = "ras6_tx",
242 .min_signal = 13,
243 .max_signal = 13,
244 .muxval = 1,
245 .cctl = 0,
246 .periph_buses = PL08X_AHB1,
247 }, {
248 .bus_id = "ras7_rx",
249 .min_signal = 14,
250 .max_signal = 14,
251 .muxval = 1,
252 .cctl = 0,
253 .periph_buses = PL08X_AHB1,
254 }, {
255 .bus_id = "ras7_tx",
256 .min_signal = 15,
257 .max_signal = 15,
258 .muxval = 1,
259 .cctl = 0,
260 .periph_buses = PL08X_AHB1,
261 },
431}; 262};
432 263
433AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE, 264/* Add SPEAr300 auxdata to pass platform data */
434 {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data); 265static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
266 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
267 &pl022_plat_data),
268 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
269 &pl080_plat_data),
270 {}
271};
435 272
436/* spear300 routines */ 273static void __init spear300_dt_init(void)
437void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
438 u8 pmx_dev_count)
439{ 274{
440 int ret = 0; 275 int ret;
276
277 pl080_plat_data.slave_channels = spear300_dma_info;
278 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
441 279
442 /* call spear3xx family common init function */ 280 of_platform_populate(NULL, of_default_bus_match_table,
443 spear3xx_init(); 281 spear300_auxdata_lookup, NULL);
444 282
445 /* shared irq registration */ 283 /* shared irq registration */
446 shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K); 284 shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
447 if (shirq_ras1.regs.base) { 285 if (shirq_ras1.regs.base) {
448 ret = spear_shirq_register(&shirq_ras1); 286 ret = spear_shirq_register(&shirq_ras1);
449 if (ret) 287 if (ret)
450 printk(KERN_ERR "Error registering Shared IRQ\n"); 288 pr_err("Error registering Shared IRQ\n");
451 } 289 }
290}
452 291
453 /* pmx initialization */ 292static const char * const spear300_dt_board_compat[] = {
454 pmx_driver.mode = pmx_mode; 293 "st,spear300",
455 pmx_driver.devs = pmx_devs; 294 "st,spear300-evb",
456 pmx_driver.devs_count = pmx_dev_count; 295 NULL,
296};
457 297
458 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); 298static void __init spear300_map_io(void)
459 if (pmx_driver.base) { 299{
460 ret = pmx_register(&pmx_driver); 300 spear3xx_map_io();
461 if (ret) 301 spear300_clk_init();
462 printk(KERN_ERR "padmux: registration failed. err no"
463 ": %d\n", ret);
464 /* Free Mapping, device selection already done */
465 iounmap(pmx_driver.base);
466 }
467} 302}
303
304DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
305 .map_io = spear300_map_io,
306 .init_irq = spear3xx_dt_init_irq,
307 .handle_irq = vic_handle_irq,
308 .timer = &spear3xx_timer,
309 .init_machine = spear300_dt_init,
310 .restart = spear_restart,
311 .dt_compat = spear300_dt_board_compat,
312MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9d612..00000000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/spear300_evb.c
3 *
4 * SPEAr300 evaluation board source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17#include <mach/generic.h>
18#include <mach/hardware.h>
19
20/* padmux devices to enable */
21static struct pmx_dev *pmx_devs[] = {
22 /* spear3xx specific devices */
23 &spear3xx_pmx_i2c,
24 &spear3xx_pmx_ssp_cs,
25 &spear3xx_pmx_ssp,
26 &spear3xx_pmx_mii,
27 &spear3xx_pmx_uart0,
28
29 /* spear300 specific devices */
30 &spear300_pmx_fsmc_2_chips,
31 &spear300_pmx_clcd,
32 &spear300_pmx_telecom_sdhci_4bit,
33 &spear300_pmx_gpio1,
34};
35
36static struct amba_device *amba_devs[] __initdata = {
37 /* spear3xx specific devices */
38 &spear3xx_gpio_device,
39 &spear3xx_uart_device,
40
41 /* spear300 specific devices */
42 &spear300_gpio1_device,
43};
44
45static struct platform_device *plat_devs[] __initdata = {
46 /* spear3xx specific devices */
47
48 /* spear300 specific devices */
49};
50
51static void __init spear300_evb_init(void)
52{
53 unsigned int i;
54
55 /* call spear300 machine init function */
56 spear300_init(&spear300_photo_frame_mode, pmx_devs,
57 ARRAY_SIZE(pmx_devs));
58
59 /* Add Platform Devices */
60 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
61
62 /* Add Amba Devices */
63 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
64 amba_device_register(amba_devs[i], &iomem_resource);
65}
66
67MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
68 .atag_offset = 0x100,
69 .map_io = spear3xx_map_io,
70 .init_irq = spear3xx_init_irq,
71 .handle_irq = vic_handle_irq,
72 .timer = &spear3xx_timer,
73 .init_machine = spear300_evb_init,
74 .restart = spear_restart,
75MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6fcfb6..aec07c95120 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,142 +3,25 @@
3 * 3 *
4 * SPEAr310 machine source file 4 * SPEAr310 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/ptrace.h> 14#define pr_fmt(fmt) "SPEAr310: " fmt
15#include <asm/irq.h> 15
16#include <linux/amba/pl08x.h>
17#include <linux/amba/serial.h>
18#include <linux/of_platform.h>
19#include <asm/hardware/vic.h>
20#include <asm/mach/arch.h>
16#include <plat/shirq.h> 21#include <plat/shirq.h>
17#include <mach/generic.h> 22#include <mach/generic.h>
18#include <mach/hardware.h> 23#include <mach/hardware.h>
19 24
20/* pad multiplexing support */
21/* muxing registers */
22#define PAD_MUX_CONFIG_REG 0x08
23
24/* devices */
25static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
26 {
27 .ids = 0x00,
28 .mask = PMX_TIMER_3_4_MASK,
29 },
30};
31
32struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
33 .name = "emi_cs_0_1_4_5",
34 .modes = pmx_emi_cs_0_1_4_5_modes,
35 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
36 .enb_on_reset = 1,
37};
38
39static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
40 {
41 .ids = 0x00,
42 .mask = PMX_TIMER_1_2_MASK,
43 },
44};
45
46struct pmx_dev spear310_pmx_emi_cs_2_3 = {
47 .name = "emi_cs_2_3",
48 .modes = pmx_emi_cs_2_3_modes,
49 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
50 .enb_on_reset = 1,
51};
52
53static struct pmx_dev_mode pmx_uart1_modes[] = {
54 {
55 .ids = 0x00,
56 .mask = PMX_FIRDA_MASK,
57 },
58};
59
60struct pmx_dev spear310_pmx_uart1 = {
61 .name = "uart1",
62 .modes = pmx_uart1_modes,
63 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
64 .enb_on_reset = 1,
65};
66
67static struct pmx_dev_mode pmx_uart2_modes[] = {
68 {
69 .ids = 0x00,
70 .mask = PMX_TIMER_1_2_MASK,
71 },
72};
73
74struct pmx_dev spear310_pmx_uart2 = {
75 .name = "uart2",
76 .modes = pmx_uart2_modes,
77 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
78 .enb_on_reset = 1,
79};
80
81static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
82 {
83 .ids = 0x00,
84 .mask = PMX_UART0_MODEM_MASK,
85 },
86};
87
88struct pmx_dev spear310_pmx_uart3_4_5 = {
89 .name = "uart3_4_5",
90 .modes = pmx_uart3_4_5_modes,
91 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
92 .enb_on_reset = 1,
93};
94
95static struct pmx_dev_mode pmx_fsmc_modes[] = {
96 {
97 .ids = 0x00,
98 .mask = PMX_SSP_CS_MASK,
99 },
100};
101
102struct pmx_dev spear310_pmx_fsmc = {
103 .name = "fsmc",
104 .modes = pmx_fsmc_modes,
105 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
106 .enb_on_reset = 1,
107};
108
109static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
110 {
111 .ids = 0x00,
112 .mask = PMX_MII_MASK,
113 },
114};
115
116struct pmx_dev spear310_pmx_rs485_0_1 = {
117 .name = "rs485_0_1",
118 .modes = pmx_rs485_0_1_modes,
119 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
120 .enb_on_reset = 1,
121};
122
123static struct pmx_dev_mode pmx_tdm0_modes[] = {
124 {
125 .ids = 0x00,
126 .mask = PMX_MII_MASK,
127 },
128};
129
130struct pmx_dev spear310_pmx_tdm0 = {
131 .name = "tdm0",
132 .modes = pmx_tdm0_modes,
133 .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
134 .enb_on_reset = 1,
135};
136
137/* pmx driver structure */
138static struct pmx_driver pmx_driver = {
139 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
140};
141
142/* spear3xx shared irq */ 25/* spear3xx shared irq */
143static struct shirq_dev_config shirq_ras1_config[] = { 26static struct shirq_dev_config shirq_ras1_config[] = {
144 { 27 {
@@ -255,17 +138,247 @@ static struct spear_shirq shirq_intrcomm_ras = {
255 }, 138 },
256}; 139};
257 140
258/* Add spear310 specific devices here */ 141/* DMAC platform data's slave info */
142struct pl08x_channel_data spear310_dma_info[] = {
143 {
144 .bus_id = "uart0_rx",
145 .min_signal = 2,
146 .max_signal = 2,
147 .muxval = 0,
148 .cctl = 0,
149 .periph_buses = PL08X_AHB1,
150 }, {
151 .bus_id = "uart0_tx",
152 .min_signal = 3,
153 .max_signal = 3,
154 .muxval = 0,
155 .cctl = 0,
156 .periph_buses = PL08X_AHB1,
157 }, {
158 .bus_id = "ssp0_rx",
159 .min_signal = 8,
160 .max_signal = 8,
161 .muxval = 0,
162 .cctl = 0,
163 .periph_buses = PL08X_AHB1,
164 }, {
165 .bus_id = "ssp0_tx",
166 .min_signal = 9,
167 .max_signal = 9,
168 .muxval = 0,
169 .cctl = 0,
170 .periph_buses = PL08X_AHB1,
171 }, {
172 .bus_id = "i2c_rx",
173 .min_signal = 10,
174 .max_signal = 10,
175 .muxval = 0,
176 .cctl = 0,
177 .periph_buses = PL08X_AHB1,
178 }, {
179 .bus_id = "i2c_tx",
180 .min_signal = 11,
181 .max_signal = 11,
182 .muxval = 0,
183 .cctl = 0,
184 .periph_buses = PL08X_AHB1,
185 }, {
186 .bus_id = "irda",
187 .min_signal = 12,
188 .max_signal = 12,
189 .muxval = 0,
190 .cctl = 0,
191 .periph_buses = PL08X_AHB1,
192 }, {
193 .bus_id = "adc",
194 .min_signal = 13,
195 .max_signal = 13,
196 .muxval = 0,
197 .cctl = 0,
198 .periph_buses = PL08X_AHB1,
199 }, {
200 .bus_id = "to_jpeg",
201 .min_signal = 14,
202 .max_signal = 14,
203 .muxval = 0,
204 .cctl = 0,
205 .periph_buses = PL08X_AHB1,
206 }, {
207 .bus_id = "from_jpeg",
208 .min_signal = 15,
209 .max_signal = 15,
210 .muxval = 0,
211 .cctl = 0,
212 .periph_buses = PL08X_AHB1,
213 }, {
214 .bus_id = "uart1_rx",
215 .min_signal = 0,
216 .max_signal = 0,
217 .muxval = 1,
218 .cctl = 0,
219 .periph_buses = PL08X_AHB1,
220 }, {
221 .bus_id = "uart1_tx",
222 .min_signal = 1,
223 .max_signal = 1,
224 .muxval = 1,
225 .cctl = 0,
226 .periph_buses = PL08X_AHB1,
227 }, {
228 .bus_id = "uart2_rx",
229 .min_signal = 2,
230 .max_signal = 2,
231 .muxval = 1,
232 .cctl = 0,
233 .periph_buses = PL08X_AHB1,
234 }, {
235 .bus_id = "uart2_tx",
236 .min_signal = 3,
237 .max_signal = 3,
238 .muxval = 1,
239 .cctl = 0,
240 .periph_buses = PL08X_AHB1,
241 }, {
242 .bus_id = "uart3_rx",
243 .min_signal = 4,
244 .max_signal = 4,
245 .muxval = 1,
246 .cctl = 0,
247 .periph_buses = PL08X_AHB1,
248 }, {
249 .bus_id = "uart3_tx",
250 .min_signal = 5,
251 .max_signal = 5,
252 .muxval = 1,
253 .cctl = 0,
254 .periph_buses = PL08X_AHB1,
255 }, {
256 .bus_id = "uart4_rx",
257 .min_signal = 6,
258 .max_signal = 6,
259 .muxval = 1,
260 .cctl = 0,
261 .periph_buses = PL08X_AHB1,
262 }, {
263 .bus_id = "uart4_tx",
264 .min_signal = 7,
265 .max_signal = 7,
266 .muxval = 1,
267 .cctl = 0,
268 .periph_buses = PL08X_AHB1,
269 }, {
270 .bus_id = "uart5_rx",
271 .min_signal = 8,
272 .max_signal = 8,
273 .muxval = 1,
274 .cctl = 0,
275 .periph_buses = PL08X_AHB1,
276 }, {
277 .bus_id = "uart5_tx",
278 .min_signal = 9,
279 .max_signal = 9,
280 .muxval = 1,
281 .cctl = 0,
282 .periph_buses = PL08X_AHB1,
283 }, {
284 .bus_id = "ras5_rx",
285 .min_signal = 10,
286 .max_signal = 10,
287 .muxval = 1,
288 .cctl = 0,
289 .periph_buses = PL08X_AHB1,
290 }, {
291 .bus_id = "ras5_tx",
292 .min_signal = 11,
293 .max_signal = 11,
294 .muxval = 1,
295 .cctl = 0,
296 .periph_buses = PL08X_AHB1,
297 }, {
298 .bus_id = "ras6_rx",
299 .min_signal = 12,
300 .max_signal = 12,
301 .muxval = 1,
302 .cctl = 0,
303 .periph_buses = PL08X_AHB1,
304 }, {
305 .bus_id = "ras6_tx",
306 .min_signal = 13,
307 .max_signal = 13,
308 .muxval = 1,
309 .cctl = 0,
310 .periph_buses = PL08X_AHB1,
311 }, {
312 .bus_id = "ras7_rx",
313 .min_signal = 14,
314 .max_signal = 14,
315 .muxval = 1,
316 .cctl = 0,
317 .periph_buses = PL08X_AHB1,
318 }, {
319 .bus_id = "ras7_tx",
320 .min_signal = 15,
321 .max_signal = 15,
322 .muxval = 1,
323 .cctl = 0,
324 .periph_buses = PL08X_AHB1,
325 },
326};
259 327
260/* spear310 routines */ 328/* uart devices plat data */
261void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 329static struct amba_pl011_data spear310_uart_data[] = {
262 u8 pmx_dev_count) 330 {
331 .dma_filter = pl08x_filter_id,
332 .dma_tx_param = "uart1_tx",
333 .dma_rx_param = "uart1_rx",
334 }, {
335 .dma_filter = pl08x_filter_id,
336 .dma_tx_param = "uart2_tx",
337 .dma_rx_param = "uart2_rx",
338 }, {
339 .dma_filter = pl08x_filter_id,
340 .dma_tx_param = "uart3_tx",
341 .dma_rx_param = "uart3_rx",
342 }, {
343 .dma_filter = pl08x_filter_id,
344 .dma_tx_param = "uart4_tx",
345 .dma_rx_param = "uart4_rx",
346 }, {
347 .dma_filter = pl08x_filter_id,
348 .dma_tx_param = "uart5_tx",
349 .dma_rx_param = "uart5_rx",
350 },
351};
352
353/* Add SPEAr310 auxdata to pass platform data */
354static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
355 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
356 &pl022_plat_data),
357 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
358 &pl080_plat_data),
359 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
360 &spear310_uart_data[0]),
361 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
362 &spear310_uart_data[1]),
363 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
364 &spear310_uart_data[2]),
365 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
366 &spear310_uart_data[3]),
367 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
368 &spear310_uart_data[4]),
369 {}
370};
371
372static void __init spear310_dt_init(void)
263{ 373{
264 void __iomem *base; 374 void __iomem *base;
265 int ret = 0; 375 int ret;
266 376
267 /* call spear3xx family common init function */ 377 pl080_plat_data.slave_channels = spear310_dma_info;
268 spear3xx_init(); 378 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
379
380 of_platform_populate(NULL, of_default_bus_match_table,
381 spear310_auxdata_lookup, NULL);
269 382
270 /* shared irq registration */ 383 /* shared irq registration */
271 base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K); 384 base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -274,35 +387,46 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
274 shirq_ras1.regs.base = base; 387 shirq_ras1.regs.base = base;
275 ret = spear_shirq_register(&shirq_ras1); 388 ret = spear_shirq_register(&shirq_ras1);
276 if (ret) 389 if (ret)
277 printk(KERN_ERR "Error registering Shared IRQ 1\n"); 390 pr_err("Error registering Shared IRQ 1\n");
278 391
279 /* shirq 2 */ 392 /* shirq 2 */
280 shirq_ras2.regs.base = base; 393 shirq_ras2.regs.base = base;
281 ret = spear_shirq_register(&shirq_ras2); 394 ret = spear_shirq_register(&shirq_ras2);
282 if (ret) 395 if (ret)
283 printk(KERN_ERR "Error registering Shared IRQ 2\n"); 396 pr_err("Error registering Shared IRQ 2\n");
284 397
285 /* shirq 3 */ 398 /* shirq 3 */
286 shirq_ras3.regs.base = base; 399 shirq_ras3.regs.base = base;
287 ret = spear_shirq_register(&shirq_ras3); 400 ret = spear_shirq_register(&shirq_ras3);
288 if (ret) 401 if (ret)
289 printk(KERN_ERR "Error registering Shared IRQ 3\n"); 402 pr_err("Error registering Shared IRQ 3\n");
290 403
291 /* shirq 4 */ 404 /* shirq 4 */
292 shirq_intrcomm_ras.regs.base = base; 405 shirq_intrcomm_ras.regs.base = base;
293 ret = spear_shirq_register(&shirq_intrcomm_ras); 406 ret = spear_shirq_register(&shirq_intrcomm_ras);
294 if (ret) 407 if (ret)
295 printk(KERN_ERR "Error registering Shared IRQ 4\n"); 408 pr_err("Error registering Shared IRQ 4\n");
296 } 409 }
410}
297 411
298 /* pmx initialization */ 412static const char * const spear310_dt_board_compat[] = {
299 pmx_driver.base = base; 413 "st,spear310",
300 pmx_driver.mode = pmx_mode; 414 "st,spear310-evb",
301 pmx_driver.devs = pmx_devs; 415 NULL,
302 pmx_driver.devs_count = pmx_dev_count; 416};
303 417
304 ret = pmx_register(&pmx_driver); 418static void __init spear310_map_io(void)
305 if (ret) 419{
306 printk(KERN_ERR "padmux: registration failed. err no: %d\n", 420 spear3xx_map_io();
307 ret); 421 spear310_clk_init();
308} 422}
423
424DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
425 .map_io = spear310_map_io,
426 .init_irq = spear3xx_dt_init_irq,
427 .handle_irq = vic_handle_irq,
428 .timer = &spear3xx_timer,
429 .init_machine = spear310_dt_init,
430 .restart = spear_restart,
431 .dt_compat = spear310_dt_board_compat,
432MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c4993f65..00000000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/spear310_evb.c
3 *
4 * SPEAr310 evaluation board source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17#include <mach/generic.h>
18#include <mach/hardware.h>
19
20/* padmux devices to enable */
21static struct pmx_dev *pmx_devs[] = {
22 /* spear3xx specific devices */
23 &spear3xx_pmx_i2c,
24 &spear3xx_pmx_ssp,
25 &spear3xx_pmx_gpio_pin0,
26 &spear3xx_pmx_gpio_pin1,
27 &spear3xx_pmx_gpio_pin2,
28 &spear3xx_pmx_gpio_pin3,
29 &spear3xx_pmx_gpio_pin4,
30 &spear3xx_pmx_gpio_pin5,
31 &spear3xx_pmx_uart0,
32
33 /* spear310 specific devices */
34 &spear310_pmx_emi_cs_0_1_4_5,
35 &spear310_pmx_emi_cs_2_3,
36 &spear310_pmx_uart1,
37 &spear310_pmx_uart2,
38 &spear310_pmx_uart3_4_5,
39 &spear310_pmx_fsmc,
40 &spear310_pmx_rs485_0_1,
41 &spear310_pmx_tdm0,
42};
43
44static struct amba_device *amba_devs[] __initdata = {
45 /* spear3xx specific devices */
46 &spear3xx_gpio_device,
47 &spear3xx_uart_device,
48
49 /* spear310 specific devices */
50};
51
52static struct platform_device *plat_devs[] __initdata = {
53 /* spear3xx specific devices */
54
55 /* spear310 specific devices */
56};
57
58static void __init spear310_evb_init(void)
59{
60 unsigned int i;
61
62 /* call spear310 machine init function */
63 spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
64
65 /* Add Platform Devices */
66 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
67
68 /* Add Amba Devices */
69 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
70 amba_device_register(amba_devs[i], &iomem_resource);
71}
72
73MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
74 .atag_offset = 0x100,
75 .map_io = spear3xx_map_io,
76 .init_irq = spear3xx_init_irq,
77 .handle_irq = vic_handle_irq,
78 .timer = &spear3xx_timer,
79 .init_machine = spear310_evb_init,
80 .restart = spear_restart,
81MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf199612..4812c692ca3 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,387 +3,26 @@
3 * 3 *
4 * SPEAr320 machine source file 4 * SPEAr320 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/ptrace.h> 14#define pr_fmt(fmt) "SPEAr320: " fmt
15#include <asm/irq.h> 15
16#include <linux/amba/pl022.h>
17#include <linux/amba/pl08x.h>
18#include <linux/amba/serial.h>
19#include <linux/of_platform.h>
20#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h>
16#include <plat/shirq.h> 22#include <plat/shirq.h>
17#include <mach/generic.h> 23#include <mach/generic.h>
18#include <mach/hardware.h> 24#include <mach/hardware.h>
19 25
20/* pad multiplexing support */
21/* muxing registers */
22#define PAD_MUX_CONFIG_REG 0x0C
23#define MODE_CONFIG_REG 0x10
24
25/* modes */
26#define AUTO_NET_SMII_MODE (1 << 0)
27#define AUTO_NET_MII_MODE (1 << 1)
28#define AUTO_EXP_MODE (1 << 2)
29#define SMALL_PRINTERS_MODE (1 << 3)
30#define ALL_MODES 0xF
31
32struct pmx_mode spear320_auto_net_smii_mode = {
33 .id = AUTO_NET_SMII_MODE,
34 .name = "Automation Networking SMII Mode",
35 .mask = 0x00,
36};
37
38struct pmx_mode spear320_auto_net_mii_mode = {
39 .id = AUTO_NET_MII_MODE,
40 .name = "Automation Networking MII Mode",
41 .mask = 0x01,
42};
43
44struct pmx_mode spear320_auto_exp_mode = {
45 .id = AUTO_EXP_MODE,
46 .name = "Automation Expanded Mode",
47 .mask = 0x02,
48};
49
50struct pmx_mode spear320_small_printers_mode = {
51 .id = SMALL_PRINTERS_MODE,
52 .name = "Small Printers Mode",
53 .mask = 0x03,
54};
55
56/* devices */
57static struct pmx_dev_mode pmx_clcd_modes[] = {
58 {
59 .ids = AUTO_NET_SMII_MODE,
60 .mask = 0x0,
61 },
62};
63
64struct pmx_dev spear320_pmx_clcd = {
65 .name = "clcd",
66 .modes = pmx_clcd_modes,
67 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
68 .enb_on_reset = 1,
69};
70
71static struct pmx_dev_mode pmx_emi_modes[] = {
72 {
73 .ids = AUTO_EXP_MODE,
74 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
75 },
76};
77
78struct pmx_dev spear320_pmx_emi = {
79 .name = "emi",
80 .modes = pmx_emi_modes,
81 .mode_count = ARRAY_SIZE(pmx_emi_modes),
82 .enb_on_reset = 1,
83};
84
85static struct pmx_dev_mode pmx_fsmc_modes[] = {
86 {
87 .ids = ALL_MODES,
88 .mask = 0x0,
89 },
90};
91
92struct pmx_dev spear320_pmx_fsmc = {
93 .name = "fsmc",
94 .modes = pmx_fsmc_modes,
95 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
96 .enb_on_reset = 1,
97};
98
99static struct pmx_dev_mode pmx_spp_modes[] = {
100 {
101 .ids = SMALL_PRINTERS_MODE,
102 .mask = 0x0,
103 },
104};
105
106struct pmx_dev spear320_pmx_spp = {
107 .name = "spp",
108 .modes = pmx_spp_modes,
109 .mode_count = ARRAY_SIZE(pmx_spp_modes),
110 .enb_on_reset = 1,
111};
112
113static struct pmx_dev_mode pmx_sdhci_modes[] = {
114 {
115 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
116 SMALL_PRINTERS_MODE,
117 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
118 },
119};
120
121struct pmx_dev spear320_pmx_sdhci = {
122 .name = "sdhci",
123 .modes = pmx_sdhci_modes,
124 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
125 .enb_on_reset = 1,
126};
127
128static struct pmx_dev_mode pmx_i2s_modes[] = {
129 {
130 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
131 .mask = PMX_UART0_MODEM_MASK,
132 },
133};
134
135struct pmx_dev spear320_pmx_i2s = {
136 .name = "i2s",
137 .modes = pmx_i2s_modes,
138 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
139 .enb_on_reset = 1,
140};
141
142static struct pmx_dev_mode pmx_uart1_modes[] = {
143 {
144 .ids = ALL_MODES,
145 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
146 },
147};
148
149struct pmx_dev spear320_pmx_uart1 = {
150 .name = "uart1",
151 .modes = pmx_uart1_modes,
152 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
153 .enb_on_reset = 1,
154};
155
156static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
157 {
158 .ids = AUTO_EXP_MODE,
159 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
160 PMX_SSP_CS_MASK,
161 }, {
162 .ids = SMALL_PRINTERS_MODE,
163 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
164 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
165 },
166};
167
168struct pmx_dev spear320_pmx_uart1_modem = {
169 .name = "uart1_modem",
170 .modes = pmx_uart1_modem_modes,
171 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
172 .enb_on_reset = 1,
173};
174
175static struct pmx_dev_mode pmx_uart2_modes[] = {
176 {
177 .ids = ALL_MODES,
178 .mask = PMX_FIRDA_MASK,
179 },
180};
181
182struct pmx_dev spear320_pmx_uart2 = {
183 .name = "uart2",
184 .modes = pmx_uart2_modes,
185 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
186 .enb_on_reset = 1,
187};
188
189static struct pmx_dev_mode pmx_touchscreen_modes[] = {
190 {
191 .ids = AUTO_NET_SMII_MODE,
192 .mask = PMX_SSP_CS_MASK,
193 },
194};
195
196struct pmx_dev spear320_pmx_touchscreen = {
197 .name = "touchscreen",
198 .modes = pmx_touchscreen_modes,
199 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
200 .enb_on_reset = 1,
201};
202
203static struct pmx_dev_mode pmx_can_modes[] = {
204 {
205 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
206 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
207 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
208 },
209};
210
211struct pmx_dev spear320_pmx_can = {
212 .name = "can",
213 .modes = pmx_can_modes,
214 .mode_count = ARRAY_SIZE(pmx_can_modes),
215 .enb_on_reset = 1,
216};
217
218static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
219 {
220 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
221 .mask = PMX_SSP_CS_MASK,
222 },
223};
224
225struct pmx_dev spear320_pmx_sdhci_led = {
226 .name = "sdhci_led",
227 .modes = pmx_sdhci_led_modes,
228 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
229 .enb_on_reset = 1,
230};
231
232static struct pmx_dev_mode pmx_pwm0_modes[] = {
233 {
234 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
235 .mask = PMX_UART0_MODEM_MASK,
236 }, {
237 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
238 .mask = PMX_MII_MASK,
239 },
240};
241
242struct pmx_dev spear320_pmx_pwm0 = {
243 .name = "pwm0",
244 .modes = pmx_pwm0_modes,
245 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
246 .enb_on_reset = 1,
247};
248
249static struct pmx_dev_mode pmx_pwm1_modes[] = {
250 {
251 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
252 .mask = PMX_UART0_MODEM_MASK,
253 }, {
254 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
255 .mask = PMX_MII_MASK,
256 },
257};
258
259struct pmx_dev spear320_pmx_pwm1 = {
260 .name = "pwm1",
261 .modes = pmx_pwm1_modes,
262 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
263 .enb_on_reset = 1,
264};
265
266static struct pmx_dev_mode pmx_pwm2_modes[] = {
267 {
268 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
269 .mask = PMX_SSP_CS_MASK,
270 }, {
271 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
272 .mask = PMX_MII_MASK,
273 },
274};
275
276struct pmx_dev spear320_pmx_pwm2 = {
277 .name = "pwm2",
278 .modes = pmx_pwm2_modes,
279 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
280 .enb_on_reset = 1,
281};
282
283static struct pmx_dev_mode pmx_pwm3_modes[] = {
284 {
285 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
286 .mask = PMX_MII_MASK,
287 },
288};
289
290struct pmx_dev spear320_pmx_pwm3 = {
291 .name = "pwm3",
292 .modes = pmx_pwm3_modes,
293 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
294 .enb_on_reset = 1,
295};
296
297static struct pmx_dev_mode pmx_ssp1_modes[] = {
298 {
299 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
300 .mask = PMX_MII_MASK,
301 },
302};
303
304struct pmx_dev spear320_pmx_ssp1 = {
305 .name = "ssp1",
306 .modes = pmx_ssp1_modes,
307 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
308 .enb_on_reset = 1,
309};
310
311static struct pmx_dev_mode pmx_ssp2_modes[] = {
312 {
313 .ids = AUTO_NET_SMII_MODE,
314 .mask = PMX_MII_MASK,
315 },
316};
317
318struct pmx_dev spear320_pmx_ssp2 = {
319 .name = "ssp2",
320 .modes = pmx_ssp2_modes,
321 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
322 .enb_on_reset = 1,
323};
324
325static struct pmx_dev_mode pmx_mii1_modes[] = {
326 {
327 .ids = AUTO_NET_MII_MODE,
328 .mask = 0x0,
329 },
330};
331
332struct pmx_dev spear320_pmx_mii1 = {
333 .name = "mii1",
334 .modes = pmx_mii1_modes,
335 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
336 .enb_on_reset = 1,
337};
338
339static struct pmx_dev_mode pmx_smii0_modes[] = {
340 {
341 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
342 .mask = PMX_MII_MASK,
343 },
344};
345
346struct pmx_dev spear320_pmx_smii0 = {
347 .name = "smii0",
348 .modes = pmx_smii0_modes,
349 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
350 .enb_on_reset = 1,
351};
352
353static struct pmx_dev_mode pmx_smii1_modes[] = {
354 {
355 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
356 .mask = PMX_MII_MASK,
357 },
358};
359
360struct pmx_dev spear320_pmx_smii1 = {
361 .name = "smii1",
362 .modes = pmx_smii1_modes,
363 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
364 .enb_on_reset = 1,
365};
366
367static struct pmx_dev_mode pmx_i2c1_modes[] = {
368 {
369 .ids = AUTO_EXP_MODE,
370 .mask = 0x0,
371 },
372};
373
374struct pmx_dev spear320_pmx_i2c1 = {
375 .name = "i2c1",
376 .modes = pmx_i2c1_modes,
377 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
378 .enb_on_reset = 1,
379};
380
381/* pmx driver structure */
382static struct pmx_driver pmx_driver = {
383 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
384 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
385};
386
387/* spear3xx shared irq */ 26/* spear3xx shared irq */
388static struct shirq_dev_config shirq_ras1_config[] = { 27static struct shirq_dev_config shirq_ras1_config[] = {
389 { 28 {
@@ -508,17 +147,250 @@ static struct spear_shirq shirq_intrcomm_ras = {
508 }, 147 },
509}; 148};
510 149
511/* Add spear320 specific devices here */ 150/* DMAC platform data's slave info */
151struct pl08x_channel_data spear320_dma_info[] = {
152 {
153 .bus_id = "uart0_rx",
154 .min_signal = 2,
155 .max_signal = 2,
156 .muxval = 0,
157 .cctl = 0,
158 .periph_buses = PL08X_AHB1,
159 }, {
160 .bus_id = "uart0_tx",
161 .min_signal = 3,
162 .max_signal = 3,
163 .muxval = 0,
164 .cctl = 0,
165 .periph_buses = PL08X_AHB1,
166 }, {
167 .bus_id = "ssp0_rx",
168 .min_signal = 8,
169 .max_signal = 8,
170 .muxval = 0,
171 .cctl = 0,
172 .periph_buses = PL08X_AHB1,
173 }, {
174 .bus_id = "ssp0_tx",
175 .min_signal = 9,
176 .max_signal = 9,
177 .muxval = 0,
178 .cctl = 0,
179 .periph_buses = PL08X_AHB1,
180 }, {
181 .bus_id = "i2c0_rx",
182 .min_signal = 10,
183 .max_signal = 10,
184 .muxval = 0,
185 .cctl = 0,
186 .periph_buses = PL08X_AHB1,
187 }, {
188 .bus_id = "i2c0_tx",
189 .min_signal = 11,
190 .max_signal = 11,
191 .muxval = 0,
192 .cctl = 0,
193 .periph_buses = PL08X_AHB1,
194 }, {
195 .bus_id = "irda",
196 .min_signal = 12,
197 .max_signal = 12,
198 .muxval = 0,
199 .cctl = 0,
200 .periph_buses = PL08X_AHB1,
201 }, {
202 .bus_id = "adc",
203 .min_signal = 13,
204 .max_signal = 13,
205 .muxval = 0,
206 .cctl = 0,
207 .periph_buses = PL08X_AHB1,
208 }, {
209 .bus_id = "to_jpeg",
210 .min_signal = 14,
211 .max_signal = 14,
212 .muxval = 0,
213 .cctl = 0,
214 .periph_buses = PL08X_AHB1,
215 }, {
216 .bus_id = "from_jpeg",
217 .min_signal = 15,
218 .max_signal = 15,
219 .muxval = 0,
220 .cctl = 0,
221 .periph_buses = PL08X_AHB1,
222 }, {
223 .bus_id = "ssp1_rx",
224 .min_signal = 0,
225 .max_signal = 0,
226 .muxval = 1,
227 .cctl = 0,
228 .periph_buses = PL08X_AHB2,
229 }, {
230 .bus_id = "ssp1_tx",
231 .min_signal = 1,
232 .max_signal = 1,
233 .muxval = 1,
234 .cctl = 0,
235 .periph_buses = PL08X_AHB2,
236 }, {
237 .bus_id = "ssp2_rx",
238 .min_signal = 2,
239 .max_signal = 2,
240 .muxval = 1,
241 .cctl = 0,
242 .periph_buses = PL08X_AHB2,
243 }, {
244 .bus_id = "ssp2_tx",
245 .min_signal = 3,
246 .max_signal = 3,
247 .muxval = 1,
248 .cctl = 0,
249 .periph_buses = PL08X_AHB2,
250 }, {
251 .bus_id = "uart1_rx",
252 .min_signal = 4,
253 .max_signal = 4,
254 .muxval = 1,
255 .cctl = 0,
256 .periph_buses = PL08X_AHB2,
257 }, {
258 .bus_id = "uart1_tx",
259 .min_signal = 5,
260 .max_signal = 5,
261 .muxval = 1,
262 .cctl = 0,
263 .periph_buses = PL08X_AHB2,
264 }, {
265 .bus_id = "uart2_rx",
266 .min_signal = 6,
267 .max_signal = 6,
268 .muxval = 1,
269 .cctl = 0,
270 .periph_buses = PL08X_AHB2,
271 }, {
272 .bus_id = "uart2_tx",
273 .min_signal = 7,
274 .max_signal = 7,
275 .muxval = 1,
276 .cctl = 0,
277 .periph_buses = PL08X_AHB2,
278 }, {
279 .bus_id = "i2c1_rx",
280 .min_signal = 8,
281 .max_signal = 8,
282 .muxval = 1,
283 .cctl = 0,
284 .periph_buses = PL08X_AHB2,
285 }, {
286 .bus_id = "i2c1_tx",
287 .min_signal = 9,
288 .max_signal = 9,
289 .muxval = 1,
290 .cctl = 0,
291 .periph_buses = PL08X_AHB2,
292 }, {
293 .bus_id = "i2c2_rx",
294 .min_signal = 10,
295 .max_signal = 10,
296 .muxval = 1,
297 .cctl = 0,
298 .periph_buses = PL08X_AHB2,
299 }, {
300 .bus_id = "i2c2_tx",
301 .min_signal = 11,
302 .max_signal = 11,
303 .muxval = 1,
304 .cctl = 0,
305 .periph_buses = PL08X_AHB2,
306 }, {
307 .bus_id = "i2s_rx",
308 .min_signal = 12,
309 .max_signal = 12,
310 .muxval = 1,
311 .cctl = 0,
312 .periph_buses = PL08X_AHB2,
313 }, {
314 .bus_id = "i2s_tx",
315 .min_signal = 13,
316 .max_signal = 13,
317 .muxval = 1,
318 .cctl = 0,
319 .periph_buses = PL08X_AHB2,
320 }, {
321 .bus_id = "rs485_rx",
322 .min_signal = 14,
323 .max_signal = 14,
324 .muxval = 1,
325 .cctl = 0,
326 .periph_buses = PL08X_AHB2,
327 }, {
328 .bus_id = "rs485_tx",
329 .min_signal = 15,
330 .max_signal = 15,
331 .muxval = 1,
332 .cctl = 0,
333 .periph_buses = PL08X_AHB2,
334 },
335};
336
337static struct pl022_ssp_controller spear320_ssp_data[] = {
338 {
339 .bus_id = 1,
340 .enable_dma = 1,
341 .dma_filter = pl08x_filter_id,
342 .dma_tx_param = "ssp1_tx",
343 .dma_rx_param = "ssp1_rx",
344 .num_chipselect = 2,
345 }, {
346 .bus_id = 2,
347 .enable_dma = 1,
348 .dma_filter = pl08x_filter_id,
349 .dma_tx_param = "ssp2_tx",
350 .dma_rx_param = "ssp2_rx",
351 .num_chipselect = 2,
352 }
353};
354
355static struct amba_pl011_data spear320_uart_data[] = {
356 {
357 .dma_filter = pl08x_filter_id,
358 .dma_tx_param = "uart1_tx",
359 .dma_rx_param = "uart1_rx",
360 }, {
361 .dma_filter = pl08x_filter_id,
362 .dma_tx_param = "uart2_tx",
363 .dma_rx_param = "uart2_rx",
364 },
365};
512 366
513/* spear320 routines */ 367/* Add SPEAr310 auxdata to pass platform data */
514void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 368static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
515 u8 pmx_dev_count) 369 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
370 &pl022_plat_data),
371 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
372 &pl080_plat_data),
373 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
374 &spear320_ssp_data[0]),
375 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
376 &spear320_ssp_data[1]),
377 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
378 &spear320_uart_data[0]),
379 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
380 &spear320_uart_data[1]),
381 {}
382};
383
384static void __init spear320_dt_init(void)
516{ 385{
517 void __iomem *base; 386 void __iomem *base;
518 int ret = 0; 387 int ret;
388
389 pl080_plat_data.slave_channels = spear320_dma_info;
390 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
519 391
520 /* call spear3xx family common init function */ 392 of_platform_populate(NULL, of_default_bus_match_table,
521 spear3xx_init(); 393 spear320_auxdata_lookup, NULL);
522 394
523 /* shared irq registration */ 395 /* shared irq registration */
524 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K); 396 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -527,29 +399,40 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
527 shirq_ras1.regs.base = base; 399 shirq_ras1.regs.base = base;
528 ret = spear_shirq_register(&shirq_ras1); 400 ret = spear_shirq_register(&shirq_ras1);
529 if (ret) 401 if (ret)
530 printk(KERN_ERR "Error registering Shared IRQ 1\n"); 402 pr_err("Error registering Shared IRQ 1\n");
531 403
532 /* shirq 3 */ 404 /* shirq 3 */
533 shirq_ras3.regs.base = base; 405 shirq_ras3.regs.base = base;
534 ret = spear_shirq_register(&shirq_ras3); 406 ret = spear_shirq_register(&shirq_ras3);
535 if (ret) 407 if (ret)
536 printk(KERN_ERR "Error registering Shared IRQ 3\n"); 408 pr_err("Error registering Shared IRQ 3\n");
537 409
538 /* shirq 4 */ 410 /* shirq 4 */
539 shirq_intrcomm_ras.regs.base = base; 411 shirq_intrcomm_ras.regs.base = base;
540 ret = spear_shirq_register(&shirq_intrcomm_ras); 412 ret = spear_shirq_register(&shirq_intrcomm_ras);
541 if (ret) 413 if (ret)
542 printk(KERN_ERR "Error registering Shared IRQ 4\n"); 414 pr_err("Error registering Shared IRQ 4\n");
543 } 415 }
416}
544 417
545 /* pmx initialization */ 418static const char * const spear320_dt_board_compat[] = {
546 pmx_driver.base = base; 419 "st,spear320",
547 pmx_driver.mode = pmx_mode; 420 "st,spear320-evb",
548 pmx_driver.devs = pmx_devs; 421 NULL,
549 pmx_driver.devs_count = pmx_dev_count; 422};
550 423
551 ret = pmx_register(&pmx_driver); 424static void __init spear320_map_io(void)
552 if (ret) 425{
553 printk(KERN_ERR "padmux: registration failed. err no: %d\n", 426 spear3xx_map_io();
554 ret); 427 spear320_clk_init();
555} 428}
429
430DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
431 .map_io = spear320_map_io,
432 .init_irq = spear3xx_dt_init_irq,
433 .handle_irq = vic_handle_irq,
434 .timer = &spear3xx_timer,
435 .init_machine = spear320_dt_init,
436 .restart = spear_restart,
437 .dt_compat = spear320_dt_board_compat,
438MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334ab702..00000000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/spear320_evb.c
3 *
4 * SPEAr320 evaluation board source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17#include <mach/generic.h>
18#include <mach/hardware.h>
19
20/* padmux devices to enable */
21static struct pmx_dev *pmx_devs[] = {
22 /* spear3xx specific devices */
23 &spear3xx_pmx_i2c,
24 &spear3xx_pmx_ssp,
25 &spear3xx_pmx_mii,
26 &spear3xx_pmx_uart0,
27
28 /* spear320 specific devices */
29 &spear320_pmx_fsmc,
30 &spear320_pmx_sdhci,
31 &spear320_pmx_i2s,
32 &spear320_pmx_uart1,
33 &spear320_pmx_uart2,
34 &spear320_pmx_can,
35 &spear320_pmx_pwm0,
36 &spear320_pmx_pwm1,
37 &spear320_pmx_pwm2,
38 &spear320_pmx_mii1,
39};
40
41static struct amba_device *amba_devs[] __initdata = {
42 /* spear3xx specific devices */
43 &spear3xx_gpio_device,
44 &spear3xx_uart_device,
45
46 /* spear320 specific devices */
47};
48
49static struct platform_device *plat_devs[] __initdata = {
50 /* spear3xx specific devices */
51
52 /* spear320 specific devices */
53};
54
55static void __init spear320_evb_init(void)
56{
57 unsigned int i;
58
59 /* call spear320 machine init function */
60 spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
61 ARRAY_SIZE(pmx_devs));
62
63 /* Add Platform Devices */
64 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
65
66 /* Add Amba Devices */
67 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
68 amba_device_register(amba_devs[i], &iomem_resource);
69}
70
71MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
72 .atag_offset = 0x100,
73 .map_io = spear3xx_map_io,
74 .init_irq = spear3xx_init_irq,
75 .handle_irq = vic_handle_irq,
76 .timer = &spear3xx_timer,
77 .init_machine = spear320_evb_init,
78 .restart = spear_restart,
79MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c37f20..12bf879a9ef 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,71 +3,78 @@
3 * 3 *
4 * SPEAr3XX machines common source file 4 * SPEAr3XX machines common source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/types.h> 14#define pr_fmt(fmt) "SPEAr3xx: " fmt
15#include <linux/amba/pl061.h> 15
16#include <linux/ptrace.h> 16#include <linux/amba/pl022.h>
17#include <linux/amba/pl08x.h>
18#include <linux/of_irq.h>
17#include <linux/io.h> 19#include <linux/io.h>
20#include <asm/hardware/pl080.h>
18#include <asm/hardware/vic.h> 21#include <asm/hardware/vic.h>
19#include <asm/irq.h> 22#include <plat/pl080.h>
20#include <asm/mach/arch.h>
21#include <mach/generic.h> 23#include <mach/generic.h>
22#include <mach/hardware.h> 24#include <mach/hardware.h>
23 25
24/* Add spear3xx machines common devices here */ 26/* ssp device registration */
25/* gpio device registration */ 27struct pl022_ssp_controller pl022_plat_data = {
26static struct pl061_platform_data gpio_plat_data = { 28 .bus_id = 0,
27 .gpio_base = 0, 29 .enable_dma = 1,
28 .irq_base = SPEAR3XX_GPIO_INT_BASE, 30 .dma_filter = pl08x_filter_id,
31 .dma_tx_param = "ssp0_tx",
32 .dma_rx_param = "ssp0_rx",
33 /*
34 * This is number of spi devices that can be connected to spi. There are
35 * two type of chipselects on which slave devices can work. One is chip
36 * select provided by spi masters other is controlled through external
37 * gpio's. We can't use chipselect provided from spi master (because as
38 * soon as FIFO becomes empty, CS is disabled and transfer ends). So
39 * this number now depends on number of gpios available for spi. each
40 * slave on each master requires a separate gpio pin.
41 */
42 .num_chipselect = 2,
43};
44
45/* dmac device registration */
46struct pl08x_platform_data pl080_plat_data = {
47 .memcpy_channel = {
48 .bus_id = "memcpy",
49 .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
50 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
51 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
52 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
53 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
54 PL080_CONTROL_PROT_SYS),
55 },
56 .lli_buses = PL08X_AHB1,
57 .mem_buses = PL08X_AHB1,
58 .get_signal = pl080_get_signal,
59 .put_signal = pl080_put_signal,
29}; 60};
30 61
31AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE, 62/*
32 {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data); 63 * Following will create 16MB static virtual/physical mappings
33 64 * PHYSICAL VIRTUAL
34/* uart device registration */ 65 * 0xD0000000 0xFD000000
35AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE, 66 * 0xFC000000 0xFC000000
36 {SPEAR3XX_IRQ_UART}, NULL); 67 */
37
38/* Do spear3xx familiy common initialization part here */
39void __init spear3xx_init(void)
40{
41 /* nothing to do for now */
42}
43
44/* This will initialize vic */
45void __init spear3xx_init_irq(void)
46{
47 vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
48}
49
50/* Following will create static virtual/physical mappings */
51struct map_desc spear3xx_io_desc[] __initdata = { 68struct map_desc spear3xx_io_desc[] __initdata = {
52 { 69 {
53 .virtual = VA_SPEAR3XX_ICM1_UART_BASE, 70 .virtual = VA_SPEAR3XX_ICM1_2_BASE,
54 .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE), 71 .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
55 .length = SZ_4K, 72 .length = SZ_16M,
56 .type = MT_DEVICE
57 }, {
58 .virtual = VA_SPEAR3XX_ML1_VIC_BASE,
59 .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
60 .length = SZ_4K,
61 .type = MT_DEVICE 73 .type = MT_DEVICE
62 }, { 74 }, {
63 .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE, 75 .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
64 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE), 76 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
65 .length = SZ_4K, 77 .length = SZ_16M,
66 .type = MT_DEVICE
67 }, {
68 .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
69 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
70 .length = SZ_4K,
71 .type = MT_DEVICE 78 .type = MT_DEVICE
72 }, 79 },
73}; 80};
@@ -76,436 +83,8 @@ struct map_desc spear3xx_io_desc[] __initdata = {
76void __init spear3xx_map_io(void) 83void __init spear3xx_map_io(void)
77{ 84{
78 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); 85 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
79
80 /* This will initialize clock framework */
81 spear3xx_clk_init();
82} 86}
83 87
84/* pad multiplexing support */
85/* devices */
86static struct pmx_dev_mode pmx_firda_modes[] = {
87 {
88 .ids = 0xffffffff,
89 .mask = PMX_FIRDA_MASK,
90 },
91};
92
93struct pmx_dev spear3xx_pmx_firda = {
94 .name = "firda",
95 .modes = pmx_firda_modes,
96 .mode_count = ARRAY_SIZE(pmx_firda_modes),
97 .enb_on_reset = 0,
98};
99
100static struct pmx_dev_mode pmx_i2c_modes[] = {
101 {
102 .ids = 0xffffffff,
103 .mask = PMX_I2C_MASK,
104 },
105};
106
107struct pmx_dev spear3xx_pmx_i2c = {
108 .name = "i2c",
109 .modes = pmx_i2c_modes,
110 .mode_count = ARRAY_SIZE(pmx_i2c_modes),
111 .enb_on_reset = 0,
112};
113
114static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
115 {
116 .ids = 0xffffffff,
117 .mask = PMX_SSP_CS_MASK,
118 },
119};
120
121struct pmx_dev spear3xx_pmx_ssp_cs = {
122 .name = "ssp_chip_selects",
123 .modes = pmx_ssp_cs_modes,
124 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
125 .enb_on_reset = 0,
126};
127
128static struct pmx_dev_mode pmx_ssp_modes[] = {
129 {
130 .ids = 0xffffffff,
131 .mask = PMX_SSP_MASK,
132 },
133};
134
135struct pmx_dev spear3xx_pmx_ssp = {
136 .name = "ssp",
137 .modes = pmx_ssp_modes,
138 .mode_count = ARRAY_SIZE(pmx_ssp_modes),
139 .enb_on_reset = 0,
140};
141
142static struct pmx_dev_mode pmx_mii_modes[] = {
143 {
144 .ids = 0xffffffff,
145 .mask = PMX_MII_MASK,
146 },
147};
148
149struct pmx_dev spear3xx_pmx_mii = {
150 .name = "mii",
151 .modes = pmx_mii_modes,
152 .mode_count = ARRAY_SIZE(pmx_mii_modes),
153 .enb_on_reset = 0,
154};
155
156static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
157 {
158 .ids = 0xffffffff,
159 .mask = PMX_GPIO_PIN0_MASK,
160 },
161};
162
163struct pmx_dev spear3xx_pmx_gpio_pin0 = {
164 .name = "gpio_pin0",
165 .modes = pmx_gpio_pin0_modes,
166 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
167 .enb_on_reset = 0,
168};
169
170static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
171 {
172 .ids = 0xffffffff,
173 .mask = PMX_GPIO_PIN1_MASK,
174 },
175};
176
177struct pmx_dev spear3xx_pmx_gpio_pin1 = {
178 .name = "gpio_pin1",
179 .modes = pmx_gpio_pin1_modes,
180 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
181 .enb_on_reset = 0,
182};
183
184static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
185 {
186 .ids = 0xffffffff,
187 .mask = PMX_GPIO_PIN2_MASK,
188 },
189};
190
191struct pmx_dev spear3xx_pmx_gpio_pin2 = {
192 .name = "gpio_pin2",
193 .modes = pmx_gpio_pin2_modes,
194 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
195 .enb_on_reset = 0,
196};
197
198static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
199 {
200 .ids = 0xffffffff,
201 .mask = PMX_GPIO_PIN3_MASK,
202 },
203};
204
205struct pmx_dev spear3xx_pmx_gpio_pin3 = {
206 .name = "gpio_pin3",
207 .modes = pmx_gpio_pin3_modes,
208 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
209 .enb_on_reset = 0,
210};
211
212static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
213 {
214 .ids = 0xffffffff,
215 .mask = PMX_GPIO_PIN4_MASK,
216 },
217};
218
219struct pmx_dev spear3xx_pmx_gpio_pin4 = {
220 .name = "gpio_pin4",
221 .modes = pmx_gpio_pin4_modes,
222 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
223 .enb_on_reset = 0,
224};
225
226static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
227 {
228 .ids = 0xffffffff,
229 .mask = PMX_GPIO_PIN5_MASK,
230 },
231};
232
233struct pmx_dev spear3xx_pmx_gpio_pin5 = {
234 .name = "gpio_pin5",
235 .modes = pmx_gpio_pin5_modes,
236 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
237 .enb_on_reset = 0,
238};
239
240static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
241 {
242 .ids = 0xffffffff,
243 .mask = PMX_UART0_MODEM_MASK,
244 },
245};
246
247struct pmx_dev spear3xx_pmx_uart0_modem = {
248 .name = "uart0_modem",
249 .modes = pmx_uart0_modem_modes,
250 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
251 .enb_on_reset = 0,
252};
253
254static struct pmx_dev_mode pmx_uart0_modes[] = {
255 {
256 .ids = 0xffffffff,
257 .mask = PMX_UART0_MASK,
258 },
259};
260
261struct pmx_dev spear3xx_pmx_uart0 = {
262 .name = "uart0",
263 .modes = pmx_uart0_modes,
264 .mode_count = ARRAY_SIZE(pmx_uart0_modes),
265 .enb_on_reset = 0,
266};
267
268static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
269 {
270 .ids = 0xffffffff,
271 .mask = PMX_TIMER_3_4_MASK,
272 },
273};
274
275struct pmx_dev spear3xx_pmx_timer_3_4 = {
276 .name = "timer_3_4",
277 .modes = pmx_timer_3_4_modes,
278 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
279 .enb_on_reset = 0,
280};
281
282static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
283 {
284 .ids = 0xffffffff,
285 .mask = PMX_TIMER_1_2_MASK,
286 },
287};
288
289struct pmx_dev spear3xx_pmx_timer_1_2 = {
290 .name = "timer_1_2",
291 .modes = pmx_timer_1_2_modes,
292 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
293 .enb_on_reset = 0,
294};
295
296#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
297/* plgpios devices */
298static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
299 {
300 .ids = 0x00,
301 .mask = PMX_FIRDA_MASK,
302 },
303};
304
305struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
306 .name = "plgpio 0 and 1",
307 .modes = pmx_plgpio_0_1_modes,
308 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
309 .enb_on_reset = 1,
310};
311
312static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
313 {
314 .ids = 0x00,
315 .mask = PMX_UART0_MASK,
316 },
317};
318
319struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
320 .name = "plgpio 2 and 3",
321 .modes = pmx_plgpio_2_3_modes,
322 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
323 .enb_on_reset = 1,
324};
325
326static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
327 {
328 .ids = 0x00,
329 .mask = PMX_I2C_MASK,
330 },
331};
332
333struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
334 .name = "plgpio 4 and 5",
335 .modes = pmx_plgpio_4_5_modes,
336 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
337 .enb_on_reset = 1,
338};
339
340static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
341 {
342 .ids = 0x00,
343 .mask = PMX_SSP_MASK,
344 },
345};
346
347struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
348 .name = "plgpio 6 to 9",
349 .modes = pmx_plgpio_6_9_modes,
350 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
351 .enb_on_reset = 1,
352};
353
354static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
355 {
356 .ids = 0x00,
357 .mask = PMX_MII_MASK,
358 },
359};
360
361struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
362 .name = "plgpio 10 to 27",
363 .modes = pmx_plgpio_10_27_modes,
364 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
365 .enb_on_reset = 1,
366};
367
368static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
369 {
370 .ids = 0x00,
371 .mask = PMX_GPIO_PIN0_MASK,
372 },
373};
374
375struct pmx_dev spear3xx_pmx_plgpio_28 = {
376 .name = "plgpio 28",
377 .modes = pmx_plgpio_28_modes,
378 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
379 .enb_on_reset = 1,
380};
381
382static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
383 {
384 .ids = 0x00,
385 .mask = PMX_GPIO_PIN1_MASK,
386 },
387};
388
389struct pmx_dev spear3xx_pmx_plgpio_29 = {
390 .name = "plgpio 29",
391 .modes = pmx_plgpio_29_modes,
392 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
393 .enb_on_reset = 1,
394};
395
396static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
397 {
398 .ids = 0x00,
399 .mask = PMX_GPIO_PIN2_MASK,
400 },
401};
402
403struct pmx_dev spear3xx_pmx_plgpio_30 = {
404 .name = "plgpio 30",
405 .modes = pmx_plgpio_30_modes,
406 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
407 .enb_on_reset = 1,
408};
409
410static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
411 {
412 .ids = 0x00,
413 .mask = PMX_GPIO_PIN3_MASK,
414 },
415};
416
417struct pmx_dev spear3xx_pmx_plgpio_31 = {
418 .name = "plgpio 31",
419 .modes = pmx_plgpio_31_modes,
420 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
421 .enb_on_reset = 1,
422};
423
424static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
425 {
426 .ids = 0x00,
427 .mask = PMX_GPIO_PIN4_MASK,
428 },
429};
430
431struct pmx_dev spear3xx_pmx_plgpio_32 = {
432 .name = "plgpio 32",
433 .modes = pmx_plgpio_32_modes,
434 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
435 .enb_on_reset = 1,
436};
437
438static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
439 {
440 .ids = 0x00,
441 .mask = PMX_GPIO_PIN5_MASK,
442 },
443};
444
445struct pmx_dev spear3xx_pmx_plgpio_33 = {
446 .name = "plgpio 33",
447 .modes = pmx_plgpio_33_modes,
448 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
449 .enb_on_reset = 1,
450};
451
452static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
453 {
454 .ids = 0x00,
455 .mask = PMX_SSP_CS_MASK,
456 },
457};
458
459struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
460 .name = "plgpio 34 to 36",
461 .modes = pmx_plgpio_34_36_modes,
462 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
463 .enb_on_reset = 1,
464};
465
466static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
467 {
468 .ids = 0x00,
469 .mask = PMX_UART0_MODEM_MASK,
470 },
471};
472
473struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
474 .name = "plgpio 37 to 42",
475 .modes = pmx_plgpio_37_42_modes,
476 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
477 .enb_on_reset = 1,
478};
479
480static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
481 {
482 .ids = 0x00,
483 .mask = PMX_TIMER_1_2_MASK,
484 },
485};
486
487struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
488 .name = "plgpio 43, 44, 47 and 48",
489 .modes = pmx_plgpio_43_44_47_48_modes,
490 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
491 .enb_on_reset = 1,
492};
493
494static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
495 {
496 .ids = 0x00,
497 .mask = PMX_TIMER_3_4_MASK,
498 },
499};
500
501struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
502 .name = "plgpio 45, 46, 49 and 50",
503 .modes = pmx_plgpio_45_46_49_50_modes,
504 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
505 .enb_on_reset = 1,
506};
507#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
508
509static void __init spear3xx_timer_init(void) 88static void __init spear3xx_timer_init(void)
510{ 89{
511 char pclk_name[] = "pll3_48m_clk"; 90 char pclk_name[] = "pll3_48m_clk";
@@ -536,3 +115,13 @@ static void __init spear3xx_timer_init(void)
536struct sys_timer spear3xx_timer = { 115struct sys_timer spear3xx_timer = {
537 .init = spear3xx_timer_init, 116 .init = spear3xx_timer_init,
538}; 117};
118
119static const struct of_device_id vic_of_match[] __initconst = {
120 { .compatible = "arm,pl190-vic", .data = vic_of_init, },
121 { /* Sentinel */ }
122};
123
124void __init spear3xx_dt_init_irq(void)
125{
126 of_irq_init(vic_of_match);
127}
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c221d..af493da37ab 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
1zreladdr-y += 0x00008000 1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100 2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000 3initrd_phys-y := 0x00800000
4
5dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index a86499a8a15..adadef2b27b 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -623,53 +623,53 @@ static struct clk dummy_apb_pclk;
623 623
624/* array of all spear 6xx clock lookups */ 624/* array of all spear 6xx clock lookups */
625static struct clk_lookup spear_clk_lookups[] = { 625static struct clk_lookup spear_clk_lookups[] = {
626 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, 626 CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
627 /* root clks */ 627 /* root clks */
628 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, 628 CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
629 { .con_id = "osc_30m_clk", .clk = &osc_30m_clk}, 629 CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk),
630 /* clock derived from 32 KHz os clk */ 630 /* clock derived from 32 KHz os clk */
631 { .dev_id = "rtc-spear", .clk = &rtc_clk}, 631 CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
632 /* clock derived from 30 MHz os clk */ 632 /* clock derived from 30 MHz os clk */
633 { .con_id = "pll1_clk", .clk = &pll1_clk}, 633 CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
634 { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, 634 CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
635 { .dev_id = "wdt", .clk = &wdt_clk}, 635 CLKDEV_INIT("wdt", NULL, &wdt_clk),
636 /* clock derived from pll1 clk */ 636 /* clock derived from pll1 clk */
637 { .con_id = "cpu_clk", .clk = &cpu_clk}, 637 CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
638 { .con_id = "ahb_clk", .clk = &ahb_clk}, 638 CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
639 { .con_id = "uart_synth_clk", .clk = &uart_synth_clk}, 639 CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
640 { .con_id = "firda_synth_clk", .clk = &firda_synth_clk}, 640 CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
641 { .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk}, 641 CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk),
642 { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk}, 642 CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
643 { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk}, 643 CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
644 { .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk}, 644 CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk),
645 { .dev_id = "d0000000.serial", .clk = &uart0_clk}, 645 CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk),
646 { .dev_id = "d0080000.serial", .clk = &uart1_clk}, 646 CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk),
647 { .dev_id = "firda", .clk = &firda_clk}, 647 CLKDEV_INIT("firda", NULL, &firda_clk),
648 { .dev_id = "clcd", .clk = &clcd_clk}, 648 CLKDEV_INIT("clcd", NULL, &clcd_clk),
649 { .dev_id = "gpt0", .clk = &gpt0_clk}, 649 CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
650 { .dev_id = "gpt1", .clk = &gpt1_clk}, 650 CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
651 { .dev_id = "gpt2", .clk = &gpt2_clk}, 651 CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
652 { .dev_id = "gpt3", .clk = &gpt3_clk}, 652 CLKDEV_INIT("gpt3", NULL, &gpt3_clk),
653 /* clock derived from pll3 clk */ 653 /* clock derived from pll3 clk */
654 { .dev_id = "designware_udc", .clk = &usbd_clk}, 654 CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
655 { .con_id = "usbh.0_clk", .clk = &usbh0_clk}, 655 CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
656 { .con_id = "usbh.1_clk", .clk = &usbh1_clk}, 656 CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
657 /* clock derived from ahb clk */ 657 /* clock derived from ahb clk */
658 { .con_id = "apb_clk", .clk = &apb_clk}, 658 CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
659 { .dev_id = "d0200000.i2c", .clk = &i2c_clk}, 659 CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
660 { .dev_id = "dma", .clk = &dma_clk}, 660 CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
661 { .dev_id = "jpeg", .clk = &jpeg_clk}, 661 CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
662 { .dev_id = "gmac", .clk = &gmac_clk}, 662 CLKDEV_INIT("gmac", NULL, &gmac_clk),
663 { .dev_id = "smi", .clk = &smi_clk}, 663 CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
664 { .dev_id = "fsmc-nand", .clk = &fsmc_clk}, 664 CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk),
665 /* clock derived from apb clk */ 665 /* clock derived from apb clk */
666 { .dev_id = "adc", .clk = &adc_clk}, 666 CLKDEV_INIT("adc", NULL, &adc_clk),
667 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, 667 CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
668 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, 668 CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
669 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, 669 CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
670 { .dev_id = "f0100000.gpio", .clk = &gpio0_clk}, 670 CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk),
671 { .dev_id = "fc980000.gpio", .clk = &gpio1_clk}, 671 CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk),
672 { .dev_id = "d8100000.gpio", .clk = &gpio2_clk}, 672 CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk),
673}; 673};
674 674
675void __init spear6xx_clk_init(void) 675void __init spear6xx_clk_init(void)
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14c82c..5b9e30f54cd 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,15 +13,377 @@
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 */ 14 */
15 15
16#include <linux/amba/pl08x.h>
16#include <linux/of.h> 17#include <linux/of.h>
17#include <linux/of_address.h> 18#include <linux/of_address.h>
18#include <linux/of_irq.h> 19#include <linux/of_irq.h>
19#include <linux/of_platform.h> 20#include <linux/of_platform.h>
21#include <asm/hardware/pl080.h>
20#include <asm/hardware/vic.h> 22#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24#include <plat/pl080.h>
22#include <mach/generic.h> 25#include <mach/generic.h>
23#include <mach/hardware.h> 26#include <mach/hardware.h>
24 27
28/* dmac device registration */
29static struct pl08x_channel_data spear600_dma_info[] = {
30 {
31 .bus_id = "ssp1_rx",
32 .min_signal = 0,
33 .max_signal = 0,
34 .muxval = 0,
35 .cctl = 0,
36 .periph_buses = PL08X_AHB1,
37 }, {
38 .bus_id = "ssp1_tx",
39 .min_signal = 1,
40 .max_signal = 1,
41 .muxval = 0,
42 .cctl = 0,
43 .periph_buses = PL08X_AHB1,
44 }, {
45 .bus_id = "uart0_rx",
46 .min_signal = 2,
47 .max_signal = 2,
48 .muxval = 0,
49 .cctl = 0,
50 .periph_buses = PL08X_AHB1,
51 }, {
52 .bus_id = "uart0_tx",
53 .min_signal = 3,
54 .max_signal = 3,
55 .muxval = 0,
56 .cctl = 0,
57 .periph_buses = PL08X_AHB1,
58 }, {
59 .bus_id = "uart1_rx",
60 .min_signal = 4,
61 .max_signal = 4,
62 .muxval = 0,
63 .cctl = 0,
64 .periph_buses = PL08X_AHB1,
65 }, {
66 .bus_id = "uart1_tx",
67 .min_signal = 5,
68 .max_signal = 5,
69 .muxval = 0,
70 .cctl = 0,
71 .periph_buses = PL08X_AHB1,
72 }, {
73 .bus_id = "ssp2_rx",
74 .min_signal = 6,
75 .max_signal = 6,
76 .muxval = 0,
77 .cctl = 0,
78 .periph_buses = PL08X_AHB2,
79 }, {
80 .bus_id = "ssp2_tx",
81 .min_signal = 7,
82 .max_signal = 7,
83 .muxval = 0,
84 .cctl = 0,
85 .periph_buses = PL08X_AHB2,
86 }, {
87 .bus_id = "ssp0_rx",
88 .min_signal = 8,
89 .max_signal = 8,
90 .muxval = 0,
91 .cctl = 0,
92 .periph_buses = PL08X_AHB1,
93 }, {
94 .bus_id = "ssp0_tx",
95 .min_signal = 9,
96 .max_signal = 9,
97 .muxval = 0,
98 .cctl = 0,
99 .periph_buses = PL08X_AHB1,
100 }, {
101 .bus_id = "i2c_rx",
102 .min_signal = 10,
103 .max_signal = 10,
104 .muxval = 0,
105 .cctl = 0,
106 .periph_buses = PL08X_AHB1,
107 }, {
108 .bus_id = "i2c_tx",
109 .min_signal = 11,
110 .max_signal = 11,
111 .muxval = 0,
112 .cctl = 0,
113 .periph_buses = PL08X_AHB1,
114 }, {
115 .bus_id = "irda",
116 .min_signal = 12,
117 .max_signal = 12,
118 .muxval = 0,
119 .cctl = 0,
120 .periph_buses = PL08X_AHB1,
121 }, {
122 .bus_id = "adc",
123 .min_signal = 13,
124 .max_signal = 13,
125 .muxval = 0,
126 .cctl = 0,
127 .periph_buses = PL08X_AHB2,
128 }, {
129 .bus_id = "to_jpeg",
130 .min_signal = 14,
131 .max_signal = 14,
132 .muxval = 0,
133 .cctl = 0,
134 .periph_buses = PL08X_AHB1,
135 }, {
136 .bus_id = "from_jpeg",
137 .min_signal = 15,
138 .max_signal = 15,
139 .muxval = 0,
140 .cctl = 0,
141 .periph_buses = PL08X_AHB1,
142 }, {
143 .bus_id = "ras0_rx",
144 .min_signal = 0,
145 .max_signal = 0,
146 .muxval = 1,
147 .cctl = 0,
148 .periph_buses = PL08X_AHB1,
149 }, {
150 .bus_id = "ras0_tx",
151 .min_signal = 1,
152 .max_signal = 1,
153 .muxval = 1,
154 .cctl = 0,
155 .periph_buses = PL08X_AHB1,
156 }, {
157 .bus_id = "ras1_rx",
158 .min_signal = 2,
159 .max_signal = 2,
160 .muxval = 1,
161 .cctl = 0,
162 .periph_buses = PL08X_AHB1,
163 }, {
164 .bus_id = "ras1_tx",
165 .min_signal = 3,
166 .max_signal = 3,
167 .muxval = 1,
168 .cctl = 0,
169 .periph_buses = PL08X_AHB1,
170 }, {
171 .bus_id = "ras2_rx",
172 .min_signal = 4,
173 .max_signal = 4,
174 .muxval = 1,
175 .cctl = 0,
176 .periph_buses = PL08X_AHB1,
177 }, {
178 .bus_id = "ras2_tx",
179 .min_signal = 5,
180 .max_signal = 5,
181 .muxval = 1,
182 .cctl = 0,
183 .periph_buses = PL08X_AHB1,
184 }, {
185 .bus_id = "ras3_rx",
186 .min_signal = 6,
187 .max_signal = 6,
188 .muxval = 1,
189 .cctl = 0,
190 .periph_buses = PL08X_AHB1,
191 }, {
192 .bus_id = "ras3_tx",
193 .min_signal = 7,
194 .max_signal = 7,
195 .muxval = 1,
196 .cctl = 0,
197 .periph_buses = PL08X_AHB1,
198 }, {
199 .bus_id = "ras4_rx",
200 .min_signal = 8,
201 .max_signal = 8,
202 .muxval = 1,
203 .cctl = 0,
204 .periph_buses = PL08X_AHB1,
205 }, {
206 .bus_id = "ras4_tx",
207 .min_signal = 9,
208 .max_signal = 9,
209 .muxval = 1,
210 .cctl = 0,
211 .periph_buses = PL08X_AHB1,
212 }, {
213 .bus_id = "ras5_rx",
214 .min_signal = 10,
215 .max_signal = 10,
216 .muxval = 1,
217 .cctl = 0,
218 .periph_buses = PL08X_AHB1,
219 }, {
220 .bus_id = "ras5_tx",
221 .min_signal = 11,
222 .max_signal = 11,
223 .muxval = 1,
224 .cctl = 0,
225 .periph_buses = PL08X_AHB1,
226 }, {
227 .bus_id = "ras6_rx",
228 .min_signal = 12,
229 .max_signal = 12,
230 .muxval = 1,
231 .cctl = 0,
232 .periph_buses = PL08X_AHB1,
233 }, {
234 .bus_id = "ras6_tx",
235 .min_signal = 13,
236 .max_signal = 13,
237 .muxval = 1,
238 .cctl = 0,
239 .periph_buses = PL08X_AHB1,
240 }, {
241 .bus_id = "ras7_rx",
242 .min_signal = 14,
243 .max_signal = 14,
244 .muxval = 1,
245 .cctl = 0,
246 .periph_buses = PL08X_AHB1,
247 }, {
248 .bus_id = "ras7_tx",
249 .min_signal = 15,
250 .max_signal = 15,
251 .muxval = 1,
252 .cctl = 0,
253 .periph_buses = PL08X_AHB1,
254 }, {
255 .bus_id = "ext0_rx",
256 .min_signal = 0,
257 .max_signal = 0,
258 .muxval = 2,
259 .cctl = 0,
260 .periph_buses = PL08X_AHB2,
261 }, {
262 .bus_id = "ext0_tx",
263 .min_signal = 1,
264 .max_signal = 1,
265 .muxval = 2,
266 .cctl = 0,
267 .periph_buses = PL08X_AHB2,
268 }, {
269 .bus_id = "ext1_rx",
270 .min_signal = 2,
271 .max_signal = 2,
272 .muxval = 2,
273 .cctl = 0,
274 .periph_buses = PL08X_AHB2,
275 }, {
276 .bus_id = "ext1_tx",
277 .min_signal = 3,
278 .max_signal = 3,
279 .muxval = 2,
280 .cctl = 0,
281 .periph_buses = PL08X_AHB2,
282 }, {
283 .bus_id = "ext2_rx",
284 .min_signal = 4,
285 .max_signal = 4,
286 .muxval = 2,
287 .cctl = 0,
288 .periph_buses = PL08X_AHB2,
289 }, {
290 .bus_id = "ext2_tx",
291 .min_signal = 5,
292 .max_signal = 5,
293 .muxval = 2,
294 .cctl = 0,
295 .periph_buses = PL08X_AHB2,
296 }, {
297 .bus_id = "ext3_rx",
298 .min_signal = 6,
299 .max_signal = 6,
300 .muxval = 2,
301 .cctl = 0,
302 .periph_buses = PL08X_AHB2,
303 }, {
304 .bus_id = "ext3_tx",
305 .min_signal = 7,
306 .max_signal = 7,
307 .muxval = 2,
308 .cctl = 0,
309 .periph_buses = PL08X_AHB2,
310 }, {
311 .bus_id = "ext4_rx",
312 .min_signal = 8,
313 .max_signal = 8,
314 .muxval = 2,
315 .cctl = 0,
316 .periph_buses = PL08X_AHB2,
317 }, {
318 .bus_id = "ext4_tx",
319 .min_signal = 9,
320 .max_signal = 9,
321 .muxval = 2,
322 .cctl = 0,
323 .periph_buses = PL08X_AHB2,
324 }, {
325 .bus_id = "ext5_rx",
326 .min_signal = 10,
327 .max_signal = 10,
328 .muxval = 2,
329 .cctl = 0,
330 .periph_buses = PL08X_AHB2,
331 }, {
332 .bus_id = "ext5_tx",
333 .min_signal = 11,
334 .max_signal = 11,
335 .muxval = 2,
336 .cctl = 0,
337 .periph_buses = PL08X_AHB2,
338 }, {
339 .bus_id = "ext6_rx",
340 .min_signal = 12,
341 .max_signal = 12,
342 .muxval = 2,
343 .cctl = 0,
344 .periph_buses = PL08X_AHB2,
345 }, {
346 .bus_id = "ext6_tx",
347 .min_signal = 13,
348 .max_signal = 13,
349 .muxval = 2,
350 .cctl = 0,
351 .periph_buses = PL08X_AHB2,
352 }, {
353 .bus_id = "ext7_rx",
354 .min_signal = 14,
355 .max_signal = 14,
356 .muxval = 2,
357 .cctl = 0,
358 .periph_buses = PL08X_AHB2,
359 }, {
360 .bus_id = "ext7_tx",
361 .min_signal = 15,
362 .max_signal = 15,
363 .muxval = 2,
364 .cctl = 0,
365 .periph_buses = PL08X_AHB2,
366 },
367};
368
369struct pl08x_platform_data pl080_plat_data = {
370 .memcpy_channel = {
371 .bus_id = "memcpy",
372 .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
373 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
374 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
375 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
376 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
377 PL080_CONTROL_PROT_SYS),
378 },
379 .lli_buses = PL08X_AHB1,
380 .mem_buses = PL08X_AHB1,
381 .get_signal = pl080_get_signal,
382 .put_signal = pl080_put_signal,
383 .slave_channels = spear600_dma_info,
384 .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
385};
386
25/* Following will create static virtual/physical mappings */ 387/* Following will create static virtual/physical mappings */
26static struct map_desc spear6xx_io_desc[] __initdata = { 388static struct map_desc spear6xx_io_desc[] __initdata = {
27 { 389 {
@@ -92,9 +454,17 @@ struct sys_timer spear6xx_timer = {
92 .init = spear6xx_timer_init, 454 .init = spear6xx_timer_init,
93}; 455};
94 456
457/* Add auxdata to pass platform data */
458struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
459 OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
460 &pl080_plat_data),
461 {}
462};
463
95static void __init spear600_dt_init(void) 464static void __init spear600_dt_init(void)
96{ 465{
97 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 466 of_platform_populate(NULL, of_default_bus_match_table,
467 spear6xx_auxdata_lookup, NULL);
98} 468}
99 469
100static const char *spear600_dt_board_compat[] = { 470static const char *spear600_dt_board_compat[] = {
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbce881..387655b5ce0 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -9,9 +9,11 @@ choice
9 default ARCH_SPEAR3XX 9 default ARCH_SPEAR3XX
10 10
11config ARCH_SPEAR3XX 11config ARCH_SPEAR3XX
12 bool "SPEAr3XX" 12 bool "ST SPEAr3xx with Device Tree"
13 select ARM_VIC 13 select ARM_VIC
14 select CPU_ARM926T 14 select CPU_ARM926T
15 select USE_OF
16 select PINCTRL
15 help 17 help
16 Supports for ARM's SPEAR3XX family 18 Supports for ARM's SPEAR3XX family
17 19
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e0f2e5b9530..7744802c83e 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := clock.o restart.o time.o 6obj-y := clock.o restart.o time.o pl080.o
7 7
8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o 8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
deleted file mode 100644
index 877f3adcf61..00000000000
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/padmux.h
3 *
4 * SPEAr platform specific gpio pads muxing file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_PADMUX_H
15#define __PLAT_PADMUX_H
16
17#include <linux/types.h>
18
19/*
20 * struct pmx_reg: configuration structure for mode reg and mux reg
21 *
22 * offset: offset of mode reg
23 * mask: mask of mode reg
24 */
25struct pmx_reg {
26 u32 offset;
27 u32 mask;
28};
29
30/*
31 * struct pmx_dev_mode: configuration structure every group of modes of a device
32 *
33 * ids: all modes for this configuration
34 * mask: mask for supported mode
35 */
36struct pmx_dev_mode {
37 u32 ids;
38 u32 mask;
39};
40
41/*
42 * struct pmx_mode: mode definition structure
43 *
44 * name: mode name
45 * mask: mode mask
46 */
47struct pmx_mode {
48 char *name;
49 u32 id;
50 u32 mask;
51};
52
53/*
54 * struct pmx_dev: device definition structure
55 *
56 * name: device name
57 * modes: device configuration array for different modes supported
58 * mode_count: size of modes array
59 * is_active: is peripheral active/enabled
60 * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
61 */
62struct pmx_dev {
63 char *name;
64 struct pmx_dev_mode *modes;
65 u8 mode_count;
66 bool is_active;
67 bool enb_on_reset;
68};
69
70/*
71 * struct pmx_driver: driver definition structure
72 *
73 * mode: mode to be set
74 * devs: array of pointer to pmx devices
75 * devs_count: ARRAY_SIZE of devs
76 * base: base address of soc config registers
77 * mode_reg: structure of mode config register
78 * mux_reg: structure of device mux config register
79 */
80struct pmx_driver {
81 struct pmx_mode *mode;
82 struct pmx_dev **devs;
83 u8 devs_count;
84 u32 *base;
85 struct pmx_reg mode_reg;
86 struct pmx_reg mux_reg;
87};
88
89/* pmx functions */
90int pmx_register(struct pmx_driver *driver);
91
92#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
new file mode 100644
index 00000000000..e14a3e4932f
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -0,0 +1,21 @@
1/*
2 * arch/arm/plat-spear/include/plat/pl080.h
3 *
4 * DMAC pl080 definitions for SPEAr platform
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_PL080_H
15#define __PLAT_PL080_H
16
17struct pl08x_dma_chan;
18int pl080_get_signal(struct pl08x_dma_chan *ch);
19void pl080_put_signal(struct pl08x_dma_chan *ch);
20
21#endif /* __PLAT_PL080_H */
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
deleted file mode 100644
index 555eec6dc1c..00000000000
--- a/arch/arm/plat-spear/padmux.c
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/padmux.c
3 *
4 * SPEAr platform specific gpio pads muxing source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <plat/padmux.h>
18
19/*
20 * struct pmx: pmx definition structure
21 *
22 * base: base address of configuration registers
23 * mode_reg: mode configurations
24 * mux_reg: muxing configurations
25 * active_mode: pointer to current active mode
26 */
27struct pmx {
28 u32 base;
29 struct pmx_reg mode_reg;
30 struct pmx_reg mux_reg;
31 struct pmx_mode *active_mode;
32};
33
34static struct pmx *pmx;
35
36/**
37 * pmx_mode_set - Enables an multiplexing mode
38 * @mode - pointer to pmx mode
39 *
40 * It will set mode of operation in hardware.
41 * Returns -ve on Err otherwise 0
42 */
43static int pmx_mode_set(struct pmx_mode *mode)
44{
45 u32 val;
46
47 if (!mode->name)
48 return -EFAULT;
49
50 pmx->active_mode = mode;
51
52 val = readl(pmx->base + pmx->mode_reg.offset);
53 val &= ~pmx->mode_reg.mask;
54 val |= mode->mask & pmx->mode_reg.mask;
55 writel(val, pmx->base + pmx->mode_reg.offset);
56
57 return 0;
58}
59
60/**
61 * pmx_devs_enable - Enables list of devices
62 * @devs - pointer to pmx device array
63 * @count - number of devices to enable
64 *
65 * It will enable pads for all required peripherals once and only once.
66 * If peripheral is not supported by current mode then request is rejected.
67 * Conflicts between peripherals are not handled and peripherals will be
68 * enabled in the order they are present in pmx_dev array.
69 * In case of conflicts last peripheral enabled will be present.
70 * Returns -ve on Err otherwise 0
71 */
72static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
73{
74 u32 val, i, mask;
75
76 if (!count)
77 return -EINVAL;
78
79 val = readl(pmx->base + pmx->mux_reg.offset);
80 for (i = 0; i < count; i++) {
81 u8 j = 0;
82
83 if (!devs[i]->name || !devs[i]->modes) {
84 printk(KERN_ERR "padmux: dev name or modes is null\n");
85 continue;
86 }
87 /* check if peripheral exists in active mode */
88 if (pmx->active_mode) {
89 bool found = false;
90 for (j = 0; j < devs[i]->mode_count; j++) {
91 if (devs[i]->modes[j].ids &
92 pmx->active_mode->id) {
93 found = true;
94 break;
95 }
96 }
97 if (found == false) {
98 printk(KERN_ERR "%s device not available in %s"\
99 "mode\n", devs[i]->name,
100 pmx->active_mode->name);
101 continue;
102 }
103 }
104
105 /* enable peripheral */
106 mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
107 if (devs[i]->enb_on_reset)
108 val &= ~mask;
109 else
110 val |= mask;
111
112 devs[i]->is_active = true;
113 }
114 writel(val, pmx->base + pmx->mux_reg.offset);
115 kfree(pmx);
116
117 /* this will ensure that multiplexing can't be changed now */
118 pmx = (struct pmx *)-1;
119
120 return 0;
121}
122
123/**
124 * pmx_register - registers a platform requesting pad mux feature
125 * @driver - pointer to driver structure containing driver specific parameters
126 *
127 * Also this must be called only once. This will allocate memory for pmx
128 * structure, will call pmx_mode_set, will call pmx_devs_enable.
129 * Returns -ve on Err otherwise 0
130 */
131int pmx_register(struct pmx_driver *driver)
132{
133 int ret = 0;
134
135 if (pmx)
136 return -EPERM;
137 if (!driver->base || !driver->devs)
138 return -EFAULT;
139
140 pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
141 if (!pmx)
142 return -ENOMEM;
143
144 pmx->base = (u32)driver->base;
145 pmx->mode_reg.offset = driver->mode_reg.offset;
146 pmx->mode_reg.mask = driver->mode_reg.mask;
147 pmx->mux_reg.offset = driver->mux_reg.offset;
148 pmx->mux_reg.mask = driver->mux_reg.mask;
149
150 /* choose mode to enable */
151 if (driver->mode) {
152 ret = pmx_mode_set(driver->mode);
153 if (ret)
154 goto pmx_fail;
155 }
156 ret = pmx_devs_enable(driver->devs, driver->devs_count);
157 if (ret)
158 goto pmx_fail;
159
160 return 0;
161
162pmx_fail:
163 return ret;
164}
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
new file mode 100644
index 00000000000..d53d75e1af5
--- /dev/null
+++ b/arch/arm/plat-spear/pl080.c
@@ -0,0 +1,79 @@
1/*
2 * arch/arm/plat-spear/pl080.c
3 *
4 * DMAC pl080 definitions for SPEAr platform
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/amba/pl08x.h>
15#include <linux/amba/bus.h>
16#include <linux/bug.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/spinlock_types.h>
20#include <mach/misc_regs.h>
21
22static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
23
24struct {
25 unsigned char busy;
26 unsigned char val;
27} signals[16] = {{0, 0}, };
28
29int pl080_get_signal(struct pl08x_dma_chan *ch)
30{
31 const struct pl08x_channel_data *cd = ch->cd;
32 unsigned int signal = cd->min_signal, val;
33 unsigned long flags;
34
35 spin_lock_irqsave(&lock, flags);
36
37 /* Return if signal is already acquired by somebody else */
38 if (signals[signal].busy &&
39 (signals[signal].val != cd->muxval)) {
40 spin_unlock_irqrestore(&lock, flags);
41 return -EBUSY;
42 }
43
44 /* If acquiring for the first time, configure it */
45 if (!signals[signal].busy) {
46 val = readl(DMA_CHN_CFG);
47
48 /*
49 * Each request line has two bits in DMA_CHN_CFG register. To
50 * goto the bits of current request line, do left shift of
51 * value by 2 * signal number.
52 */
53 val &= ~(0x3 << (signal * 2));
54 val |= cd->muxval << (signal * 2);
55 writel(val, DMA_CHN_CFG);
56 }
57
58 signals[signal].busy++;
59 signals[signal].val = cd->muxval;
60 spin_unlock_irqrestore(&lock, flags);
61
62 return signal;
63}
64
65void pl080_put_signal(struct pl08x_dma_chan *ch)
66{
67 const struct pl08x_channel_data *cd = ch->cd;
68 unsigned long flags;
69
70 spin_lock_irqsave(&lock, flags);
71
72 /* if signal is not used */
73 if (!signals[cd->min_signal].busy)
74 BUG();
75
76 signals[cd->min_signal].busy--;
77
78 spin_unlock_irqrestore(&lock, flags);
79}
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 6db161f64ae..c535cf8c577 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -35,7 +35,12 @@ static DEFINE_MUTEX(clocks_mutex);
35static struct clk_lookup *clk_find(const char *dev_id, const char *con_id) 35static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
36{ 36{
37 struct clk_lookup *p, *cl = NULL; 37 struct clk_lookup *p, *cl = NULL;
38 int match, best = 0; 38 int match, best_found = 0, best_possible = 0;
39
40 if (dev_id)
41 best_possible += 2;
42 if (con_id)
43 best_possible += 1;
39 44
40 list_for_each_entry(p, &clocks, node) { 45 list_for_each_entry(p, &clocks, node) {
41 match = 0; 46 match = 0;
@@ -50,10 +55,10 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
50 match += 1; 55 match += 1;
51 } 56 }
52 57
53 if (match > best) { 58 if (match > best_found) {
54 cl = p; 59 cl = p;
55 if (match != 3) 60 if (match != best_possible)
56 best = match; 61 best_found = match;
57 else 62 else
58 break; 63 break;
59 } 64 }
@@ -89,6 +94,51 @@ void clk_put(struct clk *clk)
89} 94}
90EXPORT_SYMBOL(clk_put); 95EXPORT_SYMBOL(clk_put);
91 96
97static void devm_clk_release(struct device *dev, void *res)
98{
99 clk_put(*(struct clk **)res);
100}
101
102struct clk *devm_clk_get(struct device *dev, const char *id)
103{
104 struct clk **ptr, *clk;
105
106 ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL);
107 if (!ptr)
108 return ERR_PTR(-ENOMEM);
109
110 clk = clk_get(dev, id);
111 if (!IS_ERR(clk)) {
112 *ptr = clk;
113 devres_add(dev, ptr);
114 } else {
115 devres_free(ptr);
116 }
117
118 return clk;
119}
120EXPORT_SYMBOL(devm_clk_get);
121
122static int devm_clk_match(struct device *dev, void *res, void *data)
123{
124 struct clk **c = res;
125 if (!c || !*c) {
126 WARN_ON(!c || !*c);
127 return 0;
128 }
129 return *c == data;
130}
131
132void devm_clk_put(struct device *dev, struct clk *clk)
133{
134 int ret;
135
136 ret = devres_destroy(dev, devm_clk_release, devm_clk_match, clk);
137
138 WARN_ON(ret);
139}
140EXPORT_SYMBOL(devm_clk_put);
141
92void clkdev_add(struct clk_lookup *cl) 142void clkdev_add(struct clk_lookup *cl)
93{ 143{
94 mutex_lock(&clocks_mutex); 144 mutex_lock(&clocks_mutex);
@@ -116,8 +166,9 @@ struct clk_lookup_alloc {
116 char con_id[MAX_CON_ID]; 166 char con_id[MAX_CON_ID];
117}; 167};
118 168
119struct clk_lookup * __init_refok 169static struct clk_lookup * __init_refok
120clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...) 170vclkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt,
171 va_list ap)
121{ 172{
122 struct clk_lookup_alloc *cla; 173 struct clk_lookup_alloc *cla;
123 174
@@ -132,16 +183,25 @@ clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
132 } 183 }
133 184
134 if (dev_fmt) { 185 if (dev_fmt) {
135 va_list ap;
136
137 va_start(ap, dev_fmt);
138 vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap); 186 vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
139 cla->cl.dev_id = cla->dev_id; 187 cla->cl.dev_id = cla->dev_id;
140 va_end(ap);
141 } 188 }
142 189
143 return &cla->cl; 190 return &cla->cl;
144} 191}
192
193struct clk_lookup * __init_refok
194clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
195{
196 struct clk_lookup *cl;
197 va_list ap;
198
199 va_start(ap, dev_fmt);
200 cl = vclkdev_alloc(clk, con_id, dev_fmt, ap);
201 va_end(ap);
202
203 return cl;
204}
145EXPORT_SYMBOL(clkdev_alloc); 205EXPORT_SYMBOL(clkdev_alloc);
146 206
147int clk_add_alias(const char *alias, const char *alias_dev_name, char *id, 207int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
@@ -173,3 +233,65 @@ void clkdev_drop(struct clk_lookup *cl)
173 kfree(cl); 233 kfree(cl);
174} 234}
175EXPORT_SYMBOL(clkdev_drop); 235EXPORT_SYMBOL(clkdev_drop);
236
237/**
238 * clk_register_clkdev - register one clock lookup for a struct clk
239 * @clk: struct clk to associate with all clk_lookups
240 * @con_id: connection ID string on device
241 * @dev_id: format string describing device name
242 *
243 * con_id or dev_id may be NULL as a wildcard, just as in the rest of
244 * clkdev.
245 *
246 * To make things easier for mass registration, we detect error clks
247 * from a previous clk_register() call, and return the error code for
248 * those. This is to permit this function to be called immediately
249 * after clk_register().
250 */
251int clk_register_clkdev(struct clk *clk, const char *con_id,
252 const char *dev_fmt, ...)
253{
254 struct clk_lookup *cl;
255 va_list ap;
256
257 if (IS_ERR(clk))
258 return PTR_ERR(clk);
259
260 va_start(ap, dev_fmt);
261 cl = vclkdev_alloc(clk, con_id, dev_fmt, ap);
262 va_end(ap);
263
264 if (!cl)
265 return -ENOMEM;
266
267 clkdev_add(cl);
268
269 return 0;
270}
271
272/**
273 * clk_register_clkdevs - register a set of clk_lookup for a struct clk
274 * @clk: struct clk to associate with all clk_lookups
275 * @cl: array of clk_lookup structures with con_id and dev_id pre-initialized
276 * @num: number of clk_lookup structures to register
277 *
278 * To make things easier for mass registration, we detect error clks
279 * from a previous clk_register() call, and return the error code for
280 * those. This is to permit this function to be called immediately
281 * after clk_register().
282 */
283int clk_register_clkdevs(struct clk *clk, struct clk_lookup *cl, size_t num)
284{
285 unsigned i;
286
287 if (IS_ERR(clk))
288 return PTR_ERR(clk);
289
290 for (i = 0; i < num; i++, cl++) {
291 cl->clk = clk;
292 clkdev_add(cl);
293 }
294
295 return 0;
296}
297EXPORT_SYMBOL(clk_register_clkdevs);
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 73f2fd66d65..a54a93112cb 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -111,6 +111,8 @@ config PINCTRL_COH901
111 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 111 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
112 ports of 8 GPIO pins each. 112 ports of 8 GPIO pins each.
113 113
114source "drivers/pinctrl/spear/Kconfig"
115
114endmenu 116endmenu
115 117
116endif 118endif
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 5f5a0a6414a..c9b0be56ff4 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -24,3 +24,5 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
24obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o 24obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
25obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o 25obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
26obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o 26obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
27
28obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig
new file mode 100644
index 00000000000..6a2596b4f35
--- /dev/null
+++ b/drivers/pinctrl/spear/Kconfig
@@ -0,0 +1,34 @@
1#
2# ST Microelectronics SPEAr PINCTRL drivers
3#
4
5if PLAT_SPEAR
6
7config PINCTRL_SPEAR
8 bool
9 depends on OF
10 select PINMUX
11 help
12 This enables pin control drivers for SPEAr Platform
13
14config PINCTRL_SPEAR3XX
15 bool
16 depends on ARCH_SPEAR3XX
17 select PINCTRL_SPEAR
18
19config PINCTRL_SPEAR300
20 bool "ST Microelectronics SPEAr300 SoC pin controller driver"
21 depends on MACH_SPEAR300
22 select PINCTRL_SPEAR3XX
23
24config PINCTRL_SPEAR310
25 bool "ST Microelectronics SPEAr310 SoC pin controller driver"
26 depends on MACH_SPEAR310
27 select PINCTRL_SPEAR3XX
28
29config PINCTRL_SPEAR320
30 bool "ST Microelectronics SPEAr320 SoC pin controller driver"
31 depends on MACH_SPEAR320
32 select PINCTRL_SPEAR3XX
33
34endif
diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile
new file mode 100644
index 00000000000..15dcb85da22
--- /dev/null
+++ b/drivers/pinctrl/spear/Makefile
@@ -0,0 +1,7 @@
1# SPEAr pinmux support
2
3obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o
4obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o
5obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o
6obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o
7obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
new file mode 100644
index 00000000000..5ae50aadf88
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -0,0 +1,354 @@
1/*
2 * Driver for the ST Microelectronics SPEAr pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * Inspired from:
8 * - U300 Pinctl drivers
9 * - Tegra Pinctl drivers
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinmux.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26
27#include "pinctrl-spear.h"
28
29#define DRIVER_NAME "spear-pinmux"
30
31static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
32{
33 return readl_relaxed(pmx->vbase + reg);
34}
35
36static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
37{
38 writel_relaxed(val, pmx->vbase + reg);
39}
40
41static int set_mode(struct spear_pmx *pmx, int mode)
42{
43 struct spear_pmx_mode *pmx_mode = NULL;
44 int i;
45 u32 val;
46
47 if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes)
48 return -EINVAL;
49
50 for (i = 0; i < pmx->machdata->npmx_modes; i++) {
51 if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) {
52 pmx_mode = pmx->machdata->pmx_modes[i];
53 break;
54 }
55 }
56
57 if (!pmx_mode)
58 return -EINVAL;
59
60 val = pmx_readl(pmx, pmx_mode->reg);
61 val &= ~pmx_mode->mask;
62 val |= pmx_mode->val;
63 pmx_writel(pmx, val, pmx_mode->reg);
64
65 pmx->machdata->mode = pmx_mode->mode;
66 dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n",
67 pmx_mode->name ? pmx_mode->name : "no_name",
68 pmx_mode->reg);
69
70 return 0;
71}
72
73void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
74{
75 struct spear_pingroup *pgroup;
76 struct spear_modemux *modemux;
77 int i, j, group;
78
79 for (group = 0; group < machdata->ngroups; group++) {
80 pgroup = machdata->groups[group];
81
82 for (i = 0; i < pgroup->nmodemuxs; i++) {
83 modemux = &pgroup->modemuxs[i];
84
85 for (j = 0; j < modemux->nmuxregs; j++)
86 if (modemux->muxregs[j].reg == 0xFFFF)
87 modemux->muxregs[j].reg = reg;
88 }
89 }
90}
91
92static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev)
93{
94 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
95
96 return pmx->machdata->ngroups;
97}
98
99static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
100 unsigned group)
101{
102 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
103
104 return pmx->machdata->groups[group]->name;
105}
106
107static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
108 unsigned group, const unsigned **pins, unsigned *num_pins)
109{
110 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
111
112 *pins = pmx->machdata->groups[group]->pins;
113 *num_pins = pmx->machdata->groups[group]->npins;
114
115 return 0;
116}
117
118static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
119 struct seq_file *s, unsigned offset)
120{
121 seq_printf(s, " " DRIVER_NAME);
122}
123
124int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
125 struct device_node *np_config,
126 struct pinctrl_map **map, unsigned *num_maps)
127{
128 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
129 struct device_node *np;
130 struct property *prop;
131 const char *function, *group;
132 int ret, index = 0, count = 0;
133
134 /* calculate number of maps required */
135 for_each_child_of_node(np_config, np) {
136 ret = of_property_read_string(np, "st,function", &function);
137 if (ret < 0)
138 return ret;
139
140 ret = of_property_count_strings(np, "st,pins");
141 if (ret < 0)
142 return ret;
143
144 count += ret;
145 }
146
147 if (!count) {
148 dev_err(pmx->dev, "No child nodes passed via DT\n");
149 return -ENODEV;
150 }
151
152 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
153 if (!*map)
154 return -ENOMEM;
155
156 for_each_child_of_node(np_config, np) {
157 of_property_read_string(np, "st,function", &function);
158 of_property_for_each_string(np, "st,pins", prop, group) {
159 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
160 (*map)[index].data.mux.group = group;
161 (*map)[index].data.mux.function = function;
162 index++;
163 }
164 }
165
166 *num_maps = count;
167
168 return 0;
169}
170
171void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
172 struct pinctrl_map *map, unsigned num_maps)
173{
174 kfree(map);
175}
176
177static struct pinctrl_ops spear_pinctrl_ops = {
178 .get_groups_count = spear_pinctrl_get_groups_cnt,
179 .get_group_name = spear_pinctrl_get_group_name,
180 .get_group_pins = spear_pinctrl_get_group_pins,
181 .pin_dbg_show = spear_pinctrl_pin_dbg_show,
182 .dt_node_to_map = spear_pinctrl_dt_node_to_map,
183 .dt_free_map = spear_pinctrl_dt_free_map,
184};
185
186static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
187{
188 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
189
190 return pmx->machdata->nfunctions;
191}
192
193static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
194 unsigned function)
195{
196 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
197
198 return pmx->machdata->functions[function]->name;
199}
200
201static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
202 unsigned function, const char *const **groups,
203 unsigned * const ngroups)
204{
205 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
206
207 *groups = pmx->machdata->functions[function]->groups;
208 *ngroups = pmx->machdata->functions[function]->ngroups;
209
210 return 0;
211}
212
213static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
214 unsigned function, unsigned group, bool enable)
215{
216 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
217 const struct spear_pingroup *pgroup;
218 const struct spear_modemux *modemux;
219 struct spear_muxreg *muxreg;
220 u32 val, temp;
221 int i, j;
222 bool found = false;
223
224 pgroup = pmx->machdata->groups[group];
225
226 for (i = 0; i < pgroup->nmodemuxs; i++) {
227 modemux = &pgroup->modemuxs[i];
228
229 /* SoC have any modes */
230 if (pmx->machdata->modes_supported) {
231 if (!(pmx->machdata->mode & modemux->modes))
232 continue;
233 }
234
235 found = true;
236 for (j = 0; j < modemux->nmuxregs; j++) {
237 muxreg = &modemux->muxregs[j];
238
239 val = pmx_readl(pmx, muxreg->reg);
240 val &= ~muxreg->mask;
241
242 if (enable)
243 temp = muxreg->val;
244 else
245 temp = ~muxreg->val;
246
247 val |= temp;
248 pmx_writel(pmx, val, muxreg->reg);
249 }
250 }
251
252 if (!found) {
253 dev_err(pmx->dev, "pinmux group: %s not supported\n",
254 pgroup->name);
255 return -ENODEV;
256 }
257
258 return 0;
259}
260
261static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
262 unsigned group)
263{
264 return spear_pinctrl_endisable(pctldev, function, group, true);
265}
266
267static void spear_pinctrl_disable(struct pinctrl_dev *pctldev,
268 unsigned function, unsigned group)
269{
270 spear_pinctrl_endisable(pctldev, function, group, false);
271}
272
273static struct pinmux_ops spear_pinmux_ops = {
274 .get_functions_count = spear_pinctrl_get_funcs_count,
275 .get_function_name = spear_pinctrl_get_func_name,
276 .get_function_groups = spear_pinctrl_get_func_groups,
277 .enable = spear_pinctrl_enable,
278 .disable = spear_pinctrl_disable,
279};
280
281static struct pinctrl_desc spear_pinctrl_desc = {
282 .name = DRIVER_NAME,
283 .pctlops = &spear_pinctrl_ops,
284 .pmxops = &spear_pinmux_ops,
285 .owner = THIS_MODULE,
286};
287
288int __devinit spear_pinctrl_probe(struct platform_device *pdev,
289 struct spear_pinctrl_machdata *machdata)
290{
291 struct device_node *np = pdev->dev.of_node;
292 struct resource *res;
293 struct spear_pmx *pmx;
294
295 if (!machdata)
296 return -ENODEV;
297
298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
299 if (!res)
300 return -EINVAL;
301
302 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
303 if (!pmx) {
304 dev_err(&pdev->dev, "Can't alloc spear_pmx\n");
305 return -ENOMEM;
306 }
307
308 pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
309 if (!pmx->vbase) {
310 dev_err(&pdev->dev, "Couldn't ioremap at index 0\n");
311 return -ENODEV;
312 }
313
314 pmx->dev = &pdev->dev;
315 pmx->machdata = machdata;
316
317 /* configure mode, if supported by SoC */
318 if (machdata->modes_supported) {
319 int mode = 0;
320
321 if (of_property_read_u32(np, "st,pinmux-mode", &mode)) {
322 dev_err(&pdev->dev, "OF: pinmux mode not passed\n");
323 return -EINVAL;
324 }
325
326 if (set_mode(pmx, mode)) {
327 dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n",
328 mode);
329 return -EINVAL;
330 }
331 }
332
333 platform_set_drvdata(pdev, pmx);
334
335 spear_pinctrl_desc.pins = machdata->pins;
336 spear_pinctrl_desc.npins = machdata->npins;
337
338 pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx);
339 if (IS_ERR(pmx->pctl)) {
340 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
341 return PTR_ERR(pmx->pctl);
342 }
343
344 return 0;
345}
346
347int __devexit spear_pinctrl_remove(struct platform_device *pdev)
348{
349 struct spear_pmx *pmx = platform_get_drvdata(pdev);
350
351 pinctrl_unregister(pmx->pctl);
352
353 return 0;
354}
diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h
new file mode 100644
index 00000000000..47a6b5b72f9
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear.h
@@ -0,0 +1,142 @@
1/*
2 * Driver header file for the ST Microelectronics SPEAr pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __PINMUX_SPEAR_H__
13#define __PINMUX_SPEAR_H__
14
15#include <linux/pinctrl/pinctrl.h>
16#include <linux/types.h>
17
18struct platform_device;
19struct device;
20
21/**
22 * struct spear_pmx_mode - SPEAr pmx mode
23 * @name: name of pmx mode
24 * @mode: mode id
25 * @reg: register for configuring this mode
26 * @mask: mask of this mode in reg
27 * @val: val to be configured at reg after doing (val & mask)
28 */
29struct spear_pmx_mode {
30 const char *const name;
31 u16 mode;
32 u16 reg;
33 u16 mask;
34 u32 val;
35};
36
37/**
38 * struct spear_muxreg - SPEAr mux reg configuration
39 * @reg: register offset
40 * @mask: mask bits
41 * @val: val to be written on mask bits
42 */
43struct spear_muxreg {
44 u16 reg;
45 u32 mask;
46 u32 val;
47};
48
49/**
50 * struct spear_modemux - SPEAr mode mux configuration
51 * @modes: mode ids supported by this group of muxregs
52 * @nmuxregs: number of muxreg configurations to be done for modes
53 * @muxregs: array of muxreg configurations to be done for modes
54 */
55struct spear_modemux {
56 u16 modes;
57 u8 nmuxregs;
58 struct spear_muxreg *muxregs;
59};
60
61/**
62 * struct spear_pingroup - SPEAr pin group configurations
63 * @name: name of pin group
64 * @pins: array containing pin numbers
65 * @npins: size of pins array
66 * @modemuxs: array of modemux configurations for this pin group
67 * @nmodemuxs: size of array modemuxs
68 *
69 * A representation of a group of pins in the SPEAr pin controller. Each group
70 * allows some parameter or parameters to be configured.
71 */
72struct spear_pingroup {
73 const char *name;
74 const unsigned *pins;
75 unsigned npins;
76 struct spear_modemux *modemuxs;
77 unsigned nmodemuxs;
78};
79
80/**
81 * struct spear_function - SPEAr pinctrl mux function
82 * @name: The name of the function, exported to pinctrl core.
83 * @groups: An array of pin groups that may select this function.
84 * @ngroups: The number of entries in @groups.
85 */
86struct spear_function {
87 const char *name;
88 const char *const *groups;
89 unsigned ngroups;
90};
91
92/**
93 * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
94 * configuration
95 * @pins: An array describing all pins the pin controller affects.
96 * All pins which are also GPIOs must be listed first within the *array,
97 * and be numbered identically to the GPIO controller's *numbering.
98 * @npins: The numbmer of entries in @pins.
99 * @functions: An array describing all mux functions the SoC supports.
100 * @nfunctions: The numbmer of entries in @functions.
101 * @groups: An array describing all pin groups the pin SoC supports.
102 * @ngroups: The numbmer of entries in @groups.
103 *
104 * @modes_supported: Does SoC support modes
105 * @mode: mode configured from probe
106 * @pmx_modes: array of modes supported by SoC
107 * @npmx_modes: number of entries in pmx_modes.
108 */
109struct spear_pinctrl_machdata {
110 const struct pinctrl_pin_desc *pins;
111 unsigned npins;
112 struct spear_function **functions;
113 unsigned nfunctions;
114 struct spear_pingroup **groups;
115 unsigned ngroups;
116
117 bool modes_supported;
118 u16 mode;
119 struct spear_pmx_mode **pmx_modes;
120 unsigned npmx_modes;
121};
122
123/**
124 * struct spear_pmx - SPEAr pinctrl mux
125 * @dev: pointer to struct dev of platform_device registered
126 * @pctl: pointer to struct pinctrl_dev
127 * @machdata: pointer to SoC or machine specific structure
128 * @vbase: virtual base address of pinmux controller
129 */
130struct spear_pmx {
131 struct device *dev;
132 struct pinctrl_dev *pctl;
133 struct spear_pinctrl_machdata *machdata;
134 void __iomem *vbase;
135};
136
137/* exported routines */
138void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
139int __devinit spear_pinctrl_probe(struct platform_device *pdev,
140 struct spear_pinctrl_machdata *machdata);
141int __devexit spear_pinctrl_remove(struct platform_device *pdev);
142#endif /* __PINMUX_SPEAR_H__ */
diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c
new file mode 100644
index 00000000000..9c82a35e4e7
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear300.c
@@ -0,0 +1,708 @@
1/*
2 * Driver for the ST Microelectronics SPEAr300 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear300-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG 0x00
23#define MODE_CONFIG_REG 0x04
24
25/* modes */
26#define NAND_MODE (1 << 0)
27#define NOR_MODE (1 << 1)
28#define PHOTO_FRAME_MODE (1 << 2)
29#define LEND_IP_PHONE_MODE (1 << 3)
30#define HEND_IP_PHONE_MODE (1 << 4)
31#define LEND_WIFI_PHONE_MODE (1 << 5)
32#define HEND_WIFI_PHONE_MODE (1 << 6)
33#define ATA_PABX_WI2S_MODE (1 << 7)
34#define ATA_PABX_I2S_MODE (1 << 8)
35#define CAML_LCDW_MODE (1 << 9)
36#define CAMU_LCD_MODE (1 << 10)
37#define CAMU_WLCD_MODE (1 << 11)
38#define CAML_LCD_MODE (1 << 12)
39
40static struct spear_pmx_mode pmx_mode_nand = {
41 .name = "nand",
42 .mode = NAND_MODE,
43 .reg = MODE_CONFIG_REG,
44 .mask = 0x0000000F,
45 .val = 0x00,
46};
47
48static struct spear_pmx_mode pmx_mode_nor = {
49 .name = "nor",
50 .mode = NOR_MODE,
51 .reg = MODE_CONFIG_REG,
52 .mask = 0x0000000F,
53 .val = 0x01,
54};
55
56static struct spear_pmx_mode pmx_mode_photo_frame = {
57 .name = "photo frame mode",
58 .mode = PHOTO_FRAME_MODE,
59 .reg = MODE_CONFIG_REG,
60 .mask = 0x0000000F,
61 .val = 0x02,
62};
63
64static struct spear_pmx_mode pmx_mode_lend_ip_phone = {
65 .name = "lend ip phone mode",
66 .mode = LEND_IP_PHONE_MODE,
67 .reg = MODE_CONFIG_REG,
68 .mask = 0x0000000F,
69 .val = 0x03,
70};
71
72static struct spear_pmx_mode pmx_mode_hend_ip_phone = {
73 .name = "hend ip phone mode",
74 .mode = HEND_IP_PHONE_MODE,
75 .reg = MODE_CONFIG_REG,
76 .mask = 0x0000000F,
77 .val = 0x04,
78};
79
80static struct spear_pmx_mode pmx_mode_lend_wifi_phone = {
81 .name = "lend wifi phone mode",
82 .mode = LEND_WIFI_PHONE_MODE,
83 .reg = MODE_CONFIG_REG,
84 .mask = 0x0000000F,
85 .val = 0x05,
86};
87
88static struct spear_pmx_mode pmx_mode_hend_wifi_phone = {
89 .name = "hend wifi phone mode",
90 .mode = HEND_WIFI_PHONE_MODE,
91 .reg = MODE_CONFIG_REG,
92 .mask = 0x0000000F,
93 .val = 0x06,
94};
95
96static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = {
97 .name = "ata pabx wi2s mode",
98 .mode = ATA_PABX_WI2S_MODE,
99 .reg = MODE_CONFIG_REG,
100 .mask = 0x0000000F,
101 .val = 0x07,
102};
103
104static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = {
105 .name = "ata pabx i2s mode",
106 .mode = ATA_PABX_I2S_MODE,
107 .reg = MODE_CONFIG_REG,
108 .mask = 0x0000000F,
109 .val = 0x08,
110};
111
112static struct spear_pmx_mode pmx_mode_caml_lcdw = {
113 .name = "caml lcdw mode",
114 .mode = CAML_LCDW_MODE,
115 .reg = MODE_CONFIG_REG,
116 .mask = 0x0000000F,
117 .val = 0x0C,
118};
119
120static struct spear_pmx_mode pmx_mode_camu_lcd = {
121 .name = "camu lcd mode",
122 .mode = CAMU_LCD_MODE,
123 .reg = MODE_CONFIG_REG,
124 .mask = 0x0000000F,
125 .val = 0x0D,
126};
127
128static struct spear_pmx_mode pmx_mode_camu_wlcd = {
129 .name = "camu wlcd mode",
130 .mode = CAMU_WLCD_MODE,
131 .reg = MODE_CONFIG_REG,
132 .mask = 0x0000000F,
133 .val = 0xE,
134};
135
136static struct spear_pmx_mode pmx_mode_caml_lcd = {
137 .name = "caml lcd mode",
138 .mode = CAML_LCD_MODE,
139 .reg = MODE_CONFIG_REG,
140 .mask = 0x0000000F,
141 .val = 0x0F,
142};
143
144static struct spear_pmx_mode *spear300_pmx_modes[] = {
145 &pmx_mode_nand,
146 &pmx_mode_nor,
147 &pmx_mode_photo_frame,
148 &pmx_mode_lend_ip_phone,
149 &pmx_mode_hend_ip_phone,
150 &pmx_mode_lend_wifi_phone,
151 &pmx_mode_hend_wifi_phone,
152 &pmx_mode_ata_pabx_wi2s,
153 &pmx_mode_ata_pabx_i2s,
154 &pmx_mode_caml_lcdw,
155 &pmx_mode_camu_lcd,
156 &pmx_mode_camu_wlcd,
157 &pmx_mode_caml_lcd,
158};
159
160/* fsmc_2chips_pins */
161static const unsigned fsmc_2chips_pins[] = { 1, 97 };
162static struct spear_muxreg fsmc_2chips_muxreg[] = {
163 {
164 .reg = PMX_CONFIG_REG,
165 .mask = PMX_FIRDA_MASK,
166 .val = 0,
167 },
168};
169
170static struct spear_modemux fsmc_2chips_modemux[] = {
171 {
172 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
173 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
174 .muxregs = fsmc_2chips_muxreg,
175 .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg),
176 },
177};
178
179static struct spear_pingroup fsmc_2chips_pingroup = {
180 .name = "fsmc_2chips_grp",
181 .pins = fsmc_2chips_pins,
182 .npins = ARRAY_SIZE(fsmc_2chips_pins),
183 .modemuxs = fsmc_2chips_modemux,
184 .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux),
185};
186
187/* fsmc_4chips_pins */
188static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 };
189static struct spear_muxreg fsmc_4chips_muxreg[] = {
190 {
191 .reg = PMX_CONFIG_REG,
192 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
193 .val = 0,
194 },
195};
196
197static struct spear_modemux fsmc_4chips_modemux[] = {
198 {
199 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
200 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
201 .muxregs = fsmc_4chips_muxreg,
202 .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg),
203 },
204};
205
206static struct spear_pingroup fsmc_4chips_pingroup = {
207 .name = "fsmc_4chips_grp",
208 .pins = fsmc_4chips_pins,
209 .npins = ARRAY_SIZE(fsmc_4chips_pins),
210 .modemuxs = fsmc_4chips_modemux,
211 .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux),
212};
213
214static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp"
215};
216static struct spear_function fsmc_function = {
217 .name = "fsmc",
218 .groups = fsmc_grps,
219 .ngroups = ARRAY_SIZE(fsmc_grps),
220};
221
222/* clcd_lcdmode_pins */
223static const unsigned clcd_lcdmode_pins[] = { 49, 50 };
224static struct spear_muxreg clcd_lcdmode_muxreg[] = {
225 {
226 .reg = PMX_CONFIG_REG,
227 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
228 .val = 0,
229 },
230};
231
232static struct spear_modemux clcd_lcdmode_modemux[] = {
233 {
234 .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
235 CAMU_LCD_MODE | CAML_LCD_MODE,
236 .muxregs = clcd_lcdmode_muxreg,
237 .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg),
238 },
239};
240
241static struct spear_pingroup clcd_lcdmode_pingroup = {
242 .name = "clcd_lcdmode_grp",
243 .pins = clcd_lcdmode_pins,
244 .npins = ARRAY_SIZE(clcd_lcdmode_pins),
245 .modemuxs = clcd_lcdmode_modemux,
246 .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux),
247};
248
249/* clcd_pfmode_pins */
250static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 };
251static struct spear_muxreg clcd_pfmode_muxreg[] = {
252 {
253 .reg = PMX_CONFIG_REG,
254 .mask = PMX_TIMER_2_3_MASK,
255 .val = 0,
256 },
257};
258
259static struct spear_modemux clcd_pfmode_modemux[] = {
260 {
261 .modes = PHOTO_FRAME_MODE,
262 .muxregs = clcd_pfmode_muxreg,
263 .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg),
264 },
265};
266
267static struct spear_pingroup clcd_pfmode_pingroup = {
268 .name = "clcd_pfmode_grp",
269 .pins = clcd_pfmode_pins,
270 .npins = ARRAY_SIZE(clcd_pfmode_pins),
271 .modemuxs = clcd_pfmode_modemux,
272 .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux),
273};
274
275static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp"
276};
277static struct spear_function clcd_function = {
278 .name = "clcd",
279 .groups = clcd_grps,
280 .ngroups = ARRAY_SIZE(clcd_grps),
281};
282
283/* tdm_pins */
284static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 };
285static struct spear_muxreg tdm_muxreg[] = {
286 {
287 .reg = PMX_CONFIG_REG,
288 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
289 .val = 0,
290 },
291};
292
293static struct spear_modemux tdm_modemux[] = {
294 {
295 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
296 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
297 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
298 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
299 | CAMU_WLCD_MODE | CAML_LCD_MODE,
300 .muxregs = tdm_muxreg,
301 .nmuxregs = ARRAY_SIZE(tdm_muxreg),
302 },
303};
304
305static struct spear_pingroup tdm_pingroup = {
306 .name = "tdm_grp",
307 .pins = tdm_pins,
308 .npins = ARRAY_SIZE(tdm_pins),
309 .modemuxs = tdm_modemux,
310 .nmodemuxs = ARRAY_SIZE(tdm_modemux),
311};
312
313static const char *const tdm_grps[] = { "tdm_grp" };
314static struct spear_function tdm_function = {
315 .name = "tdm",
316 .groups = tdm_grps,
317 .ngroups = ARRAY_SIZE(tdm_grps),
318};
319
320/* i2c_clk_pins */
321static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 };
322static struct spear_muxreg i2c_clk_muxreg[] = {
323 {
324 .reg = PMX_CONFIG_REG,
325 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
326 .val = 0,
327 },
328};
329
330static struct spear_modemux i2c_clk_modemux[] = {
331 {
332 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
333 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
334 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE
335 | CAML_LCD_MODE,
336 .muxregs = i2c_clk_muxreg,
337 .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg),
338 },
339};
340
341static struct spear_pingroup i2c_clk_pingroup = {
342 .name = "i2c_clk_grp_grp",
343 .pins = i2c_clk_pins,
344 .npins = ARRAY_SIZE(i2c_clk_pins),
345 .modemuxs = i2c_clk_modemux,
346 .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux),
347};
348
349static const char *const i2c_grps[] = { "i2c_clk_grp" };
350static struct spear_function i2c_function = {
351 .name = "i2c1",
352 .groups = i2c_grps,
353 .ngroups = ARRAY_SIZE(i2c_grps),
354};
355
356/* caml_pins */
357static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
358static struct spear_muxreg caml_muxreg[] = {
359 {
360 .reg = PMX_CONFIG_REG,
361 .mask = PMX_MII_MASK,
362 .val = 0,
363 },
364};
365
366static struct spear_modemux caml_modemux[] = {
367 {
368 .modes = CAML_LCDW_MODE | CAML_LCD_MODE,
369 .muxregs = caml_muxreg,
370 .nmuxregs = ARRAY_SIZE(caml_muxreg),
371 },
372};
373
374static struct spear_pingroup caml_pingroup = {
375 .name = "caml_grp",
376 .pins = caml_pins,
377 .npins = ARRAY_SIZE(caml_pins),
378 .modemuxs = caml_modemux,
379 .nmodemuxs = ARRAY_SIZE(caml_modemux),
380};
381
382/* camu_pins */
383static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 };
384static struct spear_muxreg camu_muxreg[] = {
385 {
386 .reg = PMX_CONFIG_REG,
387 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
388 .val = 0,
389 },
390};
391
392static struct spear_modemux camu_modemux[] = {
393 {
394 .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE,
395 .muxregs = camu_muxreg,
396 .nmuxregs = ARRAY_SIZE(camu_muxreg),
397 },
398};
399
400static struct spear_pingroup camu_pingroup = {
401 .name = "camu_grp",
402 .pins = camu_pins,
403 .npins = ARRAY_SIZE(camu_pins),
404 .modemuxs = camu_modemux,
405 .nmodemuxs = ARRAY_SIZE(camu_modemux),
406};
407
408static const char *const cam_grps[] = { "caml_grp", "camu_grp" };
409static struct spear_function cam_function = {
410 .name = "cam",
411 .groups = cam_grps,
412 .ngroups = ARRAY_SIZE(cam_grps),
413};
414
415/* dac_pins */
416static const unsigned dac_pins[] = { 43, 44 };
417static struct spear_muxreg dac_muxreg[] = {
418 {
419 .reg = PMX_CONFIG_REG,
420 .mask = PMX_TIMER_0_1_MASK,
421 .val = 0,
422 },
423};
424
425static struct spear_modemux dac_modemux[] = {
426 {
427 .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
428 | CAMU_WLCD_MODE | CAML_LCD_MODE,
429 .muxregs = dac_muxreg,
430 .nmuxregs = ARRAY_SIZE(dac_muxreg),
431 },
432};
433
434static struct spear_pingroup dac_pingroup = {
435 .name = "dac_grp",
436 .pins = dac_pins,
437 .npins = ARRAY_SIZE(dac_pins),
438 .modemuxs = dac_modemux,
439 .nmodemuxs = ARRAY_SIZE(dac_modemux),
440};
441
442static const char *const dac_grps[] = { "dac_grp" };
443static struct spear_function dac_function = {
444 .name = "dac",
445 .groups = dac_grps,
446 .ngroups = ARRAY_SIZE(dac_grps),
447};
448
449/* i2s_pins */
450static const unsigned i2s_pins[] = { 39, 40, 41, 42 };
451static struct spear_muxreg i2s_muxreg[] = {
452 {
453 .reg = PMX_CONFIG_REG,
454 .mask = PMX_UART0_MODEM_MASK,
455 .val = 0,
456 },
457};
458
459static struct spear_modemux i2s_modemux[] = {
460 {
461 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
462 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
463 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
464 | CAMU_WLCD_MODE | CAML_LCD_MODE,
465 .muxregs = i2s_muxreg,
466 .nmuxregs = ARRAY_SIZE(i2s_muxreg),
467 },
468};
469
470static struct spear_pingroup i2s_pingroup = {
471 .name = "i2s_grp",
472 .pins = i2s_pins,
473 .npins = ARRAY_SIZE(i2s_pins),
474 .modemuxs = i2s_modemux,
475 .nmodemuxs = ARRAY_SIZE(i2s_modemux),
476};
477
478static const char *const i2s_grps[] = { "i2s_grp" };
479static struct spear_function i2s_function = {
480 .name = "i2s",
481 .groups = i2s_grps,
482 .ngroups = ARRAY_SIZE(i2s_grps),
483};
484
485/* sdhci_4bit_pins */
486static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 };
487static struct spear_muxreg sdhci_4bit_muxreg[] = {
488 {
489 .reg = PMX_CONFIG_REG,
490 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
491 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
492 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
493 .val = 0,
494 },
495};
496
497static struct spear_modemux sdhci_4bit_modemux[] = {
498 {
499 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
500 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
501 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
502 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE,
503 .muxregs = sdhci_4bit_muxreg,
504 .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg),
505 },
506};
507
508static struct spear_pingroup sdhci_4bit_pingroup = {
509 .name = "sdhci_4bit_grp",
510 .pins = sdhci_4bit_pins,
511 .npins = ARRAY_SIZE(sdhci_4bit_pins),
512 .modemuxs = sdhci_4bit_modemux,
513 .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux),
514};
515
516/* sdhci_8bit_pins */
517static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
518 33 };
519static struct spear_muxreg sdhci_8bit_muxreg[] = {
520 {
521 .reg = PMX_CONFIG_REG,
522 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
523 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
524 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
525 .val = 0,
526 },
527};
528
529static struct spear_modemux sdhci_8bit_modemux[] = {
530 {
531 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
532 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
533 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
534 CAMU_WLCD_MODE | CAML_LCD_MODE,
535 .muxregs = sdhci_8bit_muxreg,
536 .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg),
537 },
538};
539
540static struct spear_pingroup sdhci_8bit_pingroup = {
541 .name = "sdhci_8bit_grp",
542 .pins = sdhci_8bit_pins,
543 .npins = ARRAY_SIZE(sdhci_8bit_pins),
544 .modemuxs = sdhci_8bit_modemux,
545 .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux),
546};
547
548static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" };
549static struct spear_function sdhci_function = {
550 .name = "sdhci",
551 .groups = sdhci_grps,
552 .ngroups = ARRAY_SIZE(sdhci_grps),
553};
554
555/* gpio1_0_to_3_pins */
556static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 };
557static struct spear_muxreg gpio1_0_to_3_muxreg[] = {
558 {
559 .reg = PMX_CONFIG_REG,
560 .mask = PMX_UART0_MODEM_MASK,
561 .val = 0,
562 },
563};
564
565static struct spear_modemux gpio1_0_to_3_modemux[] = {
566 {
567 .modes = PHOTO_FRAME_MODE,
568 .muxregs = gpio1_0_to_3_muxreg,
569 .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg),
570 },
571};
572
573static struct spear_pingroup gpio1_0_to_3_pingroup = {
574 .name = "gpio1_0_to_3_grp",
575 .pins = gpio1_0_to_3_pins,
576 .npins = ARRAY_SIZE(gpio1_0_to_3_pins),
577 .modemuxs = gpio1_0_to_3_modemux,
578 .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux),
579};
580
581/* gpio1_4_to_7_pins */
582static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 };
583
584static struct spear_muxreg gpio1_4_to_7_muxreg[] = {
585 {
586 .reg = PMX_CONFIG_REG,
587 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
588 .val = 0,
589 },
590};
591
592static struct spear_modemux gpio1_4_to_7_modemux[] = {
593 {
594 .modes = PHOTO_FRAME_MODE,
595 .muxregs = gpio1_4_to_7_muxreg,
596 .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg),
597 },
598};
599
600static struct spear_pingroup gpio1_4_to_7_pingroup = {
601 .name = "gpio1_4_to_7_grp",
602 .pins = gpio1_4_to_7_pins,
603 .npins = ARRAY_SIZE(gpio1_4_to_7_pins),
604 .modemuxs = gpio1_4_to_7_modemux,
605 .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux),
606};
607
608static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
609};
610static struct spear_function gpio1_function = {
611 .name = "gpio1",
612 .groups = gpio1_grps,
613 .ngroups = ARRAY_SIZE(gpio1_grps),
614};
615
616/* pingroups */
617static struct spear_pingroup *spear300_pingroups[] = {
618 SPEAR3XX_COMMON_PINGROUPS,
619 &fsmc_2chips_pingroup,
620 &fsmc_4chips_pingroup,
621 &clcd_lcdmode_pingroup,
622 &clcd_pfmode_pingroup,
623 &tdm_pingroup,
624 &i2c_clk_pingroup,
625 &caml_pingroup,
626 &camu_pingroup,
627 &dac_pingroup,
628 &i2s_pingroup,
629 &sdhci_4bit_pingroup,
630 &sdhci_8bit_pingroup,
631 &gpio1_0_to_3_pingroup,
632 &gpio1_4_to_7_pingroup,
633};
634
635/* functions */
636static struct spear_function *spear300_functions[] = {
637 SPEAR3XX_COMMON_FUNCTIONS,
638 &fsmc_function,
639 &clcd_function,
640 &tdm_function,
641 &i2c_function,
642 &cam_function,
643 &dac_function,
644 &i2s_function,
645 &sdhci_function,
646 &gpio1_function,
647};
648
649static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = {
650 {
651 .compatible = "st,spear300-pinmux",
652 },
653 {},
654};
655
656static int __devinit spear300_pinctrl_probe(struct platform_device *pdev)
657{
658 int ret;
659
660 spear3xx_machdata.groups = spear300_pingroups;
661 spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
662 spear3xx_machdata.functions = spear300_functions;
663 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
664
665 spear3xx_machdata.modes_supported = true;
666 spear3xx_machdata.pmx_modes = spear300_pmx_modes;
667 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes);
668
669 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
670
671 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
672 if (ret)
673 return ret;
674
675 return 0;
676}
677
678static int __devexit spear300_pinctrl_remove(struct platform_device *pdev)
679{
680 return spear_pinctrl_remove(pdev);
681}
682
683static struct platform_driver spear300_pinctrl_driver = {
684 .driver = {
685 .name = DRIVER_NAME,
686 .owner = THIS_MODULE,
687 .of_match_table = spear300_pinctrl_of_match,
688 },
689 .probe = spear300_pinctrl_probe,
690 .remove = __devexit_p(spear300_pinctrl_remove),
691};
692
693static int __init spear300_pinctrl_init(void)
694{
695 return platform_driver_register(&spear300_pinctrl_driver);
696}
697arch_initcall(spear300_pinctrl_init);
698
699static void __exit spear300_pinctrl_exit(void)
700{
701 platform_driver_unregister(&spear300_pinctrl_driver);
702}
703module_exit(spear300_pinctrl_exit);
704
705MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
706MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver");
707MODULE_LICENSE("GPL v2");
708MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c
new file mode 100644
index 00000000000..1a970760512
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear310.c
@@ -0,0 +1,431 @@
1/*
2 * Driver for the ST Microelectronics SPEAr310 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear310-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG 0x08
23
24/* emi_cs_0_to_5_pins */
25static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
26static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
27 {
28 .reg = PMX_CONFIG_REG,
29 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
30 .val = 0,
31 },
32};
33
34static struct spear_modemux emi_cs_0_to_5_modemux[] = {
35 {
36 .muxregs = emi_cs_0_to_5_muxreg,
37 .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
38 },
39};
40
41static struct spear_pingroup emi_cs_0_to_5_pingroup = {
42 .name = "emi_cs_0_to_5_grp",
43 .pins = emi_cs_0_to_5_pins,
44 .npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
45 .modemuxs = emi_cs_0_to_5_modemux,
46 .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
47};
48
49static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
50static struct spear_function emi_cs_0_to_5_function = {
51 .name = "emi",
52 .groups = emi_cs_0_to_5_grps,
53 .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
54};
55
56/* uart1_pins */
57static const unsigned uart1_pins[] = { 0, 1 };
58static struct spear_muxreg uart1_muxreg[] = {
59 {
60 .reg = PMX_CONFIG_REG,
61 .mask = PMX_FIRDA_MASK,
62 .val = 0,
63 },
64};
65
66static struct spear_modemux uart1_modemux[] = {
67 {
68 .muxregs = uart1_muxreg,
69 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
70 },
71};
72
73static struct spear_pingroup uart1_pingroup = {
74 .name = "uart1_grp",
75 .pins = uart1_pins,
76 .npins = ARRAY_SIZE(uart1_pins),
77 .modemuxs = uart1_modemux,
78 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
79};
80
81static const char *const uart1_grps[] = { "uart1_grp" };
82static struct spear_function uart1_function = {
83 .name = "uart1",
84 .groups = uart1_grps,
85 .ngroups = ARRAY_SIZE(uart1_grps),
86};
87
88/* uart2_pins */
89static const unsigned uart2_pins[] = { 43, 44 };
90static struct spear_muxreg uart2_muxreg[] = {
91 {
92 .reg = PMX_CONFIG_REG,
93 .mask = PMX_TIMER_0_1_MASK,
94 .val = 0,
95 },
96};
97
98static struct spear_modemux uart2_modemux[] = {
99 {
100 .muxregs = uart2_muxreg,
101 .nmuxregs = ARRAY_SIZE(uart2_muxreg),
102 },
103};
104
105static struct spear_pingroup uart2_pingroup = {
106 .name = "uart2_grp",
107 .pins = uart2_pins,
108 .npins = ARRAY_SIZE(uart2_pins),
109 .modemuxs = uart2_modemux,
110 .nmodemuxs = ARRAY_SIZE(uart2_modemux),
111};
112
113static const char *const uart2_grps[] = { "uart2_grp" };
114static struct spear_function uart2_function = {
115 .name = "uart2",
116 .groups = uart2_grps,
117 .ngroups = ARRAY_SIZE(uart2_grps),
118};
119
120/* uart3_pins */
121static const unsigned uart3_pins[] = { 37, 38 };
122static struct spear_muxreg uart3_muxreg[] = {
123 {
124 .reg = PMX_CONFIG_REG,
125 .mask = PMX_UART0_MODEM_MASK,
126 .val = 0,
127 },
128};
129
130static struct spear_modemux uart3_modemux[] = {
131 {
132 .muxregs = uart3_muxreg,
133 .nmuxregs = ARRAY_SIZE(uart3_muxreg),
134 },
135};
136
137static struct spear_pingroup uart3_pingroup = {
138 .name = "uart3_grp",
139 .pins = uart3_pins,
140 .npins = ARRAY_SIZE(uart3_pins),
141 .modemuxs = uart3_modemux,
142 .nmodemuxs = ARRAY_SIZE(uart3_modemux),
143};
144
145static const char *const uart3_grps[] = { "uart3_grp" };
146static struct spear_function uart3_function = {
147 .name = "uart3",
148 .groups = uart3_grps,
149 .ngroups = ARRAY_SIZE(uart3_grps),
150};
151
152/* uart4_pins */
153static const unsigned uart4_pins[] = { 39, 40 };
154static struct spear_muxreg uart4_muxreg[] = {
155 {
156 .reg = PMX_CONFIG_REG,
157 .mask = PMX_UART0_MODEM_MASK,
158 .val = 0,
159 },
160};
161
162static struct spear_modemux uart4_modemux[] = {
163 {
164 .muxregs = uart4_muxreg,
165 .nmuxregs = ARRAY_SIZE(uart4_muxreg),
166 },
167};
168
169static struct spear_pingroup uart4_pingroup = {
170 .name = "uart4_grp",
171 .pins = uart4_pins,
172 .npins = ARRAY_SIZE(uart4_pins),
173 .modemuxs = uart4_modemux,
174 .nmodemuxs = ARRAY_SIZE(uart4_modemux),
175};
176
177static const char *const uart4_grps[] = { "uart4_grp" };
178static struct spear_function uart4_function = {
179 .name = "uart4",
180 .groups = uart4_grps,
181 .ngroups = ARRAY_SIZE(uart4_grps),
182};
183
184/* uart5_pins */
185static const unsigned uart5_pins[] = { 41, 42 };
186static struct spear_muxreg uart5_muxreg[] = {
187 {
188 .reg = PMX_CONFIG_REG,
189 .mask = PMX_UART0_MODEM_MASK,
190 .val = 0,
191 },
192};
193
194static struct spear_modemux uart5_modemux[] = {
195 {
196 .muxregs = uart5_muxreg,
197 .nmuxregs = ARRAY_SIZE(uart5_muxreg),
198 },
199};
200
201static struct spear_pingroup uart5_pingroup = {
202 .name = "uart5_grp",
203 .pins = uart5_pins,
204 .npins = ARRAY_SIZE(uart5_pins),
205 .modemuxs = uart5_modemux,
206 .nmodemuxs = ARRAY_SIZE(uart5_modemux),
207};
208
209static const char *const uart5_grps[] = { "uart5_grp" };
210static struct spear_function uart5_function = {
211 .name = "uart5",
212 .groups = uart5_grps,
213 .ngroups = ARRAY_SIZE(uart5_grps),
214};
215
216/* fsmc_pins */
217static const unsigned fsmc_pins[] = { 34, 35, 36 };
218static struct spear_muxreg fsmc_muxreg[] = {
219 {
220 .reg = PMX_CONFIG_REG,
221 .mask = PMX_SSP_CS_MASK,
222 .val = 0,
223 },
224};
225
226static struct spear_modemux fsmc_modemux[] = {
227 {
228 .muxregs = fsmc_muxreg,
229 .nmuxregs = ARRAY_SIZE(fsmc_muxreg),
230 },
231};
232
233static struct spear_pingroup fsmc_pingroup = {
234 .name = "fsmc_grp",
235 .pins = fsmc_pins,
236 .npins = ARRAY_SIZE(fsmc_pins),
237 .modemuxs = fsmc_modemux,
238 .nmodemuxs = ARRAY_SIZE(fsmc_modemux),
239};
240
241static const char *const fsmc_grps[] = { "fsmc_grp" };
242static struct spear_function fsmc_function = {
243 .name = "fsmc",
244 .groups = fsmc_grps,
245 .ngroups = ARRAY_SIZE(fsmc_grps),
246};
247
248/* rs485_0_pins */
249static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
250static struct spear_muxreg rs485_0_muxreg[] = {
251 {
252 .reg = PMX_CONFIG_REG,
253 .mask = PMX_MII_MASK,
254 .val = 0,
255 },
256};
257
258static struct spear_modemux rs485_0_modemux[] = {
259 {
260 .muxregs = rs485_0_muxreg,
261 .nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
262 },
263};
264
265static struct spear_pingroup rs485_0_pingroup = {
266 .name = "rs485_0_grp",
267 .pins = rs485_0_pins,
268 .npins = ARRAY_SIZE(rs485_0_pins),
269 .modemuxs = rs485_0_modemux,
270 .nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
271};
272
273static const char *const rs485_0_grps[] = { "rs485_0" };
274static struct spear_function rs485_0_function = {
275 .name = "rs485_0",
276 .groups = rs485_0_grps,
277 .ngroups = ARRAY_SIZE(rs485_0_grps),
278};
279
280/* rs485_1_pins */
281static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
282static struct spear_muxreg rs485_1_muxreg[] = {
283 {
284 .reg = PMX_CONFIG_REG,
285 .mask = PMX_MII_MASK,
286 .val = 0,
287 },
288};
289
290static struct spear_modemux rs485_1_modemux[] = {
291 {
292 .muxregs = rs485_1_muxreg,
293 .nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
294 },
295};
296
297static struct spear_pingroup rs485_1_pingroup = {
298 .name = "rs485_1_grp",
299 .pins = rs485_1_pins,
300 .npins = ARRAY_SIZE(rs485_1_pins),
301 .modemuxs = rs485_1_modemux,
302 .nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
303};
304
305static const char *const rs485_1_grps[] = { "rs485_1" };
306static struct spear_function rs485_1_function = {
307 .name = "rs485_1",
308 .groups = rs485_1_grps,
309 .ngroups = ARRAY_SIZE(rs485_1_grps),
310};
311
312/* tdm_pins */
313static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
314static struct spear_muxreg tdm_muxreg[] = {
315 {
316 .reg = PMX_CONFIG_REG,
317 .mask = PMX_MII_MASK,
318 .val = 0,
319 },
320};
321
322static struct spear_modemux tdm_modemux[] = {
323 {
324 .muxregs = tdm_muxreg,
325 .nmuxregs = ARRAY_SIZE(tdm_muxreg),
326 },
327};
328
329static struct spear_pingroup tdm_pingroup = {
330 .name = "tdm_grp",
331 .pins = tdm_pins,
332 .npins = ARRAY_SIZE(tdm_pins),
333 .modemuxs = tdm_modemux,
334 .nmodemuxs = ARRAY_SIZE(tdm_modemux),
335};
336
337static const char *const tdm_grps[] = { "tdm_grp" };
338static struct spear_function tdm_function = {
339 .name = "tdm",
340 .groups = tdm_grps,
341 .ngroups = ARRAY_SIZE(tdm_grps),
342};
343
344/* pingroups */
345static struct spear_pingroup *spear310_pingroups[] = {
346 SPEAR3XX_COMMON_PINGROUPS,
347 &emi_cs_0_to_5_pingroup,
348 &uart1_pingroup,
349 &uart2_pingroup,
350 &uart3_pingroup,
351 &uart4_pingroup,
352 &uart5_pingroup,
353 &fsmc_pingroup,
354 &rs485_0_pingroup,
355 &rs485_1_pingroup,
356 &tdm_pingroup,
357};
358
359/* functions */
360static struct spear_function *spear310_functions[] = {
361 SPEAR3XX_COMMON_FUNCTIONS,
362 &emi_cs_0_to_5_function,
363 &uart1_function,
364 &uart2_function,
365 &uart3_function,
366 &uart4_function,
367 &uart5_function,
368 &fsmc_function,
369 &rs485_0_function,
370 &rs485_1_function,
371 &tdm_function,
372};
373
374static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = {
375 {
376 .compatible = "st,spear310-pinmux",
377 },
378 {},
379};
380
381static int __devinit spear310_pinctrl_probe(struct platform_device *pdev)
382{
383 int ret;
384
385 spear3xx_machdata.groups = spear310_pingroups;
386 spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
387 spear3xx_machdata.functions = spear310_functions;
388 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
389
390 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
391
392 spear3xx_machdata.modes_supported = false;
393
394 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
395 if (ret)
396 return ret;
397
398 return 0;
399}
400
401static int __devexit spear310_pinctrl_remove(struct platform_device *pdev)
402{
403 return spear_pinctrl_remove(pdev);
404}
405
406static struct platform_driver spear310_pinctrl_driver = {
407 .driver = {
408 .name = DRIVER_NAME,
409 .owner = THIS_MODULE,
410 .of_match_table = spear310_pinctrl_of_match,
411 },
412 .probe = spear310_pinctrl_probe,
413 .remove = __devexit_p(spear310_pinctrl_remove),
414};
415
416static int __init spear310_pinctrl_init(void)
417{
418 return platform_driver_register(&spear310_pinctrl_driver);
419}
420arch_initcall(spear310_pinctrl_init);
421
422static void __exit spear310_pinctrl_exit(void)
423{
424 platform_driver_unregister(&spear310_pinctrl_driver);
425}
426module_exit(spear310_pinctrl_exit);
427
428MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
429MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver");
430MODULE_LICENSE("GPL v2");
431MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c
new file mode 100644
index 00000000000..de726e6c283
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear320.c
@@ -0,0 +1,3468 @@
1/*
2 * Driver for the ST Microelectronics SPEAr320 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear320-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG 0x0C
23#define MODE_CONFIG_REG 0x10
24#define MODE_EXT_CONFIG_REG 0x18
25
26/* modes */
27#define AUTO_NET_SMII_MODE (1 << 0)
28#define AUTO_NET_MII_MODE (1 << 1)
29#define AUTO_EXP_MODE (1 << 2)
30#define SMALL_PRINTERS_MODE (1 << 3)
31#define EXTENDED_MODE (1 << 4)
32
33static struct spear_pmx_mode pmx_mode_auto_net_smii = {
34 .name = "Automation Networking SMII mode",
35 .mode = AUTO_NET_SMII_MODE,
36 .reg = MODE_CONFIG_REG,
37 .mask = 0x00000007,
38 .val = 0x0,
39};
40
41static struct spear_pmx_mode pmx_mode_auto_net_mii = {
42 .name = "Automation Networking MII mode",
43 .mode = AUTO_NET_MII_MODE,
44 .reg = MODE_CONFIG_REG,
45 .mask = 0x00000007,
46 .val = 0x1,
47};
48
49static struct spear_pmx_mode pmx_mode_auto_exp = {
50 .name = "Automation Expanded mode",
51 .mode = AUTO_EXP_MODE,
52 .reg = MODE_CONFIG_REG,
53 .mask = 0x00000007,
54 .val = 0x2,
55};
56
57static struct spear_pmx_mode pmx_mode_small_printers = {
58 .name = "Small Printers mode",
59 .mode = SMALL_PRINTERS_MODE,
60 .reg = MODE_CONFIG_REG,
61 .mask = 0x00000007,
62 .val = 0x3,
63};
64
65static struct spear_pmx_mode pmx_mode_extended = {
66 .name = "extended mode",
67 .mode = EXTENDED_MODE,
68 .reg = MODE_EXT_CONFIG_REG,
69 .mask = 0x00000001,
70 .val = 0x1,
71};
72
73static struct spear_pmx_mode *spear320_pmx_modes[] = {
74 &pmx_mode_auto_net_smii,
75 &pmx_mode_auto_net_mii,
76 &pmx_mode_auto_exp,
77 &pmx_mode_small_printers,
78 &pmx_mode_extended,
79};
80
81/* Extended mode registers and their offsets */
82#define EXT_CTRL_REG 0x0018
83 #define MII_MDIO_MASK (1 << 4)
84 #define MII_MDIO_10_11_VAL 0
85 #define MII_MDIO_81_VAL (1 << 4)
86 #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5)
87 #define MAC_MODE_MII 0
88 #define MAC_MODE_RMII 1
89 #define MAC_MODE_SMII 2
90 #define MAC_MODE_SS_SMII 3
91 #define MAC_MODE_MASK 0x3
92 #define MAC1_MODE_SHIFT 16
93 #define MAC2_MODE_SHIFT 18
94
95#define IP_SEL_PAD_0_9_REG 0x00A4
96 #define PMX_PL_0_1_MASK (0x3F << 0)
97 #define PMX_UART2_PL_0_1_VAL 0x0
98 #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3))
99
100 #define PMX_PL_2_3_MASK (0x3F << 6)
101 #define PMX_I2C2_PL_2_3_VAL 0x0
102 #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9))
103 #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9))
104
105 #define PMX_PL_4_5_MASK (0x3F << 12)
106 #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15))
107 #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15))
108 #define PMX_PL_5_MASK (0x7 << 15)
109 #define PMX_TOUCH_Y_PL_5_VAL 0x0
110
111 #define PMX_PL_6_7_MASK (0x3F << 18)
112 #define PMX_PL_6_MASK (0x7 << 18)
113 #define PMX_PL_7_MASK (0x7 << 21)
114 #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21))
115 #define PMX_PWM_3_PL_6_VAL (0x2 << 18)
116 #define PMX_PWM_2_PL_7_VAL (0x2 << 21)
117 #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21))
118
119 #define PMX_PL_8_9_MASK (0x3F << 24)
120 #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27))
121 #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
122 #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27))
123
124#define IP_SEL_PAD_10_19_REG 0x00A8
125 #define PMX_PL_10_11_MASK (0x3F << 0)
126 #define PMX_SMII_PL_10_11_VAL 0
127 #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3))
128
129 #define PMX_PL_12_MASK (0x7 << 6)
130 #define PMX_PWM3_PL_12_VAL 0
131 #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6)
132
133 #define PMX_PL_13_14_MASK (0x3F << 9)
134 #define PMX_PL_13_MASK (0x7 << 9)
135 #define PMX_PL_14_MASK (0x7 << 12)
136 #define PMX_SSP2_PL_13_14_15_16_VAL 0
137 #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12))
138 #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12))
139 #define PMX_PWM2_PL_13_VAL (0x2 << 9)
140 #define PMX_PWM1_PL_14_VAL (0x2 << 12)
141
142 #define PMX_PL_15_MASK (0x7 << 15)
143 #define PMX_PWM0_PL_15_VAL (0x2 << 15)
144 #define PMX_PL_15_16_MASK (0x3F << 15)
145 #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18))
146 #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18))
147
148 #define PMX_PL_17_18_MASK (0x3F << 21)
149 #define PMX_SSP1_PL_17_18_19_20_VAL 0
150 #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24))
151
152 #define PMX_PL_19_MASK (0x7 << 27)
153 #define PMX_I2C2_PL_19_VAL (0x1 << 27)
154 #define PMX_RMII_PL_19_VAL (0x4 << 27)
155
156#define IP_SEL_PAD_20_29_REG 0x00AC
157 #define PMX_PL_20_MASK (0x7 << 0)
158 #define PMX_I2C2_PL_20_VAL (0x1 << 0)
159 #define PMX_RMII_PL_20_VAL (0x4 << 0)
160
161 #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3)
162 #define PMX_SMII_PL_21_TO_27_VAL 0
163 #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
164
165 #define PMX_PL_28_29_MASK (0x3F << 24)
166 #define PMX_PL_28_MASK (0x7 << 24)
167 #define PMX_PL_29_MASK (0x7 << 27)
168 #define PMX_UART1_PL_28_29_VAL 0
169 #define PMX_PWM_3_PL_28_VAL (0x4 << 24)
170 #define PMX_PWM_2_PL_29_VAL (0x4 << 27)
171
172#define IP_SEL_PAD_30_39_REG 0x00B0
173 #define PMX_PL_30_31_MASK (0x3F << 0)
174 #define PMX_CAN1_PL_30_31_VAL (0)
175 #define PMX_PL_30_MASK (0x7 << 0)
176 #define PMX_PL_31_MASK (0x7 << 3)
177 #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0)
178 #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3)
179 #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3)
180
181 #define PMX_PL_32_33_MASK (0x3F << 6)
182 #define PMX_CAN0_PL_32_33_VAL 0
183 #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9))
184 #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9))
185
186 #define PMX_PL_34_MASK (0x7 << 12)
187 #define PMX_PWM2_PL_34_VAL 0
188 #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
189 #define PMX_SSP2_PL_34_VAL (0x4 << 12)
190
191 #define PMX_PL_35_MASK (0x7 << 15)
192 #define PMX_I2S_REF_CLK_PL_35_VAL 0
193 #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
194 #define PMX_SSP2_PL_35_VAL (0x4 << 15)
195
196 #define PMX_PL_36_MASK (0x7 << 18)
197 #define PMX_TOUCH_X_PL_36_VAL 0
198 #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
199 #define PMX_SSP1_PL_36_VAL (0x4 << 18)
200
201 #define PMX_PL_37_38_MASK (0x3F << 21)
202 #define PMX_PWM0_1_PL_37_38_VAL 0
203 #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
204 #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24))
205
206 #define PMX_PL_39_MASK (0x7 << 27)
207 #define PMX_I2S_PL_39_VAL 0
208 #define PMX_UART4_PL_39_VAL (0x2 << 27)
209 #define PMX_SSP1_PL_39_VAL (0x4 << 27)
210
211#define IP_SEL_PAD_40_49_REG 0x00B4
212 #define PMX_PL_40_MASK (0x7 << 0)
213 #define PMX_I2S_PL_40_VAL 0
214 #define PMX_UART4_PL_40_VAL (0x2 << 0)
215 #define PMX_PWM3_PL_40_VAL (0x4 << 0)
216
217 #define PMX_PL_41_42_MASK (0x3F << 3)
218 #define PMX_PL_41_MASK (0x7 << 3)
219 #define PMX_PL_42_MASK (0x7 << 6)
220 #define PMX_I2S_PL_41_42_VAL 0
221 #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
222 #define PMX_PWM2_PL_41_VAL (0x4 << 3)
223 #define PMX_PWM1_PL_42_VAL (0x4 << 6)
224
225 #define PMX_PL_43_MASK (0x7 << 9)
226 #define PMX_SDHCI_PL_43_VAL 0
227 #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
228 #define PMX_PWM0_PL_43_VAL (0x4 << 9)
229
230 #define PMX_PL_44_45_MASK (0x3F << 12)
231 #define PMX_SDHCI_PL_44_45_VAL 0
232 #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
233 #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15))
234
235 #define PMX_PL_46_47_MASK (0x3F << 18)
236 #define PMX_SDHCI_PL_46_47_VAL 0
237 #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
238 #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21))
239
240 #define PMX_PL_48_49_MASK (0x3F << 24)
241 #define PMX_SDHCI_PL_48_49_VAL 0
242 #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
243 #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27))
244
245#define IP_SEL_PAD_50_59_REG 0x00B8
246 #define PMX_PL_50_51_MASK (0x3F << 0)
247 #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
248 #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3))
249 #define PMX_PL_50_MASK (0x7 << 0)
250 #define PMX_PL_51_MASK (0x7 << 3)
251 #define PMX_SDHCI_PL_50_VAL 0
252 #define PMX_SDHCI_CD_PL_51_VAL 0
253
254 #define PMX_PL_52_53_MASK (0x3F << 6)
255 #define PMX_FSMC_PL_52_53_VAL 0
256 #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
257 #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9))
258
259 #define PMX_PL_54_55_56_MASK (0x1FF << 12)
260 #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
261
262 #define PMX_PL_57_MASK (0x7 << 21)
263 #define PMX_FSMC_PL_57_VAL 0
264 #define PMX_PWM3_PL_57_VAL (0x4 << 21)
265
266 #define PMX_PL_58_59_MASK (0x3F << 24)
267 #define PMX_PL_58_MASK (0x7 << 24)
268 #define PMX_PL_59_MASK (0x7 << 27)
269 #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
270 #define PMX_PWM2_PL_58_VAL (0x4 << 24)
271 #define PMX_PWM1_PL_59_VAL (0x4 << 27)
272
273#define IP_SEL_PAD_60_69_REG 0x00BC
274 #define PMX_PL_60_MASK (0x7 << 0)
275 #define PMX_FSMC_PL_60_VAL 0
276 #define PMX_PWM0_PL_60_VAL (0x4 << 0)
277
278 #define PMX_PL_61_TO_64_MASK (0xFFF << 3)
279 #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
280 #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
281
282 #define PMX_PL_65_TO_68_MASK (0xFFF << 15)
283 #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
284 #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
285
286 #define PMX_PL_69_MASK (0x7 << 27)
287 #define PMX_CLCD_PL_69_VAL (0)
288 #define PMX_EMI_PL_69_VAL (0x2 << 27)
289 #define PMX_SPP_PL_69_VAL (0x3 << 27)
290 #define PMX_UART5_PL_69_VAL (0x4 << 27)
291
292#define IP_SEL_PAD_70_79_REG 0x00C0
293 #define PMX_PL_70_MASK (0x7 << 0)
294 #define PMX_CLCD_PL_70_VAL (0)
295 #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
296 #define PMX_SPP_PL_70_VAL (0x3 << 0)
297 #define PMX_UART5_PL_70_VAL (0x4 << 0)
298
299 #define PMX_PL_71_72_MASK (0x3F << 3)
300 #define PMX_CLCD_PL_71_72_VAL (0)
301 #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
302 #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6))
303 #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6))
304
305 #define PMX_PL_73_MASK (0x7 << 9)
306 #define PMX_CLCD_PL_73_VAL (0)
307 #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
308 #define PMX_SPP_PL_73_VAL (0x3 << 9)
309 #define PMX_UART3_PL_73_VAL (0x4 << 9)
310
311 #define PMX_PL_74_MASK (0x7 << 12)
312 #define PMX_CLCD_PL_74_VAL (0)
313 #define PMX_EMI_PL_74_VAL (0x2 << 12)
314 #define PMX_SPP_PL_74_VAL (0x3 << 12)
315 #define PMX_UART3_PL_74_VAL (0x4 << 12)
316
317 #define PMX_PL_75_76_MASK (0x3F << 15)
318 #define PMX_CLCD_PL_75_76_VAL (0)
319 #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
320 #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18))
321 #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18))
322
323 #define PMX_PL_77_78_79_MASK (0x1FF << 21)
324 #define PMX_CLCD_PL_77_78_79_VAL (0)
325 #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
326 #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
327 #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
328
329#define IP_SEL_PAD_80_89_REG 0x00C4
330 #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0)
331 #define PMX_CLCD_PL_80_TO_85_VAL 0
332 #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
333 #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
334 #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
335 #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
336
337 #define PMX_PL_86_87_MASK (0x3F << 18)
338 #define PMX_PL_86_MASK (0x7 << 18)
339 #define PMX_PL_87_MASK (0x7 << 21)
340 #define PMX_CLCD_PL_86_87_VAL 0
341 #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21))
342 #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
343 #define PMX_PWM3_PL_86_VAL (0x4 << 18)
344 #define PMX_PWM2_PL_87_VAL (0x4 << 21)
345
346 #define PMX_PL_88_89_MASK (0x3F << 24)
347 #define PMX_CLCD_PL_88_89_VAL 0
348 #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27))
349 #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
350 #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27))
351 #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27))
352
353#define IP_SEL_PAD_90_99_REG 0x00C8
354 #define PMX_PL_90_91_MASK (0x3F << 0)
355 #define PMX_CLCD_PL_90_91_VAL 0
356 #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3))
357 #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
358 #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3))
359 #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3))
360
361 #define PMX_PL_92_93_MASK (0x3F << 6)
362 #define PMX_CLCD_PL_92_93_VAL 0
363 #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9))
364 #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
365 #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9))
366 #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9))
367
368 #define PMX_PL_94_95_MASK (0x3F << 12)
369 #define PMX_CLCD_PL_94_95_VAL 0
370 #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15))
371 #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
372 #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15))
373 #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15))
374
375 #define PMX_PL_96_97_MASK (0x3F << 18)
376 #define PMX_CLCD_PL_96_97_VAL 0
377 #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21))
378 #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
379 #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21))
380 #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21))
381
382 #define PMX_PL_98_MASK (0x7 << 24)
383 #define PMX_CLCD_PL_98_VAL 0
384 #define PMX_I2C1_PL_98_VAL (0x2 << 24)
385 #define PMX_UART3_PL_98_VAL (0x4 << 24)
386
387 #define PMX_PL_99_MASK (0x7 << 27)
388 #define PMX_SDHCI_PL_99_VAL 0
389 #define PMX_I2C1_PL_99_VAL (0x2 << 27)
390 #define PMX_UART3_PL_99_VAL (0x4 << 27)
391
392#define IP_SEL_MIX_PAD_REG 0x00CC
393 #define PMX_PL_100_101_MASK (0x3F << 0)
394 #define PMX_SDHCI_PL_100_101_VAL 0
395 #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3))
396
397 #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8)
398 #define PMX_SSP1_PORT_94_TO_97_VAL 0
399 #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8)
400 #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
401 #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8)
402 #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8)
403
404 #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11)
405 #define PMX_SSP2_PORT_90_TO_93_VAL 0
406 #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11)
407 #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
408 #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11)
409 #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11)
410
411 #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14)
412 #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0
413 #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14)
414 #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
415 #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14)
416
417 #define PMX_UART3_PORT_SEL_MASK (0x7 << 16)
418 #define PMX_UART3_PORT_94_VAL 0
419 #define PMX_UART3_PORT_73_VAL (0x1 << 16)
420 #define PMX_UART3_PORT_52_VAL (0x2 << 16)
421 #define PMX_UART3_PORT_41_VAL (0x3 << 16)
422 #define PMX_UART3_PORT_15_VAL (0x4 << 16)
423 #define PMX_UART3_PORT_8_VAL (0x5 << 16)
424 #define PMX_UART3_PORT_99_VAL (0x6 << 16)
425
426 #define PMX_UART4_PORT_SEL_MASK (0x7 << 19)
427 #define PMX_UART4_PORT_92_VAL 0
428 #define PMX_UART4_PORT_71_VAL (0x1 << 19)
429 #define PMX_UART4_PORT_39_VAL (0x2 << 19)
430 #define PMX_UART4_PORT_13_VAL (0x3 << 19)
431 #define PMX_UART4_PORT_6_VAL (0x4 << 19)
432 #define PMX_UART4_PORT_101_VAL (0x5 << 19)
433
434 #define PMX_UART5_PORT_SEL_MASK (0x3 << 22)
435 #define PMX_UART5_PORT_90_VAL 0
436 #define PMX_UART5_PORT_69_VAL (0x1 << 22)
437 #define PMX_UART5_PORT_37_VAL (0x2 << 22)
438 #define PMX_UART5_PORT_4_VAL (0x3 << 22)
439
440 #define PMX_UART6_PORT_SEL_MASK (0x1 << 24)
441 #define PMX_UART6_PORT_88_VAL 0
442 #define PMX_UART6_PORT_2_VAL (0x1 << 24)
443
444 #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25)
445 #define PMX_I2C1_PORT_8_9_VAL 0
446 #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25)
447
448 #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26)
449 #define PMX_I2C2_PORT_96_97_VAL 0
450 #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26)
451 #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
452 #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26)
453 #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26)
454
455 #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29)
456 #define PMX_SDHCI_CD_PORT_12_VAL 0
457 #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
458
459/* Pad multiplexing for CLCD device */
460static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
461 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
462 97 };
463static struct spear_muxreg clcd_muxreg[] = {
464 {
465 .reg = IP_SEL_PAD_60_69_REG,
466 .mask = PMX_PL_69_MASK,
467 .val = PMX_CLCD_PL_69_VAL,
468 }, {
469 .reg = IP_SEL_PAD_70_79_REG,
470 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
471 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
472 PMX_PL_77_78_79_MASK,
473 .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
474 PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
475 PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
476 }, {
477 .reg = IP_SEL_PAD_80_89_REG,
478 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
479 PMX_PL_88_89_MASK,
480 .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
481 PMX_CLCD_PL_88_89_VAL,
482 }, {
483 .reg = IP_SEL_PAD_90_99_REG,
484 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
485 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
486 .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
487 PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
488 PMX_CLCD_PL_98_VAL,
489 },
490};
491
492static struct spear_modemux clcd_modemux[] = {
493 {
494 .modes = EXTENDED_MODE,
495 .muxregs = clcd_muxreg,
496 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
497 },
498};
499
500static struct spear_pingroup clcd_pingroup = {
501 .name = "clcd_grp",
502 .pins = clcd_pins,
503 .npins = ARRAY_SIZE(clcd_pins),
504 .modemuxs = clcd_modemux,
505 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
506};
507
508static const char *const clcd_grps[] = { "clcd_grp" };
509static struct spear_function clcd_function = {
510 .name = "clcd",
511 .groups = clcd_grps,
512 .ngroups = ARRAY_SIZE(clcd_grps),
513};
514
515/* Pad multiplexing for EMI (Parallel NOR flash) device */
516static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
517 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
518 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
519 93, 94, 95, 96, 97 };
520static struct spear_muxreg emi_muxreg[] = {
521 {
522 .reg = PMX_CONFIG_REG,
523 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
524 .val = 0,
525 },
526};
527
528static struct spear_muxreg emi_ext_muxreg[] = {
529 {
530 .reg = IP_SEL_PAD_40_49_REG,
531 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
532 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
533 }, {
534 .reg = IP_SEL_PAD_50_59_REG,
535 .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
536 PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
537 .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
538 PMX_FSMC_EMI_PL_54_55_56_VAL |
539 PMX_FSMC_EMI_PL_58_59_VAL,
540 }, {
541 .reg = IP_SEL_PAD_60_69_REG,
542 .mask = PMX_PL_69_MASK,
543 .val = PMX_EMI_PL_69_VAL,
544 }, {
545 .reg = IP_SEL_PAD_70_79_REG,
546 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
547 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
548 PMX_PL_77_78_79_MASK,
549 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
550 PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
551 PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
552 }, {
553 .reg = IP_SEL_PAD_80_89_REG,
554 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
555 PMX_PL_88_89_MASK,
556 .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
557 PMX_EMI_PL_88_89_VAL,
558 }, {
559 .reg = IP_SEL_PAD_90_99_REG,
560 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
561 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
562 .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
563 PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
564 }, {
565 .reg = EXT_CTRL_REG,
566 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
567 .val = EMI_FSMC_DYNAMIC_MUX_MASK,
568 },
569};
570
571static struct spear_modemux emi_modemux[] = {
572 {
573 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
574 .muxregs = emi_muxreg,
575 .nmuxregs = ARRAY_SIZE(emi_muxreg),
576 }, {
577 .modes = EXTENDED_MODE,
578 .muxregs = emi_ext_muxreg,
579 .nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
580 },
581};
582
583static struct spear_pingroup emi_pingroup = {
584 .name = "emi_grp",
585 .pins = emi_pins,
586 .npins = ARRAY_SIZE(emi_pins),
587 .modemuxs = emi_modemux,
588 .nmodemuxs = ARRAY_SIZE(emi_modemux),
589};
590
591static const char *const emi_grps[] = { "emi_grp" };
592static struct spear_function emi_function = {
593 .name = "emi",
594 .groups = emi_grps,
595 .ngroups = ARRAY_SIZE(emi_grps),
596};
597
598/* Pad multiplexing for FSMC (NAND flash) device */
599static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
600 61, 62, 63, 64, 65, 66, 67, 68 };
601static struct spear_muxreg fsmc_8bit_muxreg[] = {
602 {
603 .reg = IP_SEL_PAD_50_59_REG,
604 .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
605 PMX_PL_57_MASK | PMX_PL_58_59_MASK,
606 .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
607 PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
608 }, {
609 .reg = IP_SEL_PAD_60_69_REG,
610 .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
611 PMX_PL_65_TO_68_MASK,
612 .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
613 PMX_FSMC_PL_65_TO_68_VAL,
614 }, {
615 .reg = EXT_CTRL_REG,
616 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
617 .val = EMI_FSMC_DYNAMIC_MUX_MASK,
618 },
619};
620
621static struct spear_modemux fsmc_8bit_modemux[] = {
622 {
623 .modes = EXTENDED_MODE,
624 .muxregs = fsmc_8bit_muxreg,
625 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
626 },
627};
628
629static struct spear_pingroup fsmc_8bit_pingroup = {
630 .name = "fsmc_8bit_grp",
631 .pins = fsmc_8bit_pins,
632 .npins = ARRAY_SIZE(fsmc_8bit_pins),
633 .modemuxs = fsmc_8bit_modemux,
634 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
635};
636
637static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
638 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
639static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
640 {
641 .reg = PMX_CONFIG_REG,
642 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
643 .val = 0,
644 },
645};
646
647static struct spear_muxreg fsmc_16bit_muxreg[] = {
648 {
649 .reg = IP_SEL_PAD_40_49_REG,
650 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
651 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
652 }, {
653 .reg = IP_SEL_PAD_70_79_REG,
654 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
655 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
656 PMX_FSMC_EMI_PL_73_VAL,
657 }
658};
659
660static struct spear_modemux fsmc_16bit_modemux[] = {
661 {
662 .modes = EXTENDED_MODE,
663 .muxregs = fsmc_8bit_muxreg,
664 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
665 }, {
666 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
667 .muxregs = fsmc_16bit_autoexp_muxreg,
668 .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
669 }, {
670 .modes = EXTENDED_MODE,
671 .muxregs = fsmc_16bit_muxreg,
672 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
673 },
674};
675
676static struct spear_pingroup fsmc_16bit_pingroup = {
677 .name = "fsmc_16bit_grp",
678 .pins = fsmc_16bit_pins,
679 .npins = ARRAY_SIZE(fsmc_16bit_pins),
680 .modemuxs = fsmc_16bit_modemux,
681 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
682};
683
684static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
685static struct spear_function fsmc_function = {
686 .name = "fsmc",
687 .groups = fsmc_grps,
688 .ngroups = ARRAY_SIZE(fsmc_grps),
689};
690
691/* Pad multiplexing for SPP device */
692static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
693 80, 81, 82, 83, 84, 85 };
694static struct spear_muxreg spp_muxreg[] = {
695 {
696 .reg = IP_SEL_PAD_60_69_REG,
697 .mask = PMX_PL_69_MASK,
698 .val = PMX_SPP_PL_69_VAL,
699 }, {
700 .reg = IP_SEL_PAD_70_79_REG,
701 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
702 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
703 PMX_PL_77_78_79_MASK,
704 .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
705 PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
706 PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
707 }, {
708 .reg = IP_SEL_PAD_80_89_REG,
709 .mask = PMX_PL_80_TO_85_MASK,
710 .val = PMX_SPP_PL_80_TO_85_VAL,
711 },
712};
713
714static struct spear_modemux spp_modemux[] = {
715 {
716 .modes = EXTENDED_MODE,
717 .muxregs = spp_muxreg,
718 .nmuxregs = ARRAY_SIZE(spp_muxreg),
719 },
720};
721
722static struct spear_pingroup spp_pingroup = {
723 .name = "spp_grp",
724 .pins = spp_pins,
725 .npins = ARRAY_SIZE(spp_pins),
726 .modemuxs = spp_modemux,
727 .nmodemuxs = ARRAY_SIZE(spp_modemux),
728};
729
730static const char *const spp_grps[] = { "spp_grp" };
731static struct spear_function spp_function = {
732 .name = "spp",
733 .groups = spp_grps,
734 .ngroups = ARRAY_SIZE(spp_grps),
735};
736
737/* Pad multiplexing for SDHCI device */
738static const unsigned sdhci_led_pins[] = { 34 };
739static struct spear_muxreg sdhci_led_muxreg[] = {
740 {
741 .reg = PMX_CONFIG_REG,
742 .mask = PMX_SSP_CS_MASK,
743 .val = 0,
744 },
745};
746
747static struct spear_muxreg sdhci_led_ext_muxreg[] = {
748 {
749 .reg = IP_SEL_PAD_30_39_REG,
750 .mask = PMX_PL_34_MASK,
751 .val = PMX_PWM2_PL_34_VAL,
752 },
753};
754
755static struct spear_modemux sdhci_led_modemux[] = {
756 {
757 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
758 .muxregs = sdhci_led_muxreg,
759 .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
760 }, {
761 .modes = EXTENDED_MODE,
762 .muxregs = sdhci_led_ext_muxreg,
763 .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
764 },
765};
766
767static struct spear_pingroup sdhci_led_pingroup = {
768 .name = "sdhci_led_grp",
769 .pins = sdhci_led_pins,
770 .npins = ARRAY_SIZE(sdhci_led_pins),
771 .modemuxs = sdhci_led_modemux,
772 .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
773};
774
775static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
776 50};
777static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
778};
779static struct spear_muxreg sdhci_muxreg[] = {
780 {
781 .reg = PMX_CONFIG_REG,
782 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
783 .val = 0,
784 },
785};
786
787static struct spear_muxreg sdhci_ext_muxreg[] = {
788 {
789 .reg = IP_SEL_PAD_40_49_REG,
790 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
791 PMX_PL_48_49_MASK,
792 .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
793 PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
794 }, {
795 .reg = IP_SEL_PAD_50_59_REG,
796 .mask = PMX_PL_50_MASK,
797 .val = PMX_SDHCI_PL_50_VAL,
798 }, {
799 .reg = IP_SEL_PAD_90_99_REG,
800 .mask = PMX_PL_99_MASK,
801 .val = PMX_SDHCI_PL_99_VAL,
802 }, {
803 .reg = IP_SEL_MIX_PAD_REG,
804 .mask = PMX_PL_100_101_MASK,
805 .val = PMX_SDHCI_PL_100_101_VAL,
806 },
807};
808
809static struct spear_muxreg sdhci_cd_12_muxreg[] = {
810 {
811 .reg = PMX_CONFIG_REG,
812 .mask = PMX_MII_MASK,
813 .val = 0,
814 }, {
815 .reg = IP_SEL_PAD_10_19_REG,
816 .mask = PMX_PL_12_MASK,
817 .val = PMX_SDHCI_CD_PL_12_VAL,
818 }, {
819 .reg = IP_SEL_MIX_PAD_REG,
820 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
821 .val = PMX_SDHCI_CD_PORT_12_VAL,
822 },
823};
824
825static struct spear_muxreg sdhci_cd_51_muxreg[] = {
826 {
827 .reg = IP_SEL_PAD_50_59_REG,
828 .mask = PMX_PL_51_MASK,
829 .val = PMX_SDHCI_CD_PL_51_VAL,
830 }, {
831 .reg = IP_SEL_MIX_PAD_REG,
832 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
833 .val = PMX_SDHCI_CD_PORT_51_VAL,
834 },
835};
836
837#define pmx_sdhci_common_modemux \
838 { \
839 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \
840 SMALL_PRINTERS_MODE | EXTENDED_MODE, \
841 .muxregs = sdhci_muxreg, \
842 .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \
843 }, { \
844 .modes = EXTENDED_MODE, \
845 .muxregs = sdhci_ext_muxreg, \
846 .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \
847 }
848
849static struct spear_modemux sdhci_modemux[][3] = {
850 {
851 /* select pin 12 for cd */
852 pmx_sdhci_common_modemux,
853 {
854 .modes = EXTENDED_MODE,
855 .muxregs = sdhci_cd_12_muxreg,
856 .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
857 },
858 }, {
859 /* select pin 51 for cd */
860 pmx_sdhci_common_modemux,
861 {
862 .modes = EXTENDED_MODE,
863 .muxregs = sdhci_cd_51_muxreg,
864 .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
865 },
866 }
867};
868
869static struct spear_pingroup sdhci_pingroup[] = {
870 {
871 .name = "sdhci_cd_12_grp",
872 .pins = sdhci_cd_12_pins,
873 .npins = ARRAY_SIZE(sdhci_cd_12_pins),
874 .modemuxs = sdhci_modemux[0],
875 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
876 }, {
877 .name = "sdhci_cd_51_grp",
878 .pins = sdhci_cd_51_pins,
879 .npins = ARRAY_SIZE(sdhci_cd_51_pins),
880 .modemuxs = sdhci_modemux[1],
881 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
882 },
883};
884
885static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
886 "sdhci_led_grp" };
887
888static struct spear_function sdhci_function = {
889 .name = "sdhci",
890 .groups = sdhci_grps,
891 .ngroups = ARRAY_SIZE(sdhci_grps),
892};
893
894/* Pad multiplexing for I2S device */
895static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
896static struct spear_muxreg i2s_muxreg[] = {
897 {
898 .reg = PMX_CONFIG_REG,
899 .mask = PMX_SSP_CS_MASK,
900 .val = 0,
901 }, {
902 .reg = PMX_CONFIG_REG,
903 .mask = PMX_UART0_MODEM_MASK,
904 .val = 0,
905 },
906};
907
908static struct spear_muxreg i2s_ext_muxreg[] = {
909 {
910 .reg = IP_SEL_PAD_30_39_REG,
911 .mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
912 .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
913 }, {
914 .reg = IP_SEL_PAD_40_49_REG,
915 .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
916 .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
917 },
918};
919
920static struct spear_modemux i2s_modemux[] = {
921 {
922 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
923 .muxregs = i2s_muxreg,
924 .nmuxregs = ARRAY_SIZE(i2s_muxreg),
925 }, {
926 .modes = EXTENDED_MODE,
927 .muxregs = i2s_ext_muxreg,
928 .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
929 },
930};
931
932static struct spear_pingroup i2s_pingroup = {
933 .name = "i2s_grp",
934 .pins = i2s_pins,
935 .npins = ARRAY_SIZE(i2s_pins),
936 .modemuxs = i2s_modemux,
937 .nmodemuxs = ARRAY_SIZE(i2s_modemux),
938};
939
940static const char *const i2s_grps[] = { "i2s_grp" };
941static struct spear_function i2s_function = {
942 .name = "i2s",
943 .groups = i2s_grps,
944 .ngroups = ARRAY_SIZE(i2s_grps),
945};
946
947/* Pad multiplexing for UART1 device */
948static const unsigned uart1_pins[] = { 28, 29 };
949static struct spear_muxreg uart1_muxreg[] = {
950 {
951 .reg = PMX_CONFIG_REG,
952 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
953 .val = 0,
954 },
955};
956
957static struct spear_muxreg uart1_ext_muxreg[] = {
958 {
959 .reg = IP_SEL_PAD_20_29_REG,
960 .mask = PMX_PL_28_29_MASK,
961 .val = PMX_UART1_PL_28_29_VAL,
962 },
963};
964
965static struct spear_modemux uart1_modemux[] = {
966 {
967 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
968 | SMALL_PRINTERS_MODE | EXTENDED_MODE,
969 .muxregs = uart1_muxreg,
970 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
971 }, {
972 .modes = EXTENDED_MODE,
973 .muxregs = uart1_ext_muxreg,
974 .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
975 },
976};
977
978static struct spear_pingroup uart1_pingroup = {
979 .name = "uart1_grp",
980 .pins = uart1_pins,
981 .npins = ARRAY_SIZE(uart1_pins),
982 .modemuxs = uart1_modemux,
983 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
984};
985
986static const char *const uart1_grps[] = { "uart1_grp" };
987static struct spear_function uart1_function = {
988 .name = "uart1",
989 .groups = uart1_grps,
990 .ngroups = ARRAY_SIZE(uart1_grps),
991};
992
993/* Pad multiplexing for UART1 Modem device */
994static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
995static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
996static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
997static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
998
999static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
1000 {
1001 .reg = PMX_CONFIG_REG,
1002 .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
1003 .val = 0,
1004 }, {
1005 .reg = IP_SEL_PAD_0_9_REG,
1006 .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
1007 .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
1008 PMX_UART1_ENH_PL_6_7_VAL,
1009 }, {
1010 .reg = IP_SEL_MIX_PAD_REG,
1011 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1012 .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
1013 },
1014};
1015
1016static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
1017 {
1018 .reg = PMX_CONFIG_REG,
1019 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
1020 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
1021 .val = 0,
1022 },
1023};
1024
1025static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
1026 {
1027 .reg = IP_SEL_PAD_30_39_REG,
1028 .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
1029 PMX_PL_35_MASK | PMX_PL_36_MASK,
1030 .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
1031 PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1032 PMX_UART1_ENH_PL_36_VAL,
1033 }, {
1034 .reg = IP_SEL_MIX_PAD_REG,
1035 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1036 .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
1037 },
1038};
1039
1040static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
1041 {
1042 .reg = PMX_CONFIG_REG,
1043 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
1044 PMX_SSP_CS_MASK,
1045 .val = 0,
1046 },
1047};
1048
1049static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
1050 {
1051 .reg = IP_SEL_PAD_30_39_REG,
1052 .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
1053 .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1054 PMX_UART1_ENH_PL_36_VAL,
1055 }, {
1056 .reg = IP_SEL_PAD_40_49_REG,
1057 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1058 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1059 }, {
1060 .reg = IP_SEL_MIX_PAD_REG,
1061 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1062 .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
1063 },
1064};
1065
1066static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
1067 {
1068 .reg = IP_SEL_PAD_80_89_REG,
1069 .mask = PMX_PL_80_TO_85_MASK,
1070 .val = PMX_UART1_ENH_PL_80_TO_85_VAL,
1071 }, {
1072 .reg = IP_SEL_PAD_40_49_REG,
1073 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1074 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1075 }, {
1076 .reg = IP_SEL_MIX_PAD_REG,
1077 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1078 .val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
1079 },
1080};
1081
1082static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
1083 {
1084 .modes = EXTENDED_MODE,
1085 .muxregs = uart1_modem_ext_2_to_7_muxreg,
1086 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
1087 },
1088};
1089
1090static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
1091 {
1092 .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
1093 .muxregs = uart1_modem_31_to_36_muxreg,
1094 .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
1095 }, {
1096 .modes = EXTENDED_MODE,
1097 .muxregs = uart1_modem_ext_31_to_36_muxreg,
1098 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
1099 },
1100};
1101
1102static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
1103 {
1104 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
1105 .muxregs = uart1_modem_34_to_45_muxreg,
1106 .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
1107 }, {
1108 .modes = EXTENDED_MODE,
1109 .muxregs = uart1_modem_ext_34_to_45_muxreg,
1110 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
1111 },
1112};
1113
1114static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
1115 {
1116 .modes = EXTENDED_MODE,
1117 .muxregs = uart1_modem_ext_80_to_85_muxreg,
1118 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
1119 },
1120};
1121
1122static struct spear_pingroup uart1_modem_pingroup[] = {
1123 {
1124 .name = "uart1_modem_2_to_7_grp",
1125 .pins = uart1_modem_2_to_7_pins,
1126 .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
1127 .modemuxs = uart1_modem_2_to_7_modemux,
1128 .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
1129 }, {
1130 .name = "uart1_modem_31_to_36_grp",
1131 .pins = uart1_modem_31_to_36_pins,
1132 .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
1133 .modemuxs = uart1_modem_31_to_36_modemux,
1134 .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
1135 }, {
1136 .name = "uart1_modem_34_to_45_grp",
1137 .pins = uart1_modem_34_to_45_pins,
1138 .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
1139 .modemuxs = uart1_modem_34_to_45_modemux,
1140 .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
1141 }, {
1142 .name = "uart1_modem_80_to_85_grp",
1143 .pins = uart1_modem_80_to_85_pins,
1144 .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
1145 .modemuxs = uart1_modem_80_to_85_modemux,
1146 .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
1147 },
1148};
1149
1150static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
1151 "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
1152 "uart1_modem_80_to_85_grp" };
1153static struct spear_function uart1_modem_function = {
1154 .name = "uart1_modem",
1155 .groups = uart1_modem_grps,
1156 .ngroups = ARRAY_SIZE(uart1_modem_grps),
1157};
1158
1159/* Pad multiplexing for UART2 device */
1160static const unsigned uart2_pins[] = { 0, 1 };
1161static struct spear_muxreg uart2_muxreg[] = {
1162 {
1163 .reg = PMX_CONFIG_REG,
1164 .mask = PMX_FIRDA_MASK,
1165 .val = 0,
1166 },
1167};
1168
1169static struct spear_muxreg uart2_ext_muxreg[] = {
1170 {
1171 .reg = IP_SEL_PAD_0_9_REG,
1172 .mask = PMX_PL_0_1_MASK,
1173 .val = PMX_UART2_PL_0_1_VAL,
1174 },
1175};
1176
1177static struct spear_modemux uart2_modemux[] = {
1178 {
1179 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1180 | SMALL_PRINTERS_MODE | EXTENDED_MODE,
1181 .muxregs = uart2_muxreg,
1182 .nmuxregs = ARRAY_SIZE(uart2_muxreg),
1183 }, {
1184 .modes = EXTENDED_MODE,
1185 .muxregs = uart2_ext_muxreg,
1186 .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
1187 },
1188};
1189
1190static struct spear_pingroup uart2_pingroup = {
1191 .name = "uart2_grp",
1192 .pins = uart2_pins,
1193 .npins = ARRAY_SIZE(uart2_pins),
1194 .modemuxs = uart2_modemux,
1195 .nmodemuxs = ARRAY_SIZE(uart2_modemux),
1196};
1197
1198static const char *const uart2_grps[] = { "uart2_grp" };
1199static struct spear_function uart2_function = {
1200 .name = "uart2",
1201 .groups = uart2_grps,
1202 .ngroups = ARRAY_SIZE(uart2_grps),
1203};
1204
1205/* Pad multiplexing for uart3 device */
1206static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
1207 { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
1208
1209static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
1210 {
1211 .reg = PMX_CONFIG_REG,
1212 .mask = PMX_SSP_MASK,
1213 .val = 0,
1214 }, {
1215 .reg = IP_SEL_PAD_0_9_REG,
1216 .mask = PMX_PL_8_9_MASK,
1217 .val = PMX_UART3_PL_8_9_VAL,
1218 }, {
1219 .reg = IP_SEL_MIX_PAD_REG,
1220 .mask = PMX_UART3_PORT_SEL_MASK,
1221 .val = PMX_UART3_PORT_8_VAL,
1222 },
1223};
1224
1225static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
1226 {
1227 .reg = PMX_CONFIG_REG,
1228 .mask = PMX_MII_MASK,
1229 .val = 0,
1230 }, {
1231 .reg = IP_SEL_PAD_10_19_REG,
1232 .mask = PMX_PL_15_16_MASK,
1233 .val = PMX_UART3_PL_15_16_VAL,
1234 }, {
1235 .reg = IP_SEL_MIX_PAD_REG,
1236 .mask = PMX_UART3_PORT_SEL_MASK,
1237 .val = PMX_UART3_PORT_15_VAL,
1238 },
1239};
1240
1241static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
1242 {
1243 .reg = PMX_CONFIG_REG,
1244 .mask = PMX_UART0_MODEM_MASK,
1245 .val = 0,
1246 }, {
1247 .reg = IP_SEL_PAD_40_49_REG,
1248 .mask = PMX_PL_41_42_MASK,
1249 .val = PMX_UART3_PL_41_42_VAL,
1250 }, {
1251 .reg = IP_SEL_MIX_PAD_REG,
1252 .mask = PMX_UART3_PORT_SEL_MASK,
1253 .val = PMX_UART3_PORT_41_VAL,
1254 },
1255};
1256
1257static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
1258 {
1259 .reg = IP_SEL_PAD_50_59_REG,
1260 .mask = PMX_PL_52_53_MASK,
1261 .val = PMX_UART3_PL_52_53_VAL,
1262 }, {
1263 .reg = IP_SEL_MIX_PAD_REG,
1264 .mask = PMX_UART3_PORT_SEL_MASK,
1265 .val = PMX_UART3_PORT_52_VAL,
1266 },
1267};
1268
1269static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
1270 {
1271 .reg = IP_SEL_PAD_70_79_REG,
1272 .mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
1273 .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
1274 }, {
1275 .reg = IP_SEL_MIX_PAD_REG,
1276 .mask = PMX_UART3_PORT_SEL_MASK,
1277 .val = PMX_UART3_PORT_73_VAL,
1278 },
1279};
1280
1281static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
1282 {
1283 .reg = IP_SEL_PAD_90_99_REG,
1284 .mask = PMX_PL_94_95_MASK,
1285 .val = PMX_UART3_PL_94_95_VAL,
1286 }, {
1287 .reg = IP_SEL_MIX_PAD_REG,
1288 .mask = PMX_UART3_PORT_SEL_MASK,
1289 .val = PMX_UART3_PORT_94_VAL,
1290 },
1291};
1292
1293static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
1294 {
1295 .reg = IP_SEL_PAD_90_99_REG,
1296 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
1297 .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
1298 }, {
1299 .reg = IP_SEL_MIX_PAD_REG,
1300 .mask = PMX_UART3_PORT_SEL_MASK,
1301 .val = PMX_UART3_PORT_99_VAL,
1302 },
1303};
1304
1305static struct spear_modemux uart3_modemux[][1] = {
1306 {
1307 /* Select signals on pins 8_9 */
1308 {
1309 .modes = EXTENDED_MODE,
1310 .muxregs = uart3_ext_8_9_muxreg,
1311 .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
1312 },
1313 }, {
1314 /* Select signals on pins 15_16 */
1315 {
1316 .modes = EXTENDED_MODE,
1317 .muxregs = uart3_ext_15_16_muxreg,
1318 .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
1319 },
1320 }, {
1321 /* Select signals on pins 41_42 */
1322 {
1323 .modes = EXTENDED_MODE,
1324 .muxregs = uart3_ext_41_42_muxreg,
1325 .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
1326 },
1327 }, {
1328 /* Select signals on pins 52_53 */
1329 {
1330 .modes = EXTENDED_MODE,
1331 .muxregs = uart3_ext_52_53_muxreg,
1332 .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
1333 },
1334 }, {
1335 /* Select signals on pins 73_74 */
1336 {
1337 .modes = EXTENDED_MODE,
1338 .muxregs = uart3_ext_73_74_muxreg,
1339 .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
1340 },
1341 }, {
1342 /* Select signals on pins 94_95 */
1343 {
1344 .modes = EXTENDED_MODE,
1345 .muxregs = uart3_ext_94_95_muxreg,
1346 .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
1347 },
1348 }, {
1349 /* Select signals on pins 98_99 */
1350 {
1351 .modes = EXTENDED_MODE,
1352 .muxregs = uart3_ext_98_99_muxreg,
1353 .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
1354 },
1355 },
1356};
1357
1358static struct spear_pingroup uart3_pingroup[] = {
1359 {
1360 .name = "uart3_8_9_grp",
1361 .pins = uart3_pins[0],
1362 .npins = ARRAY_SIZE(uart3_pins[0]),
1363 .modemuxs = uart3_modemux[0],
1364 .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
1365 }, {
1366 .name = "uart3_15_16_grp",
1367 .pins = uart3_pins[1],
1368 .npins = ARRAY_SIZE(uart3_pins[1]),
1369 .modemuxs = uart3_modemux[1],
1370 .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
1371 }, {
1372 .name = "uart3_41_42_grp",
1373 .pins = uart3_pins[2],
1374 .npins = ARRAY_SIZE(uart3_pins[2]),
1375 .modemuxs = uart3_modemux[2],
1376 .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
1377 }, {
1378 .name = "uart3_52_53_grp",
1379 .pins = uart3_pins[3],
1380 .npins = ARRAY_SIZE(uart3_pins[3]),
1381 .modemuxs = uart3_modemux[3],
1382 .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
1383 }, {
1384 .name = "uart3_73_74_grp",
1385 .pins = uart3_pins[4],
1386 .npins = ARRAY_SIZE(uart3_pins[4]),
1387 .modemuxs = uart3_modemux[4],
1388 .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
1389 }, {
1390 .name = "uart3_94_95_grp",
1391 .pins = uart3_pins[5],
1392 .npins = ARRAY_SIZE(uart3_pins[5]),
1393 .modemuxs = uart3_modemux[5],
1394 .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
1395 }, {
1396 .name = "uart3_98_99_grp",
1397 .pins = uart3_pins[6],
1398 .npins = ARRAY_SIZE(uart3_pins[6]),
1399 .modemuxs = uart3_modemux[6],
1400 .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
1401 },
1402};
1403
1404static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
1405 "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
1406 "uart3_94_95_grp", "uart3_98_99_grp" };
1407
1408static struct spear_function uart3_function = {
1409 .name = "uart3",
1410 .groups = uart3_grps,
1411 .ngroups = ARRAY_SIZE(uart3_grps),
1412};
1413
1414/* Pad multiplexing for uart4 device */
1415static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
1416 { 71, 72 }, { 92, 93 }, { 100, 101 } };
1417
1418static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
1419 {
1420 .reg = PMX_CONFIG_REG,
1421 .mask = PMX_SSP_MASK,
1422 .val = 0,
1423 }, {
1424 .reg = IP_SEL_PAD_0_9_REG,
1425 .mask = PMX_PL_6_7_MASK,
1426 .val = PMX_UART4_PL_6_7_VAL,
1427 }, {
1428 .reg = IP_SEL_MIX_PAD_REG,
1429 .mask = PMX_UART4_PORT_SEL_MASK,
1430 .val = PMX_UART4_PORT_6_VAL,
1431 },
1432};
1433
1434static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
1435 {
1436 .reg = PMX_CONFIG_REG,
1437 .mask = PMX_MII_MASK,
1438 .val = 0,
1439 }, {
1440 .reg = IP_SEL_PAD_10_19_REG,
1441 .mask = PMX_PL_13_14_MASK,
1442 .val = PMX_UART4_PL_13_14_VAL,
1443 }, {
1444 .reg = IP_SEL_MIX_PAD_REG,
1445 .mask = PMX_UART4_PORT_SEL_MASK,
1446 .val = PMX_UART4_PORT_13_VAL,
1447 },
1448};
1449
1450static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
1451 {
1452 .reg = PMX_CONFIG_REG,
1453 .mask = PMX_UART0_MODEM_MASK,
1454 .val = 0,
1455 }, {
1456 .reg = IP_SEL_PAD_30_39_REG,
1457 .mask = PMX_PL_39_MASK,
1458 .val = PMX_UART4_PL_39_VAL,
1459 }, {
1460 .reg = IP_SEL_PAD_40_49_REG,
1461 .mask = PMX_PL_40_MASK,
1462 .val = PMX_UART4_PL_40_VAL,
1463 }, {
1464 .reg = IP_SEL_MIX_PAD_REG,
1465 .mask = PMX_UART4_PORT_SEL_MASK,
1466 .val = PMX_UART4_PORT_39_VAL,
1467 },
1468};
1469
1470static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
1471 {
1472 .reg = IP_SEL_PAD_70_79_REG,
1473 .mask = PMX_PL_71_72_MASK,
1474 .val = PMX_UART4_PL_71_72_VAL,
1475 }, {
1476 .reg = IP_SEL_MIX_PAD_REG,
1477 .mask = PMX_UART4_PORT_SEL_MASK,
1478 .val = PMX_UART4_PORT_71_VAL,
1479 },
1480};
1481
1482static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
1483 {
1484 .reg = IP_SEL_PAD_90_99_REG,
1485 .mask = PMX_PL_92_93_MASK,
1486 .val = PMX_UART4_PL_92_93_VAL,
1487 }, {
1488 .reg = IP_SEL_MIX_PAD_REG,
1489 .mask = PMX_UART4_PORT_SEL_MASK,
1490 .val = PMX_UART4_PORT_92_VAL,
1491 },
1492};
1493
1494static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
1495 {
1496 .reg = IP_SEL_MIX_PAD_REG,
1497 .mask = PMX_PL_100_101_MASK |
1498 PMX_UART4_PORT_SEL_MASK,
1499 .val = PMX_UART4_PL_100_101_VAL |
1500 PMX_UART4_PORT_101_VAL,
1501 },
1502};
1503
1504static struct spear_modemux uart4_modemux[][1] = {
1505 {
1506 /* Select signals on pins 6_7 */
1507 {
1508 .modes = EXTENDED_MODE,
1509 .muxregs = uart4_ext_6_7_muxreg,
1510 .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
1511 },
1512 }, {
1513 /* Select signals on pins 13_14 */
1514 {
1515 .modes = EXTENDED_MODE,
1516 .muxregs = uart4_ext_13_14_muxreg,
1517 .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
1518 },
1519 }, {
1520 /* Select signals on pins 39_40 */
1521 {
1522 .modes = EXTENDED_MODE,
1523 .muxregs = uart4_ext_39_40_muxreg,
1524 .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
1525 },
1526 }, {
1527 /* Select signals on pins 71_72 */
1528 {
1529 .modes = EXTENDED_MODE,
1530 .muxregs = uart4_ext_71_72_muxreg,
1531 .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
1532 },
1533 }, {
1534 /* Select signals on pins 92_93 */
1535 {
1536 .modes = EXTENDED_MODE,
1537 .muxregs = uart4_ext_92_93_muxreg,
1538 .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
1539 },
1540 }, {
1541 /* Select signals on pins 100_101_ */
1542 {
1543 .modes = EXTENDED_MODE,
1544 .muxregs = uart4_ext_100_101_muxreg,
1545 .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
1546 },
1547 },
1548};
1549
1550static struct spear_pingroup uart4_pingroup[] = {
1551 {
1552 .name = "uart4_6_7_grp",
1553 .pins = uart4_pins[0],
1554 .npins = ARRAY_SIZE(uart4_pins[0]),
1555 .modemuxs = uart4_modemux[0],
1556 .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
1557 }, {
1558 .name = "uart4_13_14_grp",
1559 .pins = uart4_pins[1],
1560 .npins = ARRAY_SIZE(uart4_pins[1]),
1561 .modemuxs = uart4_modemux[1],
1562 .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
1563 }, {
1564 .name = "uart4_39_40_grp",
1565 .pins = uart4_pins[2],
1566 .npins = ARRAY_SIZE(uart4_pins[2]),
1567 .modemuxs = uart4_modemux[2],
1568 .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
1569 }, {
1570 .name = "uart4_71_72_grp",
1571 .pins = uart4_pins[3],
1572 .npins = ARRAY_SIZE(uart4_pins[3]),
1573 .modemuxs = uart4_modemux[3],
1574 .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
1575 }, {
1576 .name = "uart4_92_93_grp",
1577 .pins = uart4_pins[4],
1578 .npins = ARRAY_SIZE(uart4_pins[4]),
1579 .modemuxs = uart4_modemux[4],
1580 .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
1581 }, {
1582 .name = "uart4_100_101_grp",
1583 .pins = uart4_pins[5],
1584 .npins = ARRAY_SIZE(uart4_pins[5]),
1585 .modemuxs = uart4_modemux[5],
1586 .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
1587 },
1588};
1589
1590static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
1591 "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
1592 "uart4_100_101_grp" };
1593
1594static struct spear_function uart4_function = {
1595 .name = "uart4",
1596 .groups = uart4_grps,
1597 .ngroups = ARRAY_SIZE(uart4_grps),
1598};
1599
1600/* Pad multiplexing for uart5 device */
1601static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
1602 { 90, 91 } };
1603
1604static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
1605 {
1606 .reg = PMX_CONFIG_REG,
1607 .mask = PMX_I2C_MASK,
1608 .val = 0,
1609 }, {
1610 .reg = IP_SEL_PAD_0_9_REG,
1611 .mask = PMX_PL_4_5_MASK,
1612 .val = PMX_UART5_PL_4_5_VAL,
1613 }, {
1614 .reg = IP_SEL_MIX_PAD_REG,
1615 .mask = PMX_UART5_PORT_SEL_MASK,
1616 .val = PMX_UART5_PORT_4_VAL,
1617 },
1618};
1619
1620static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
1621 {
1622 .reg = PMX_CONFIG_REG,
1623 .mask = PMX_UART0_MODEM_MASK,
1624 .val = 0,
1625 }, {
1626 .reg = IP_SEL_PAD_30_39_REG,
1627 .mask = PMX_PL_37_38_MASK,
1628 .val = PMX_UART5_PL_37_38_VAL,
1629 }, {
1630 .reg = IP_SEL_MIX_PAD_REG,
1631 .mask = PMX_UART5_PORT_SEL_MASK,
1632 .val = PMX_UART5_PORT_37_VAL,
1633 },
1634};
1635
1636static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
1637 {
1638 .reg = IP_SEL_PAD_60_69_REG,
1639 .mask = PMX_PL_69_MASK,
1640 .val = PMX_UART5_PL_69_VAL,
1641 }, {
1642 .reg = IP_SEL_PAD_70_79_REG,
1643 .mask = PMX_PL_70_MASK,
1644 .val = PMX_UART5_PL_70_VAL,
1645 }, {
1646 .reg = IP_SEL_MIX_PAD_REG,
1647 .mask = PMX_UART5_PORT_SEL_MASK,
1648 .val = PMX_UART5_PORT_69_VAL,
1649 },
1650};
1651
1652static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
1653 {
1654 .reg = IP_SEL_PAD_90_99_REG,
1655 .mask = PMX_PL_90_91_MASK,
1656 .val = PMX_UART5_PL_90_91_VAL,
1657 }, {
1658 .reg = IP_SEL_MIX_PAD_REG,
1659 .mask = PMX_UART5_PORT_SEL_MASK,
1660 .val = PMX_UART5_PORT_90_VAL,
1661 },
1662};
1663
1664static struct spear_modemux uart5_modemux[][1] = {
1665 {
1666 /* Select signals on pins 4_5 */
1667 {
1668 .modes = EXTENDED_MODE,
1669 .muxregs = uart5_ext_4_5_muxreg,
1670 .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
1671 },
1672 }, {
1673 /* Select signals on pins 37_38 */
1674 {
1675 .modes = EXTENDED_MODE,
1676 .muxregs = uart5_ext_37_38_muxreg,
1677 .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
1678 },
1679 }, {
1680 /* Select signals on pins 69_70 */
1681 {
1682 .modes = EXTENDED_MODE,
1683 .muxregs = uart5_ext_69_70_muxreg,
1684 .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
1685 },
1686 }, {
1687 /* Select signals on pins 90_91 */
1688 {
1689 .modes = EXTENDED_MODE,
1690 .muxregs = uart5_ext_90_91_muxreg,
1691 .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
1692 },
1693 },
1694};
1695
1696static struct spear_pingroup uart5_pingroup[] = {
1697 {
1698 .name = "uart5_4_5_grp",
1699 .pins = uart5_pins[0],
1700 .npins = ARRAY_SIZE(uart5_pins[0]),
1701 .modemuxs = uart5_modemux[0],
1702 .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
1703 }, {
1704 .name = "uart5_37_38_grp",
1705 .pins = uart5_pins[1],
1706 .npins = ARRAY_SIZE(uart5_pins[1]),
1707 .modemuxs = uart5_modemux[1],
1708 .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
1709 }, {
1710 .name = "uart5_69_70_grp",
1711 .pins = uart5_pins[2],
1712 .npins = ARRAY_SIZE(uart5_pins[2]),
1713 .modemuxs = uart5_modemux[2],
1714 .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
1715 }, {
1716 .name = "uart5_90_91_grp",
1717 .pins = uart5_pins[3],
1718 .npins = ARRAY_SIZE(uart5_pins[3]),
1719 .modemuxs = uart5_modemux[3],
1720 .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
1721 },
1722};
1723
1724static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
1725 "uart5_69_70_grp", "uart5_90_91_grp" };
1726static struct spear_function uart5_function = {
1727 .name = "uart5",
1728 .groups = uart5_grps,
1729 .ngroups = ARRAY_SIZE(uart5_grps),
1730};
1731
1732/* Pad multiplexing for uart6 device */
1733static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
1734static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
1735 {
1736 .reg = PMX_CONFIG_REG,
1737 .mask = PMX_UART0_MASK,
1738 .val = 0,
1739 }, {
1740 .reg = IP_SEL_PAD_0_9_REG,
1741 .mask = PMX_PL_2_3_MASK,
1742 .val = PMX_UART6_PL_2_3_VAL,
1743 }, {
1744 .reg = IP_SEL_MIX_PAD_REG,
1745 .mask = PMX_UART6_PORT_SEL_MASK,
1746 .val = PMX_UART6_PORT_2_VAL,
1747 },
1748};
1749
1750static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
1751 {
1752 .reg = IP_SEL_PAD_80_89_REG,
1753 .mask = PMX_PL_88_89_MASK,
1754 .val = PMX_UART6_PL_88_89_VAL,
1755 }, {
1756 .reg = IP_SEL_MIX_PAD_REG,
1757 .mask = PMX_UART6_PORT_SEL_MASK,
1758 .val = PMX_UART6_PORT_88_VAL,
1759 },
1760};
1761
1762static struct spear_modemux uart6_modemux[][1] = {
1763 {
1764 /* Select signals on pins 2_3 */
1765 {
1766 .modes = EXTENDED_MODE,
1767 .muxregs = uart6_ext_2_3_muxreg,
1768 .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
1769 },
1770 }, {
1771 /* Select signals on pins 88_89 */
1772 {
1773 .modes = EXTENDED_MODE,
1774 .muxregs = uart6_ext_88_89_muxreg,
1775 .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
1776 },
1777 },
1778};
1779
1780static struct spear_pingroup uart6_pingroup[] = {
1781 {
1782 .name = "uart6_2_3_grp",
1783 .pins = uart6_pins[0],
1784 .npins = ARRAY_SIZE(uart6_pins[0]),
1785 .modemuxs = uart6_modemux[0],
1786 .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
1787 }, {
1788 .name = "uart6_88_89_grp",
1789 .pins = uart6_pins[1],
1790 .npins = ARRAY_SIZE(uart6_pins[1]),
1791 .modemuxs = uart6_modemux[1],
1792 .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
1793 },
1794};
1795
1796static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
1797static struct spear_function uart6_function = {
1798 .name = "uart6",
1799 .groups = uart6_grps,
1800 .ngroups = ARRAY_SIZE(uart6_grps),
1801};
1802
1803/* UART - RS485 pmx */
1804static const unsigned rs485_pins[] = { 77, 78, 79 };
1805static struct spear_muxreg rs485_muxreg[] = {
1806 {
1807 .reg = IP_SEL_PAD_70_79_REG,
1808 .mask = PMX_PL_77_78_79_MASK,
1809 .val = PMX_RS485_PL_77_78_79_VAL,
1810 },
1811};
1812
1813static struct spear_modemux rs485_modemux[] = {
1814 {
1815 .modes = EXTENDED_MODE,
1816 .muxregs = rs485_muxreg,
1817 .nmuxregs = ARRAY_SIZE(rs485_muxreg),
1818 },
1819};
1820
1821static struct spear_pingroup rs485_pingroup = {
1822 .name = "rs485_grp",
1823 .pins = rs485_pins,
1824 .npins = ARRAY_SIZE(rs485_pins),
1825 .modemuxs = rs485_modemux,
1826 .nmodemuxs = ARRAY_SIZE(rs485_modemux),
1827};
1828
1829static const char *const rs485_grps[] = { "rs485_grp" };
1830static struct spear_function rs485_function = {
1831 .name = "rs485",
1832 .groups = rs485_grps,
1833 .ngroups = ARRAY_SIZE(rs485_grps),
1834};
1835
1836/* Pad multiplexing for Touchscreen device */
1837static const unsigned touchscreen_pins[] = { 5, 36 };
1838static struct spear_muxreg touchscreen_muxreg[] = {
1839 {
1840 .reg = PMX_CONFIG_REG,
1841 .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
1842 .val = 0,
1843 },
1844};
1845
1846static struct spear_muxreg touchscreen_ext_muxreg[] = {
1847 {
1848 .reg = IP_SEL_PAD_0_9_REG,
1849 .mask = PMX_PL_5_MASK,
1850 .val = PMX_TOUCH_Y_PL_5_VAL,
1851 }, {
1852 .reg = IP_SEL_PAD_30_39_REG,
1853 .mask = PMX_PL_36_MASK,
1854 .val = PMX_TOUCH_X_PL_36_VAL,
1855 },
1856};
1857
1858static struct spear_modemux touchscreen_modemux[] = {
1859 {
1860 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
1861 .muxregs = touchscreen_muxreg,
1862 .nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
1863 }, {
1864 .modes = EXTENDED_MODE,
1865 .muxregs = touchscreen_ext_muxreg,
1866 .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
1867 },
1868};
1869
1870static struct spear_pingroup touchscreen_pingroup = {
1871 .name = "touchscreen_grp",
1872 .pins = touchscreen_pins,
1873 .npins = ARRAY_SIZE(touchscreen_pins),
1874 .modemuxs = touchscreen_modemux,
1875 .nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
1876};
1877
1878static const char *const touchscreen_grps[] = { "touchscreen_grp" };
1879static struct spear_function touchscreen_function = {
1880 .name = "touchscreen",
1881 .groups = touchscreen_grps,
1882 .ngroups = ARRAY_SIZE(touchscreen_grps),
1883};
1884
1885/* Pad multiplexing for CAN device */
1886static const unsigned can0_pins[] = { 32, 33 };
1887static struct spear_muxreg can0_muxreg[] = {
1888 {
1889 .reg = PMX_CONFIG_REG,
1890 .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
1891 .val = 0,
1892 },
1893};
1894
1895static struct spear_muxreg can0_ext_muxreg[] = {
1896 {
1897 .reg = IP_SEL_PAD_30_39_REG,
1898 .mask = PMX_PL_32_33_MASK,
1899 .val = PMX_CAN0_PL_32_33_VAL,
1900 },
1901};
1902
1903static struct spear_modemux can0_modemux[] = {
1904 {
1905 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1906 | EXTENDED_MODE,
1907 .muxregs = can0_muxreg,
1908 .nmuxregs = ARRAY_SIZE(can0_muxreg),
1909 }, {
1910 .modes = EXTENDED_MODE,
1911 .muxregs = can0_ext_muxreg,
1912 .nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
1913 },
1914};
1915
1916static struct spear_pingroup can0_pingroup = {
1917 .name = "can0_grp",
1918 .pins = can0_pins,
1919 .npins = ARRAY_SIZE(can0_pins),
1920 .modemuxs = can0_modemux,
1921 .nmodemuxs = ARRAY_SIZE(can0_modemux),
1922};
1923
1924static const char *const can0_grps[] = { "can0_grp" };
1925static struct spear_function can0_function = {
1926 .name = "can0",
1927 .groups = can0_grps,
1928 .ngroups = ARRAY_SIZE(can0_grps),
1929};
1930
1931static const unsigned can1_pins[] = { 30, 31 };
1932static struct spear_muxreg can1_muxreg[] = {
1933 {
1934 .reg = PMX_CONFIG_REG,
1935 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
1936 .val = 0,
1937 },
1938};
1939
1940static struct spear_muxreg can1_ext_muxreg[] = {
1941 {
1942 .reg = IP_SEL_PAD_30_39_REG,
1943 .mask = PMX_PL_30_31_MASK,
1944 .val = PMX_CAN1_PL_30_31_VAL,
1945 },
1946};
1947
1948static struct spear_modemux can1_modemux[] = {
1949 {
1950 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1951 | EXTENDED_MODE,
1952 .muxregs = can1_muxreg,
1953 .nmuxregs = ARRAY_SIZE(can1_muxreg),
1954 }, {
1955 .modes = EXTENDED_MODE,
1956 .muxregs = can1_ext_muxreg,
1957 .nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
1958 },
1959};
1960
1961static struct spear_pingroup can1_pingroup = {
1962 .name = "can1_grp",
1963 .pins = can1_pins,
1964 .npins = ARRAY_SIZE(can1_pins),
1965 .modemuxs = can1_modemux,
1966 .nmodemuxs = ARRAY_SIZE(can1_modemux),
1967};
1968
1969static const char *const can1_grps[] = { "can1_grp" };
1970static struct spear_function can1_function = {
1971 .name = "can1",
1972 .groups = can1_grps,
1973 .ngroups = ARRAY_SIZE(can1_grps),
1974};
1975
1976/* Pad multiplexing for PWM0_1 device */
1977static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
1978 { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
1979
1980static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
1981 {
1982 .reg = PMX_CONFIG_REG,
1983 .mask = PMX_SSP_MASK,
1984 .val = 0,
1985 }, {
1986 .reg = IP_SEL_PAD_0_9_REG,
1987 .mask = PMX_PL_8_9_MASK,
1988 .val = PMX_PWM_0_1_PL_8_9_VAL,
1989 },
1990};
1991
1992static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
1993 {
1994 .reg = PMX_CONFIG_REG,
1995 .mask = PMX_MII_MASK,
1996 .val = 0,
1997 },
1998};
1999
2000static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
2001 {
2002 .reg = IP_SEL_PAD_10_19_REG,
2003 .mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
2004 .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
2005 },
2006};
2007
2008static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
2009 {
2010 .reg = PMX_CONFIG_REG,
2011 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
2012 .val = 0,
2013 }, {
2014 .reg = IP_SEL_PAD_30_39_REG,
2015 .mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
2016 .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
2017 },
2018};
2019
2020static struct spear_muxreg pwm0_1_net_muxreg[] = {
2021 {
2022 .reg = PMX_CONFIG_REG,
2023 .mask = PMX_UART0_MODEM_MASK,
2024 .val = 0,
2025 },
2026};
2027
2028static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
2029 {
2030 .reg = IP_SEL_PAD_30_39_REG,
2031 .mask = PMX_PL_37_38_MASK,
2032 .val = PMX_PWM0_1_PL_37_38_VAL,
2033 },
2034};
2035
2036static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
2037 {
2038 .reg = PMX_CONFIG_REG,
2039 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
2040 .val = 0,
2041 }, {
2042 .reg = IP_SEL_PAD_40_49_REG,
2043 .mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
2044 .val = PMX_PWM1_PL_42_VAL |
2045 PMX_PWM0_PL_43_VAL,
2046 },
2047};
2048
2049static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
2050 {
2051 .reg = IP_SEL_PAD_50_59_REG,
2052 .mask = PMX_PL_59_MASK,
2053 .val = PMX_PWM1_PL_59_VAL,
2054 }, {
2055 .reg = IP_SEL_PAD_60_69_REG,
2056 .mask = PMX_PL_60_MASK,
2057 .val = PMX_PWM0_PL_60_VAL,
2058 },
2059};
2060
2061static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
2062 {
2063 .reg = IP_SEL_PAD_80_89_REG,
2064 .mask = PMX_PL_88_89_MASK,
2065 .val = PMX_PWM0_1_PL_88_89_VAL,
2066 },
2067};
2068
2069static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
2070 {
2071 .modes = EXTENDED_MODE,
2072 .muxregs = pwm0_1_pin_8_9_muxreg,
2073 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
2074 },
2075};
2076
2077static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
2078 {
2079 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2080 .muxregs = pwm0_1_autoexpsmallpri_muxreg,
2081 .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
2082 }, {
2083 .modes = EXTENDED_MODE,
2084 .muxregs = pwm0_1_pin_14_15_muxreg,
2085 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
2086 },
2087};
2088
2089static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
2090 {
2091 .modes = EXTENDED_MODE,
2092 .muxregs = pwm0_1_pin_30_31_muxreg,
2093 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
2094 },
2095};
2096
2097static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
2098 {
2099 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2100 .muxregs = pwm0_1_net_muxreg,
2101 .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
2102 }, {
2103 .modes = EXTENDED_MODE,
2104 .muxregs = pwm0_1_pin_37_38_muxreg,
2105 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
2106 },
2107};
2108
2109static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
2110 {
2111 .modes = EXTENDED_MODE,
2112 .muxregs = pwm0_1_pin_42_43_muxreg,
2113 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
2114 },
2115};
2116
2117static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
2118 {
2119 .modes = EXTENDED_MODE,
2120 .muxregs = pwm0_1_pin_59_60_muxreg,
2121 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
2122 },
2123};
2124
2125static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
2126 {
2127 .modes = EXTENDED_MODE,
2128 .muxregs = pwm0_1_pin_88_89_muxreg,
2129 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
2130 },
2131};
2132
2133static struct spear_pingroup pwm0_1_pingroup[] = {
2134 {
2135 .name = "pwm0_1_pin_8_9_grp",
2136 .pins = pwm0_1_pins[0],
2137 .npins = ARRAY_SIZE(pwm0_1_pins[0]),
2138 .modemuxs = pwm0_1_pin_8_9_modemux,
2139 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
2140 }, {
2141 .name = "pwm0_1_pin_14_15_grp",
2142 .pins = pwm0_1_pins[1],
2143 .npins = ARRAY_SIZE(pwm0_1_pins[1]),
2144 .modemuxs = pwm0_1_pin_14_15_modemux,
2145 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
2146 }, {
2147 .name = "pwm0_1_pin_30_31_grp",
2148 .pins = pwm0_1_pins[2],
2149 .npins = ARRAY_SIZE(pwm0_1_pins[2]),
2150 .modemuxs = pwm0_1_pin_30_31_modemux,
2151 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
2152 }, {
2153 .name = "pwm0_1_pin_37_38_grp",
2154 .pins = pwm0_1_pins[3],
2155 .npins = ARRAY_SIZE(pwm0_1_pins[3]),
2156 .modemuxs = pwm0_1_pin_37_38_modemux,
2157 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
2158 }, {
2159 .name = "pwm0_1_pin_42_43_grp",
2160 .pins = pwm0_1_pins[4],
2161 .npins = ARRAY_SIZE(pwm0_1_pins[4]),
2162 .modemuxs = pwm0_1_pin_42_43_modemux,
2163 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
2164 }, {
2165 .name = "pwm0_1_pin_59_60_grp",
2166 .pins = pwm0_1_pins[5],
2167 .npins = ARRAY_SIZE(pwm0_1_pins[5]),
2168 .modemuxs = pwm0_1_pin_59_60_modemux,
2169 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
2170 }, {
2171 .name = "pwm0_1_pin_88_89_grp",
2172 .pins = pwm0_1_pins[6],
2173 .npins = ARRAY_SIZE(pwm0_1_pins[6]),
2174 .modemuxs = pwm0_1_pin_88_89_modemux,
2175 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
2176 },
2177};
2178
2179static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
2180 "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
2181 "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
2182};
2183
2184static struct spear_function pwm0_1_function = {
2185 .name = "pwm0_1",
2186 .groups = pwm0_1_grps,
2187 .ngroups = ARRAY_SIZE(pwm0_1_grps),
2188};
2189
2190/* Pad multiplexing for PWM2 device */
2191static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
2192 { 58 }, { 87 } };
2193static struct spear_muxreg pwm2_net_muxreg[] = {
2194 {
2195 .reg = PMX_CONFIG_REG,
2196 .mask = PMX_SSP_CS_MASK,
2197 .val = 0,
2198 },
2199};
2200
2201static struct spear_muxreg pwm2_pin_7_muxreg[] = {
2202 {
2203 .reg = IP_SEL_PAD_0_9_REG,
2204 .mask = PMX_PL_7_MASK,
2205 .val = PMX_PWM_2_PL_7_VAL,
2206 },
2207};
2208
2209static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
2210 {
2211 .reg = PMX_CONFIG_REG,
2212 .mask = PMX_MII_MASK,
2213 .val = 0,
2214 },
2215};
2216
2217static struct spear_muxreg pwm2_pin_13_muxreg[] = {
2218 {
2219 .reg = IP_SEL_PAD_10_19_REG,
2220 .mask = PMX_PL_13_MASK,
2221 .val = PMX_PWM2_PL_13_VAL,
2222 },
2223};
2224
2225static struct spear_muxreg pwm2_pin_29_muxreg[] = {
2226 {
2227 .reg = PMX_CONFIG_REG,
2228 .mask = PMX_GPIO_PIN1_MASK,
2229 .val = 0,
2230 }, {
2231 .reg = IP_SEL_PAD_20_29_REG,
2232 .mask = PMX_PL_29_MASK,
2233 .val = PMX_PWM_2_PL_29_VAL,
2234 },
2235};
2236
2237static struct spear_muxreg pwm2_pin_34_muxreg[] = {
2238 {
2239 .reg = PMX_CONFIG_REG,
2240 .mask = PMX_SSP_CS_MASK,
2241 .val = 0,
2242 }, {
2243 .reg = IP_SEL_PAD_30_39_REG,
2244 .mask = PMX_PL_34_MASK,
2245 .val = PMX_PWM2_PL_34_VAL,
2246 },
2247};
2248
2249static struct spear_muxreg pwm2_pin_41_muxreg[] = {
2250 {
2251 .reg = PMX_CONFIG_REG,
2252 .mask = PMX_UART0_MODEM_MASK,
2253 .val = 0,
2254 }, {
2255 .reg = IP_SEL_PAD_40_49_REG,
2256 .mask = PMX_PL_41_MASK,
2257 .val = PMX_PWM2_PL_41_VAL,
2258 },
2259};
2260
2261static struct spear_muxreg pwm2_pin_58_muxreg[] = {
2262 {
2263 .reg = IP_SEL_PAD_50_59_REG,
2264 .mask = PMX_PL_58_MASK,
2265 .val = PMX_PWM2_PL_58_VAL,
2266 },
2267};
2268
2269static struct spear_muxreg pwm2_pin_87_muxreg[] = {
2270 {
2271 .reg = IP_SEL_PAD_80_89_REG,
2272 .mask = PMX_PL_87_MASK,
2273 .val = PMX_PWM2_PL_87_VAL,
2274 },
2275};
2276
2277static struct spear_modemux pwm2_pin_7_modemux[] = {
2278 {
2279 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2280 .muxregs = pwm2_net_muxreg,
2281 .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
2282 }, {
2283 .modes = EXTENDED_MODE,
2284 .muxregs = pwm2_pin_7_muxreg,
2285 .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
2286 },
2287};
2288static struct spear_modemux pwm2_pin_13_modemux[] = {
2289 {
2290 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2291 .muxregs = pwm2_autoexpsmallpri_muxreg,
2292 .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
2293 }, {
2294 .modes = EXTENDED_MODE,
2295 .muxregs = pwm2_pin_13_muxreg,
2296 .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
2297 },
2298};
2299static struct spear_modemux pwm2_pin_29_modemux[] = {
2300 {
2301 .modes = EXTENDED_MODE,
2302 .muxregs = pwm2_pin_29_muxreg,
2303 .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
2304 },
2305};
2306static struct spear_modemux pwm2_pin_34_modemux[] = {
2307 {
2308 .modes = EXTENDED_MODE,
2309 .muxregs = pwm2_pin_34_muxreg,
2310 .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
2311 },
2312};
2313
2314static struct spear_modemux pwm2_pin_41_modemux[] = {
2315 {
2316 .modes = EXTENDED_MODE,
2317 .muxregs = pwm2_pin_41_muxreg,
2318 .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
2319 },
2320};
2321
2322static struct spear_modemux pwm2_pin_58_modemux[] = {
2323 {
2324 .modes = EXTENDED_MODE,
2325 .muxregs = pwm2_pin_58_muxreg,
2326 .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
2327 },
2328};
2329
2330static struct spear_modemux pwm2_pin_87_modemux[] = {
2331 {
2332 .modes = EXTENDED_MODE,
2333 .muxregs = pwm2_pin_87_muxreg,
2334 .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
2335 },
2336};
2337
2338static struct spear_pingroup pwm2_pingroup[] = {
2339 {
2340 .name = "pwm2_pin_7_grp",
2341 .pins = pwm2_pins[0],
2342 .npins = ARRAY_SIZE(pwm2_pins[0]),
2343 .modemuxs = pwm2_pin_7_modemux,
2344 .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
2345 }, {
2346 .name = "pwm2_pin_13_grp",
2347 .pins = pwm2_pins[1],
2348 .npins = ARRAY_SIZE(pwm2_pins[1]),
2349 .modemuxs = pwm2_pin_13_modemux,
2350 .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
2351 }, {
2352 .name = "pwm2_pin_29_grp",
2353 .pins = pwm2_pins[2],
2354 .npins = ARRAY_SIZE(pwm2_pins[2]),
2355 .modemuxs = pwm2_pin_29_modemux,
2356 .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
2357 }, {
2358 .name = "pwm2_pin_34_grp",
2359 .pins = pwm2_pins[3],
2360 .npins = ARRAY_SIZE(pwm2_pins[3]),
2361 .modemuxs = pwm2_pin_34_modemux,
2362 .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
2363 }, {
2364 .name = "pwm2_pin_41_grp",
2365 .pins = pwm2_pins[4],
2366 .npins = ARRAY_SIZE(pwm2_pins[4]),
2367 .modemuxs = pwm2_pin_41_modemux,
2368 .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
2369 }, {
2370 .name = "pwm2_pin_58_grp",
2371 .pins = pwm2_pins[5],
2372 .npins = ARRAY_SIZE(pwm2_pins[5]),
2373 .modemuxs = pwm2_pin_58_modemux,
2374 .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
2375 }, {
2376 .name = "pwm2_pin_87_grp",
2377 .pins = pwm2_pins[6],
2378 .npins = ARRAY_SIZE(pwm2_pins[6]),
2379 .modemuxs = pwm2_pin_87_modemux,
2380 .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
2381 },
2382};
2383
2384static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
2385 "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
2386 "pwm2_pin_58_grp", "pwm2_pin_87_grp" };
2387static struct spear_function pwm2_function = {
2388 .name = "pwm2",
2389 .groups = pwm2_grps,
2390 .ngroups = ARRAY_SIZE(pwm2_grps),
2391};
2392
2393/* Pad multiplexing for PWM3 device */
2394static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
2395 { 86 } };
2396static struct spear_muxreg pwm3_pin_6_muxreg[] = {
2397 {
2398 .reg = PMX_CONFIG_REG,
2399 .mask = PMX_SSP_MASK,
2400 .val = 0,
2401 }, {
2402 .reg = IP_SEL_PAD_0_9_REG,
2403 .mask = PMX_PL_6_MASK,
2404 .val = PMX_PWM_3_PL_6_VAL,
2405 },
2406};
2407
2408static struct spear_muxreg pwm3_muxreg[] = {
2409 {
2410 .reg = PMX_CONFIG_REG,
2411 .mask = PMX_MII_MASK,
2412 .val = 0,
2413 },
2414};
2415
2416static struct spear_muxreg pwm3_pin_12_muxreg[] = {
2417 {
2418 .reg = IP_SEL_PAD_10_19_REG,
2419 .mask = PMX_PL_12_MASK,
2420 .val = PMX_PWM3_PL_12_VAL,
2421 },
2422};
2423
2424static struct spear_muxreg pwm3_pin_28_muxreg[] = {
2425 {
2426 .reg = PMX_CONFIG_REG,
2427 .mask = PMX_GPIO_PIN0_MASK,
2428 .val = 0,
2429 }, {
2430 .reg = IP_SEL_PAD_20_29_REG,
2431 .mask = PMX_PL_28_MASK,
2432 .val = PMX_PWM_3_PL_28_VAL,
2433 },
2434};
2435
2436static struct spear_muxreg pwm3_pin_40_muxreg[] = {
2437 {
2438 .reg = PMX_CONFIG_REG,
2439 .mask = PMX_UART0_MODEM_MASK,
2440 .val = 0,
2441 }, {
2442 .reg = IP_SEL_PAD_40_49_REG,
2443 .mask = PMX_PL_40_MASK,
2444 .val = PMX_PWM3_PL_40_VAL,
2445 },
2446};
2447
2448static struct spear_muxreg pwm3_pin_57_muxreg[] = {
2449 {
2450 .reg = IP_SEL_PAD_50_59_REG,
2451 .mask = PMX_PL_57_MASK,
2452 .val = PMX_PWM3_PL_57_VAL,
2453 },
2454};
2455
2456static struct spear_muxreg pwm3_pin_86_muxreg[] = {
2457 {
2458 .reg = IP_SEL_PAD_80_89_REG,
2459 .mask = PMX_PL_86_MASK,
2460 .val = PMX_PWM3_PL_86_VAL,
2461 },
2462};
2463
2464static struct spear_modemux pwm3_pin_6_modemux[] = {
2465 {
2466 .modes = EXTENDED_MODE,
2467 .muxregs = pwm3_pin_6_muxreg,
2468 .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
2469 },
2470};
2471
2472static struct spear_modemux pwm3_pin_12_modemux[] = {
2473 {
2474 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
2475 AUTO_NET_SMII_MODE | EXTENDED_MODE,
2476 .muxregs = pwm3_muxreg,
2477 .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
2478 }, {
2479 .modes = EXTENDED_MODE,
2480 .muxregs = pwm3_pin_12_muxreg,
2481 .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
2482 },
2483};
2484
2485static struct spear_modemux pwm3_pin_28_modemux[] = {
2486 {
2487 .modes = EXTENDED_MODE,
2488 .muxregs = pwm3_pin_28_muxreg,
2489 .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
2490 },
2491};
2492
2493static struct spear_modemux pwm3_pin_40_modemux[] = {
2494 {
2495 .modes = EXTENDED_MODE,
2496 .muxregs = pwm3_pin_40_muxreg,
2497 .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
2498 },
2499};
2500
2501static struct spear_modemux pwm3_pin_57_modemux[] = {
2502 {
2503 .modes = EXTENDED_MODE,
2504 .muxregs = pwm3_pin_57_muxreg,
2505 .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
2506 },
2507};
2508
2509static struct spear_modemux pwm3_pin_86_modemux[] = {
2510 {
2511 .modes = EXTENDED_MODE,
2512 .muxregs = pwm3_pin_86_muxreg,
2513 .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
2514 },
2515};
2516
2517static struct spear_pingroup pwm3_pingroup[] = {
2518 {
2519 .name = "pwm3_pin_6_grp",
2520 .pins = pwm3_pins[0],
2521 .npins = ARRAY_SIZE(pwm3_pins[0]),
2522 .modemuxs = pwm3_pin_6_modemux,
2523 .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
2524 }, {
2525 .name = "pwm3_pin_12_grp",
2526 .pins = pwm3_pins[1],
2527 .npins = ARRAY_SIZE(pwm3_pins[1]),
2528 .modemuxs = pwm3_pin_12_modemux,
2529 .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
2530 }, {
2531 .name = "pwm3_pin_28_grp",
2532 .pins = pwm3_pins[2],
2533 .npins = ARRAY_SIZE(pwm3_pins[2]),
2534 .modemuxs = pwm3_pin_28_modemux,
2535 .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
2536 }, {
2537 .name = "pwm3_pin_40_grp",
2538 .pins = pwm3_pins[3],
2539 .npins = ARRAY_SIZE(pwm3_pins[3]),
2540 .modemuxs = pwm3_pin_40_modemux,
2541 .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
2542 }, {
2543 .name = "pwm3_pin_57_grp",
2544 .pins = pwm3_pins[4],
2545 .npins = ARRAY_SIZE(pwm3_pins[4]),
2546 .modemuxs = pwm3_pin_57_modemux,
2547 .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
2548 }, {
2549 .name = "pwm3_pin_86_grp",
2550 .pins = pwm3_pins[5],
2551 .npins = ARRAY_SIZE(pwm3_pins[5]),
2552 .modemuxs = pwm3_pin_86_modemux,
2553 .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
2554 },
2555};
2556
2557static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
2558 "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
2559 "pwm3_pin_86_grp" };
2560static struct spear_function pwm3_function = {
2561 .name = "pwm3",
2562 .groups = pwm3_grps,
2563 .ngroups = ARRAY_SIZE(pwm3_grps),
2564};
2565
2566/* Pad multiplexing for SSP1 device */
2567static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
2568 { 65, 68 }, { 94, 97 } };
2569static struct spear_muxreg ssp1_muxreg[] = {
2570 {
2571 .reg = PMX_CONFIG_REG,
2572 .mask = PMX_MII_MASK,
2573 .val = 0,
2574 },
2575};
2576
2577static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
2578 {
2579 .reg = IP_SEL_PAD_10_19_REG,
2580 .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2581 .val = PMX_SSP1_PL_17_18_19_20_VAL,
2582 }, {
2583 .reg = IP_SEL_PAD_20_29_REG,
2584 .mask = PMX_PL_20_MASK,
2585 .val = PMX_SSP1_PL_17_18_19_20_VAL,
2586 }, {
2587 .reg = IP_SEL_MIX_PAD_REG,
2588 .mask = PMX_SSP1_PORT_SEL_MASK,
2589 .val = PMX_SSP1_PORT_17_TO_20_VAL,
2590 },
2591};
2592
2593static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
2594 {
2595 .reg = PMX_CONFIG_REG,
2596 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
2597 .val = 0,
2598 }, {
2599 .reg = IP_SEL_PAD_30_39_REG,
2600 .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
2601 .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
2602 PMX_SSP1_PL_39_VAL,
2603 }, {
2604 .reg = IP_SEL_MIX_PAD_REG,
2605 .mask = PMX_SSP1_PORT_SEL_MASK,
2606 .val = PMX_SSP1_PORT_36_TO_39_VAL,
2607 },
2608};
2609
2610static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
2611 {
2612 .reg = PMX_CONFIG_REG,
2613 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2614 .val = 0,
2615 }, {
2616 .reg = IP_SEL_PAD_40_49_REG,
2617 .mask = PMX_PL_48_49_MASK,
2618 .val = PMX_SSP1_PL_48_49_VAL,
2619 }, {
2620 .reg = IP_SEL_PAD_50_59_REG,
2621 .mask = PMX_PL_50_51_MASK,
2622 .val = PMX_SSP1_PL_50_51_VAL,
2623 }, {
2624 .reg = IP_SEL_MIX_PAD_REG,
2625 .mask = PMX_SSP1_PORT_SEL_MASK,
2626 .val = PMX_SSP1_PORT_48_TO_51_VAL,
2627 },
2628};
2629
2630static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
2631 {
2632 .reg = IP_SEL_PAD_60_69_REG,
2633 .mask = PMX_PL_65_TO_68_MASK,
2634 .val = PMX_SSP1_PL_65_TO_68_VAL,
2635 }, {
2636 .reg = IP_SEL_MIX_PAD_REG,
2637 .mask = PMX_SSP1_PORT_SEL_MASK,
2638 .val = PMX_SSP1_PORT_65_TO_68_VAL,
2639 },
2640};
2641
2642static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
2643 {
2644 .reg = IP_SEL_PAD_90_99_REG,
2645 .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2646 .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
2647 }, {
2648 .reg = IP_SEL_MIX_PAD_REG,
2649 .mask = PMX_SSP1_PORT_SEL_MASK,
2650 .val = PMX_SSP1_PORT_94_TO_97_VAL,
2651 },
2652};
2653
2654static struct spear_modemux ssp1_17_20_modemux[] = {
2655 {
2656 .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
2657 EXTENDED_MODE,
2658 .muxregs = ssp1_muxreg,
2659 .nmuxregs = ARRAY_SIZE(ssp1_muxreg),
2660 }, {
2661 .modes = EXTENDED_MODE,
2662 .muxregs = ssp1_ext_17_20_muxreg,
2663 .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
2664 },
2665};
2666
2667static struct spear_modemux ssp1_36_39_modemux[] = {
2668 {
2669 .modes = EXTENDED_MODE,
2670 .muxregs = ssp1_ext_36_39_muxreg,
2671 .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
2672 },
2673};
2674
2675static struct spear_modemux ssp1_48_51_modemux[] = {
2676 {
2677 .modes = EXTENDED_MODE,
2678 .muxregs = ssp1_ext_48_51_muxreg,
2679 .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
2680 },
2681};
2682static struct spear_modemux ssp1_65_68_modemux[] = {
2683 {
2684 .modes = EXTENDED_MODE,
2685 .muxregs = ssp1_ext_65_68_muxreg,
2686 .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
2687 },
2688};
2689
2690static struct spear_modemux ssp1_94_97_modemux[] = {
2691 {
2692 .modes = EXTENDED_MODE,
2693 .muxregs = ssp1_ext_94_97_muxreg,
2694 .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
2695 },
2696};
2697
2698static struct spear_pingroup ssp1_pingroup[] = {
2699 {
2700 .name = "ssp1_17_20_grp",
2701 .pins = ssp1_pins[0],
2702 .npins = ARRAY_SIZE(ssp1_pins[0]),
2703 .modemuxs = ssp1_17_20_modemux,
2704 .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
2705 }, {
2706 .name = "ssp1_36_39_grp",
2707 .pins = ssp1_pins[1],
2708 .npins = ARRAY_SIZE(ssp1_pins[1]),
2709 .modemuxs = ssp1_36_39_modemux,
2710 .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
2711 }, {
2712 .name = "ssp1_48_51_grp",
2713 .pins = ssp1_pins[2],
2714 .npins = ARRAY_SIZE(ssp1_pins[2]),
2715 .modemuxs = ssp1_48_51_modemux,
2716 .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
2717 }, {
2718 .name = "ssp1_65_68_grp",
2719 .pins = ssp1_pins[3],
2720 .npins = ARRAY_SIZE(ssp1_pins[3]),
2721 .modemuxs = ssp1_65_68_modemux,
2722 .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
2723 }, {
2724 .name = "ssp1_94_97_grp",
2725 .pins = ssp1_pins[4],
2726 .npins = ARRAY_SIZE(ssp1_pins[4]),
2727 .modemuxs = ssp1_94_97_modemux,
2728 .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
2729 },
2730};
2731
2732static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
2733 "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
2734};
2735static struct spear_function ssp1_function = {
2736 .name = "ssp1",
2737 .groups = ssp1_grps,
2738 .ngroups = ARRAY_SIZE(ssp1_grps),
2739};
2740
2741/* Pad multiplexing for SSP2 device */
2742static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
2743 { 61, 64 }, { 90, 93 } };
2744static struct spear_muxreg ssp2_muxreg[] = {
2745 {
2746 .reg = PMX_CONFIG_REG,
2747 .mask = PMX_MII_MASK,
2748 .val = 0,
2749 },
2750};
2751
2752static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
2753 {
2754 .reg = IP_SEL_PAD_10_19_REG,
2755 .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
2756 .val = PMX_SSP2_PL_13_14_15_16_VAL,
2757 }, {
2758 .reg = IP_SEL_MIX_PAD_REG,
2759 .mask = PMX_SSP2_PORT_SEL_MASK,
2760 .val = PMX_SSP2_PORT_13_TO_16_VAL,
2761 },
2762};
2763
2764static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
2765 {
2766 .reg = PMX_CONFIG_REG,
2767 .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
2768 PMX_GPIO_PIN5_MASK,
2769 .val = 0,
2770 }, {
2771 .reg = IP_SEL_PAD_30_39_REG,
2772 .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
2773 .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
2774 PMX_SSP2_PL_35_VAL,
2775 }, {
2776 .reg = IP_SEL_MIX_PAD_REG,
2777 .mask = PMX_SSP2_PORT_SEL_MASK,
2778 .val = PMX_SSP2_PORT_32_TO_35_VAL,
2779 },
2780};
2781
2782static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
2783 {
2784 .reg = PMX_CONFIG_REG,
2785 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2786 .val = 0,
2787 }, {
2788 .reg = IP_SEL_PAD_40_49_REG,
2789 .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
2790 .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
2791 }, {
2792 .reg = IP_SEL_MIX_PAD_REG,
2793 .mask = PMX_SSP2_PORT_SEL_MASK,
2794 .val = PMX_SSP2_PORT_44_TO_47_VAL,
2795 },
2796};
2797
2798static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
2799 {
2800 .reg = IP_SEL_PAD_60_69_REG,
2801 .mask = PMX_PL_61_TO_64_MASK,
2802 .val = PMX_SSP2_PL_61_TO_64_VAL,
2803 }, {
2804 .reg = IP_SEL_MIX_PAD_REG,
2805 .mask = PMX_SSP2_PORT_SEL_MASK,
2806 .val = PMX_SSP2_PORT_61_TO_64_VAL,
2807 },
2808};
2809
2810static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
2811 {
2812 .reg = IP_SEL_PAD_90_99_REG,
2813 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
2814 .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
2815 }, {
2816 .reg = IP_SEL_MIX_PAD_REG,
2817 .mask = PMX_SSP2_PORT_SEL_MASK,
2818 .val = PMX_SSP2_PORT_90_TO_93_VAL,
2819 },
2820};
2821
2822static struct spear_modemux ssp2_13_16_modemux[] = {
2823 {
2824 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
2825 .muxregs = ssp2_muxreg,
2826 .nmuxregs = ARRAY_SIZE(ssp2_muxreg),
2827 }, {
2828 .modes = EXTENDED_MODE,
2829 .muxregs = ssp2_ext_13_16_muxreg,
2830 .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
2831 },
2832};
2833
2834static struct spear_modemux ssp2_32_35_modemux[] = {
2835 {
2836 .modes = EXTENDED_MODE,
2837 .muxregs = ssp2_ext_32_35_muxreg,
2838 .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
2839 },
2840};
2841
2842static struct spear_modemux ssp2_44_47_modemux[] = {
2843 {
2844 .modes = EXTENDED_MODE,
2845 .muxregs = ssp2_ext_44_47_muxreg,
2846 .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
2847 },
2848};
2849
2850static struct spear_modemux ssp2_61_64_modemux[] = {
2851 {
2852 .modes = EXTENDED_MODE,
2853 .muxregs = ssp2_ext_61_64_muxreg,
2854 .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
2855 },
2856};
2857
2858static struct spear_modemux ssp2_90_93_modemux[] = {
2859 {
2860 .modes = EXTENDED_MODE,
2861 .muxregs = ssp2_ext_90_93_muxreg,
2862 .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
2863 },
2864};
2865
2866static struct spear_pingroup ssp2_pingroup[] = {
2867 {
2868 .name = "ssp2_13_16_grp",
2869 .pins = ssp2_pins[0],
2870 .npins = ARRAY_SIZE(ssp2_pins[0]),
2871 .modemuxs = ssp2_13_16_modemux,
2872 .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
2873 }, {
2874 .name = "ssp2_32_35_grp",
2875 .pins = ssp2_pins[1],
2876 .npins = ARRAY_SIZE(ssp2_pins[1]),
2877 .modemuxs = ssp2_32_35_modemux,
2878 .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
2879 }, {
2880 .name = "ssp2_44_47_grp",
2881 .pins = ssp2_pins[2],
2882 .npins = ARRAY_SIZE(ssp2_pins[2]),
2883 .modemuxs = ssp2_44_47_modemux,
2884 .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
2885 }, {
2886 .name = "ssp2_61_64_grp",
2887 .pins = ssp2_pins[3],
2888 .npins = ARRAY_SIZE(ssp2_pins[3]),
2889 .modemuxs = ssp2_61_64_modemux,
2890 .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
2891 }, {
2892 .name = "ssp2_90_93_grp",
2893 .pins = ssp2_pins[4],
2894 .npins = ARRAY_SIZE(ssp2_pins[4]),
2895 .modemuxs = ssp2_90_93_modemux,
2896 .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
2897 },
2898};
2899
2900static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
2901 "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
2902static struct spear_function ssp2_function = {
2903 .name = "ssp2",
2904 .groups = ssp2_grps,
2905 .ngroups = ARRAY_SIZE(ssp2_grps),
2906};
2907
2908/* Pad multiplexing for cadence mii2 as mii device */
2909static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
2910 90, 91, 92, 93, 94, 95, 96, 97 };
2911static struct spear_muxreg mii2_muxreg[] = {
2912 {
2913 .reg = IP_SEL_PAD_80_89_REG,
2914 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
2915 PMX_PL_88_89_MASK,
2916 .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
2917 PMX_MII2_PL_88_89_VAL,
2918 }, {
2919 .reg = IP_SEL_PAD_90_99_REG,
2920 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
2921 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2922 .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
2923 PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
2924 }, {
2925 .reg = EXT_CTRL_REG,
2926 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2927 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2928 MII_MDIO_MASK,
2929 .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
2930 (MAC_MODE_MII << MAC1_MODE_SHIFT) |
2931 MII_MDIO_81_VAL,
2932 },
2933};
2934
2935static struct spear_modemux mii2_modemux[] = {
2936 {
2937 .modes = EXTENDED_MODE,
2938 .muxregs = mii2_muxreg,
2939 .nmuxregs = ARRAY_SIZE(mii2_muxreg),
2940 },
2941};
2942
2943static struct spear_pingroup mii2_pingroup = {
2944 .name = "mii2_grp",
2945 .pins = mii2_pins,
2946 .npins = ARRAY_SIZE(mii2_pins),
2947 .modemuxs = mii2_modemux,
2948 .nmodemuxs = ARRAY_SIZE(mii2_modemux),
2949};
2950
2951static const char *const mii2_grps[] = { "mii2_grp" };
2952static struct spear_function mii2_function = {
2953 .name = "mii2",
2954 .groups = mii2_grps,
2955 .ngroups = ARRAY_SIZE(mii2_grps),
2956};
2957
2958/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
2959static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
2960 21, 22, 23, 24, 25, 26, 27 };
2961static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
2962static struct spear_muxreg mii0_1_muxreg[] = {
2963 {
2964 .reg = PMX_CONFIG_REG,
2965 .mask = PMX_MII_MASK,
2966 .val = 0,
2967 },
2968};
2969
2970static struct spear_muxreg smii0_1_ext_muxreg[] = {
2971 {
2972 .reg = IP_SEL_PAD_10_19_REG,
2973 .mask = PMX_PL_10_11_MASK,
2974 .val = PMX_SMII_PL_10_11_VAL,
2975 }, {
2976 .reg = IP_SEL_PAD_20_29_REG,
2977 .mask = PMX_PL_21_TO_27_MASK,
2978 .val = PMX_SMII_PL_21_TO_27_VAL,
2979 }, {
2980 .reg = EXT_CTRL_REG,
2981 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2982 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2983 MII_MDIO_MASK,
2984 .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
2985 | (MAC_MODE_SMII << MAC1_MODE_SHIFT)
2986 | MII_MDIO_10_11_VAL,
2987 },
2988};
2989
2990static struct spear_muxreg rmii0_1_ext_muxreg[] = {
2991 {
2992 .reg = IP_SEL_PAD_10_19_REG,
2993 .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
2994 PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2995 .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
2996 PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
2997 PMX_RMII_PL_19_VAL,
2998 }, {
2999 .reg = IP_SEL_PAD_20_29_REG,
3000 .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
3001 .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
3002 }, {
3003 .reg = EXT_CTRL_REG,
3004 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
3005 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
3006 MII_MDIO_MASK,
3007 .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
3008 | (MAC_MODE_RMII << MAC1_MODE_SHIFT)
3009 | MII_MDIO_10_11_VAL,
3010 },
3011};
3012
3013static struct spear_modemux mii0_1_modemux[][2] = {
3014 {
3015 /* configure as smii */
3016 {
3017 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3018 SMALL_PRINTERS_MODE | EXTENDED_MODE,
3019 .muxregs = mii0_1_muxreg,
3020 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3021 }, {
3022 .modes = EXTENDED_MODE,
3023 .muxregs = smii0_1_ext_muxreg,
3024 .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
3025 },
3026 }, {
3027 /* configure as rmii */
3028 {
3029 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3030 SMALL_PRINTERS_MODE | EXTENDED_MODE,
3031 .muxregs = mii0_1_muxreg,
3032 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3033 }, {
3034 .modes = EXTENDED_MODE,
3035 .muxregs = rmii0_1_ext_muxreg,
3036 .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
3037 },
3038 },
3039};
3040
3041static struct spear_pingroup mii0_1_pingroup[] = {
3042 {
3043 .name = "smii0_1_grp",
3044 .pins = smii0_1_pins,
3045 .npins = ARRAY_SIZE(smii0_1_pins),
3046 .modemuxs = mii0_1_modemux[0],
3047 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
3048 }, {
3049 .name = "rmii0_1_grp",
3050 .pins = rmii0_1_pins,
3051 .npins = ARRAY_SIZE(rmii0_1_pins),
3052 .modemuxs = mii0_1_modemux[1],
3053 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
3054 },
3055};
3056
3057static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
3058static struct spear_function mii0_1_function = {
3059 .name = "mii0_1",
3060 .groups = mii0_1_grps,
3061 .ngroups = ARRAY_SIZE(mii0_1_grps),
3062};
3063
3064/* Pad multiplexing for i2c1 device */
3065static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
3066static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
3067 {
3068 .reg = PMX_CONFIG_REG,
3069 .mask = PMX_SSP_CS_MASK,
3070 .val = 0,
3071 }, {
3072 .reg = IP_SEL_PAD_0_9_REG,
3073 .mask = PMX_PL_8_9_MASK,
3074 .val = PMX_I2C1_PL_8_9_VAL,
3075 }, {
3076 .reg = IP_SEL_MIX_PAD_REG,
3077 .mask = PMX_I2C1_PORT_SEL_MASK,
3078 .val = PMX_I2C1_PORT_8_9_VAL,
3079 },
3080};
3081
3082static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
3083 {
3084 .reg = IP_SEL_PAD_90_99_REG,
3085 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
3086 .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
3087 }, {
3088 .reg = IP_SEL_MIX_PAD_REG,
3089 .mask = PMX_I2C1_PORT_SEL_MASK,
3090 .val = PMX_I2C1_PORT_98_99_VAL,
3091 },
3092};
3093
3094static struct spear_modemux i2c1_modemux[][1] = {
3095 {
3096 /* Select signals on pins 8-9 */
3097 {
3098 .modes = EXTENDED_MODE,
3099 .muxregs = i2c1_ext_8_9_muxreg,
3100 .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
3101 },
3102 }, {
3103 /* Select signals on pins 98-99 */
3104 {
3105 .modes = EXTENDED_MODE,
3106 .muxregs = i2c1_ext_98_99_muxreg,
3107 .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
3108 },
3109 },
3110};
3111
3112static struct spear_pingroup i2c1_pingroup[] = {
3113 {
3114 .name = "i2c1_8_9_grp",
3115 .pins = i2c1_pins[0],
3116 .npins = ARRAY_SIZE(i2c1_pins[0]),
3117 .modemuxs = i2c1_modemux[0],
3118 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
3119 }, {
3120 .name = "i2c1_98_99_grp",
3121 .pins = i2c1_pins[1],
3122 .npins = ARRAY_SIZE(i2c1_pins[1]),
3123 .modemuxs = i2c1_modemux[1],
3124 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
3125 },
3126};
3127
3128static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
3129static struct spear_function i2c1_function = {
3130 .name = "i2c1",
3131 .groups = i2c1_grps,
3132 .ngroups = ARRAY_SIZE(i2c1_grps),
3133};
3134
3135/* Pad multiplexing for i2c2 device */
3136static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
3137 { 75, 76 }, { 96, 97 } };
3138static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
3139 {
3140 .reg = PMX_CONFIG_REG,
3141 .mask = PMX_FIRDA_MASK,
3142 .val = 0,
3143 }, {
3144 .reg = IP_SEL_PAD_0_9_REG,
3145 .mask = PMX_PL_0_1_MASK,
3146 .val = PMX_I2C2_PL_0_1_VAL,
3147 }, {
3148 .reg = IP_SEL_MIX_PAD_REG,
3149 .mask = PMX_I2C2_PORT_SEL_MASK,
3150 .val = PMX_I2C2_PORT_0_1_VAL,
3151 },
3152};
3153
3154static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
3155 {
3156 .reg = PMX_CONFIG_REG,
3157 .mask = PMX_UART0_MASK,
3158 .val = 0,
3159 }, {
3160 .reg = IP_SEL_PAD_0_9_REG,
3161 .mask = PMX_PL_2_3_MASK,
3162 .val = PMX_I2C2_PL_2_3_VAL,
3163 }, {
3164 .reg = IP_SEL_MIX_PAD_REG,
3165 .mask = PMX_I2C2_PORT_SEL_MASK,
3166 .val = PMX_I2C2_PORT_2_3_VAL,
3167 },
3168};
3169
3170static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
3171 {
3172 .reg = PMX_CONFIG_REG,
3173 .mask = PMX_MII_MASK,
3174 .val = 0,
3175 }, {
3176 .reg = IP_SEL_PAD_10_19_REG,
3177 .mask = PMX_PL_19_MASK,
3178 .val = PMX_I2C2_PL_19_VAL,
3179 }, {
3180 .reg = IP_SEL_PAD_20_29_REG,
3181 .mask = PMX_PL_20_MASK,
3182 .val = PMX_I2C2_PL_20_VAL,
3183 }, {
3184 .reg = IP_SEL_MIX_PAD_REG,
3185 .mask = PMX_I2C2_PORT_SEL_MASK,
3186 .val = PMX_I2C2_PORT_19_20_VAL,
3187 },
3188};
3189
3190static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
3191 {
3192 .reg = IP_SEL_PAD_70_79_REG,
3193 .mask = PMX_PL_75_76_MASK,
3194 .val = PMX_I2C2_PL_75_76_VAL,
3195 }, {
3196 .reg = IP_SEL_MIX_PAD_REG,
3197 .mask = PMX_I2C2_PORT_SEL_MASK,
3198 .val = PMX_I2C2_PORT_75_76_VAL,
3199 },
3200};
3201
3202static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
3203 {
3204 .reg = IP_SEL_PAD_90_99_REG,
3205 .mask = PMX_PL_96_97_MASK,
3206 .val = PMX_I2C2_PL_96_97_VAL,
3207 }, {
3208 .reg = IP_SEL_MIX_PAD_REG,
3209 .mask = PMX_I2C2_PORT_SEL_MASK,
3210 .val = PMX_I2C2_PORT_96_97_VAL,
3211 },
3212};
3213
3214static struct spear_modemux i2c2_modemux[][1] = {
3215 {
3216 /* Select signals on pins 0_1 */
3217 {
3218 .modes = EXTENDED_MODE,
3219 .muxregs = i2c2_ext_0_1_muxreg,
3220 .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
3221 },
3222 }, {
3223 /* Select signals on pins 2_3 */
3224 {
3225 .modes = EXTENDED_MODE,
3226 .muxregs = i2c2_ext_2_3_muxreg,
3227 .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
3228 },
3229 }, {
3230 /* Select signals on pins 19_20 */
3231 {
3232 .modes = EXTENDED_MODE,
3233 .muxregs = i2c2_ext_19_20_muxreg,
3234 .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
3235 },
3236 }, {
3237 /* Select signals on pins 75_76 */
3238 {
3239 .modes = EXTENDED_MODE,
3240 .muxregs = i2c2_ext_75_76_muxreg,
3241 .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
3242 },
3243 }, {
3244 /* Select signals on pins 96_97 */
3245 {
3246 .modes = EXTENDED_MODE,
3247 .muxregs = i2c2_ext_96_97_muxreg,
3248 .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
3249 },
3250 },
3251};
3252
3253static struct spear_pingroup i2c2_pingroup[] = {
3254 {
3255 .name = "i2c2_0_1_grp",
3256 .pins = i2c2_pins[0],
3257 .npins = ARRAY_SIZE(i2c2_pins[0]),
3258 .modemuxs = i2c2_modemux[0],
3259 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
3260 }, {
3261 .name = "i2c2_2_3_grp",
3262 .pins = i2c2_pins[1],
3263 .npins = ARRAY_SIZE(i2c2_pins[1]),
3264 .modemuxs = i2c2_modemux[1],
3265 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
3266 }, {
3267 .name = "i2c2_19_20_grp",
3268 .pins = i2c2_pins[2],
3269 .npins = ARRAY_SIZE(i2c2_pins[2]),
3270 .modemuxs = i2c2_modemux[2],
3271 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
3272 }, {
3273 .name = "i2c2_75_76_grp",
3274 .pins = i2c2_pins[3],
3275 .npins = ARRAY_SIZE(i2c2_pins[3]),
3276 .modemuxs = i2c2_modemux[3],
3277 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
3278 }, {
3279 .name = "i2c2_96_97_grp",
3280 .pins = i2c2_pins[4],
3281 .npins = ARRAY_SIZE(i2c2_pins[4]),
3282 .modemuxs = i2c2_modemux[4],
3283 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
3284 },
3285};
3286
3287static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
3288 "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
3289static struct spear_function i2c2_function = {
3290 .name = "i2c2",
3291 .groups = i2c2_grps,
3292 .ngroups = ARRAY_SIZE(i2c2_grps),
3293};
3294
3295/* pingroups */
3296static struct spear_pingroup *spear320_pingroups[] = {
3297 SPEAR3XX_COMMON_PINGROUPS,
3298 &clcd_pingroup,
3299 &emi_pingroup,
3300 &fsmc_8bit_pingroup,
3301 &fsmc_16bit_pingroup,
3302 &spp_pingroup,
3303 &sdhci_led_pingroup,
3304 &sdhci_pingroup[0],
3305 &sdhci_pingroup[1],
3306 &i2s_pingroup,
3307 &uart1_pingroup,
3308 &uart1_modem_pingroup[0],
3309 &uart1_modem_pingroup[1],
3310 &uart1_modem_pingroup[2],
3311 &uart1_modem_pingroup[3],
3312 &uart2_pingroup,
3313 &uart3_pingroup[0],
3314 &uart3_pingroup[1],
3315 &uart3_pingroup[2],
3316 &uart3_pingroup[3],
3317 &uart3_pingroup[4],
3318 &uart3_pingroup[5],
3319 &uart3_pingroup[6],
3320 &uart4_pingroup[0],
3321 &uart4_pingroup[1],
3322 &uart4_pingroup[2],
3323 &uart4_pingroup[3],
3324 &uart4_pingroup[4],
3325 &uart4_pingroup[5],
3326 &uart5_pingroup[0],
3327 &uart5_pingroup[1],
3328 &uart5_pingroup[2],
3329 &uart5_pingroup[3],
3330 &uart6_pingroup[0],
3331 &uart6_pingroup[1],
3332 &rs485_pingroup,
3333 &touchscreen_pingroup,
3334 &can0_pingroup,
3335 &can1_pingroup,
3336 &pwm0_1_pingroup[0],
3337 &pwm0_1_pingroup[1],
3338 &pwm0_1_pingroup[2],
3339 &pwm0_1_pingroup[3],
3340 &pwm0_1_pingroup[4],
3341 &pwm0_1_pingroup[5],
3342 &pwm0_1_pingroup[6],
3343 &pwm2_pingroup[0],
3344 &pwm2_pingroup[1],
3345 &pwm2_pingroup[2],
3346 &pwm2_pingroup[3],
3347 &pwm2_pingroup[4],
3348 &pwm2_pingroup[5],
3349 &pwm2_pingroup[6],
3350 &pwm3_pingroup[0],
3351 &pwm3_pingroup[1],
3352 &pwm3_pingroup[2],
3353 &pwm3_pingroup[3],
3354 &pwm3_pingroup[4],
3355 &pwm3_pingroup[5],
3356 &ssp1_pingroup[0],
3357 &ssp1_pingroup[1],
3358 &ssp1_pingroup[2],
3359 &ssp1_pingroup[3],
3360 &ssp1_pingroup[4],
3361 &ssp2_pingroup[0],
3362 &ssp2_pingroup[1],
3363 &ssp2_pingroup[2],
3364 &ssp2_pingroup[3],
3365 &ssp2_pingroup[4],
3366 &mii2_pingroup,
3367 &mii0_1_pingroup[0],
3368 &mii0_1_pingroup[1],
3369 &i2c1_pingroup[0],
3370 &i2c1_pingroup[1],
3371 &i2c2_pingroup[0],
3372 &i2c2_pingroup[1],
3373 &i2c2_pingroup[2],
3374 &i2c2_pingroup[3],
3375 &i2c2_pingroup[4],
3376};
3377
3378/* functions */
3379static struct spear_function *spear320_functions[] = {
3380 SPEAR3XX_COMMON_FUNCTIONS,
3381 &clcd_function,
3382 &emi_function,
3383 &fsmc_function,
3384 &spp_function,
3385 &sdhci_function,
3386 &i2s_function,
3387 &uart1_function,
3388 &uart1_modem_function,
3389 &uart2_function,
3390 &uart3_function,
3391 &uart4_function,
3392 &uart5_function,
3393 &uart6_function,
3394 &rs485_function,
3395 &touchscreen_function,
3396 &can0_function,
3397 &can1_function,
3398 &pwm0_1_function,
3399 &pwm2_function,
3400 &pwm3_function,
3401 &ssp1_function,
3402 &ssp2_function,
3403 &mii2_function,
3404 &mii0_1_function,
3405 &i2c1_function,
3406 &i2c2_function,
3407};
3408
3409static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = {
3410 {
3411 .compatible = "st,spear320-pinmux",
3412 },
3413 {},
3414};
3415
3416static int __devinit spear320_pinctrl_probe(struct platform_device *pdev)
3417{
3418 int ret;
3419
3420 spear3xx_machdata.groups = spear320_pingroups;
3421 spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
3422 spear3xx_machdata.functions = spear320_functions;
3423 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
3424
3425 spear3xx_machdata.modes_supported = true;
3426 spear3xx_machdata.pmx_modes = spear320_pmx_modes;
3427 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
3428
3429 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
3430
3431 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
3432 if (ret)
3433 return ret;
3434
3435 return 0;
3436}
3437
3438static int __devexit spear320_pinctrl_remove(struct platform_device *pdev)
3439{
3440 return spear_pinctrl_remove(pdev);
3441}
3442
3443static struct platform_driver spear320_pinctrl_driver = {
3444 .driver = {
3445 .name = DRIVER_NAME,
3446 .owner = THIS_MODULE,
3447 .of_match_table = spear320_pinctrl_of_match,
3448 },
3449 .probe = spear320_pinctrl_probe,
3450 .remove = __devexit_p(spear320_pinctrl_remove),
3451};
3452
3453static int __init spear320_pinctrl_init(void)
3454{
3455 return platform_driver_register(&spear320_pinctrl_driver);
3456}
3457arch_initcall(spear320_pinctrl_init);
3458
3459static void __exit spear320_pinctrl_exit(void)
3460{
3461 platform_driver_unregister(&spear320_pinctrl_driver);
3462}
3463module_exit(spear320_pinctrl_exit);
3464
3465MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
3466MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver");
3467MODULE_LICENSE("GPL v2");
3468MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.c b/drivers/pinctrl/spear/pinctrl-spear3xx.c
new file mode 100644
index 00000000000..832049a8b1c
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.c
@@ -0,0 +1,588 @@
1/*
2 * Driver for the ST Microelectronics SPEAr3xx pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/pinctrl/pinctrl.h>
13
14#include "pinctrl-spear3xx.h"
15
16/* pins */
17static const struct pinctrl_pin_desc spear3xx_pins[] = {
18 PINCTRL_PIN(0, "PLGPIO0"),
19 PINCTRL_PIN(1, "PLGPIO1"),
20 PINCTRL_PIN(2, "PLGPIO2"),
21 PINCTRL_PIN(3, "PLGPIO3"),
22 PINCTRL_PIN(4, "PLGPIO4"),
23 PINCTRL_PIN(5, "PLGPIO5"),
24 PINCTRL_PIN(6, "PLGPIO6"),
25 PINCTRL_PIN(7, "PLGPIO7"),
26 PINCTRL_PIN(8, "PLGPIO8"),
27 PINCTRL_PIN(9, "PLGPIO9"),
28 PINCTRL_PIN(10, "PLGPIO10"),
29 PINCTRL_PIN(11, "PLGPIO11"),
30 PINCTRL_PIN(12, "PLGPIO12"),
31 PINCTRL_PIN(13, "PLGPIO13"),
32 PINCTRL_PIN(14, "PLGPIO14"),
33 PINCTRL_PIN(15, "PLGPIO15"),
34 PINCTRL_PIN(16, "PLGPIO16"),
35 PINCTRL_PIN(17, "PLGPIO17"),
36 PINCTRL_PIN(18, "PLGPIO18"),
37 PINCTRL_PIN(19, "PLGPIO19"),
38 PINCTRL_PIN(20, "PLGPIO20"),
39 PINCTRL_PIN(21, "PLGPIO21"),
40 PINCTRL_PIN(22, "PLGPIO22"),
41 PINCTRL_PIN(23, "PLGPIO23"),
42 PINCTRL_PIN(24, "PLGPIO24"),
43 PINCTRL_PIN(25, "PLGPIO25"),
44 PINCTRL_PIN(26, "PLGPIO26"),
45 PINCTRL_PIN(27, "PLGPIO27"),
46 PINCTRL_PIN(28, "PLGPIO28"),
47 PINCTRL_PIN(29, "PLGPIO29"),
48 PINCTRL_PIN(30, "PLGPIO30"),
49 PINCTRL_PIN(31, "PLGPIO31"),
50 PINCTRL_PIN(32, "PLGPIO32"),
51 PINCTRL_PIN(33, "PLGPIO33"),
52 PINCTRL_PIN(34, "PLGPIO34"),
53 PINCTRL_PIN(35, "PLGPIO35"),
54 PINCTRL_PIN(36, "PLGPIO36"),
55 PINCTRL_PIN(37, "PLGPIO37"),
56 PINCTRL_PIN(38, "PLGPIO38"),
57 PINCTRL_PIN(39, "PLGPIO39"),
58 PINCTRL_PIN(40, "PLGPIO40"),
59 PINCTRL_PIN(41, "PLGPIO41"),
60 PINCTRL_PIN(42, "PLGPIO42"),
61 PINCTRL_PIN(43, "PLGPIO43"),
62 PINCTRL_PIN(44, "PLGPIO44"),
63 PINCTRL_PIN(45, "PLGPIO45"),
64 PINCTRL_PIN(46, "PLGPIO46"),
65 PINCTRL_PIN(47, "PLGPIO47"),
66 PINCTRL_PIN(48, "PLGPIO48"),
67 PINCTRL_PIN(49, "PLGPIO49"),
68 PINCTRL_PIN(50, "PLGPIO50"),
69 PINCTRL_PIN(51, "PLGPIO51"),
70 PINCTRL_PIN(52, "PLGPIO52"),
71 PINCTRL_PIN(53, "PLGPIO53"),
72 PINCTRL_PIN(54, "PLGPIO54"),
73 PINCTRL_PIN(55, "PLGPIO55"),
74 PINCTRL_PIN(56, "PLGPIO56"),
75 PINCTRL_PIN(57, "PLGPIO57"),
76 PINCTRL_PIN(58, "PLGPIO58"),
77 PINCTRL_PIN(59, "PLGPIO59"),
78 PINCTRL_PIN(60, "PLGPIO60"),
79 PINCTRL_PIN(61, "PLGPIO61"),
80 PINCTRL_PIN(62, "PLGPIO62"),
81 PINCTRL_PIN(63, "PLGPIO63"),
82 PINCTRL_PIN(64, "PLGPIO64"),
83 PINCTRL_PIN(65, "PLGPIO65"),
84 PINCTRL_PIN(66, "PLGPIO66"),
85 PINCTRL_PIN(67, "PLGPIO67"),
86 PINCTRL_PIN(68, "PLGPIO68"),
87 PINCTRL_PIN(69, "PLGPIO69"),
88 PINCTRL_PIN(70, "PLGPIO70"),
89 PINCTRL_PIN(71, "PLGPIO71"),
90 PINCTRL_PIN(72, "PLGPIO72"),
91 PINCTRL_PIN(73, "PLGPIO73"),
92 PINCTRL_PIN(74, "PLGPIO74"),
93 PINCTRL_PIN(75, "PLGPIO75"),
94 PINCTRL_PIN(76, "PLGPIO76"),
95 PINCTRL_PIN(77, "PLGPIO77"),
96 PINCTRL_PIN(78, "PLGPIO78"),
97 PINCTRL_PIN(79, "PLGPIO79"),
98 PINCTRL_PIN(80, "PLGPIO80"),
99 PINCTRL_PIN(81, "PLGPIO81"),
100 PINCTRL_PIN(82, "PLGPIO82"),
101 PINCTRL_PIN(83, "PLGPIO83"),
102 PINCTRL_PIN(84, "PLGPIO84"),
103 PINCTRL_PIN(85, "PLGPIO85"),
104 PINCTRL_PIN(86, "PLGPIO86"),
105 PINCTRL_PIN(87, "PLGPIO87"),
106 PINCTRL_PIN(88, "PLGPIO88"),
107 PINCTRL_PIN(89, "PLGPIO89"),
108 PINCTRL_PIN(90, "PLGPIO90"),
109 PINCTRL_PIN(91, "PLGPIO91"),
110 PINCTRL_PIN(92, "PLGPIO92"),
111 PINCTRL_PIN(93, "PLGPIO93"),
112 PINCTRL_PIN(94, "PLGPIO94"),
113 PINCTRL_PIN(95, "PLGPIO95"),
114 PINCTRL_PIN(96, "PLGPIO96"),
115 PINCTRL_PIN(97, "PLGPIO97"),
116 PINCTRL_PIN(98, "PLGPIO98"),
117 PINCTRL_PIN(99, "PLGPIO99"),
118 PINCTRL_PIN(100, "PLGPIO100"),
119 PINCTRL_PIN(101, "PLGPIO101"),
120};
121
122/* firda_pins */
123static const unsigned firda_pins[] = { 0, 1 };
124static struct spear_muxreg firda_muxreg[] = {
125 {
126 .reg = -1,
127 .mask = PMX_FIRDA_MASK,
128 .val = PMX_FIRDA_MASK,
129 },
130};
131
132static struct spear_modemux firda_modemux[] = {
133 {
134 .modes = ~0,
135 .muxregs = firda_muxreg,
136 .nmuxregs = ARRAY_SIZE(firda_muxreg),
137 },
138};
139
140struct spear_pingroup spear3xx_firda_pingroup = {
141 .name = "firda_grp",
142 .pins = firda_pins,
143 .npins = ARRAY_SIZE(firda_pins),
144 .modemuxs = firda_modemux,
145 .nmodemuxs = ARRAY_SIZE(firda_modemux),
146};
147
148static const char *const firda_grps[] = { "firda_grp" };
149struct spear_function spear3xx_firda_function = {
150 .name = "firda",
151 .groups = firda_grps,
152 .ngroups = ARRAY_SIZE(firda_grps),
153};
154
155/* i2c_pins */
156static const unsigned i2c_pins[] = { 4, 5 };
157static struct spear_muxreg i2c_muxreg[] = {
158 {
159 .reg = -1,
160 .mask = PMX_I2C_MASK,
161 .val = PMX_I2C_MASK,
162 },
163};
164
165static struct spear_modemux i2c_modemux[] = {
166 {
167 .modes = ~0,
168 .muxregs = i2c_muxreg,
169 .nmuxregs = ARRAY_SIZE(i2c_muxreg),
170 },
171};
172
173struct spear_pingroup spear3xx_i2c_pingroup = {
174 .name = "i2c0_grp",
175 .pins = i2c_pins,
176 .npins = ARRAY_SIZE(i2c_pins),
177 .modemuxs = i2c_modemux,
178 .nmodemuxs = ARRAY_SIZE(i2c_modemux),
179};
180
181static const char *const i2c_grps[] = { "i2c0_grp" };
182struct spear_function spear3xx_i2c_function = {
183 .name = "i2c0",
184 .groups = i2c_grps,
185 .ngroups = ARRAY_SIZE(i2c_grps),
186};
187
188/* ssp_cs_pins */
189static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
190static struct spear_muxreg ssp_cs_muxreg[] = {
191 {
192 .reg = -1,
193 .mask = PMX_SSP_CS_MASK,
194 .val = PMX_SSP_CS_MASK,
195 },
196};
197
198static struct spear_modemux ssp_cs_modemux[] = {
199 {
200 .modes = ~0,
201 .muxregs = ssp_cs_muxreg,
202 .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
203 },
204};
205
206struct spear_pingroup spear3xx_ssp_cs_pingroup = {
207 .name = "ssp_cs_grp",
208 .pins = ssp_cs_pins,
209 .npins = ARRAY_SIZE(ssp_cs_pins),
210 .modemuxs = ssp_cs_modemux,
211 .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
212};
213
214static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
215struct spear_function spear3xx_ssp_cs_function = {
216 .name = "ssp_cs",
217 .groups = ssp_cs_grps,
218 .ngroups = ARRAY_SIZE(ssp_cs_grps),
219};
220
221/* ssp_pins */
222static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
223static struct spear_muxreg ssp_muxreg[] = {
224 {
225 .reg = -1,
226 .mask = PMX_SSP_MASK,
227 .val = PMX_SSP_MASK,
228 },
229};
230
231static struct spear_modemux ssp_modemux[] = {
232 {
233 .modes = ~0,
234 .muxregs = ssp_muxreg,
235 .nmuxregs = ARRAY_SIZE(ssp_muxreg),
236 },
237};
238
239struct spear_pingroup spear3xx_ssp_pingroup = {
240 .name = "ssp0_grp",
241 .pins = ssp_pins,
242 .npins = ARRAY_SIZE(ssp_pins),
243 .modemuxs = ssp_modemux,
244 .nmodemuxs = ARRAY_SIZE(ssp_modemux),
245};
246
247static const char *const ssp_grps[] = { "ssp0_grp" };
248struct spear_function spear3xx_ssp_function = {
249 .name = "ssp0",
250 .groups = ssp_grps,
251 .ngroups = ARRAY_SIZE(ssp_grps),
252};
253
254/* mii_pins */
255static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
256 21, 22, 23, 24, 25, 26, 27 };
257static struct spear_muxreg mii_muxreg[] = {
258 {
259 .reg = -1,
260 .mask = PMX_MII_MASK,
261 .val = PMX_MII_MASK,
262 },
263};
264
265static struct spear_modemux mii_modemux[] = {
266 {
267 .modes = ~0,
268 .muxregs = mii_muxreg,
269 .nmuxregs = ARRAY_SIZE(mii_muxreg),
270 },
271};
272
273struct spear_pingroup spear3xx_mii_pingroup = {
274 .name = "mii0_grp",
275 .pins = mii_pins,
276 .npins = ARRAY_SIZE(mii_pins),
277 .modemuxs = mii_modemux,
278 .nmodemuxs = ARRAY_SIZE(mii_modemux),
279};
280
281static const char *const mii_grps[] = { "mii0_grp" };
282struct spear_function spear3xx_mii_function = {
283 .name = "mii0",
284 .groups = mii_grps,
285 .ngroups = ARRAY_SIZE(mii_grps),
286};
287
288/* gpio0_pin0_pins */
289static const unsigned gpio0_pin0_pins[] = { 28 };
290static struct spear_muxreg gpio0_pin0_muxreg[] = {
291 {
292 .reg = -1,
293 .mask = PMX_GPIO_PIN0_MASK,
294 .val = PMX_GPIO_PIN0_MASK,
295 },
296};
297
298static struct spear_modemux gpio0_pin0_modemux[] = {
299 {
300 .modes = ~0,
301 .muxregs = gpio0_pin0_muxreg,
302 .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
303 },
304};
305
306struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
307 .name = "gpio0_pin0_grp",
308 .pins = gpio0_pin0_pins,
309 .npins = ARRAY_SIZE(gpio0_pin0_pins),
310 .modemuxs = gpio0_pin0_modemux,
311 .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
312};
313
314/* gpio0_pin1_pins */
315static const unsigned gpio0_pin1_pins[] = { 29 };
316static struct spear_muxreg gpio0_pin1_muxreg[] = {
317 {
318 .reg = -1,
319 .mask = PMX_GPIO_PIN1_MASK,
320 .val = PMX_GPIO_PIN1_MASK,
321 },
322};
323
324static struct spear_modemux gpio0_pin1_modemux[] = {
325 {
326 .modes = ~0,
327 .muxregs = gpio0_pin1_muxreg,
328 .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
329 },
330};
331
332struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
333 .name = "gpio0_pin1_grp",
334 .pins = gpio0_pin1_pins,
335 .npins = ARRAY_SIZE(gpio0_pin1_pins),
336 .modemuxs = gpio0_pin1_modemux,
337 .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
338};
339
340/* gpio0_pin2_pins */
341static const unsigned gpio0_pin2_pins[] = { 30 };
342static struct spear_muxreg gpio0_pin2_muxreg[] = {
343 {
344 .reg = -1,
345 .mask = PMX_GPIO_PIN2_MASK,
346 .val = PMX_GPIO_PIN2_MASK,
347 },
348};
349
350static struct spear_modemux gpio0_pin2_modemux[] = {
351 {
352 .modes = ~0,
353 .muxregs = gpio0_pin2_muxreg,
354 .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
355 },
356};
357
358struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
359 .name = "gpio0_pin2_grp",
360 .pins = gpio0_pin2_pins,
361 .npins = ARRAY_SIZE(gpio0_pin2_pins),
362 .modemuxs = gpio0_pin2_modemux,
363 .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
364};
365
366/* gpio0_pin3_pins */
367static const unsigned gpio0_pin3_pins[] = { 31 };
368static struct spear_muxreg gpio0_pin3_muxreg[] = {
369 {
370 .reg = -1,
371 .mask = PMX_GPIO_PIN3_MASK,
372 .val = PMX_GPIO_PIN3_MASK,
373 },
374};
375
376static struct spear_modemux gpio0_pin3_modemux[] = {
377 {
378 .modes = ~0,
379 .muxregs = gpio0_pin3_muxreg,
380 .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
381 },
382};
383
384struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
385 .name = "gpio0_pin3_grp",
386 .pins = gpio0_pin3_pins,
387 .npins = ARRAY_SIZE(gpio0_pin3_pins),
388 .modemuxs = gpio0_pin3_modemux,
389 .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
390};
391
392/* gpio0_pin4_pins */
393static const unsigned gpio0_pin4_pins[] = { 32 };
394static struct spear_muxreg gpio0_pin4_muxreg[] = {
395 {
396 .reg = -1,
397 .mask = PMX_GPIO_PIN4_MASK,
398 .val = PMX_GPIO_PIN4_MASK,
399 },
400};
401
402static struct spear_modemux gpio0_pin4_modemux[] = {
403 {
404 .modes = ~0,
405 .muxregs = gpio0_pin4_muxreg,
406 .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
407 },
408};
409
410struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
411 .name = "gpio0_pin4_grp",
412 .pins = gpio0_pin4_pins,
413 .npins = ARRAY_SIZE(gpio0_pin4_pins),
414 .modemuxs = gpio0_pin4_modemux,
415 .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
416};
417
418/* gpio0_pin5_pins */
419static const unsigned gpio0_pin5_pins[] = { 33 };
420static struct spear_muxreg gpio0_pin5_muxreg[] = {
421 {
422 .reg = -1,
423 .mask = PMX_GPIO_PIN5_MASK,
424 .val = PMX_GPIO_PIN5_MASK,
425 },
426};
427
428static struct spear_modemux gpio0_pin5_modemux[] = {
429 {
430 .modes = ~0,
431 .muxregs = gpio0_pin5_muxreg,
432 .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
433 },
434};
435
436struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
437 .name = "gpio0_pin5_grp",
438 .pins = gpio0_pin5_pins,
439 .npins = ARRAY_SIZE(gpio0_pin5_pins),
440 .modemuxs = gpio0_pin5_modemux,
441 .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
442};
443
444static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
445 "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
446};
447struct spear_function spear3xx_gpio0_function = {
448 .name = "gpio0",
449 .groups = gpio0_grps,
450 .ngroups = ARRAY_SIZE(gpio0_grps),
451};
452
453/* uart0_ext_pins */
454static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
455static struct spear_muxreg uart0_ext_muxreg[] = {
456 {
457 .reg = -1,
458 .mask = PMX_UART0_MODEM_MASK,
459 .val = PMX_UART0_MODEM_MASK,
460 },
461};
462
463static struct spear_modemux uart0_ext_modemux[] = {
464 {
465 .modes = ~0,
466 .muxregs = uart0_ext_muxreg,
467 .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
468 },
469};
470
471struct spear_pingroup spear3xx_uart0_ext_pingroup = {
472 .name = "uart0_ext_grp",
473 .pins = uart0_ext_pins,
474 .npins = ARRAY_SIZE(uart0_ext_pins),
475 .modemuxs = uart0_ext_modemux,
476 .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
477};
478
479static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
480struct spear_function spear3xx_uart0_ext_function = {
481 .name = "uart0_ext",
482 .groups = uart0_ext_grps,
483 .ngroups = ARRAY_SIZE(uart0_ext_grps),
484};
485
486/* uart0_pins */
487static const unsigned uart0_pins[] = { 2, 3 };
488static struct spear_muxreg uart0_muxreg[] = {
489 {
490 .reg = -1,
491 .mask = PMX_UART0_MASK,
492 .val = PMX_UART0_MASK,
493 },
494};
495
496static struct spear_modemux uart0_modemux[] = {
497 {
498 .modes = ~0,
499 .muxregs = uart0_muxreg,
500 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
501 },
502};
503
504struct spear_pingroup spear3xx_uart0_pingroup = {
505 .name = "uart0_grp",
506 .pins = uart0_pins,
507 .npins = ARRAY_SIZE(uart0_pins),
508 .modemuxs = uart0_modemux,
509 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
510};
511
512static const char *const uart0_grps[] = { "uart0_grp" };
513struct spear_function spear3xx_uart0_function = {
514 .name = "uart0",
515 .groups = uart0_grps,
516 .ngroups = ARRAY_SIZE(uart0_grps),
517};
518
519/* timer_0_1_pins */
520static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
521static struct spear_muxreg timer_0_1_muxreg[] = {
522 {
523 .reg = -1,
524 .mask = PMX_TIMER_0_1_MASK,
525 .val = PMX_TIMER_0_1_MASK,
526 },
527};
528
529static struct spear_modemux timer_0_1_modemux[] = {
530 {
531 .modes = ~0,
532 .muxregs = timer_0_1_muxreg,
533 .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
534 },
535};
536
537struct spear_pingroup spear3xx_timer_0_1_pingroup = {
538 .name = "timer_0_1_grp",
539 .pins = timer_0_1_pins,
540 .npins = ARRAY_SIZE(timer_0_1_pins),
541 .modemuxs = timer_0_1_modemux,
542 .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
543};
544
545static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
546struct spear_function spear3xx_timer_0_1_function = {
547 .name = "timer_0_1",
548 .groups = timer_0_1_grps,
549 .ngroups = ARRAY_SIZE(timer_0_1_grps),
550};
551
552/* timer_2_3_pins */
553static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
554static struct spear_muxreg timer_2_3_muxreg[] = {
555 {
556 .reg = -1,
557 .mask = PMX_TIMER_2_3_MASK,
558 .val = PMX_TIMER_2_3_MASK,
559 },
560};
561
562static struct spear_modemux timer_2_3_modemux[] = {
563 {
564 .modes = ~0,
565 .muxregs = timer_2_3_muxreg,
566 .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
567 },
568};
569
570struct spear_pingroup spear3xx_timer_2_3_pingroup = {
571 .name = "timer_2_3_grp",
572 .pins = timer_2_3_pins,
573 .npins = ARRAY_SIZE(timer_2_3_pins),
574 .modemuxs = timer_2_3_modemux,
575 .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
576};
577
578static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
579struct spear_function spear3xx_timer_2_3_function = {
580 .name = "timer_2_3",
581 .groups = timer_2_3_grps,
582 .ngroups = ARRAY_SIZE(timer_2_3_grps),
583};
584
585struct spear_pinctrl_machdata spear3xx_machdata = {
586 .pins = spear3xx_pins,
587 .npins = ARRAY_SIZE(spear3xx_pins),
588};
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.h b/drivers/pinctrl/spear/pinctrl-spear3xx.h
new file mode 100644
index 00000000000..5d5fdd8df7b
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.h
@@ -0,0 +1,92 @@
1/*
2 * Header file for the ST Microelectronics SPEAr3xx pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __PINMUX_SPEAR3XX_H__
13#define __PINMUX_SPEAR3XX_H__
14
15#include "pinctrl-spear.h"
16
17/* pad mux declarations */
18#define PMX_FIRDA_MASK (1 << 14)
19#define PMX_I2C_MASK (1 << 13)
20#define PMX_SSP_CS_MASK (1 << 12)
21#define PMX_SSP_MASK (1 << 11)
22#define PMX_MII_MASK (1 << 10)
23#define PMX_GPIO_PIN0_MASK (1 << 9)
24#define PMX_GPIO_PIN1_MASK (1 << 8)
25#define PMX_GPIO_PIN2_MASK (1 << 7)
26#define PMX_GPIO_PIN3_MASK (1 << 6)
27#define PMX_GPIO_PIN4_MASK (1 << 5)
28#define PMX_GPIO_PIN5_MASK (1 << 4)
29#define PMX_UART0_MODEM_MASK (1 << 3)
30#define PMX_UART0_MASK (1 << 2)
31#define PMX_TIMER_2_3_MASK (1 << 1)
32#define PMX_TIMER_0_1_MASK (1 << 0)
33
34extern struct spear_pingroup spear3xx_firda_pingroup;
35extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup;
36extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup;
37extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup;
38extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup;
39extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup;
40extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup;
41extern struct spear_pingroup spear3xx_i2c_pingroup;
42extern struct spear_pingroup spear3xx_mii_pingroup;
43extern struct spear_pingroup spear3xx_ssp_cs_pingroup;
44extern struct spear_pingroup spear3xx_ssp_pingroup;
45extern struct spear_pingroup spear3xx_timer_0_1_pingroup;
46extern struct spear_pingroup spear3xx_timer_2_3_pingroup;
47extern struct spear_pingroup spear3xx_uart0_ext_pingroup;
48extern struct spear_pingroup spear3xx_uart0_pingroup;
49
50#define SPEAR3XX_COMMON_PINGROUPS \
51 &spear3xx_firda_pingroup, \
52 &spear3xx_gpio0_pin0_pingroup, \
53 &spear3xx_gpio0_pin1_pingroup, \
54 &spear3xx_gpio0_pin2_pingroup, \
55 &spear3xx_gpio0_pin3_pingroup, \
56 &spear3xx_gpio0_pin4_pingroup, \
57 &spear3xx_gpio0_pin5_pingroup, \
58 &spear3xx_i2c_pingroup, \
59 &spear3xx_mii_pingroup, \
60 &spear3xx_ssp_cs_pingroup, \
61 &spear3xx_ssp_pingroup, \
62 &spear3xx_timer_0_1_pingroup, \
63 &spear3xx_timer_2_3_pingroup, \
64 &spear3xx_uart0_ext_pingroup, \
65 &spear3xx_uart0_pingroup
66
67extern struct spear_function spear3xx_firda_function;
68extern struct spear_function spear3xx_gpio0_function;
69extern struct spear_function spear3xx_i2c_function;
70extern struct spear_function spear3xx_mii_function;
71extern struct spear_function spear3xx_ssp_cs_function;
72extern struct spear_function spear3xx_ssp_function;
73extern struct spear_function spear3xx_timer_0_1_function;
74extern struct spear_function spear3xx_timer_2_3_function;
75extern struct spear_function spear3xx_uart0_ext_function;
76extern struct spear_function spear3xx_uart0_function;
77
78#define SPEAR3XX_COMMON_FUNCTIONS \
79 &spear3xx_firda_function, \
80 &spear3xx_gpio0_function, \
81 &spear3xx_i2c_function, \
82 &spear3xx_mii_function, \
83 &spear3xx_ssp_cs_function, \
84 &spear3xx_ssp_function, \
85 &spear3xx_timer_0_1_function, \
86 &spear3xx_timer_2_3_function, \
87 &spear3xx_uart0_ext_function, \
88 &spear3xx_uart0_function
89
90extern struct spear_pinctrl_machdata spear3xx_machdata;
91
92#endif /* __PINMUX_SPEAR3XX_H__ */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index b0252726df6..70cf722ac3a 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -101,6 +101,26 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
101struct clk *clk_get(struct device *dev, const char *id); 101struct clk *clk_get(struct device *dev, const char *id);
102 102
103/** 103/**
104 * devm_clk_get - lookup and obtain a managed reference to a clock producer.
105 * @dev: device for clock "consumer"
106 * @id: clock comsumer ID
107 *
108 * Returns a struct clk corresponding to the clock producer, or
109 * valid IS_ERR() condition containing errno. The implementation
110 * uses @dev and @id to determine the clock consumer, and thereby
111 * the clock producer. (IOW, @id may be identical strings, but
112 * clk_get may return different clock producers depending on @dev.)
113 *
114 * Drivers must assume that the clock source is not enabled.
115 *
116 * devm_clk_get should not be called from within interrupt context.
117 *
118 * The clock will automatically be freed when the device is unbound
119 * from the bus.
120 */
121struct clk *devm_clk_get(struct device *dev, const char *id);
122
123/**
104 * clk_prepare - prepare a clock source 124 * clk_prepare - prepare a clock source
105 * @clk: clock source 125 * @clk: clock source
106 * 126 *
@@ -206,6 +226,18 @@ unsigned long clk_get_rate(struct clk *clk);
206 */ 226 */
207void clk_put(struct clk *clk); 227void clk_put(struct clk *clk);
208 228
229/**
230 * devm_clk_put - "free" a managed clock source
231 * @dev: device used to acuqire the clock
232 * @clk: clock source acquired with devm_clk_get()
233 *
234 * Note: drivers must ensure that all clk_enable calls made on this
235 * clock source are balanced by clk_disable calls prior to calling
236 * this function.
237 *
238 * clk_put should not be called from within interrupt context.
239 */
240void devm_clk_put(struct device *dev, struct clk *clk);
209 241
210/* 242/*
211 * The remaining APIs are optional for machine class support. 243 * The remaining APIs are optional for machine class support.
diff --git a/include/linux/clkdev.h b/include/linux/clkdev.h
index d9a4fd028c9..a6a6f603103 100644
--- a/include/linux/clkdev.h
+++ b/include/linux/clkdev.h
@@ -40,4 +40,7 @@ void clkdev_drop(struct clk_lookup *cl);
40void clkdev_add_table(struct clk_lookup *, size_t); 40void clkdev_add_table(struct clk_lookup *, size_t);
41int clk_add_alias(const char *, const char *, char *, struct device *); 41int clk_add_alias(const char *, const char *, char *, struct device *);
42 42
43int clk_register_clkdev(struct clk *, const char *, const char *, ...);
44int clk_register_clkdevs(struct clk *, struct clk_lookup *, size_t);
45
43#endif 46#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 06:44:07 -0500