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-rw-r--r--drivers/video/sh_mobile_hdmi.c1
-rw-r--r--include/sound/soc-dapm.h43
-rw-r--r--include/sound/soc.h4
-rw-r--r--sound/soc/Kconfig17
-rw-r--r--sound/soc/codecs/88pm860x-codec.c8
-rw-r--r--sound/soc/codecs/Kconfig4
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/ad193x.c1
-rw-r--r--sound/soc/codecs/ak4671.c1
-rw-r--r--sound/soc/codecs/cs4270.c1
-rw-r--r--sound/soc/codecs/cs42l51.c1
-rw-r--r--sound/soc/codecs/cx20442.c1
-rw-r--r--sound/soc/codecs/max98088.c10
-rw-r--r--sound/soc/codecs/tlv320aic26.c4
-rw-r--r--sound/soc/codecs/tlv320aic3x.c2
-rw-r--r--sound/soc/codecs/uda1380.c1
-rw-r--r--sound/soc/codecs/wm8350.c73
-rw-r--r--sound/soc/codecs/wm8523.c9
-rw-r--r--sound/soc/codecs/wm8580.c1
-rw-r--r--sound/soc/codecs/wm8711.c1
-rw-r--r--sound/soc/codecs/wm8731.c1
-rw-r--r--sound/soc/codecs/wm8741.c10
-rw-r--r--sound/soc/codecs/wm8750.c1
-rw-r--r--sound/soc/codecs/wm8753.c226
-rw-r--r--sound/soc/codecs/wm8900.c1
-rw-r--r--sound/soc/codecs/wm8903.c28
-rw-r--r--sound/soc/codecs/wm8903.h25
-rw-r--r--sound/soc/codecs/wm8904.c37
-rw-r--r--sound/soc/codecs/wm8940.c2
-rw-r--r--sound/soc/codecs/wm8955.c31
-rw-r--r--sound/soc/codecs/wm8960.c6
-rw-r--r--sound/soc/codecs/wm8961.c1
-rw-r--r--sound/soc/codecs/wm8962.c50
-rw-r--r--sound/soc/codecs/wm8971.c1
-rw-r--r--sound/soc/codecs/wm8974.c1
-rw-r--r--sound/soc/codecs/wm8978.c1
-rw-r--r--sound/soc/codecs/wm8988.c1
-rw-r--r--sound/soc/codecs/wm8993.c1
-rw-r--r--sound/soc/codecs/wm8994.c15
-rw-r--r--sound/soc/codecs/wm8995.c1818
-rw-r--r--sound/soc/codecs/wm8995.h4269
-rw-r--r--sound/soc/codecs/wm9081.c2
-rw-r--r--sound/soc/codecs/wm9090.c18
-rw-r--r--sound/soc/davinci/davinci-evm.c1
-rw-r--r--sound/soc/omap/n810.c1
-rw-r--r--sound/soc/omap/rx51.c1
-rw-r--r--sound/soc/s6000/s6105-ipcam.c1
-rw-r--r--sound/soc/samsung/Kconfig78
-rw-r--r--sound/soc/samsung/Makefile36
-rw-r--r--sound/soc/samsung/goni_wm8994.c2
-rw-r--r--sound/soc/samsung/i2s.c12
-rw-r--r--sound/soc/samsung/s3c24xx_simtec_hermes.c2
-rw-r--r--sound/soc/samsung/smdk_wm8580.c17
-rw-r--r--sound/soc/samsung/smdk_wm8994.c176
-rw-r--r--sound/soc/samsung/smdk_wm9713.c1
-rw-r--r--sound/soc/sh/Kconfig4
-rw-r--r--sound/soc/sh/fsi-da7210.c2
-rw-r--r--sound/soc/sh/fsi.c80
-rw-r--r--sound/soc/soc-cache.c13
-rw-r--r--sound/soc/soc-core.c20
-rw-r--r--sound/soc/soc-dapm.c366
61 files changed, 6956 insertions, 588 deletions
diff --git a/drivers/video/sh_mobile_hdmi.c b/drivers/video/sh_mobile_hdmi.c
index d7df10315d8..b19941d37ed 100644
--- a/drivers/video/sh_mobile_hdmi.c
+++ b/drivers/video/sh_mobile_hdmi.c
@@ -22,6 +22,7 @@
22#include <linux/slab.h> 22#include <linux/slab.h>
23#include <linux/types.h> 23#include <linux/types.h>
24#include <linux/workqueue.h> 24#include <linux/workqueue.h>
25#include <sound/soc.h>
25#include <sound/soc-dapm.h> 26#include <sound/soc-dapm.h>
26#include <sound/initval.h> 27#include <sound/initval.h>
27 28
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index 2f76a51bbaa..8031769ac48 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -93,6 +93,9 @@
93#define SND_SOC_DAPM_MUX(wname, wreg, wshift, winvert, wcontrols) \ 93#define SND_SOC_DAPM_MUX(wname, wreg, wshift, winvert, wcontrols) \
94{ .id = snd_soc_dapm_mux, .name = wname, .reg = wreg, .shift = wshift, \ 94{ .id = snd_soc_dapm_mux, .name = wname, .reg = wreg, .shift = wshift, \
95 .invert = winvert, .kcontrols = wcontrols, .num_kcontrols = 1} 95 .invert = winvert, .kcontrols = wcontrols, .num_kcontrols = 1}
96#define SND_SOC_DAPM_VIRT_MUX(wname, wreg, wshift, winvert, wcontrols) \
97{ .id = snd_soc_dapm_virt_mux, .name = wname, .reg = wreg, .shift = wshift, \
98 .invert = winvert, .kcontrols = wcontrols, .num_kcontrols = 1}
96#define SND_SOC_DAPM_VALUE_MUX(wname, wreg, wshift, winvert, wcontrols) \ 99#define SND_SOC_DAPM_VALUE_MUX(wname, wreg, wshift, winvert, wcontrols) \
97{ .id = snd_soc_dapm_value_mux, .name = wname, .reg = wreg, \ 100{ .id = snd_soc_dapm_value_mux, .name = wname, .reg = wreg, \
98 .shift = wshift, .invert = winvert, .kcontrols = wcontrols, \ 101 .shift = wshift, .invert = winvert, .kcontrols = wcontrols, \
@@ -148,6 +151,11 @@
148{ .id = snd_soc_dapm_mux, .name = wname, .reg = wreg, .shift = wshift, \ 151{ .id = snd_soc_dapm_mux, .name = wname, .reg = wreg, .shift = wshift, \
149 .invert = winvert, .kcontrols = wcontrols, .num_kcontrols = 1, \ 152 .invert = winvert, .kcontrols = wcontrols, .num_kcontrols = 1, \
150 .event = wevent, .event_flags = wflags} 153 .event = wevent, .event_flags = wflags}
154#define SND_SOC_DAPM_VIRT_MUX_E(wname, wreg, wshift, winvert, wcontrols, \
155 wevent, wflags) \
156{ .id = snd_soc_dapm_virt_mux, .name = wname, .reg = wreg, .shift = wshift, \
157 .invert = winvert, .kcontrols = wcontrols, .num_kcontrols = 1, \
158 .event = wevent, .event_flags = wflags}
151 159
152/* Simplified versions of above macros, assuming wncontrols = ARRAY_SIZE(wcontrols) */ 160/* Simplified versions of above macros, assuming wncontrols = ARRAY_SIZE(wcontrols) */
153#define SOC_PGA_E_ARRAY(wname, wreg, wshift, winvert, wcontrols, \ 161#define SOC_PGA_E_ARRAY(wname, wreg, wshift, winvert, wcontrols, \
@@ -227,13 +235,6 @@
227 .info = snd_soc_info_volsw, \ 235 .info = snd_soc_info_volsw, \
228 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ 236 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \
229 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 237 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
230#define SOC_DAPM_DOUBLE(xname, reg, shift_left, shift_right, max, invert, \
231 power) \
232{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
233 .info = snd_soc_info_volsw, \
234 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \
235 .private_value = (reg) | ((shift_left) << 8) | ((shift_right) << 12) |\
236 ((max) << 16) | ((invert) << 24) }
237#define SOC_DAPM_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \ 238#define SOC_DAPM_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \
238{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 239{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
239 .info = snd_soc_info_volsw, \ 240 .info = snd_soc_info_volsw, \
@@ -241,15 +242,6 @@
241 .tlv.p = (tlv_array), \ 242 .tlv.p = (tlv_array), \
242 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ 243 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \
243 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 244 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
244#define SOC_DAPM_DOUBLE_TLV(xname, reg, shift_left, shift_right, max, invert, \
245 power, tlv_array) \
246{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
247 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,\
248 .tlv.p = (tlv_array), \
249 .info = snd_soc_info_volsw, \
250 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \
251 .private_value = (reg) | ((shift_left) << 8) | ((shift_right) << 12) |\
252 ((max) << 16) | ((invert) << 24) }
253#define SOC_DAPM_ENUM(xname, xenum) \ 245#define SOC_DAPM_ENUM(xname, xenum) \
254{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 246{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
255 .info = snd_soc_info_enum_double, \ 247 .info = snd_soc_info_enum_double, \
@@ -373,6 +365,7 @@ enum snd_soc_dapm_type {
373 snd_soc_dapm_input = 0, /* input pin */ 365 snd_soc_dapm_input = 0, /* input pin */
374 snd_soc_dapm_output, /* output pin */ 366 snd_soc_dapm_output, /* output pin */
375 snd_soc_dapm_mux, /* selects 1 analog signal from many inputs */ 367 snd_soc_dapm_mux, /* selects 1 analog signal from many inputs */
368 snd_soc_dapm_virt_mux, /* virtual version of snd_soc_dapm_mux */
376 snd_soc_dapm_value_mux, /* selects 1 analog signal from many inputs */ 369 snd_soc_dapm_value_mux, /* selects 1 analog signal from many inputs */
377 snd_soc_dapm_mixer, /* mixes several analog signals together */ 370 snd_soc_dapm_mixer, /* mixes several analog signals together */
378 snd_soc_dapm_mixer_named_ctl, /* mixer with named controls */ 371 snd_soc_dapm_mixer_named_ctl, /* mixer with named controls */
@@ -476,18 +469,32 @@ struct snd_soc_dapm_widget {
476 struct list_head power_list; 469 struct list_head power_list;
477}; 470};
478 471
472struct snd_soc_dapm_update {
473 struct snd_soc_dapm_widget *widget;
474 struct snd_kcontrol *kcontrol;
475 int reg;
476 int mask;
477 int val;
478};
479
479/* DAPM context */ 480/* DAPM context */
480struct snd_soc_dapm_context { 481struct snd_soc_dapm_context {
481 struct list_head widgets; 482 int n_widgets; /* number of widgets in this context */
482 struct list_head paths;
483 enum snd_soc_bias_level bias_level; 483 enum snd_soc_bias_level bias_level;
484 enum snd_soc_bias_level suspend_bias_level; 484 enum snd_soc_bias_level suspend_bias_level;
485 struct delayed_work delayed_work; 485 struct delayed_work delayed_work;
486 unsigned int idle_bias_off:1; /* Use BIAS_OFF instead of STANDBY */ 486 unsigned int idle_bias_off:1; /* Use BIAS_OFF instead of STANDBY */
487 487
488 struct snd_soc_dapm_update *update;
489
488 struct device *dev; /* from parent - for debug */ 490 struct device *dev; /* from parent - for debug */
489 struct snd_soc_codec *codec; /* parent codec */ 491 struct snd_soc_codec *codec; /* parent codec */
490 struct snd_soc_card *card; /* parent card */ 492 struct snd_soc_card *card; /* parent card */
493
494 /* used during DAPM updates */
495 int dev_power;
496 struct list_head list;
497
491#ifdef CONFIG_DEBUG_FS 498#ifdef CONFIG_DEBUG_FS
492 struct dentry *debugfs_dapm; 499 struct dentry *debugfs_dapm;
493#endif 500#endif
diff --git a/include/sound/soc.h b/include/sound/soc.h
index 7e65b015f8d..74921f20a1d 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -661,6 +661,10 @@ struct snd_soc_card {
661 struct list_head platform_dev_list; 661 struct list_head platform_dev_list;
662 struct list_head dai_dev_list; 662 struct list_head dai_dev_list;
663 663
664 struct list_head widgets;
665 struct list_head paths;
666 struct list_head dapm_list;
667
664#ifdef CONFIG_DEBUG_FS 668#ifdef CONFIG_DEBUG_FS
665 struct dentry *debugfs_card_root; 669 struct dentry *debugfs_card_root;
666 struct dentry *debugfs_pop_time; 670 struct dentry *debugfs_pop_time;
diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index 21a5465ceb6..a3efc52a34d 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -4,8 +4,6 @@
4 4
5menuconfig SND_SOC 5menuconfig SND_SOC
6 tristate "ALSA for SoC audio support" 6 tristate "ALSA for SoC audio support"
7 select LZO_COMPRESS
8 select LZO_DECOMPRESS
9 select SND_PCM 7 select SND_PCM
10 select AC97_BUS if SND_SOC_AC97_BUS 8 select AC97_BUS if SND_SOC_AC97_BUS
11 select SND_JACK if INPUT=y || INPUT=SND 9 select SND_JACK if INPUT=y || INPUT=SND
@@ -22,6 +20,21 @@ menuconfig SND_SOC
22 20
23if SND_SOC 21if SND_SOC
24 22
23config SND_SOC_CACHE_LZO
24 bool "Support LZO compression for register caches"
25 select LZO_COMPRESS
26 select LZO_DECOMPRESS
27 ---help---
28 Select this to enable LZO compression for register caches.
29 This will allow machine or CODEC drivers to compress register
30 caches in memory, reducing the memory consumption at the
31 expense of performance. If this is not present and is used
32 the system will fall back to uncompressed caches.
33
34 Usually it is safe to disable this option, where cache
35 compression in used the rbtree option will typically perform
36 better.
37
25config SND_SOC_AC97_BUS 38config SND_SOC_AC97_BUS
26 bool 39 bool
27 40
diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c
index 08e15dee918..06b6981b8d6 100644
--- a/sound/soc/codecs/88pm860x-codec.c
+++ b/sound/soc/codecs/88pm860x-codec.c
@@ -22,6 +22,7 @@
22#include <sound/tlv.h> 22#include <sound/tlv.h>
23#include <sound/initval.h> 23#include <sound/initval.h>
24#include <sound/jack.h> 24#include <sound/jack.h>
25#include <trace/events/asoc.h>
25 26
26#include "88pm860x-codec.h" 27#include "88pm860x-codec.h"
27 28
@@ -145,7 +146,6 @@ struct pm860x_priv {
145 146
146 int irq[4]; 147 int irq[4];
147 unsigned char name[4][MAX_NAME_LEN]; 148 unsigned char name[4][MAX_NAME_LEN];
148 unsigned char reg_cache[REG_CACHE_SIZE];
149}; 149};
150 150
151/* -9450dB to 0dB in 150dB steps ( mute instead of -9450dB) */ 151/* -9450dB to 0dB in 150dB steps ( mute instead of -9450dB) */
@@ -1262,6 +1262,12 @@ static irqreturn_t pm860x_codec_handler(int irq, void *data)
1262 mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt 1262 mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt
1263 | pm860x->det.hp_det; 1263 | pm860x->det.hp_det;
1264 1264
1265#ifndef CONFIG_SND_SOC_88PM860X_MODULE
1266 if (status & (HEADSET_STATUS | MIC_STATUS | SHORT_HS1 | SHORT_HS2 |
1267 SHORT_LO1 | SHORT_LO2))
1268 trace_snd_soc_jack_irq(dev_name(pm860x->codec->dev));
1269#endif
1270
1265 if ((pm860x->det.hp_det & SND_JACK_HEADPHONE) 1271 if ((pm860x->det.hp_det & SND_JACK_HEADPHONE)
1266 && (status & HEADSET_STATUS)) 1272 && (status & HEADSET_STATUS))
1267 report |= SND_JACK_HEADPHONE; 1273 report |= SND_JACK_HEADPHONE;
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index f6c6d316ac6..883a312bb29 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -78,6 +78,7 @@ config SND_SOC_ALL_CODECS
78 select SND_SOC_WM8990 if I2C 78 select SND_SOC_WM8990 if I2C
79 select SND_SOC_WM8993 if I2C 79 select SND_SOC_WM8993 if I2C
80 select SND_SOC_WM8994 if MFD_WM8994 80 select SND_SOC_WM8994 if MFD_WM8994
81 select SND_SOC_WM8995 if SND_SOC_I2C_AND_SPI
81 select SND_SOC_WM9081 if I2C 82 select SND_SOC_WM9081 if I2C
82 select SND_SOC_WM9090 if I2C 83 select SND_SOC_WM9090 if I2C
83 select SND_SOC_WM9705 if SND_SOC_AC97_BUS 84 select SND_SOC_WM9705 if SND_SOC_AC97_BUS
@@ -309,6 +310,9 @@ config SND_SOC_WM8993
309config SND_SOC_WM8994 310config SND_SOC_WM8994
310 tristate 311 tristate
311 312
313config SND_SOC_WM8995
314 tristate
315
312config SND_SOC_WM9081 316config SND_SOC_WM9081
313 tristate 317 tristate
314 318
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 9139cf95ff7..579af9c4f12 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -63,6 +63,7 @@ snd-soc-wm8988-objs := wm8988.o
63snd-soc-wm8990-objs := wm8990.o 63snd-soc-wm8990-objs := wm8990.o
64snd-soc-wm8993-objs := wm8993.o 64snd-soc-wm8993-objs := wm8993.o
65snd-soc-wm8994-objs := wm8994.o wm8994-tables.o 65snd-soc-wm8994-objs := wm8994.o wm8994-tables.o
66snd-soc-wm8995-objs := wm8995.o
66snd-soc-wm9081-objs := wm9081.o 67snd-soc-wm9081-objs := wm9081.o
67snd-soc-wm9705-objs := wm9705.o 68snd-soc-wm9705-objs := wm9705.o
68snd-soc-wm9712-objs := wm9712.o 69snd-soc-wm9712-objs := wm9712.o
@@ -142,6 +143,7 @@ obj-$(CONFIG_SND_SOC_WM8988) += snd-soc-wm8988.o
142obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o 143obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o
143obj-$(CONFIG_SND_SOC_WM8993) += snd-soc-wm8993.o 144obj-$(CONFIG_SND_SOC_WM8993) += snd-soc-wm8993.o
144obj-$(CONFIG_SND_SOC_WM8994) += snd-soc-wm8994.o 145obj-$(CONFIG_SND_SOC_WM8994) += snd-soc-wm8994.o
146obj-$(CONFIG_SND_SOC_WM8995) += snd-soc-wm8995.o
145obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o 147obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o
146obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o 148obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o
147obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o 149obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o
diff --git a/sound/soc/codecs/ad193x.c b/sound/soc/codecs/ad193x.c
index a007bd7326f..da46479bfcf 100644
--- a/sound/soc/codecs/ad193x.c
+++ b/sound/soc/codecs/ad193x.c
@@ -23,7 +23,6 @@
23 23
24/* codec private data */ 24/* codec private data */
25struct ad193x_priv { 25struct ad193x_priv {
26 u8 reg_cache[AD193X_NUM_REGS];
27 enum snd_soc_control_type bus_type; 26 enum snd_soc_control_type bus_type;
28 void *control_data; 27 void *control_data;
29 int sysclk; 28 int sysclk;
diff --git a/sound/soc/codecs/ak4671.c b/sound/soc/codecs/ak4671.c
index 4faf10553a3..2ec75abfa3e 100644
--- a/sound/soc/codecs/ak4671.c
+++ b/sound/soc/codecs/ak4671.c
@@ -27,7 +27,6 @@
27struct ak4671_priv { 27struct ak4671_priv {
28 enum snd_soc_control_type control_type; 28 enum snd_soc_control_type control_type;
29 void *control_data; 29 void *control_data;
30 u8 reg_cache[AK4671_CACHEREGNUM];
31}; 30};
32 31
33/* ak4671 register cache & default register settings */ 32/* ak4671 register cache & default register settings */
diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c
index 6d4bdc609ac..3a582caa6ef 100644
--- a/sound/soc/codecs/cs4270.c
+++ b/sound/soc/codecs/cs4270.c
@@ -114,7 +114,6 @@ static const char *supply_names[] = {
114struct cs4270_private { 114struct cs4270_private {
115 enum snd_soc_control_type control_type; 115 enum snd_soc_control_type control_type;
116 void *control_data; 116 void *control_data;
117 u8 reg_cache[CS4270_NUMREGS];
118 unsigned int mclk; /* Input frequency of the MCLK pin */ 117 unsigned int mclk; /* Input frequency of the MCLK pin */
119 unsigned int mode; /* The mode (I2S or left-justified) */ 118 unsigned int mode; /* The mode (I2S or left-justified) */
120 unsigned int slave_mode; 119 unsigned int slave_mode;
diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c
index d4e60dc45bf..8fb7070108d 100644
--- a/sound/soc/codecs/cs42l51.c
+++ b/sound/soc/codecs/cs42l51.c
@@ -46,7 +46,6 @@ struct cs42l51_private {
46 unsigned int mclk; 46 unsigned int mclk;
47 unsigned int audio_mode; /* The mode (I2S or left-justified) */ 47 unsigned int audio_mode; /* The mode (I2S or left-justified) */
48 enum master_slave_mode func; 48 enum master_slave_mode func;
49 u8 reg_cache[CS42L51_NUMREGS];
50}; 49};
51 50
52#define CS42L51_FORMATS ( \ 51#define CS42L51_FORMATS ( \
diff --git a/sound/soc/codecs/cx20442.c b/sound/soc/codecs/cx20442.c
index a9521acad99..03d1e860d22 100644
--- a/sound/soc/codecs/cx20442.c
+++ b/sound/soc/codecs/cx20442.c
@@ -26,7 +26,6 @@
26struct cx20442_priv { 26struct cx20442_priv {
27 enum snd_soc_control_type control_type; 27 enum snd_soc_control_type control_type;
28 void *control_data; 28 void *control_data;
29 u8 reg_cache[1];
30}; 29};
31 30
32#define CX20442_PM 0x0 31#define CX20442_PM 0x0
diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c
index 335a002aaf0..37133c40e76 100644
--- a/sound/soc/codecs/max98088.c
+++ b/sound/soc/codecs/max98088.c
@@ -39,7 +39,6 @@ struct max98088_cdata {
39}; 39};
40 40
41struct max98088_priv { 41struct max98088_priv {
42 u8 reg_cache[M98088_REG_CNT];
43 enum max98088_type devtype; 42 enum max98088_type devtype;
44 void *control_data; 43 void *control_data;
45 struct max98088_pdata *pdata; 44 struct max98088_pdata *pdata;
@@ -1589,7 +1588,7 @@ static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1589 1588
1590static void max98088_sync_cache(struct snd_soc_codec *codec) 1589static void max98088_sync_cache(struct snd_soc_codec *codec)
1591{ 1590{
1592 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1591 u16 *reg_cache = codec->reg_cache;
1593 int i; 1592 int i;
1594 1593
1595 if (!codec->cache_sync) 1594 if (!codec->cache_sync)
@@ -1600,14 +1599,14 @@ static void max98088_sync_cache(struct snd_soc_codec *codec)
1600 /* write back cached values if they're writeable and 1599 /* write back cached values if they're writeable and
1601 * different from the hardware default. 1600 * different from the hardware default.
1602 */ 1601 */
1603 for (i = 1; i < ARRAY_SIZE(max98088->reg_cache); i++) { 1602 for (i = 1; i < codec->driver->reg_cache_size; i++) {
1604 if (!max98088_access[i].writable) 1603 if (!max98088_access[i].writable)
1605 continue; 1604 continue;
1606 1605
1607 if (max98088->reg_cache[i] == max98088_reg[i]) 1606 if (reg_cache[i] == max98088_reg[i])
1608 continue; 1607 continue;
1609 1608
1610 snd_soc_write(codec, i, max98088->reg_cache[i]); 1609 snd_soc_write(codec, i, reg_cache[i]);
1611 } 1610 }
1612 1611
1613 codec->cache_sync = 0; 1612 codec->cache_sync = 0;
@@ -1952,7 +1951,6 @@ static int max98088_probe(struct snd_soc_codec *codec)
1952 int ret = 0; 1951 int ret = 0;
1953 1952
1954 codec->cache_sync = 1; 1953 codec->cache_sync = 1;
1955 memcpy(codec->reg_cache, max98088_reg, sizeof(max98088_reg));
1956 1954
1957 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 1955 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
1958 if (ret != 0) { 1956 if (ret != 0) {
diff --git a/sound/soc/codecs/tlv320aic26.c b/sound/soc/codecs/tlv320aic26.c
index 68f0ae47f60..e2a7608d394 100644
--- a/sound/soc/codecs/tlv320aic26.c
+++ b/sound/soc/codecs/tlv320aic26.c
@@ -30,7 +30,6 @@ MODULE_LICENSE("GPL");
30struct aic26 { 30struct aic26 {
31 struct spi_device *spi; 31 struct spi_device *spi;
32 struct snd_soc_codec codec; 32 struct snd_soc_codec codec;
33 u16 reg_cache[AIC26_NUM_REGS]; /* shadow registers */
34 int master; 33 int master;
35 int datfm; 34 int datfm;
36 int mclk; 35 int mclk;
@@ -354,7 +353,6 @@ static DEVICE_ATTR(keyclick, 0644, aic26_keyclick_show, aic26_keyclick_set);
354 */ 353 */
355static int aic26_probe(struct snd_soc_codec *codec) 354static int aic26_probe(struct snd_soc_codec *codec)
356{ 355{
357 struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec);
358 int ret, err, i, reg; 356 int ret, err, i, reg;
359 357
360 dev_info(codec->dev, "Probing AIC26 SoC CODEC driver\n"); 358 dev_info(codec->dev, "Probing AIC26 SoC CODEC driver\n");
@@ -372,7 +370,7 @@ static int aic26_probe(struct snd_soc_codec *codec)
372 aic26_reg_write(codec, AIC26_REG_AUDIO_CTRL3, reg); 370 aic26_reg_write(codec, AIC26_REG_AUDIO_CTRL3, reg);
373 371
374 /* Fill register cache */ 372 /* Fill register cache */
375 for (i = 0; i < ARRAY_SIZE(aic26->reg_cache); i++) 373 for (i = 0; i < codec->driver->reg_cache_size; i++)
376 aic26_reg_read(codec, i); 374 aic26_reg_read(codec, i);
377 375
378 /* Register the sysfs files for debugging */ 376 /* Register the sysfs files for debugging */
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 8cd4cf5c44d..3bedab26892 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -185,7 +185,7 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
185 185
186 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { 186 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
187 /* find dapm widget path assoc with kcontrol */ 187 /* find dapm widget path assoc with kcontrol */
188 list_for_each_entry(path, &widget->dapm->paths, list) { 188 list_for_each_entry(path, &widget->dapm->card->paths, list) {
189 if (path->kcontrol != kcontrol) 189 if (path->kcontrol != kcontrol)
190 continue; 190 continue;
191 191
diff --git a/sound/soc/codecs/uda1380.c b/sound/soc/codecs/uda1380.c
index 800980e2e9a..c5ca8cfea60 100644
--- a/sound/soc/codecs/uda1380.c
+++ b/sound/soc/codecs/uda1380.c
@@ -35,7 +35,6 @@
35/* codec private data */ 35/* codec private data */
36struct uda1380_priv { 36struct uda1380_priv {
37 struct snd_soc_codec *codec; 37 struct snd_soc_codec *codec;
38 u16 reg_cache[UDA1380_CACHEREGNUM];
39 unsigned int dac_clk; 38 unsigned int dac_clk;
40 struct work_struct work; 39 struct work_struct work;
41 void *control_data; 40 void *control_data;
diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c
index 07ba7e3f6a8..6d6dc9efe91 100644
--- a/sound/soc/codecs/wm8350.c
+++ b/sound/soc/codecs/wm8350.c
@@ -26,6 +26,7 @@
26#include <sound/soc.h> 26#include <sound/soc.h>
27#include <sound/initval.h> 27#include <sound/initval.h>
28#include <sound/tlv.h> 28#include <sound/tlv.h>
29#include <trace/events/asoc.h>
29 30
30#include "wm8350.h" 31#include "wm8350.h"
31 32
@@ -53,6 +54,7 @@ struct wm8350_output {
53 54
54struct wm8350_jack_data { 55struct wm8350_jack_data {
55 struct snd_soc_jack *jack; 56 struct snd_soc_jack *jack;
57 struct delayed_work work;
56 int report; 58 int report;
57 int short_report; 59 int short_report;
58}; 60};
@@ -1335,45 +1337,69 @@ static int wm8350_resume(struct snd_soc_codec *codec)
1335 return 0; 1337 return 0;
1336} 1338}
1337 1339
1338static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) 1340static void wm8350_hp_work(struct wm8350_data *priv,
1341 struct wm8350_jack_data *jack,
1342 u16 mask)
1339{ 1343{
1340 struct wm8350_data *priv = data;
1341 struct wm8350 *wm8350 = priv->codec.control_data; 1344 struct wm8350 *wm8350 = priv->codec.control_data;
1342 u16 reg; 1345 u16 reg;
1343 int report; 1346 int report;
1344 int mask; 1347
1348 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1349 if (reg & mask)
1350 report = jack->report;
1351 else
1352 report = 0;
1353
1354 snd_soc_jack_report(jack->jack, report, jack->report);
1355
1356}
1357
1358static void wm8350_hpl_work(struct work_struct *work)
1359{
1360 struct wm8350_data *priv =
1361 container_of(work, struct wm8350_data, hpl.work.work);
1362
1363 wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
1364}
1365
1366static void wm8350_hpr_work(struct work_struct *work)
1367{
1368 struct wm8350_data *priv =
1369 container_of(work, struct wm8350_data, hpr.work.work);
1370
1371 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1372}
1373
1374static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
1375{
1376 struct wm8350_data *priv = data;
1377 struct wm8350 *wm8350 = priv->codec.control_data;
1345 struct wm8350_jack_data *jack = NULL; 1378 struct wm8350_jack_data *jack = NULL;
1346 1379
1347 switch (irq - wm8350->irq_base) { 1380 switch (irq - wm8350->irq_base) {
1348 case WM8350_IRQ_CODEC_JCK_DET_L: 1381 case WM8350_IRQ_CODEC_JCK_DET_L:
1382#ifndef CONFIG_SND_SOC_WM8350_MODULE
1383 trace_snd_soc_jack_irq("WM8350 HPL");
1384#endif
1349 jack = &priv->hpl; 1385 jack = &priv->hpl;
1350 mask = WM8350_JACK_L_LVL;
1351 break; 1386 break;
1352 1387
1353 case WM8350_IRQ_CODEC_JCK_DET_R: 1388 case WM8350_IRQ_CODEC_JCK_DET_R:
1389#ifndef CONFIG_SND_SOC_WM8350_MODULE
1390 trace_snd_soc_jack_irq("WM8350 HPR");
1391#endif
1354 jack = &priv->hpr; 1392 jack = &priv->hpr;
1355 mask = WM8350_JACK_R_LVL;
1356 break; 1393 break;
1357 1394
1358 default: 1395 default:
1359 BUG(); 1396 BUG();
1360 } 1397 }
1361 1398
1362 if (!jack->jack) { 1399 if (device_may_wakeup(wm8350->dev))
1363 dev_warn(wm8350->dev, "Jack interrupt called with no jack\n"); 1400 pm_wakeup_event(wm8350->dev, 250);
1364 return IRQ_NONE;
1365 }
1366 1401
1367 /* Debounce */ 1402 schedule_delayed_work(&jack->work, 200);
1368 msleep(200);
1369
1370 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1371 if (reg & mask)
1372 report = jack->report;
1373 else
1374 report = 0;
1375
1376 snd_soc_jack_report(jack->jack, report, jack->report);
1377 1403
1378 return IRQ_HANDLED; 1404 return IRQ_HANDLED;
1379} 1405}
@@ -1437,6 +1463,10 @@ static irqreturn_t wm8350_mic_handler(int irq, void *data)
1437 u16 reg; 1463 u16 reg;
1438 int report = 0; 1464 int report = 0;
1439 1465
1466#ifndef CONFIG_SND_SOC_WM8350_MODULE
1467 trace_snd_soc_jack_irq("WM8350 mic");
1468#endif
1469
1440 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); 1470 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1441 if (reg & WM8350_JACK_MICSCD_LVL) 1471 if (reg & WM8350_JACK_MICSCD_LVL)
1442 report |= priv->mic.short_report; 1472 report |= priv->mic.short_report;
@@ -1552,6 +1582,8 @@ static int wm8350_codec_probe(struct snd_soc_codec *codec)
1552 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1582 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1553 1583
1554 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work); 1584 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work);
1585 INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
1586 INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
1555 1587
1556 /* Enable the codec */ 1588 /* Enable the codec */
1557 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1589 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
@@ -1641,6 +1673,9 @@ static int wm8350_codec_remove(struct snd_soc_codec *codec)
1641 priv->hpr.jack = NULL; 1673 priv->hpr.jack = NULL;
1642 priv->mic.jack = NULL; 1674 priv->mic.jack = NULL;
1643 1675
1676 cancel_delayed_work_sync(&priv->hpl.work);
1677 cancel_delayed_work_sync(&priv->hpr.work);
1678
1644 /* if there was any work waiting then we run it now and 1679 /* if there was any work waiting then we run it now and
1645 * wait for its completion */ 1680 * wait for its completion */
1646 flush_delayed_work_sync(&codec->dapm.delayed_work); 1681 flush_delayed_work_sync(&codec->dapm.delayed_work);
diff --git a/sound/soc/codecs/wm8523.c b/sound/soc/codecs/wm8523.c
index 08f3189f4b3..5eb2f501ce3 100644
--- a/sound/soc/codecs/wm8523.c
+++ b/sound/soc/codecs/wm8523.c
@@ -40,7 +40,6 @@ static const char *wm8523_supply_names[WM8523_NUM_SUPPLIES] = {
40/* codec private data */ 40/* codec private data */
41struct wm8523_priv { 41struct wm8523_priv {
42 enum snd_soc_control_type control_type; 42 enum snd_soc_control_type control_type;
43 u16 reg_cache[WM8523_REGISTER_COUNT];
44 struct regulator_bulk_data supplies[WM8523_NUM_SUPPLIES]; 43 struct regulator_bulk_data supplies[WM8523_NUM_SUPPLIES];
45 unsigned int sysclk; 44 unsigned int sysclk;
46 unsigned int rate_constraint_list[WM8523_NUM_RATES]; 45 unsigned int rate_constraint_list[WM8523_NUM_RATES];
@@ -314,6 +313,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec,
314 enum snd_soc_bias_level level) 313 enum snd_soc_bias_level level)
315{ 314{
316 struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec); 315 struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec);
316 u16 *reg_cache = codec->reg_cache;
317 int ret, i; 317 int ret, i;
318 318
319 switch (level) { 319 switch (level) {
@@ -344,7 +344,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec,
344 /* Sync back default/cached values */ 344 /* Sync back default/cached values */
345 for (i = WM8523_AIF_CTRL1; 345 for (i = WM8523_AIF_CTRL1;
346 i < WM8523_MAX_REGISTER; i++) 346 i < WM8523_MAX_REGISTER; i++)
347 snd_soc_write(codec, i, wm8523->reg_cache[i]); 347 snd_soc_write(codec, i, reg_cache[i]);
348 348
349 349
350 msleep(100); 350 msleep(100);
@@ -414,6 +414,7 @@ static int wm8523_resume(struct snd_soc_codec *codec)
414static int wm8523_probe(struct snd_soc_codec *codec) 414static int wm8523_probe(struct snd_soc_codec *codec)
415{ 415{
416 struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec); 416 struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec);
417 u16 *reg_cache = codec->reg_cache;
417 int ret, i; 418 int ret, i;
418 419
419 codec->hw_write = (hw_write_t)i2c_master_send; 420 codec->hw_write = (hw_write_t)i2c_master_send;
@@ -470,8 +471,8 @@ static int wm8523_probe(struct snd_soc_codec *codec)
470 } 471 }
471 472
472 /* Change some default settings - latch VU and enable ZC */ 473 /* Change some default settings - latch VU and enable ZC */
473 wm8523->reg_cache[WM8523_DAC_GAINR] |= WM8523_DACR_VU; 474 reg_cache[WM8523_DAC_GAINR] |= WM8523_DACR_VU;
474 wm8523->reg_cache[WM8523_DAC_CTRL3] |= WM8523_ZC; 475 reg_cache[WM8523_DAC_CTRL3] |= WM8523_ZC;
475 476
476 wm8523_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 477 wm8523_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
477 478
diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
index 0ebdecfd27a..8f6b5ee6645 100644
--- a/sound/soc/codecs/wm8580.c
+++ b/sound/soc/codecs/wm8580.c
@@ -190,7 +190,6 @@ static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
190struct wm8580_priv { 190struct wm8580_priv {
191 enum snd_soc_control_type control_type; 191 enum snd_soc_control_type control_type;
192 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES]; 192 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
193 u16 reg_cache[WM8580_MAX_REGISTER + 1];
194 struct pll_state a; 193 struct pll_state a;
195 struct pll_state b; 194 struct pll_state b;
196 int sysclk[2]; 195 int sysclk[2];
diff --git a/sound/soc/codecs/wm8711.c b/sound/soc/codecs/wm8711.c
index fec37ebfdb3..97c30382d3f 100644
--- a/sound/soc/codecs/wm8711.c
+++ b/sound/soc/codecs/wm8711.c
@@ -33,7 +33,6 @@
33/* codec private data */ 33/* codec private data */
34struct wm8711_priv { 34struct wm8711_priv {
35 enum snd_soc_control_type bus_type; 35 enum snd_soc_control_type bus_type;
36 u16 reg_cache[WM8711_CACHEREGNUM];
37 unsigned int sysclk; 36 unsigned int sysclk;
38}; 37};
39 38
diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c
index 71122dc3682..0a67c31b266 100644
--- a/sound/soc/codecs/wm8731.c
+++ b/sound/soc/codecs/wm8731.c
@@ -43,7 +43,6 @@ static const char *wm8731_supply_names[WM8731_NUM_SUPPLIES] = {
43struct wm8731_priv { 43struct wm8731_priv {
44 enum snd_soc_control_type control_type; 44 enum snd_soc_control_type control_type;
45 struct regulator_bulk_data supplies[WM8731_NUM_SUPPLIES]; 45 struct regulator_bulk_data supplies[WM8731_NUM_SUPPLIES];
46 u16 reg_cache[WM8731_CACHEREGNUM];
47 unsigned int sysclk; 46 unsigned int sysclk;
48 int sysclk_type; 47 int sysclk_type;
49 int playback_fs; 48 int playback_fs;
diff --git a/sound/soc/codecs/wm8741.c b/sound/soc/codecs/wm8741.c
index 35789b7dcac..494f2d31d75 100644
--- a/sound/soc/codecs/wm8741.c
+++ b/sound/soc/codecs/wm8741.c
@@ -40,7 +40,6 @@ static const char *wm8741_supply_names[WM8741_NUM_SUPPLIES] = {
40/* codec private data */ 40/* codec private data */
41struct wm8741_priv { 41struct wm8741_priv {
42 enum snd_soc_control_type control_type; 42 enum snd_soc_control_type control_type;
43 u16 reg_cache[WM8741_REGISTER_COUNT];
44 struct regulator_bulk_data supplies[WM8741_NUM_SUPPLIES]; 43 struct regulator_bulk_data supplies[WM8741_NUM_SUPPLIES];
45 unsigned int sysclk; 44 unsigned int sysclk;
46 struct snd_pcm_hw_constraint_list *sysclk_constraints; 45 struct snd_pcm_hw_constraint_list *sysclk_constraints;
@@ -422,6 +421,7 @@ static int wm8741_resume(struct snd_soc_codec *codec)
422static int wm8741_probe(struct snd_soc_codec *codec) 421static int wm8741_probe(struct snd_soc_codec *codec)
423{ 422{
424 struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec); 423 struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec);
424 u16 *reg_cache = codec->reg_cache;
425 int ret = 0; 425 int ret = 0;
426 426
427 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8741->control_type); 427 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8741->control_type);
@@ -437,10 +437,10 @@ static int wm8741_probe(struct snd_soc_codec *codec)
437 } 437 }
438 438
439 /* Change some default settings - latch VU */ 439 /* Change some default settings - latch VU */
440 wm8741->reg_cache[WM8741_DACLLSB_ATTENUATION] |= WM8741_UPDATELL; 440 reg_cache[WM8741_DACLLSB_ATTENUATION] |= WM8741_UPDATELL;
441 wm8741->reg_cache[WM8741_DACLMSB_ATTENUATION] |= WM8741_UPDATELM; 441 reg_cache[WM8741_DACLMSB_ATTENUATION] |= WM8741_UPDATELM;
442 wm8741->reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERL; 442 reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERL;
443 wm8741->reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERM; 443 reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERM;
444 444
445 snd_soc_add_controls(codec, wm8741_snd_controls, 445 snd_soc_add_controls(codec, wm8741_snd_controls,
446 ARRAY_SIZE(wm8741_snd_controls)); 446 ARRAY_SIZE(wm8741_snd_controls));
diff --git a/sound/soc/codecs/wm8750.c b/sound/soc/codecs/wm8750.c
index 51280e96d72..38f38fddd19 100644
--- a/sound/soc/codecs/wm8750.c
+++ b/sound/soc/codecs/wm8750.c
@@ -52,7 +52,6 @@ static const u16 wm8750_reg[] = {
52struct wm8750_priv { 52struct wm8750_priv {
53 unsigned int sysclk; 53 unsigned int sysclk;
54 enum snd_soc_control_type control_type; 54 enum snd_soc_control_type control_type;
55 u16 reg_cache[ARRAY_SIZE(wm8750_reg)];
56}; 55};
57 56
58#define wm8750_reset(c) snd_soc_write(c, WM8750_RESET, 0) 57#define wm8750_reset(c) snd_soc_write(c, WM8750_RESET, 0)
diff --git a/sound/soc/codecs/wm8753.c b/sound/soc/codecs/wm8753.c
index 73507e71cb7..79b02ae125c 100644
--- a/sound/soc/codecs/wm8753.c
+++ b/sound/soc/codecs/wm8753.c
@@ -64,22 +64,22 @@ static void wm8753_set_dai_mode(struct snd_soc_codec *codec,
64 * are using 2 wire for device control, so we cache them instead. 64 * are using 2 wire for device control, so we cache them instead.
65 */ 65 */
66static const u16 wm8753_reg[] = { 66static const u16 wm8753_reg[] = {
67 0x0008, 0x0000, 0x000a, 0x000a, 67 0x0000, 0x0008, 0x0000, 0x000a,
68 0x0033, 0x0000, 0x0007, 0x00ff, 68 0x000a, 0x0033, 0x0000, 0x0007,
69 0x00ff, 0x000f, 0x000f, 0x007b, 69 0x00ff, 0x00ff, 0x000f, 0x000f,
70 0x0000, 0x0032, 0x0000, 0x00c3, 70 0x007b, 0x0000, 0x0032, 0x0000,
71 0x00c3, 0x00c0, 0x0000, 0x0000, 71 0x00c3, 0x00c3, 0x00c0, 0x0000,
72 0x0000, 0x0000, 0x0000, 0x0000, 72 0x0000, 0x0000, 0x0000, 0x0000,
73 0x0000, 0x0000, 0x0000, 0x0000, 73 0x0000, 0x0000, 0x0000, 0x0000,
74 0x0000, 0x0000, 0x0000, 0x0055,
75 0x0005, 0x0050, 0x0055, 0x0050,
76 0x0055, 0x0050, 0x0055, 0x0079,
77 0x0079, 0x0079, 0x0079, 0x0079,
78 0x0000, 0x0000, 0x0000, 0x0000, 74 0x0000, 0x0000, 0x0000, 0x0000,
79 0x0097, 0x0097, 0x0000, 0x0004, 75 0x0055, 0x0005, 0x0050, 0x0055,
80 0x0000, 0x0083, 0x0024, 0x01ba, 76 0x0050, 0x0055, 0x0050, 0x0055,
81 0x0000, 0x0083, 0x0024, 0x01ba, 77 0x0079, 0x0079, 0x0079, 0x0079,
82 0x0000, 0x0000, 0x0000 78 0x0079, 0x0000, 0x0000, 0x0000,
79 0x0000, 0x0097, 0x0097, 0x0000,
80 0x0004, 0x0000, 0x0083, 0x0024,
81 0x01ba, 0x0000, 0x0083, 0x0024,
82 0x01ba, 0x0000, 0x0000, 0x0000
83}; 83};
84 84
85/* codec private data */ 85/* codec private data */
@@ -87,57 +87,10 @@ struct wm8753_priv {
87 enum snd_soc_control_type control_type; 87 enum snd_soc_control_type control_type;
88 unsigned int sysclk; 88 unsigned int sysclk;
89 unsigned int pcmclk; 89 unsigned int pcmclk;
90 u16 reg_cache[ARRAY_SIZE(wm8753_reg)];
91 int dai_func; 90 int dai_func;
92}; 91};
93 92
94/* 93#define wm8753_reset(c) snd_soc_write(c, WM8753_RESET, 0)
95 * read wm8753 register cache
96 */
97static inline unsigned int wm8753_read_reg_cache(struct snd_soc_codec *codec,
98 unsigned int reg)
99{
100 u16 *cache = codec->reg_cache;
101 if (reg < 1 || reg >= (ARRAY_SIZE(wm8753_reg) + 1))
102 return -1;
103 return cache[reg - 1];
104}
105
106/*
107 * write wm8753 register cache
108 */
109static inline void wm8753_write_reg_cache(struct snd_soc_codec *codec,
110 unsigned int reg, unsigned int value)
111{
112 u16 *cache = codec->reg_cache;
113 if (reg < 1 || reg >= (ARRAY_SIZE(wm8753_reg) + 1))
114 return;
115 cache[reg - 1] = value;
116}
117
118/*
119 * write to the WM8753 register space
120 */
121static int wm8753_write(struct snd_soc_codec *codec, unsigned int reg,
122 unsigned int value)
123{
124 u8 data[2];
125
126 /* data is
127 * D15..D9 WM8753 register offset
128 * D8...D0 register data
129 */
130 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
131 data[1] = value & 0x00ff;
132
133 wm8753_write_reg_cache(codec, reg, value);
134 if (codec->hw_write(codec->control_data, data, 2) == 2)
135 return 0;
136 else
137 return -EIO;
138}
139
140#define wm8753_reset(c) wm8753_write(c, WM8753_RESET, 0)
141 94
142/* 95/*
143 * WM8753 Controls 96 * WM8753 Controls
@@ -217,7 +170,7 @@ static int wm8753_get_dai(struct snd_kcontrol *kcontrol,
217 struct snd_ctl_elem_value *ucontrol) 170 struct snd_ctl_elem_value *ucontrol)
218{ 171{
219 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 172 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
220 int mode = wm8753_read_reg_cache(codec, WM8753_IOCTL); 173 int mode = snd_soc_read(codec, WM8753_IOCTL);
221 174
222 ucontrol->value.integer.value[0] = (mode & 0xc) >> 2; 175 ucontrol->value.integer.value[0] = (mode & 0xc) >> 2;
223 return 0; 176 return 0;
@@ -227,7 +180,7 @@ static int wm8753_set_dai(struct snd_kcontrol *kcontrol,
227 struct snd_ctl_elem_value *ucontrol) 180 struct snd_ctl_elem_value *ucontrol)
228{ 181{
229 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 182 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
230 int mode = wm8753_read_reg_cache(codec, WM8753_IOCTL); 183 int mode = snd_soc_read(codec, WM8753_IOCTL);
231 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); 184 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
232 185
233 if (((mode & 0xc) >> 2) == ucontrol->value.integer.value[0]) 186 if (((mode & 0xc) >> 2) == ucontrol->value.integer.value[0])
@@ -738,17 +691,17 @@ static int wm8753_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
738 if (pll_id == WM8753_PLL1) { 691 if (pll_id == WM8753_PLL1) {
739 offset = 0; 692 offset = 0;
740 enable = 0x10; 693 enable = 0x10;
741 reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xffef; 694 reg = snd_soc_read(codec, WM8753_CLOCK) & 0xffef;
742 } else { 695 } else {
743 offset = 4; 696 offset = 4;
744 enable = 0x8; 697 enable = 0x8;
745 reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfff7; 698 reg = snd_soc_read(codec, WM8753_CLOCK) & 0xfff7;
746 } 699 }
747 700
748 if (!freq_in || !freq_out) { 701 if (!freq_in || !freq_out) {
749 /* disable PLL */ 702 /* disable PLL */
750 wm8753_write(codec, WM8753_PLL1CTL1 + offset, 0x0026); 703 snd_soc_write(codec, WM8753_PLL1CTL1 + offset, 0x0026);
751 wm8753_write(codec, WM8753_CLOCK, reg); 704 snd_soc_write(codec, WM8753_CLOCK, reg);
752 return 0; 705 return 0;
753 } else { 706 } else {
754 u16 value = 0; 707 u16 value = 0;
@@ -759,20 +712,20 @@ static int wm8753_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
759 /* set up N and K PLL divisor ratios */ 712 /* set up N and K PLL divisor ratios */
760 /* bits 8:5 = PLL_N, bits 3:0 = PLL_K[21:18] */ 713 /* bits 8:5 = PLL_N, bits 3:0 = PLL_K[21:18] */
761 value = (pll_div.n << 5) + ((pll_div.k & 0x3c0000) >> 18); 714 value = (pll_div.n << 5) + ((pll_div.k & 0x3c0000) >> 18);
762 wm8753_write(codec, WM8753_PLL1CTL2 + offset, value); 715 snd_soc_write(codec, WM8753_PLL1CTL2 + offset, value);
763 716
764 /* bits 8:0 = PLL_K[17:9] */ 717 /* bits 8:0 = PLL_K[17:9] */
765 value = (pll_div.k & 0x03fe00) >> 9; 718 value = (pll_div.k & 0x03fe00) >> 9;
766 wm8753_write(codec, WM8753_PLL1CTL3 + offset, value); 719 snd_soc_write(codec, WM8753_PLL1CTL3 + offset, value);
767 720
768 /* bits 8:0 = PLL_K[8:0] */ 721 /* bits 8:0 = PLL_K[8:0] */
769 value = pll_div.k & 0x0001ff; 722 value = pll_div.k & 0x0001ff;
770 wm8753_write(codec, WM8753_PLL1CTL4 + offset, value); 723 snd_soc_write(codec, WM8753_PLL1CTL4 + offset, value);
771 724
772 /* set PLL as input and enable */ 725 /* set PLL as input and enable */
773 wm8753_write(codec, WM8753_PLL1CTL1 + offset, 0x0027 | 726 snd_soc_write(codec, WM8753_PLL1CTL1 + offset, 0x0027 |
774 (pll_div.div2 << 3)); 727 (pll_div.div2 << 3));
775 wm8753_write(codec, WM8753_CLOCK, reg | enable); 728 snd_soc_write(codec, WM8753_CLOCK, reg | enable);
776 } 729 }
777 return 0; 730 return 0;
778} 731}
@@ -879,7 +832,7 @@ static int wm8753_vdac_adc_set_dai_fmt(struct snd_soc_dai *codec_dai,
879 unsigned int fmt) 832 unsigned int fmt)
880{ 833{
881 struct snd_soc_codec *codec = codec_dai->codec; 834 struct snd_soc_codec *codec = codec_dai->codec;
882 u16 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x01ec; 835 u16 voice = snd_soc_read(codec, WM8753_PCM) & 0x01ec;
883 836
884 /* interface format */ 837 /* interface format */
885 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 838 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -901,7 +854,7 @@ static int wm8753_vdac_adc_set_dai_fmt(struct snd_soc_dai *codec_dai,
901 return -EINVAL; 854 return -EINVAL;
902 } 855 }
903 856
904 wm8753_write(codec, WM8753_PCM, voice); 857 snd_soc_write(codec, WM8753_PCM, voice);
905 return 0; 858 return 0;
906} 859}
907 860
@@ -922,8 +875,8 @@ static int wm8753_pcm_hw_params(struct snd_pcm_substream *substream,
922 struct snd_soc_pcm_runtime *rtd = substream->private_data; 875 struct snd_soc_pcm_runtime *rtd = substream->private_data;
923 struct snd_soc_codec *codec = rtd->codec; 876 struct snd_soc_codec *codec = rtd->codec;
924 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); 877 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
925 u16 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x01f3; 878 u16 voice = snd_soc_read(codec, WM8753_PCM) & 0x01f3;
926 u16 srate = wm8753_read_reg_cache(codec, WM8753_SRATE1) & 0x017f; 879 u16 srate = snd_soc_read(codec, WM8753_SRATE1) & 0x017f;
927 880
928 /* bit size */ 881 /* bit size */
929 switch (params_format(params)) { 882 switch (params_format(params)) {
@@ -943,9 +896,9 @@ static int wm8753_pcm_hw_params(struct snd_pcm_substream *substream,
943 /* sample rate */ 896 /* sample rate */
944 if (params_rate(params) * 384 == wm8753->pcmclk) 897 if (params_rate(params) * 384 == wm8753->pcmclk)
945 srate |= 0x80; 898 srate |= 0x80;
946 wm8753_write(codec, WM8753_SRATE1, srate); 899 snd_soc_write(codec, WM8753_SRATE1, srate);
947 900
948 wm8753_write(codec, WM8753_PCM, voice); 901 snd_soc_write(codec, WM8753_PCM, voice);
949 return 0; 902 return 0;
950} 903}
951 904
@@ -958,8 +911,8 @@ static int wm8753_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai,
958 struct snd_soc_codec *codec = codec_dai->codec; 911 struct snd_soc_codec *codec = codec_dai->codec;
959 u16 voice, ioctl; 912 u16 voice, ioctl;
960 913
961 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x011f; 914 voice = snd_soc_read(codec, WM8753_PCM) & 0x011f;
962 ioctl = wm8753_read_reg_cache(codec, WM8753_IOCTL) & 0x015d; 915 ioctl = snd_soc_read(codec, WM8753_IOCTL) & 0x015d;
963 916
964 /* set master/slave audio interface */ 917 /* set master/slave audio interface */
965 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 918 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -1013,8 +966,8 @@ static int wm8753_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai,
1013 return -EINVAL; 966 return -EINVAL;
1014 } 967 }
1015 968
1016 wm8753_write(codec, WM8753_PCM, voice); 969 snd_soc_write(codec, WM8753_PCM, voice);
1017 wm8753_write(codec, WM8753_IOCTL, ioctl); 970 snd_soc_write(codec, WM8753_IOCTL, ioctl);
1018 return 0; 971 return 0;
1019} 972}
1020 973
@@ -1026,16 +979,16 @@ static int wm8753_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1026 979
1027 switch (div_id) { 980 switch (div_id) {
1028 case WM8753_PCMDIV: 981 case WM8753_PCMDIV:
1029 reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0x003f; 982 reg = snd_soc_read(codec, WM8753_CLOCK) & 0x003f;
1030 wm8753_write(codec, WM8753_CLOCK, reg | div); 983 snd_soc_write(codec, WM8753_CLOCK, reg | div);
1031 break; 984 break;
1032 case WM8753_BCLKDIV: 985 case WM8753_BCLKDIV:
1033 reg = wm8753_read_reg_cache(codec, WM8753_SRATE2) & 0x01c7; 986 reg = snd_soc_read(codec, WM8753_SRATE2) & 0x01c7;
1034 wm8753_write(codec, WM8753_SRATE2, reg | div); 987 snd_soc_write(codec, WM8753_SRATE2, reg | div);
1035 break; 988 break;
1036 case WM8753_VXCLKDIV: 989 case WM8753_VXCLKDIV:
1037 reg = wm8753_read_reg_cache(codec, WM8753_SRATE2) & 0x003f; 990 reg = snd_soc_read(codec, WM8753_SRATE2) & 0x003f;
1038 wm8753_write(codec, WM8753_SRATE2, reg | div); 991 snd_soc_write(codec, WM8753_SRATE2, reg | div);
1039 break; 992 break;
1040 default: 993 default:
1041 return -EINVAL; 994 return -EINVAL;
@@ -1050,7 +1003,7 @@ static int wm8753_hdac_set_dai_fmt(struct snd_soc_dai *codec_dai,
1050 unsigned int fmt) 1003 unsigned int fmt)
1051{ 1004{
1052 struct snd_soc_codec *codec = codec_dai->codec; 1005 struct snd_soc_codec *codec = codec_dai->codec;
1053 u16 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x01e0; 1006 u16 hifi = snd_soc_read(codec, WM8753_HIFI) & 0x01e0;
1054 1007
1055 /* interface format */ 1008 /* interface format */
1056 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1009 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -1072,7 +1025,7 @@ static int wm8753_hdac_set_dai_fmt(struct snd_soc_dai *codec_dai,
1072 return -EINVAL; 1025 return -EINVAL;
1073 } 1026 }
1074 1027
1075 wm8753_write(codec, WM8753_HIFI, hifi); 1028 snd_soc_write(codec, WM8753_HIFI, hifi);
1076 return 0; 1029 return 0;
1077} 1030}
1078 1031
@@ -1085,8 +1038,8 @@ static int wm8753_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
1085 struct snd_soc_codec *codec = codec_dai->codec; 1038 struct snd_soc_codec *codec = codec_dai->codec;
1086 u16 ioctl, hifi; 1039 u16 ioctl, hifi;
1087 1040
1088 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x011f; 1041 hifi = snd_soc_read(codec, WM8753_HIFI) & 0x011f;
1089 ioctl = wm8753_read_reg_cache(codec, WM8753_IOCTL) & 0x00ae; 1042 ioctl = snd_soc_read(codec, WM8753_IOCTL) & 0x00ae;
1090 1043
1091 /* set master/slave audio interface */ 1044 /* set master/slave audio interface */
1092 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1045 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -1140,8 +1093,8 @@ static int wm8753_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
1140 return -EINVAL; 1093 return -EINVAL;
1141 } 1094 }
1142 1095
1143 wm8753_write(codec, WM8753_HIFI, hifi); 1096 snd_soc_write(codec, WM8753_HIFI, hifi);
1144 wm8753_write(codec, WM8753_IOCTL, ioctl); 1097 snd_soc_write(codec, WM8753_IOCTL, ioctl);
1145 return 0; 1098 return 0;
1146} 1099}
1147 1100
@@ -1162,8 +1115,8 @@ static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream,
1162 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1115 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1163 struct snd_soc_codec *codec = rtd->codec; 1116 struct snd_soc_codec *codec = rtd->codec;
1164 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); 1117 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1165 u16 srate = wm8753_read_reg_cache(codec, WM8753_SRATE1) & 0x01c0; 1118 u16 srate = snd_soc_read(codec, WM8753_SRATE1) & 0x01c0;
1166 u16 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x01f3; 1119 u16 hifi = snd_soc_read(codec, WM8753_HIFI) & 0x01f3;
1167 int coeff; 1120 int coeff;
1168 1121
1169 /* is digital filter coefficient valid ? */ 1122 /* is digital filter coefficient valid ? */
@@ -1172,7 +1125,7 @@ static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream,
1172 printk(KERN_ERR "wm8753 invalid MCLK or rate\n"); 1125 printk(KERN_ERR "wm8753 invalid MCLK or rate\n");
1173 return coeff; 1126 return coeff;
1174 } 1127 }
1175 wm8753_write(codec, WM8753_SRATE1, srate | (coeff_div[coeff].sr << 1) | 1128 snd_soc_write(codec, WM8753_SRATE1, srate | (coeff_div[coeff].sr << 1) |
1176 coeff_div[coeff].usb); 1129 coeff_div[coeff].usb);
1177 1130
1178 /* bit size */ 1131 /* bit size */
@@ -1190,7 +1143,7 @@ static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream,
1190 break; 1143 break;
1191 } 1144 }
1192 1145
1193 wm8753_write(codec, WM8753_HIFI, hifi); 1146 snd_soc_write(codec, WM8753_HIFI, hifi);
1194 return 0; 1147 return 0;
1195} 1148}
1196 1149
@@ -1201,8 +1154,8 @@ static int wm8753_mode1v_set_dai_fmt(struct snd_soc_dai *codec_dai,
1201 u16 clock; 1154 u16 clock;
1202 1155
1203 /* set clk source as pcmclk */ 1156 /* set clk source as pcmclk */
1204 clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb; 1157 clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb;
1205 wm8753_write(codec, WM8753_CLOCK, clock); 1158 snd_soc_write(codec, WM8753_CLOCK, clock);
1206 1159
1207 if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0) 1160 if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0)
1208 return -EINVAL; 1161 return -EINVAL;
@@ -1224,8 +1177,8 @@ static int wm8753_mode2_set_dai_fmt(struct snd_soc_dai *codec_dai,
1224 u16 clock; 1177 u16 clock;
1225 1178
1226 /* set clk source as pcmclk */ 1179 /* set clk source as pcmclk */
1227 clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb; 1180 clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb;
1228 wm8753_write(codec, WM8753_CLOCK, clock); 1181 snd_soc_write(codec, WM8753_CLOCK, clock);
1229 1182
1230 if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0) 1183 if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0)
1231 return -EINVAL; 1184 return -EINVAL;
@@ -1239,8 +1192,8 @@ static int wm8753_mode3_4_set_dai_fmt(struct snd_soc_dai *codec_dai,
1239 u16 clock; 1192 u16 clock;
1240 1193
1241 /* set clk source as mclk */ 1194 /* set clk source as mclk */
1242 clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb; 1195 clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb;
1243 wm8753_write(codec, WM8753_CLOCK, clock | 0x4); 1196 snd_soc_write(codec, WM8753_CLOCK, clock | 0x4);
1244 1197
1245 if (wm8753_hdac_set_dai_fmt(codec_dai, fmt) < 0) 1198 if (wm8753_hdac_set_dai_fmt(codec_dai, fmt) < 0)
1246 return -EINVAL; 1199 return -EINVAL;
@@ -1252,19 +1205,19 @@ static int wm8753_mode3_4_set_dai_fmt(struct snd_soc_dai *codec_dai,
1252static int wm8753_mute(struct snd_soc_dai *dai, int mute) 1205static int wm8753_mute(struct snd_soc_dai *dai, int mute)
1253{ 1206{
1254 struct snd_soc_codec *codec = dai->codec; 1207 struct snd_soc_codec *codec = dai->codec;
1255 u16 mute_reg = wm8753_read_reg_cache(codec, WM8753_DAC) & 0xfff7; 1208 u16 mute_reg = snd_soc_read(codec, WM8753_DAC) & 0xfff7;
1256 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); 1209 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1257 1210
1258 /* the digital mute covers the HiFi and Voice DAC's on the WM8753. 1211 /* the digital mute covers the HiFi and Voice DAC's on the WM8753.
1259 * make sure we check if they are not both active when we mute */ 1212 * make sure we check if they are not both active when we mute */
1260 if (mute && wm8753->dai_func == 1) { 1213 if (mute && wm8753->dai_func == 1) {
1261 if (!codec->active) 1214 if (!codec->active)
1262 wm8753_write(codec, WM8753_DAC, mute_reg | 0x8); 1215 snd_soc_write(codec, WM8753_DAC, mute_reg | 0x8);
1263 } else { 1216 } else {
1264 if (mute) 1217 if (mute)
1265 wm8753_write(codec, WM8753_DAC, mute_reg | 0x8); 1218 snd_soc_write(codec, WM8753_DAC, mute_reg | 0x8);
1266 else 1219 else
1267 wm8753_write(codec, WM8753_DAC, mute_reg); 1220 snd_soc_write(codec, WM8753_DAC, mute_reg);
1268 } 1221 }
1269 1222
1270 return 0; 1223 return 0;
@@ -1273,23 +1226,23 @@ static int wm8753_mute(struct snd_soc_dai *dai, int mute)
1273static int wm8753_set_bias_level(struct snd_soc_codec *codec, 1226static int wm8753_set_bias_level(struct snd_soc_codec *codec,
1274 enum snd_soc_bias_level level) 1227 enum snd_soc_bias_level level)
1275{ 1228{
1276 u16 pwr_reg = wm8753_read_reg_cache(codec, WM8753_PWR1) & 0xfe3e; 1229 u16 pwr_reg = snd_soc_read(codec, WM8753_PWR1) & 0xfe3e;
1277 1230
1278 switch (level) { 1231 switch (level) {
1279 case SND_SOC_BIAS_ON: 1232 case SND_SOC_BIAS_ON:
1280 /* set vmid to 50k and unmute dac */ 1233 /* set vmid to 50k and unmute dac */
1281 wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x00c0); 1234 snd_soc_write(codec, WM8753_PWR1, pwr_reg | 0x00c0);
1282 break; 1235 break;
1283 case SND_SOC_BIAS_PREPARE: 1236 case SND_SOC_BIAS_PREPARE:
1284 /* set vmid to 5k for quick power up */ 1237 /* set vmid to 5k for quick power up */
1285 wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x01c1); 1238 snd_soc_write(codec, WM8753_PWR1, pwr_reg | 0x01c1);
1286 break; 1239 break;
1287 case SND_SOC_BIAS_STANDBY: 1240 case SND_SOC_BIAS_STANDBY:
1288 /* mute dac and set vmid to 500k, enable VREF */ 1241 /* mute dac and set vmid to 500k, enable VREF */
1289 wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x0141); 1242 snd_soc_write(codec, WM8753_PWR1, pwr_reg | 0x0141);
1290 break; 1243 break;
1291 case SND_SOC_BIAS_OFF: 1244 case SND_SOC_BIAS_OFF:
1292 wm8753_write(codec, WM8753_PWR1, 0x0001); 1245 snd_soc_write(codec, WM8753_PWR1, 0x0001);
1293 break; 1246 break;
1294 } 1247 }
1295 codec->dapm.bias_level = level; 1248 codec->dapm.bias_level = level;
@@ -1477,7 +1430,7 @@ static void wm8753_set_dai_mode(struct snd_soc_codec *codec,
1477 else 1430 else
1478 dai->driver = &wm8753_all_dai[(wm8753->dai_func << 1) + 1]; 1431 dai->driver = &wm8753_all_dai[(wm8753->dai_func << 1) + 1];
1479 } 1432 }
1480 wm8753_write(codec, WM8753_IOCTL, wm8753->dai_func); 1433 snd_soc_write(codec, WM8753_IOCTL, wm8753->dai_func);
1481} 1434}
1482 1435
1483static void wm8753_work(struct work_struct *work) 1436static void wm8753_work(struct work_struct *work)
@@ -1497,22 +1450,19 @@ static int wm8753_suspend(struct snd_soc_codec *codec, pm_message_t state)
1497 1450
1498static int wm8753_resume(struct snd_soc_codec *codec) 1451static int wm8753_resume(struct snd_soc_codec *codec)
1499{ 1452{
1453 u16 *reg_cache = codec->reg_cache;
1500 int i; 1454 int i;
1501 u8 data[2];
1502 u16 *cache = codec->reg_cache;
1503 1455
1504 /* Sync reg_cache with the hardware */ 1456 /* Sync reg_cache with the hardware */
1505 for (i = 0; i < ARRAY_SIZE(wm8753_reg); i++) { 1457 for (i = 1; i < ARRAY_SIZE(wm8753_reg); i++) {
1506 if (i + 1 == WM8753_RESET) 1458 if (i == WM8753_RESET)
1507 continue; 1459 continue;
1508 1460
1509 /* No point in writing hardware default values back */ 1461 /* No point in writing hardware default values back */
1510 if (cache[i] == wm8753_reg[i]) 1462 if (reg_cache[i] == wm8753_reg[i])
1511 continue; 1463 continue;
1512 1464
1513 data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001); 1465 snd_soc_write(codec, i, reg_cache[i]);
1514 data[1] = cache[i] & 0x00ff;
1515 codec->hw_write(codec->control_data, data, 2);
1516 } 1466 }
1517 1467
1518 wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1468 wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
@@ -1531,7 +1481,7 @@ static int wm8753_resume(struct snd_soc_codec *codec)
1531static int wm8753_probe(struct snd_soc_codec *codec) 1481static int wm8753_probe(struct snd_soc_codec *codec)
1532{ 1482{
1533 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); 1483 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1534 int ret = 0, reg; 1484 int ret;
1535 1485
1536 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8753_work); 1486 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8753_work);
1537 1487
@@ -1556,26 +1506,16 @@ static int wm8753_probe(struct snd_soc_codec *codec)
1556 msecs_to_jiffies(caps_charge)); 1506 msecs_to_jiffies(caps_charge));
1557 1507
1558 /* set the update bits */ 1508 /* set the update bits */
1559 reg = wm8753_read_reg_cache(codec, WM8753_LDAC); 1509 snd_soc_update_bits(codec, WM8753_LDAC, 0x0100, 0x0100);
1560 wm8753_write(codec, WM8753_LDAC, reg | 0x0100); 1510 snd_soc_update_bits(codec, WM8753_RDAC, 0x0100, 0x0100);
1561 reg = wm8753_read_reg_cache(codec, WM8753_RDAC); 1511 snd_soc_update_bits(codec, WM8753_LDAC, 0x0100, 0x0100);
1562 wm8753_write(codec, WM8753_RDAC, reg | 0x0100); 1512 snd_soc_update_bits(codec, WM8753_RDAC, 0x0100, 0x0100);
1563 reg = wm8753_read_reg_cache(codec, WM8753_LADC); 1513 snd_soc_update_bits(codec, WM8753_LOUT1V, 0x0100, 0x0100);
1564 wm8753_write(codec, WM8753_LADC, reg | 0x0100); 1514 snd_soc_update_bits(codec, WM8753_ROUT1V, 0x0100, 0x0100);
1565 reg = wm8753_read_reg_cache(codec, WM8753_RADC); 1515 snd_soc_update_bits(codec, WM8753_LOUT2V, 0x0100, 0x0100);
1566 wm8753_write(codec, WM8753_RADC, reg | 0x0100); 1516 snd_soc_update_bits(codec, WM8753_ROUT2V, 0x0100, 0x0100);
1567 reg = wm8753_read_reg_cache(codec, WM8753_LOUT1V); 1517 snd_soc_update_bits(codec, WM8753_LINVOL, 0x0100, 0x0100);
1568 wm8753_write(codec, WM8753_LOUT1V, reg | 0x0100); 1518 snd_soc_update_bits(codec, WM8753_RINVOL, 0x0100, 0x0100);
1569 reg = wm8753_read_reg_cache(codec, WM8753_ROUT1V);
1570 wm8753_write(codec, WM8753_ROUT1V, reg | 0x0100);
1571 reg = wm8753_read_reg_cache(codec, WM8753_LOUT2V);
1572 wm8753_write(codec, WM8753_LOUT2V, reg | 0x0100);
1573 reg = wm8753_read_reg_cache(codec, WM8753_ROUT2V);
1574 wm8753_write(codec, WM8753_ROUT2V, reg | 0x0100);
1575 reg = wm8753_read_reg_cache(codec, WM8753_LINVOL);
1576 wm8753_write(codec, WM8753_LINVOL, reg | 0x0100);
1577 reg = wm8753_read_reg_cache(codec, WM8753_RINVOL);
1578 wm8753_write(codec, WM8753_RINVOL, reg | 0x0100);
1579 1519
1580 snd_soc_add_controls(codec, wm8753_snd_controls, 1520 snd_soc_add_controls(codec, wm8753_snd_controls,
1581 ARRAY_SIZE(wm8753_snd_controls)); 1521 ARRAY_SIZE(wm8753_snd_controls));
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c
index cfbaac1a0ea..cd0959926d1 100644
--- a/sound/soc/codecs/wm8900.c
+++ b/sound/soc/codecs/wm8900.c
@@ -139,7 +139,6 @@
139 139
140struct wm8900_priv { 140struct wm8900_priv {
141 enum snd_soc_control_type control_type; 141 enum snd_soc_control_type control_type;
142 u16 reg_cache[WM8900_MAXREG];
143 142
144 u32 fll_in; /* FLL input frequency */ 143 u32 fll_in; /* FLL input frequency */
145 u32 fll_out; /* FLL output frequency */ 144 u32 fll_out; /* FLL output frequency */
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index d015745a886..987476a5895 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -31,6 +31,7 @@
31#include <sound/soc.h> 31#include <sound/soc.h>
32#include <sound/initval.h> 32#include <sound/initval.h>
33#include <sound/wm8903.h> 33#include <sound/wm8903.h>
34#include <trace/events/asoc.h>
34 35
35#include "wm8903.h" 36#include "wm8903.h"
36 37
@@ -213,8 +214,6 @@ static u16 wm8903_reg_defaults[] = {
213 214
214struct wm8903_priv { 215struct wm8903_priv {
215 216
216 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
217
218 int sysclk; 217 int sysclk;
219 int irq; 218 int irq;
220 219
@@ -1013,7 +1012,7 @@ static int wm8903_add_widgets(struct snd_soc_codec *codec)
1013static int wm8903_set_bias_level(struct snd_soc_codec *codec, 1012static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1014 enum snd_soc_bias_level level) 1013 enum snd_soc_bias_level level)
1015{ 1014{
1016 u16 reg, reg2; 1015 u16 reg;
1017 1016
1018 switch (level) { 1017 switch (level) {
1019 case SND_SOC_BIAS_ON: 1018 case SND_SOC_BIAS_ON:
@@ -1037,23 +1036,15 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1037 wm8903_run_sequence(codec, 0); 1036 wm8903_run_sequence(codec, 0);
1038 wm8903_sync_reg_cache(codec, codec->reg_cache); 1037 wm8903_sync_reg_cache(codec, codec->reg_cache);
1039 1038
1040 /* Enable low impedence charge pump output */
1041 reg = snd_soc_read(codec,
1042 WM8903_CONTROL_INTERFACE_TEST_1);
1043 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1044 reg | WM8903_TEST_KEY);
1045 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
1046 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
1047 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
1048 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1049 reg);
1050
1051 /* By default no bypass paths are enabled so 1039 /* By default no bypass paths are enabled so
1052 * enable Class W support. 1040 * enable Class W support.
1053 */ 1041 */
1054 dev_dbg(codec->dev, "Enabling Class W\n"); 1042 dev_dbg(codec->dev, "Enabling Class W\n");
1055 snd_soc_write(codec, WM8903_CLASS_W_0, reg | 1043 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1056 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 1044 WM8903_CP_DYN_FREQ |
1045 WM8903_CP_DYN_V,
1046 WM8903_CP_DYN_FREQ |
1047 WM8903_CP_DYN_V);
1057 } 1048 }
1058 1049
1059 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0); 1050 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
@@ -1533,6 +1524,11 @@ static irqreturn_t wm8903_irq(int irq, void *data)
1533 mic_report = wm8903->mic_last_report; 1524 mic_report = wm8903->mic_last_report;
1534 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1); 1525 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1535 1526
1527#ifndef CONFIG_SND_SOC_WM8903_MODULE
1528 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1529 trace_snd_soc_jack_irq(dev_name(codec->dev));
1530#endif
1531
1536 if (int_val & WM8903_MICSHRT_EINT) { 1532 if (int_val & WM8903_MICSHRT_EINT) {
1537 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol); 1533 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1538 1534
diff --git a/sound/soc/codecs/wm8903.h b/sound/soc/codecs/wm8903.h
index 996435e681e..e8490f3edd0 100644
--- a/sound/soc/codecs/wm8903.h
+++ b/sound/soc/codecs/wm8903.h
@@ -19,10 +19,6 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec,
19 struct snd_soc_jack *jack, 19 struct snd_soc_jack *jack,
20 int det, int shrt); 20 int det, int shrt);
21 21
22#define WM8903_MCLK_DIV_2 1
23#define WM8903_CLK_SYS 2
24#define WM8903_BCLK 3
25#define WM8903_LRCLK 4
26 22
27/* 23/*
28 * Register values. 24 * Register values.
@@ -98,8 +94,6 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec,
98#define WM8903_INTERRUPT_STATUS_1_MASK 0x7A 94#define WM8903_INTERRUPT_STATUS_1_MASK 0x7A
99#define WM8903_INTERRUPT_POLARITY_1 0x7B 95#define WM8903_INTERRUPT_POLARITY_1 0x7B
100#define WM8903_INTERRUPT_CONTROL 0x7E 96#define WM8903_INTERRUPT_CONTROL 0x7E
101#define WM8903_CONTROL_INTERFACE_TEST_1 0x81
102#define WM8903_CHARGE_PUMP_TEST_1 0x95
103#define WM8903_CLOCK_RATE_TEST_4 0xA4 97#define WM8903_CLOCK_RATE_TEST_4 0xA4
104#define WM8903_ANALOGUE_OUTPUT_BIAS_0 0xAC 98#define WM8903_ANALOGUE_OUTPUT_BIAS_0 0xAC
105 99
@@ -1206,25 +1200,6 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec,
1206#define WM8903_IRQ_POL_WIDTH 1 /* IRQ_POL */ 1200#define WM8903_IRQ_POL_WIDTH 1 /* IRQ_POL */
1207 1201
1208/* 1202/*
1209 * R129 (0x81) - Control Interface Test 1
1210 */
1211#define WM8903_USER_KEY 0x0002 /* USER_KEY */
1212#define WM8903_USER_KEY_MASK 0x0002 /* USER_KEY */
1213#define WM8903_USER_KEY_SHIFT 1 /* USER_KEY */
1214#define WM8903_USER_KEY_WIDTH 1 /* USER_KEY */
1215#define WM8903_TEST_KEY 0x0001 /* TEST_KEY */
1216#define WM8903_TEST_KEY_MASK 0x0001 /* TEST_KEY */
1217#define WM8903_TEST_KEY_SHIFT 0 /* TEST_KEY */
1218#define WM8903_TEST_KEY_WIDTH 1 /* TEST_KEY */
1219
1220/*
1221 * R149 (0x95) - Charge Pump Test 1
1222 */
1223#define WM8903_CP_SW_KELVIN_MODE_MASK 0x0006 /* CP_SW_KELVIN_MODE - [2:1] */
1224#define WM8903_CP_SW_KELVIN_MODE_SHIFT 1 /* CP_SW_KELVIN_MODE - [2:1] */
1225#define WM8903_CP_SW_KELVIN_MODE_WIDTH 2 /* CP_SW_KELVIN_MODE - [2:1] */
1226
1227/*
1228 * R164 (0xA4) - Clock Rate Test 4 1203 * R164 (0xA4) - Clock Rate Test 4
1229 */ 1204 */
1230#define WM8903_ADC_DIG_MIC 0x0200 /* ADC_DIG_MIC */ 1205#define WM8903_ADC_DIG_MIC 0x0200 /* ADC_DIG_MIC */
diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c
index 8ba142abd8e..9de44a4c05c 100644
--- a/sound/soc/codecs/wm8904.c
+++ b/sound/soc/codecs/wm8904.c
@@ -49,8 +49,6 @@ static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
49/* codec private data */ 49/* codec private data */
50struct wm8904_priv { 50struct wm8904_priv {
51 51
52 u16 reg_cache[WM8904_MAX_REGISTER + 1];
53
54 enum wm8904_type devtype; 52 enum wm8904_type devtype;
55 void *control_data; 53 void *control_data;
56 54
@@ -2094,7 +2092,7 @@ static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2094 2092
2095static void wm8904_sync_cache(struct snd_soc_codec *codec) 2093static void wm8904_sync_cache(struct snd_soc_codec *codec)
2096{ 2094{
2097 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2095 u16 *reg_cache = codec->reg_cache;
2098 int i; 2096 int i;
2099 2097
2100 if (!codec->cache_sync) 2098 if (!codec->cache_sync)
@@ -2105,14 +2103,14 @@ static void wm8904_sync_cache(struct snd_soc_codec *codec)
2105 /* Sync back cached values if they're different from the 2103 /* Sync back cached values if they're different from the
2106 * hardware default. 2104 * hardware default.
2107 */ 2105 */
2108 for (i = 1; i < ARRAY_SIZE(wm8904->reg_cache); i++) { 2106 for (i = 1; i < codec->driver->reg_cache_size; i++) {
2109 if (!wm8904_access[i].writable) 2107 if (!wm8904_access[i].writable)
2110 continue; 2108 continue;
2111 2109
2112 if (wm8904->reg_cache[i] == wm8904_reg[i]) 2110 if (reg_cache[i] == wm8904_reg[i])
2113 continue; 2111 continue;
2114 2112
2115 snd_soc_write(codec, i, wm8904->reg_cache[i]); 2113 snd_soc_write(codec, i, reg_cache[i]);
2116 } 2114 }
2117 2115
2118 codec->cache_sync = 0; 2116 codec->cache_sync = 0;
@@ -2371,6 +2369,7 @@ static int wm8904_probe(struct snd_soc_codec *codec)
2371{ 2369{
2372 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2370 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2373 struct wm8904_pdata *pdata = wm8904->pdata; 2371 struct wm8904_pdata *pdata = wm8904->pdata;
2372 u16 *reg_cache = codec->reg_cache;
2374 int ret, i; 2373 int ret, i;
2375 2374
2376 codec->cache_sync = 1; 2375 codec->cache_sync = 1;
@@ -2437,19 +2436,19 @@ static int wm8904_probe(struct snd_soc_codec *codec)
2437 } 2436 }
2438 2437
2439 /* Change some default settings - latch VU and enable ZC */ 2438 /* Change some default settings - latch VU and enable ZC */
2440 wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU; 2439 reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU;
2441 wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU; 2440 reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU;
2442 wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU; 2441 reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU;
2443 wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU; 2442 reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU;
2444 wm8904->reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU | 2443 reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU |
2445 WM8904_HPOUTLZC; 2444 WM8904_HPOUTLZC;
2446 wm8904->reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU | 2445 reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU |
2447 WM8904_HPOUTRZC; 2446 WM8904_HPOUTRZC;
2448 wm8904->reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU | 2447 reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU |
2449 WM8904_LINEOUTLZC; 2448 WM8904_LINEOUTLZC;
2450 wm8904->reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU | 2449 reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU |
2451 WM8904_LINEOUTRZC; 2450 WM8904_LINEOUTRZC;
2452 wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE; 2451 reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE;
2453 2452
2454 /* Apply configuration from the platform data. */ 2453 /* Apply configuration from the platform data. */
2455 if (wm8904->pdata) { 2454 if (wm8904->pdata) {
@@ -2457,23 +2456,23 @@ static int wm8904_probe(struct snd_soc_codec *codec)
2457 if (!pdata->gpio_cfg[i]) 2456 if (!pdata->gpio_cfg[i])
2458 continue; 2457 continue;
2459 2458
2460 wm8904->reg_cache[WM8904_GPIO_CONTROL_1 + i] 2459 reg_cache[WM8904_GPIO_CONTROL_1 + i]
2461 = pdata->gpio_cfg[i] & 0xffff; 2460 = pdata->gpio_cfg[i] & 0xffff;
2462 } 2461 }
2463 2462
2464 /* Zero is the default value for these anyway */ 2463 /* Zero is the default value for these anyway */
2465 for (i = 0; i < WM8904_MIC_REGS; i++) 2464 for (i = 0; i < WM8904_MIC_REGS; i++)
2466 wm8904->reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i] 2465 reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i]
2467 = pdata->mic_cfg[i]; 2466 = pdata->mic_cfg[i];
2468 } 2467 }
2469 2468
2470 /* Set Class W by default - this will be managed by the Class 2469 /* Set Class W by default - this will be managed by the Class
2471 * G widget at runtime where bypass paths are available. 2470 * G widget at runtime where bypass paths are available.
2472 */ 2471 */
2473 wm8904->reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR; 2472 reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR;
2474 2473
2475 /* Use normal bias source */ 2474 /* Use normal bias source */
2476 wm8904->reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL; 2475 reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL;
2477 2476
2478 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2477 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2479 2478
diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
index 381934fff4e..25580e3ee7c 100644
--- a/sound/soc/codecs/wm8940.c
+++ b/sound/soc/codecs/wm8940.c
@@ -42,7 +42,6 @@
42 42
43struct wm8940_priv { 43struct wm8940_priv {
44 unsigned int sysclk; 44 unsigned int sysclk;
45 u16 reg_cache[WM8940_CACHEREGNUM];
46 enum snd_soc_control_type control_type; 45 enum snd_soc_control_type control_type;
47 void *control_data; 46 void *control_data;
48}; 47};
@@ -767,6 +766,7 @@ static __devinit int wm8940_i2c_probe(struct i2c_client *i2c,
767 766
768 i2c_set_clientdata(i2c, wm8940); 767 i2c_set_clientdata(i2c, wm8940);
769 wm8940->control_data = i2c; 768 wm8940->control_data = i2c;
769 wm8940->control_type = SND_SOC_I2C;
770 770
771 ret = snd_soc_register_codec(&i2c->dev, 771 ret = snd_soc_register_codec(&i2c->dev,
772 &soc_codec_dev_wm8940, &wm8940_dai, 1); 772 &soc_codec_dev_wm8940, &wm8940_dai, 1);
diff --git a/sound/soc/codecs/wm8955.c b/sound/soc/codecs/wm8955.c
index ca0265f008d..7167dfc96aa 100644
--- a/sound/soc/codecs/wm8955.c
+++ b/sound/soc/codecs/wm8955.c
@@ -41,8 +41,6 @@ static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
41struct wm8955_priv { 41struct wm8955_priv {
42 enum snd_soc_control_type control_type; 42 enum snd_soc_control_type control_type;
43 43
44 u16 reg_cache[WM8955_MAX_REGISTER + 1];
45
46 unsigned int mclk_rate; 44 unsigned int mclk_rate;
47 45
48 int deemph; 46 int deemph;
@@ -768,6 +766,7 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec,
768 enum snd_soc_bias_level level) 766 enum snd_soc_bias_level level)
769{ 767{
770 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); 768 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
769 u16 *reg_cache = codec->reg_cache;
771 int ret, i; 770 int ret, i;
772 771
773 switch (level) { 772 switch (level) {
@@ -800,14 +799,14 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec,
800 /* Sync back cached values if they're 799 /* Sync back cached values if they're
801 * different from the hardware default. 800 * different from the hardware default.
802 */ 801 */
803 for (i = 0; i < ARRAY_SIZE(wm8955->reg_cache); i++) { 802 for (i = 0; i < codec->driver->reg_cache_size; i++) {
804 if (i == WM8955_RESET) 803 if (i == WM8955_RESET)
805 continue; 804 continue;
806 805
807 if (wm8955->reg_cache[i] == wm8955_reg[i]) 806 if (reg_cache[i] == wm8955_reg[i])
808 continue; 807 continue;
809 808
810 snd_soc_write(codec, i, wm8955->reg_cache[i]); 809 snd_soc_write(codec, i, reg_cache[i]);
811 } 810 }
812 811
813 /* Enable VREF and VMID */ 812 /* Enable VREF and VMID */
@@ -902,6 +901,7 @@ static int wm8955_probe(struct snd_soc_codec *codec)
902{ 901{
903 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); 902 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
904 struct wm8955_pdata *pdata = dev_get_platdata(codec->dev); 903 struct wm8955_pdata *pdata = dev_get_platdata(codec->dev);
904 u16 *reg_cache = codec->reg_cache;
905 int ret, i; 905 int ret, i;
906 906
907 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type); 907 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type);
@@ -934,25 +934,25 @@ static int wm8955_probe(struct snd_soc_codec *codec)
934 } 934 }
935 935
936 /* Change some default settings - latch VU and enable ZC */ 936 /* Change some default settings - latch VU and enable ZC */
937 wm8955->reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU; 937 reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU;
938 wm8955->reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU; 938 reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU;
939 wm8955->reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC; 939 reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC;
940 wm8955->reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC; 940 reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC;
941 wm8955->reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC; 941 reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC;
942 wm8955->reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC; 942 reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC;
943 wm8955->reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC; 943 reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC;
944 944
945 /* Also enable adaptive bass boost by default */ 945 /* Also enable adaptive bass boost by default */
946 wm8955->reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB; 946 reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB;
947 947
948 /* Set platform data values */ 948 /* Set platform data values */
949 if (pdata) { 949 if (pdata) {
950 if (pdata->out2_speaker) 950 if (pdata->out2_speaker)
951 wm8955->reg_cache[WM8955_ADDITIONAL_CONTROL_2] 951 reg_cache[WM8955_ADDITIONAL_CONTROL_2]
952 |= WM8955_ROUT2INV; 952 |= WM8955_ROUT2INV;
953 953
954 if (pdata->monoin_diff) 954 if (pdata->monoin_diff)
955 wm8955->reg_cache[WM8955_MONO_OUT_MIX_1] 955 reg_cache[WM8955_MONO_OUT_MIX_1]
956 |= WM8955_DMEN; 956 |= WM8955_DMEN;
957 } 957 }
958 958
@@ -1003,6 +1003,7 @@ static __devinit int wm8955_i2c_probe(struct i2c_client *i2c,
1003 return -ENOMEM; 1003 return -ENOMEM;
1004 1004
1005 i2c_set_clientdata(i2c, wm8955); 1005 i2c_set_clientdata(i2c, wm8955);
1006 wm8955->control_type = SND_SOC_I2C;
1006 1007
1007 ret = snd_soc_register_codec(&i2c->dev, 1008 ret = snd_soc_register_codec(&i2c->dev,
1008 &soc_codec_dev_wm8955, &wm8955_dai, 1); 1009 &soc_codec_dev_wm8955, &wm8955_dai, 1);
diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c
index 2c5712dce1d..4393394b7bc 100644
--- a/sound/soc/codecs/wm8960.c
+++ b/sound/soc/codecs/wm8960.c
@@ -71,7 +71,6 @@ static const u16 wm8960_reg[WM8960_CACHEREGNUM] = {
71}; 71};
72 72
73struct wm8960_priv { 73struct wm8960_priv {
74 u16 reg_cache[WM8960_CACHEREGNUM];
75 enum snd_soc_control_type control_type; 74 enum snd_soc_control_type control_type;
76 void *control_data; 75 void *control_data;
77 int (*set_bias_level)(struct snd_soc_codec *, 76 int (*set_bias_level)(struct snd_soc_codec *,
@@ -418,7 +417,9 @@ static int wm8960_add_widgets(struct snd_soc_codec *codec)
418 * list each time to find the desired power state do so now 417 * list each time to find the desired power state do so now
419 * and save the result. 418 * and save the result.
420 */ 419 */
421 list_for_each_entry(w, &codec->dapm.widgets, list) { 420 list_for_each_entry(w, &codec->card->widgets, list) {
421 if (w->dapm != &codec->dapm)
422 continue;
422 if (strcmp(w->name, "LOUT1 PGA") == 0) 423 if (strcmp(w->name, "LOUT1 PGA") == 0)
423 wm8960->lout1 = w; 424 wm8960->lout1 = w;
424 if (strcmp(w->name, "ROUT1 PGA") == 0) 425 if (strcmp(w->name, "ROUT1 PGA") == 0)
@@ -1013,6 +1014,7 @@ static __devinit int wm8960_i2c_probe(struct i2c_client *i2c,
1013 return -ENOMEM; 1014 return -ENOMEM;
1014 1015
1015 i2c_set_clientdata(i2c, wm8960); 1016 i2c_set_clientdata(i2c, wm8960);
1017 wm8960->control_type = SND_SOC_I2C;
1016 wm8960->control_data = i2c; 1018 wm8960->control_data = i2c;
1017 1019
1018 ret = snd_soc_register_codec(&i2c->dev, 1020 ret = snd_soc_register_codec(&i2c->dev,
diff --git a/sound/soc/codecs/wm8961.c b/sound/soc/codecs/wm8961.c
index 6b22ef200e2..55252e7d02c 100644
--- a/sound/soc/codecs/wm8961.c
+++ b/sound/soc/codecs/wm8961.c
@@ -289,7 +289,6 @@ static u16 wm8961_reg_defaults[] = {
289struct wm8961_priv { 289struct wm8961_priv {
290 enum snd_soc_control_type control_type; 290 enum snd_soc_control_type control_type;
291 int sysclk; 291 int sysclk;
292 u16 reg_cache[WM8961_MAX_REGISTER];
293}; 292};
294 293
295static int wm8961_volatile_register(unsigned int reg) 294static int wm8961_volatile_register(unsigned int reg)
diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
index f0c9d269184..b9cb1fcf8c9 100644
--- a/sound/soc/codecs/wm8962.c
+++ b/sound/soc/codecs/wm8962.c
@@ -32,6 +32,7 @@
32#include <sound/initval.h> 32#include <sound/initval.h>
33#include <sound/tlv.h> 33#include <sound/tlv.h>
34#include <sound/wm8962.h> 34#include <sound/wm8962.h>
35#include <trace/events/asoc.h>
35 36
36#include "wm8962.h" 37#include "wm8962.h"
37 38
@@ -51,8 +52,6 @@ static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
51struct wm8962_priv { 52struct wm8962_priv {
52 struct snd_soc_codec *codec; 53 struct snd_soc_codec *codec;
53 54
54 u16 reg_cache[WM8962_MAX_REGISTER + 1];
55
56 int sysclk; 55 int sysclk;
57 int sysclk_rate; 56 int sysclk_rate;
58 57
@@ -1990,8 +1989,7 @@ static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1990 struct snd_ctl_elem_value *ucontrol) 1989 struct snd_ctl_elem_value *ucontrol)
1991{ 1990{
1992 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1991 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1993 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 1992 u16 *reg_cache = codec->reg_cache;
1994 u16 *reg_cache = wm8962->reg_cache;
1995 int ret; 1993 int ret;
1996 1994
1997 /* Apply the update (if any) */ 1995 /* Apply the update (if any) */
@@ -2019,8 +2017,7 @@ static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
2019 struct snd_ctl_elem_value *ucontrol) 2017 struct snd_ctl_elem_value *ucontrol)
2020{ 2018{
2021 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 2019 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2022 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2020 u16 *reg_cache = codec->reg_cache;
2023 u16 *reg_cache = wm8962->reg_cache;
2024 int ret; 2021 int ret;
2025 2022
2026 /* Apply the update (if any) */ 2023 /* Apply the update (if any) */
@@ -2328,8 +2325,7 @@ static int out_pga_event(struct snd_soc_dapm_widget *w,
2328 struct snd_kcontrol *kcontrol, int event) 2325 struct snd_kcontrol *kcontrol, int event)
2329{ 2326{
2330 struct snd_soc_codec *codec = w->codec; 2327 struct snd_soc_codec *codec = w->codec;
2331 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2328 u16 *reg_cache = codec->reg_cache;
2332 u16 *reg_cache = wm8962->reg_cache;
2333 int reg; 2329 int reg;
2334 2330
2335 switch (w->shift) { 2331 switch (w->shift) {
@@ -2719,7 +2715,7 @@ static int wm8962_add_widgets(struct snd_soc_codec *codec)
2719 2715
2720static void wm8962_sync_cache(struct snd_soc_codec *codec) 2716static void wm8962_sync_cache(struct snd_soc_codec *codec)
2721{ 2717{
2722 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2718 u16 *reg_cache = codec->reg_cache;
2723 int i; 2719 int i;
2724 2720
2725 if (!codec->cache_sync) 2721 if (!codec->cache_sync)
@@ -2732,13 +2728,13 @@ static void wm8962_sync_cache(struct snd_soc_codec *codec)
2732 /* Sync back cached values if they're different from the 2728 /* Sync back cached values if they're different from the
2733 * hardware default. 2729 * hardware default.
2734 */ 2730 */
2735 for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) { 2731 for (i = 1; i < codec->driver->reg_cache_size; i++) {
2736 if (i == WM8962_SOFTWARE_RESET) 2732 if (i == WM8962_SOFTWARE_RESET)
2737 continue; 2733 continue;
2738 if (wm8962->reg_cache[i] == wm8962_reg[i]) 2734 if (reg_cache[i] == wm8962_reg[i])
2739 continue; 2735 continue;
2740 2736
2741 snd_soc_write(codec, i, wm8962->reg_cache[i]); 2737 snd_soc_write(codec, i, reg_cache[i]);
2742 } 2738 }
2743 2739
2744 codec->cache_sync = 0; 2740 codec->cache_sync = 0;
@@ -3353,6 +3349,10 @@ static irqreturn_t wm8962_irq(int irq, void *data)
3353 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { 3349 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3354 dev_dbg(codec->dev, "Microphone event detected\n"); 3350 dev_dbg(codec->dev, "Microphone event detected\n");
3355 3351
3352#ifndef CONFIG_SND_SOC_WM8962_MODULE
3353 trace_snd_soc_jack_irq(dev_name(codec->dev));
3354#endif
3355
3356 pm_wakeup_event(codec->dev, 300); 3356 pm_wakeup_event(codec->dev, 300);
3357 3357
3358 schedule_delayed_work(&wm8962->mic_work, 3358 schedule_delayed_work(&wm8962->mic_work,
@@ -3408,12 +3408,11 @@ EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3408#ifdef CONFIG_PM 3408#ifdef CONFIG_PM
3409static int wm8962_resume(struct snd_soc_codec *codec) 3409static int wm8962_resume(struct snd_soc_codec *codec)
3410{ 3410{
3411 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3412 u16 *reg_cache = codec->reg_cache; 3411 u16 *reg_cache = codec->reg_cache;
3413 int i; 3412 int i;
3414 3413
3415 /* Restore the registers */ 3414 /* Restore the registers */
3416 for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) { 3415 for (i = 1; i < codec->driver->reg_cache_size; i++) {
3417 switch (i) { 3416 switch (i) {
3418 case WM8962_SOFTWARE_RESET: 3417 case WM8962_SOFTWARE_RESET:
3419 continue; 3418 continue;
@@ -3708,6 +3707,7 @@ static int wm8962_probe(struct snd_soc_codec *codec)
3708 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); 3707 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3709 struct i2c_client *i2c = container_of(codec->dev, struct i2c_client, 3708 struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
3710 dev); 3709 dev);
3710 u16 *reg_cache = codec->reg_cache;
3711 int i, trigger, irq_pol; 3711 int i, trigger, irq_pol;
3712 3712
3713 wm8962->codec = codec; 3713 wm8962->codec = codec;
@@ -3807,7 +3807,7 @@ static int wm8962_probe(struct snd_soc_codec *codec)
3807 3807
3808 /* Put the speakers into mono mode? */ 3808 /* Put the speakers into mono mode? */
3809 if (pdata->spk_mono) 3809 if (pdata->spk_mono)
3810 wm8962->reg_cache[WM8962_CLASS_D_CONTROL_2] 3810 reg_cache[WM8962_CLASS_D_CONTROL_2]
3811 |= WM8962_SPK_MONO; 3811 |= WM8962_SPK_MONO;
3812 3812
3813 /* Micbias setup, detection enable and detection 3813 /* Micbias setup, detection enable and detection
@@ -3822,16 +3822,16 @@ static int wm8962_probe(struct snd_soc_codec *codec)
3822 } 3822 }
3823 3823
3824 /* Latch volume update bits */ 3824 /* Latch volume update bits */
3825 wm8962->reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU; 3825 reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU;
3826 wm8962->reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU; 3826 reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU;
3827 wm8962->reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU; 3827 reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU;
3828 wm8962->reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU; 3828 reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU;
3829 wm8962->reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU; 3829 reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU;
3830 wm8962->reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU; 3830 reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU;
3831 wm8962->reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU; 3831 reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU;
3832 wm8962->reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU; 3832 reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU;
3833 wm8962->reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU; 3833 reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU;
3834 wm8962->reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU; 3834 reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU;
3835 3835
3836 wm8962_add_widgets(codec); 3836 wm8962_add_widgets(codec);
3837 3837
diff --git a/sound/soc/codecs/wm8971.c b/sound/soc/codecs/wm8971.c
index 8805636bda5..572bb80627a 100644
--- a/sound/soc/codecs/wm8971.c
+++ b/sound/soc/codecs/wm8971.c
@@ -720,6 +720,7 @@ static __devinit int wm8971_i2c_probe(struct i2c_client *i2c,
720 if (wm8971 == NULL) 720 if (wm8971 == NULL)
721 return -ENOMEM; 721 return -ENOMEM;
722 722
723 wm8971->control_type = SND_SOC_I2C;
723 i2c_set_clientdata(i2c, wm8971); 724 i2c_set_clientdata(i2c, wm8971);
724 725
725 ret = snd_soc_register_codec(&i2c->dev, 726 ret = snd_soc_register_codec(&i2c->dev,
diff --git a/sound/soc/codecs/wm8974.c b/sound/soc/codecs/wm8974.c
index 5d286427532..ca646a82244 100644
--- a/sound/soc/codecs/wm8974.c
+++ b/sound/soc/codecs/wm8974.c
@@ -51,7 +51,6 @@ static const u16 wm8974_reg[WM8974_CACHEREGNUM] = {
51 51
52struct wm8974_priv { 52struct wm8974_priv {
53 enum snd_soc_control_type control_type; 53 enum snd_soc_control_type control_type;
54 u16 reg_cache[WM8974_CACHEREGNUM];
55}; 54};
56 55
57#define wm8974_reset(c) snd_soc_write(c, WM8974_RESET, 0) 56#define wm8974_reset(c) snd_soc_write(c, WM8974_RESET, 0)
diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c
index a195af92b42..4bbc3442703 100644
--- a/sound/soc/codecs/wm8978.c
+++ b/sound/soc/codecs/wm8978.c
@@ -59,7 +59,6 @@ struct wm8978_priv {
59 unsigned int f_opclk; 59 unsigned int f_opclk;
60 int mclk_idx; 60 int mclk_idx;
61 enum wm8978_sysclk_src sysclk; 61 enum wm8978_sysclk_src sysclk;
62 u16 reg_cache[WM8978_CACHEREGNUM];
63}; 62};
64 63
65static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"}; 64static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
diff --git a/sound/soc/codecs/wm8988.c b/sound/soc/codecs/wm8988.c
index 65807b15a2c..d7170f1381a 100644
--- a/sound/soc/codecs/wm8988.c
+++ b/sound/soc/codecs/wm8988.c
@@ -53,7 +53,6 @@ struct wm8988_priv {
53 unsigned int sysclk; 53 unsigned int sysclk;
54 enum snd_soc_control_type control_type; 54 enum snd_soc_control_type control_type;
55 struct snd_pcm_hw_constraint_list *sysclk_constraints; 55 struct snd_pcm_hw_constraint_list *sysclk_constraints;
56 u16 reg_cache[WM8988_NUM_REG];
57}; 56};
58 57
59 58
diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c
index 15f34a26deb..18c0d9ce7c3 100644
--- a/sound/soc/codecs/wm8993.c
+++ b/sound/soc/codecs/wm8993.c
@@ -225,7 +225,6 @@ static struct {
225 225
226struct wm8993_priv { 226struct wm8993_priv {
227 struct wm_hubs_data hubs_data; 227 struct wm_hubs_data hubs_data;
228 u16 reg_cache[WM8993_REGISTER_COUNT];
229 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES]; 228 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
230 struct wm8993_platform_data pdata; 229 struct wm8993_platform_data pdata;
231 enum snd_soc_control_type control_type; 230 enum snd_soc_control_type control_type;
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index af104acd75f..247a6a99feb 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -28,6 +28,7 @@
28#include <sound/soc.h> 28#include <sound/soc.h>
29#include <sound/initval.h> 29#include <sound/initval.h>
30#include <sound/tlv.h> 30#include <sound/tlv.h>
31#include <trace/events/asoc.h>
31 32
32#include <linux/mfd/wm8994/core.h> 33#include <linux/mfd/wm8994/core.h>
33#include <linux/mfd/wm8994/registers.h> 34#include <linux/mfd/wm8994/registers.h>
@@ -869,15 +870,15 @@ SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
869 870
870SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 871SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
871 10, 15, 0, wm8994_3d_tlv), 872 10, 15, 0, wm8994_3d_tlv),
872SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 873SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
873 8, 1, 0), 874 8, 1, 0),
874SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 875SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
875 10, 15, 0, wm8994_3d_tlv), 876 10, 15, 0, wm8994_3d_tlv),
876SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 877SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
877 8, 1, 0), 878 8, 1, 0),
878SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 879SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
879 10, 15, 0, wm8994_3d_tlv), 880 10, 15, 0, wm8994_3d_tlv),
880SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 881SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
881 8, 1, 0), 882 8, 1, 0),
882}; 883};
883 884
@@ -2755,6 +2756,10 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data)
2755 int reg; 2756 int reg;
2756 int report; 2757 int report;
2757 2758
2759#ifndef CONFIG_SND_SOC_WM8994_MODULE
2760 trace_snd_soc_jack_irq(dev_name(codec->dev));
2761#endif
2762
2758 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); 2763 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2759 if (reg < 0) { 2764 if (reg < 0) {
2760 dev_err(codec->dev, "Failed to read microphone status: %d\n", 2765 dev_err(codec->dev, "Failed to read microphone status: %d\n",
@@ -2901,6 +2906,10 @@ static irqreturn_t wm8958_mic_irq(int irq, void *data)
2901 goto out; 2906 goto out;
2902 } 2907 }
2903 2908
2909#ifndef CONFIG_SND_SOC_WM8994_MODULE
2910 trace_snd_soc_jack_irq(dev_name(codec->dev));
2911#endif
2912
2904 if (wm8994->jack_cb) 2913 if (wm8994->jack_cb)
2905 wm8994->jack_cb(reg, wm8994->jack_cb_data); 2914 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2906 else 2915 else
diff --git a/sound/soc/codecs/wm8995.c b/sound/soc/codecs/wm8995.c
new file mode 100644
index 00000000000..6045cbde492
--- /dev/null
+++ b/sound/soc/codecs/wm8995.c
@@ -0,0 +1,1818 @@
1/*
2 * wm8995.c -- WM8995 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * Based on wm8994.c and wm_hubs.c by Mark Brown
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/spi/spi.h>
22#include <linux/slab.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include "wm8995.h"
32
33static const u16 wm8995_reg_defs[WM8995_MAX_REGISTER + 1] = {
34 [0] = 0x8995, [5] = 0x0100, [16] = 0x000b, [17] = 0x000b,
35 [24] = 0x02c0, [25] = 0x02c0, [26] = 0x02c0, [27] = 0x02c0,
36 [28] = 0x000f, [32] = 0x0005, [33] = 0x0005, [40] = 0x0003,
37 [41] = 0x0013, [48] = 0x0004, [56] = 0x09f8, [64] = 0x1f25,
38 [69] = 0x0004, [82] = 0xaaaa, [84] = 0x2a2a, [146] = 0x0060,
39 [256] = 0x0002, [257] = 0x8004, [520] = 0x0010, [528] = 0x0083,
40 [529] = 0x0083, [548] = 0x0c80, [580] = 0x0c80, [768] = 0x4050,
41 [769] = 0x4000, [771] = 0x0040, [772] = 0x0040, [773] = 0x0040,
42 [774] = 0x0004, [775] = 0x0100, [784] = 0x4050, [785] = 0x4000,
43 [787] = 0x0040, [788] = 0x0040, [789] = 0x0040, [1024] = 0x00c0,
44 [1025] = 0x00c0, [1026] = 0x00c0, [1027] = 0x00c0, [1028] = 0x00c0,
45 [1029] = 0x00c0, [1030] = 0x00c0, [1031] = 0x00c0, [1056] = 0x0200,
46 [1057] = 0x0010, [1058] = 0x0200, [1059] = 0x0010, [1088] = 0x0098,
47 [1089] = 0x0845, [1104] = 0x0098, [1105] = 0x0845, [1152] = 0x6318,
48 [1153] = 0x6300, [1154] = 0x0fca, [1155] = 0x0400, [1156] = 0x00d8,
49 [1157] = 0x1eb5, [1158] = 0xf145, [1159] = 0x0b75, [1160] = 0x01c5,
50 [1161] = 0x1c58, [1162] = 0xf373, [1163] = 0x0a54, [1164] = 0x0558,
51 [1165] = 0x168e, [1166] = 0xf829, [1167] = 0x07ad, [1168] = 0x1103,
52 [1169] = 0x0564, [1170] = 0x0559, [1171] = 0x4000, [1184] = 0x6318,
53 [1185] = 0x6300, [1186] = 0x0fca, [1187] = 0x0400, [1188] = 0x00d8,
54 [1189] = 0x1eb5, [1190] = 0xf145, [1191] = 0x0b75, [1192] = 0x01c5,
55 [1193] = 0x1c58, [1194] = 0xf373, [1195] = 0x0a54, [1196] = 0x0558,
56 [1197] = 0x168e, [1198] = 0xf829, [1199] = 0x07ad, [1200] = 0x1103,
57 [1201] = 0x0564, [1202] = 0x0559, [1203] = 0x4000, [1280] = 0x00c0,
58 [1281] = 0x00c0, [1282] = 0x00c0, [1283] = 0x00c0, [1312] = 0x0200,
59 [1313] = 0x0010, [1344] = 0x0098, [1345] = 0x0845, [1408] = 0x6318,
60 [1409] = 0x6300, [1410] = 0x0fca, [1411] = 0x0400, [1412] = 0x00d8,
61 [1413] = 0x1eb5, [1414] = 0xf145, [1415] = 0x0b75, [1416] = 0x01c5,
62 [1417] = 0x1c58, [1418] = 0xf373, [1419] = 0x0a54, [1420] = 0x0558,
63 [1421] = 0x168e, [1422] = 0xf829, [1423] = 0x07ad, [1424] = 0x1103,
64 [1425] = 0x0564, [1426] = 0x0559, [1427] = 0x4000, [1568] = 0x0002,
65 [1792] = 0xa100, [1793] = 0xa101, [1794] = 0xa101, [1795] = 0xa101,
66 [1796] = 0xa101, [1797] = 0xa101, [1798] = 0xa101, [1799] = 0xa101,
67 [1800] = 0xa101, [1801] = 0xa101, [1802] = 0xa101, [1803] = 0xa101,
68 [1804] = 0xa101, [1805] = 0xa101, [1825] = 0x0055, [1848] = 0x3fff,
69 [1849] = 0x1fff, [2049] = 0x0001, [2050] = 0x0069, [2056] = 0x0002,
70 [2057] = 0x0003, [2058] = 0x0069, [12288] = 0x0001, [12289] = 0x0001,
71 [12291] = 0x0006, [12292] = 0x0040, [12293] = 0x0001, [12294] = 0x000f,
72 [12295] = 0x0006, [12296] = 0x0001, [12297] = 0x0003, [12298] = 0x0104,
73 [12300] = 0x0060, [12301] = 0x0011, [12302] = 0x0401, [12304] = 0x0050,
74 [12305] = 0x0003, [12306] = 0x0100, [12308] = 0x0051, [12309] = 0x0003,
75 [12310] = 0x0104, [12311] = 0x000a, [12312] = 0x0060, [12313] = 0x003b,
76 [12314] = 0x0502, [12315] = 0x0100, [12316] = 0x2fff, [12320] = 0x2fff,
77 [12324] = 0x2fff, [12328] = 0x2fff, [12332] = 0x2fff, [12336] = 0x2fff,
78 [12340] = 0x2fff, [12344] = 0x2fff, [12348] = 0x2fff, [12352] = 0x0001,
79 [12353] = 0x0001, [12355] = 0x0006, [12356] = 0x0040, [12357] = 0x0001,
80 [12358] = 0x000f, [12359] = 0x0006, [12360] = 0x0001, [12361] = 0x0003,
81 [12362] = 0x0104, [12364] = 0x0060, [12365] = 0x0011, [12366] = 0x0401,
82 [12368] = 0x0050, [12369] = 0x0003, [12370] = 0x0100, [12372] = 0x0060,
83 [12373] = 0x003b, [12374] = 0x0502, [12375] = 0x0100, [12376] = 0x2fff,
84 [12380] = 0x2fff, [12384] = 0x2fff, [12388] = 0x2fff, [12392] = 0x2fff,
85 [12396] = 0x2fff, [12400] = 0x2fff, [12404] = 0x2fff, [12408] = 0x2fff,
86 [12412] = 0x2fff, [12416] = 0x0001, [12417] = 0x0001, [12419] = 0x0006,
87 [12420] = 0x0040, [12421] = 0x0001, [12422] = 0x000f, [12423] = 0x0006,
88 [12424] = 0x0001, [12425] = 0x0003, [12426] = 0x0106, [12428] = 0x0061,
89 [12429] = 0x0011, [12430] = 0x0401, [12432] = 0x0050, [12433] = 0x0003,
90 [12434] = 0x0102, [12436] = 0x0051, [12437] = 0x0003, [12438] = 0x0106,
91 [12439] = 0x000a, [12440] = 0x0061, [12441] = 0x003b, [12442] = 0x0502,
92 [12443] = 0x0100, [12444] = 0x2fff, [12448] = 0x2fff, [12452] = 0x2fff,
93 [12456] = 0x2fff, [12460] = 0x2fff, [12464] = 0x2fff, [12468] = 0x2fff,
94 [12472] = 0x2fff, [12476] = 0x2fff, [12480] = 0x0001, [12481] = 0x0001,
95 [12483] = 0x0006, [12484] = 0x0040, [12485] = 0x0001, [12486] = 0x000f,
96 [12487] = 0x0006, [12488] = 0x0001, [12489] = 0x0003, [12490] = 0x0106,
97 [12492] = 0x0061, [12493] = 0x0011, [12494] = 0x0401, [12496] = 0x0050,
98 [12497] = 0x0003, [12498] = 0x0102, [12500] = 0x0061, [12501] = 0x003b,
99 [12502] = 0x0502, [12503] = 0x0100, [12504] = 0x2fff, [12508] = 0x2fff,
100 [12512] = 0x2fff, [12516] = 0x2fff, [12520] = 0x2fff, [12524] = 0x2fff,
101 [12528] = 0x2fff, [12532] = 0x2fff, [12536] = 0x2fff, [12540] = 0x2fff,
102 [12544] = 0x0060, [12546] = 0x0601, [12548] = 0x0050, [12550] = 0x0100,
103 [12552] = 0x0001, [12554] = 0x0104, [12555] = 0x0100, [12556] = 0x2fff,
104 [12560] = 0x2fff, [12564] = 0x2fff, [12568] = 0x2fff, [12572] = 0x2fff,
105 [12576] = 0x2fff, [12580] = 0x2fff, [12584] = 0x2fff, [12588] = 0x2fff,
106 [12592] = 0x2fff, [12596] = 0x2fff, [12600] = 0x2fff, [12604] = 0x2fff,
107 [12608] = 0x0061, [12610] = 0x0601, [12612] = 0x0050, [12614] = 0x0102,
108 [12616] = 0x0001, [12618] = 0x0106, [12619] = 0x0100, [12620] = 0x2fff,
109 [12624] = 0x2fff, [12628] = 0x2fff, [12632] = 0x2fff, [12636] = 0x2fff,
110 [12640] = 0x2fff, [12644] = 0x2fff, [12648] = 0x2fff, [12652] = 0x2fff,
111 [12656] = 0x2fff, [12660] = 0x2fff, [12664] = 0x2fff, [12668] = 0x2fff,
112 [12672] = 0x0060, [12674] = 0x0601, [12676] = 0x0061, [12678] = 0x0601,
113 [12680] = 0x0050, [12682] = 0x0300, [12684] = 0x0001, [12686] = 0x0304,
114 [12688] = 0x0040, [12690] = 0x000f, [12692] = 0x0001, [12695] = 0x0100
115};
116
117struct fll_config {
118 int src;
119 int in;
120 int out;
121};
122
123struct wm8995_priv {
124 enum snd_soc_control_type control_type;
125 int sysclk[2];
126 int mclk[2];
127 int aifclk[2];
128 struct fll_config fll[2], fll_suspend[2];
129};
130
131static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
132static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0);
133static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0);
134static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
135
136static const char *in1l_text[] = {
137 "Differential", "Single-ended IN1LN", "Single-ended IN1LP"
138};
139
140static const SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
141 2, in1l_text);
142
143static const char *in1r_text[] = {
144 "Differential", "Single-ended IN1RN", "Single-ended IN1RP"
145};
146
147static const SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
148 0, in1r_text);
149
150static const char *dmic_src_text[] = {
151 "DMICDAT1", "DMICDAT2", "DMICDAT3"
152};
153
154static const SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5,
155 8, dmic_src_text);
156static const SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5,
157 6, dmic_src_text);
158
159static const struct snd_kcontrol_new wm8995_snd_controls[] = {
160 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME,
161 WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
162 SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME,
163 WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1),
164
165 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME,
166 WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
167 SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME,
168 WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1),
169
170 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME,
171 WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
172 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME,
173 WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
174 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME,
175 WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
176
177 SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME,
178 WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv),
179
180 SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL,
181 4, 3, 0, in1l_boost_tlv),
182
183 SOC_ENUM("IN1L Mode", in1l_enum),
184 SOC_ENUM("IN1R Mode", in1r_enum),
185
186 SOC_ENUM("DMIC1 SRC", dmic_src1_enum),
187 SOC_ENUM("DMIC2 SRC", dmic_src2_enum),
188
189 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5,
190 24, 0, sidetone_tlv),
191 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5,
192 24, 0, sidetone_tlv),
193
194 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME,
195 WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
196 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME,
197 WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
198 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME,
199 WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv)
200};
201
202static void wm8995_update_class_w(struct snd_soc_codec *codec)
203{
204 int enable = 1;
205 int source = 0; /* GCC flow analysis can't track enable */
206 int reg, reg_r;
207
208 /* We also need the same setting for L/R and only one path */
209 reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING);
210 switch (reg) {
211 case WM8995_AIF2DACL_TO_DAC1L:
212 dev_dbg(codec->dev, "Class W source AIF2DAC\n");
213 source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT;
214 break;
215 case WM8995_AIF1DAC2L_TO_DAC1L:
216 dev_dbg(codec->dev, "Class W source AIF1DAC2\n");
217 source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT;
218 break;
219 case WM8995_AIF1DAC1L_TO_DAC1L:
220 dev_dbg(codec->dev, "Class W source AIF1DAC1\n");
221 source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT;
222 break;
223 default:
224 dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg);
225 enable = 0;
226 break;
227 }
228
229 reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING);
230 if (reg_r != reg) {
231 dev_dbg(codec->dev, "Left and right DAC mixers different\n");
232 enable = 0;
233 }
234
235 if (enable) {
236 dev_dbg(codec->dev, "Class W enabled\n");
237 snd_soc_update_bits(codec, WM8995_CLASS_W_1,
238 WM8995_CP_DYN_PWR_MASK |
239 WM8995_CP_DYN_SRC_SEL_MASK,
240 source | WM8995_CP_DYN_PWR);
241 } else {
242 dev_dbg(codec->dev, "Class W disabled\n");
243 snd_soc_update_bits(codec, WM8995_CLASS_W_1,
244 WM8995_CP_DYN_PWR_MASK, 0);
245 }
246}
247
248static int check_clk_sys(struct snd_soc_dapm_widget *source,
249 struct snd_soc_dapm_widget *sink)
250{
251 unsigned int reg;
252 const char *clk;
253
254 reg = snd_soc_read(source->codec, WM8995_CLOCKING_1);
255 /* Check what we're currently using for CLK_SYS */
256 if (reg & WM8995_SYSCLK_SRC)
257 clk = "AIF2CLK";
258 else
259 clk = "AIF1CLK";
260 return !strcmp(source->name, clk);
261}
262
263static int wm8995_put_class_w(struct snd_kcontrol *kcontrol,
264 struct snd_ctl_elem_value *ucontrol)
265{
266 struct snd_soc_dapm_widget *w;
267 struct snd_soc_codec *codec;
268 int ret;
269
270 w = snd_kcontrol_chip(kcontrol);
271 codec = w->codec;
272 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
273 wm8995_update_class_w(codec);
274 return ret;
275}
276
277static int hp_supply_event(struct snd_soc_dapm_widget *w,
278 struct snd_kcontrol *kcontrol, int event)
279{
280 struct snd_soc_codec *codec;
281 struct wm8995_priv *wm8995;
282
283 codec = w->codec;
284 wm8995 = snd_soc_codec_get_drvdata(codec);
285
286 switch (event) {
287 case SND_SOC_DAPM_PRE_PMU:
288 /* Enable the headphone amp */
289 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
290 WM8995_HPOUT1L_ENA_MASK |
291 WM8995_HPOUT1R_ENA_MASK,
292 WM8995_HPOUT1L_ENA |
293 WM8995_HPOUT1R_ENA);
294
295 /* Enable the second stage */
296 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
297 WM8995_HPOUT1L_DLY_MASK |
298 WM8995_HPOUT1R_DLY_MASK,
299 WM8995_HPOUT1L_DLY |
300 WM8995_HPOUT1R_DLY);
301 break;
302 case SND_SOC_DAPM_PRE_PMD:
303 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1,
304 WM8995_CP_ENA_MASK, 0);
305 break;
306 }
307
308 return 0;
309}
310
311static void dc_servo_cmd(struct snd_soc_codec *codec,
312 unsigned int reg, unsigned int val, unsigned int mask)
313{
314 int timeout = 10;
315
316 dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n",
317 __func__, reg, val, mask);
318
319 snd_soc_write(codec, reg, val);
320 while (timeout--) {
321 msleep(10);
322 val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0);
323 if ((val & mask) == mask)
324 return;
325 }
326
327 dev_err(codec->dev, "Timed out waiting for DC Servo\n");
328}
329
330static int hp_event(struct snd_soc_dapm_widget *w,
331 struct snd_kcontrol *kcontrol, int event)
332{
333 struct snd_soc_codec *codec;
334 unsigned int reg;
335
336 codec = w->codec;
337 reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1);
338
339 switch (event) {
340 case SND_SOC_DAPM_POST_PMU:
341 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1,
342 WM8995_CP_ENA_MASK, WM8995_CP_ENA);
343
344 msleep(5);
345
346 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
347 WM8995_HPOUT1L_ENA_MASK |
348 WM8995_HPOUT1R_ENA_MASK,
349 WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA);
350
351 udelay(20);
352
353 reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY;
354 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg);
355
356 snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 |
357 WM8995_DCS_ENA_CHAN_1);
358
359 dc_servo_cmd(codec, WM8995_DC_SERVO_2,
360 WM8995_DCS_TRIG_STARTUP_0 |
361 WM8995_DCS_TRIG_STARTUP_1,
362 WM8995_DCS_TRIG_DAC_WR_0 |
363 WM8995_DCS_TRIG_DAC_WR_1);
364
365 reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT |
366 WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT;
367 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg);
368
369 break;
370 case SND_SOC_DAPM_PRE_PMD:
371 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
372 WM8995_HPOUT1L_OUTP_MASK |
373 WM8995_HPOUT1R_OUTP_MASK |
374 WM8995_HPOUT1L_RMV_SHORT_MASK |
375 WM8995_HPOUT1R_RMV_SHORT_MASK, 0);
376
377 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
378 WM8995_HPOUT1L_DLY_MASK |
379 WM8995_HPOUT1R_DLY_MASK, 0);
380
381 snd_soc_write(codec, WM8995_DC_SERVO_1, 0);
382
383 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
384 WM8995_HPOUT1L_ENA_MASK |
385 WM8995_HPOUT1R_ENA_MASK,
386 0);
387 break;
388 }
389
390 return 0;
391}
392
393static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
394{
395 struct wm8995_priv *wm8995;
396 int rate;
397 int reg1 = 0;
398 int offset;
399
400 wm8995 = snd_soc_codec_get_drvdata(codec);
401
402 if (aif)
403 offset = 4;
404 else
405 offset = 0;
406
407 switch (wm8995->sysclk[aif]) {
408 case WM8995_SYSCLK_MCLK1:
409 rate = wm8995->mclk[0];
410 break;
411 case WM8995_SYSCLK_MCLK2:
412 reg1 |= 0x8;
413 rate = wm8995->mclk[1];
414 break;
415 case WM8995_SYSCLK_FLL1:
416 reg1 |= 0x10;
417 rate = wm8995->fll[0].out;
418 break;
419 case WM8995_SYSCLK_FLL2:
420 reg1 |= 0x18;
421 rate = wm8995->fll[1].out;
422 break;
423 default:
424 return -EINVAL;
425 }
426
427 if (rate >= 13500000) {
428 rate /= 2;
429 reg1 |= WM8995_AIF1CLK_DIV;
430
431 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
432 aif + 1, rate);
433 }
434
435 wm8995->aifclk[aif] = rate;
436
437 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset,
438 WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK,
439 reg1);
440 return 0;
441}
442
443static int configure_clock(struct snd_soc_codec *codec)
444{
445 struct wm8995_priv *wm8995;
446 int old, new;
447
448 wm8995 = snd_soc_codec_get_drvdata(codec);
449
450 /* Bring up the AIF clocks first */
451 configure_aif_clock(codec, 0);
452 configure_aif_clock(codec, 1);
453
454 /*
455 * Then switch CLK_SYS over to the higher of them; a change
456 * can only happen as a result of a clocking change which can
457 * only be made outside of DAPM so we can safely redo the
458 * clocking.
459 */
460
461 /* If they're equal it doesn't matter which is used */
462 if (wm8995->aifclk[0] == wm8995->aifclk[1])
463 return 0;
464
465 if (wm8995->aifclk[0] < wm8995->aifclk[1])
466 new = WM8995_SYSCLK_SRC;
467 else
468 new = 0;
469
470 old = snd_soc_read(codec, WM8995_CLOCKING_1) & WM8995_SYSCLK_SRC;
471
472 /* If there's no change then we're done. */
473 if (old == new)
474 return 0;
475
476 snd_soc_update_bits(codec, WM8995_CLOCKING_1,
477 WM8995_SYSCLK_SRC_MASK, new);
478
479 snd_soc_dapm_sync(&codec->dapm);
480
481 return 0;
482}
483
484static int clk_sys_event(struct snd_soc_dapm_widget *w,
485 struct snd_kcontrol *kcontrol, int event)
486{
487 struct snd_soc_codec *codec;
488
489 codec = w->codec;
490
491 switch (event) {
492 case SND_SOC_DAPM_PRE_PMU:
493 return configure_clock(codec);
494
495 case SND_SOC_DAPM_POST_PMD:
496 configure_clock(codec);
497 break;
498 }
499
500 return 0;
501}
502
503static const char *sidetone_text[] = {
504 "ADC/DMIC1", "DMIC2",
505};
506
507static const struct soc_enum sidetone1_enum =
508 SOC_ENUM_SINGLE(WM8995_SIDETONE, 0, 2, sidetone_text);
509
510static const struct snd_kcontrol_new sidetone1_mux =
511 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
512
513static const struct soc_enum sidetone2_enum =
514 SOC_ENUM_SINGLE(WM8995_SIDETONE, 1, 2, sidetone_text);
515
516static const struct snd_kcontrol_new sidetone2_mux =
517 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
518
519static const struct snd_kcontrol_new aif1adc1l_mix[] = {
520 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
521 1, 1, 0),
522 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
523 0, 1, 0),
524};
525
526static const struct snd_kcontrol_new aif1adc1r_mix[] = {
527 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
528 1, 1, 0),
529 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
530 0, 1, 0),
531};
532
533static const struct snd_kcontrol_new aif1adc2l_mix[] = {
534 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
535 1, 1, 0),
536 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
537 0, 1, 0),
538};
539
540static const struct snd_kcontrol_new aif1adc2r_mix[] = {
541 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
542 1, 1, 0),
543 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
544 0, 1, 0),
545};
546
547static const struct snd_kcontrol_new dac1l_mix[] = {
548 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
549 5, 1, 0),
550 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
551 4, 1, 0),
552 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
553 2, 1, 0),
554 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
555 1, 1, 0),
556 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
557 0, 1, 0),
558};
559
560static const struct snd_kcontrol_new dac1r_mix[] = {
561 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
562 5, 1, 0),
563 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
564 4, 1, 0),
565 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
566 2, 1, 0),
567 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
568 1, 1, 0),
569 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
570 0, 1, 0),
571};
572
573static const struct snd_kcontrol_new aif2dac2l_mix[] = {
574 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
575 5, 1, 0),
576 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
577 4, 1, 0),
578 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
579 2, 1, 0),
580 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
581 1, 1, 0),
582 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
583 0, 1, 0),
584};
585
586static const struct snd_kcontrol_new aif2dac2r_mix[] = {
587 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
588 5, 1, 0),
589 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
590 4, 1, 0),
591 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
592 2, 1, 0),
593 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
594 1, 1, 0),
595 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
596 0, 1, 0),
597};
598
599static const struct snd_kcontrol_new in1l_pga =
600 SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0);
601
602static const struct snd_kcontrol_new in1r_pga =
603 SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0);
604
605static const char *adc_mux_text[] = {
606 "ADC",
607 "DMIC",
608};
609
610static const struct soc_enum adc_enum =
611 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
612
613static const struct snd_kcontrol_new adcl_mux =
614 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
615
616static const struct snd_kcontrol_new adcr_mux =
617 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
618
619static const char *spk_src_text[] = {
620 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
621};
622
623static const SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1,
624 0, spk_src_text);
625static const SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1,
626 0, spk_src_text);
627static const SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2,
628 0, spk_src_text);
629static const SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2,
630 0, spk_src_text);
631
632static const struct snd_kcontrol_new spk1l_mux =
633 SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum);
634static const struct snd_kcontrol_new spk1r_mux =
635 SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum);
636static const struct snd_kcontrol_new spk2l_mux =
637 SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum);
638static const struct snd_kcontrol_new spk2r_mux =
639 SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum);
640
641static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = {
642 SND_SOC_DAPM_INPUT("DMIC1DAT"),
643 SND_SOC_DAPM_INPUT("DMIC2DAT"),
644
645 SND_SOC_DAPM_INPUT("IN1L"),
646 SND_SOC_DAPM_INPUT("IN1R"),
647
648 SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0,
649 &in1l_pga, 1),
650 SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0,
651 &in1r_pga, 1),
652
653 SND_SOC_DAPM_MICBIAS("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0),
654 SND_SOC_DAPM_MICBIAS("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0),
655
656 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0),
657 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0),
658 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0),
659 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0),
660 SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0),
661 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
662 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
663
664 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0,
665 WM8995_POWER_MANAGEMENT_3, 9, 0),
666 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0,
667 WM8995_POWER_MANAGEMENT_3, 8, 0),
668 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0,
669 SND_SOC_NOPM, 0, 0),
670 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
671 0, WM8995_POWER_MANAGEMENT_3, 11, 0),
672 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
673 0, WM8995_POWER_MANAGEMENT_3, 10, 0),
674
675 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0,
676 &adcl_mux),
677 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
678 &adcr_mux),
679
680 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0),
681 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0),
682 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0),
683 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0),
684
685 SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0),
686 SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0),
687
688 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
689 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
690 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
691 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
692 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
693 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
694 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
695 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
696
697 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
698 9, 0),
699 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
700 8, 0),
701 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM,
702 0, 0),
703
704 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
705 11, 0),
706 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
707 10, 0),
708
709 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
710 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
711 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
712 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
713
714 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0),
715 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0),
716 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0),
717 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0),
718
719 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix,
720 ARRAY_SIZE(dac1l_mix)),
721 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix,
722 ARRAY_SIZE(dac1r_mix)),
723
724 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
725 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
726
727 SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
728 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
729
730 SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0,
731 hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
732
733 SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1,
734 4, 0, &spk1l_mux),
735 SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1,
736 4, 0, &spk1r_mux),
737 SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2,
738 4, 0, &spk2l_mux),
739 SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2,
740 4, 0, &spk2r_mux),
741
742 SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
743
744 SND_SOC_DAPM_OUTPUT("HP1L"),
745 SND_SOC_DAPM_OUTPUT("HP1R"),
746 SND_SOC_DAPM_OUTPUT("SPK1L"),
747 SND_SOC_DAPM_OUTPUT("SPK1R"),
748 SND_SOC_DAPM_OUTPUT("SPK2L"),
749 SND_SOC_DAPM_OUTPUT("SPK2R")
750};
751
752static const struct snd_soc_dapm_route wm8995_intercon[] = {
753 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
754 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
755
756 { "DSP1CLK", NULL, "CLK_SYS" },
757 { "DSP2CLK", NULL, "CLK_SYS" },
758 { "SYSDSPCLK", NULL, "CLK_SYS" },
759
760 { "AIF1ADC1L", NULL, "AIF1CLK" },
761 { "AIF1ADC1L", NULL, "DSP1CLK" },
762 { "AIF1ADC1R", NULL, "AIF1CLK" },
763 { "AIF1ADC1R", NULL, "DSP1CLK" },
764 { "AIF1ADC1R", NULL, "SYSDSPCLK" },
765
766 { "AIF1ADC2L", NULL, "AIF1CLK" },
767 { "AIF1ADC2L", NULL, "DSP1CLK" },
768 { "AIF1ADC2R", NULL, "AIF1CLK" },
769 { "AIF1ADC2R", NULL, "DSP1CLK" },
770 { "AIF1ADC2R", NULL, "SYSDSPCLK" },
771
772 { "DMIC1L", NULL, "DMIC1DAT" },
773 { "DMIC1L", NULL, "CLK_SYS" },
774 { "DMIC1R", NULL, "DMIC1DAT" },
775 { "DMIC1R", NULL, "CLK_SYS" },
776 { "DMIC2L", NULL, "DMIC2DAT" },
777 { "DMIC2L", NULL, "CLK_SYS" },
778 { "DMIC2R", NULL, "DMIC2DAT" },
779 { "DMIC2R", NULL, "CLK_SYS" },
780
781 { "ADCL", NULL, "AIF1CLK" },
782 { "ADCL", NULL, "DSP1CLK" },
783 { "ADCL", NULL, "SYSDSPCLK" },
784
785 { "ADCR", NULL, "AIF1CLK" },
786 { "ADCR", NULL, "DSP1CLK" },
787 { "ADCR", NULL, "SYSDSPCLK" },
788
789 { "IN1L PGA", "IN1L Switch", "IN1L" },
790 { "IN1R PGA", "IN1R Switch", "IN1R" },
791 { "IN1L PGA", NULL, "LDO2" },
792 { "IN1R PGA", NULL, "LDO2" },
793
794 { "ADCL", NULL, "IN1L PGA" },
795 { "ADCR", NULL, "IN1R PGA" },
796
797 { "ADCL Mux", "ADC", "ADCL" },
798 { "ADCL Mux", "DMIC", "DMIC1L" },
799 { "ADCR Mux", "ADC", "ADCR" },
800 { "ADCR Mux", "DMIC", "DMIC1R" },
801
802 /* AIF1 outputs */
803 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
804 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
805
806 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
807 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
808
809 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
810 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
811
812 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
813 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
814
815 /* Sidetone */
816 { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" },
817 { "Left Sidetone", "DMIC2", "AIF1ADC2L" },
818 { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" },
819 { "Right Sidetone", "DMIC2", "AIF1ADC2R" },
820
821 { "AIF1DAC1L", NULL, "AIF1CLK" },
822 { "AIF1DAC1L", NULL, "DSP1CLK" },
823 { "AIF1DAC1R", NULL, "AIF1CLK" },
824 { "AIF1DAC1R", NULL, "DSP1CLK" },
825 { "AIF1DAC1R", NULL, "SYSDSPCLK" },
826
827 { "AIF1DAC2L", NULL, "AIF1CLK" },
828 { "AIF1DAC2L", NULL, "DSP1CLK" },
829 { "AIF1DAC2R", NULL, "AIF1CLK" },
830 { "AIF1DAC2R", NULL, "DSP1CLK" },
831 { "AIF1DAC2R", NULL, "SYSDSPCLK" },
832
833 { "DAC1L", NULL, "AIF1CLK" },
834 { "DAC1L", NULL, "DSP1CLK" },
835 { "DAC1L", NULL, "SYSDSPCLK" },
836
837 { "DAC1R", NULL, "AIF1CLK" },
838 { "DAC1R", NULL, "DSP1CLK" },
839 { "DAC1R", NULL, "SYSDSPCLK" },
840
841 { "AIF1DAC1L", NULL, "AIF1DACDAT" },
842 { "AIF1DAC1R", NULL, "AIF1DACDAT" },
843 { "AIF1DAC2L", NULL, "AIF1DACDAT" },
844 { "AIF1DAC2R", NULL, "AIF1DACDAT" },
845
846 /* DAC1 inputs */
847 { "DAC1L", NULL, "DAC1L Mixer" },
848 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
849 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
850 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
851 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
852
853 { "DAC1R", NULL, "DAC1R Mixer" },
854 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
855 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
856 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
857 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
858
859 /* DAC2/AIF2 outputs */
860 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
861 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
862 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
863
864 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
865 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
866 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
867
868 /* Output stages */
869 { "Headphone PGA", NULL, "DAC1L" },
870 { "Headphone PGA", NULL, "DAC1R" },
871
872 { "Headphone PGA", NULL, "DAC2L" },
873 { "Headphone PGA", NULL, "DAC2R" },
874
875 { "Headphone PGA", NULL, "Headphone Supply" },
876 { "Headphone PGA", NULL, "CLK_SYS" },
877 { "Headphone PGA", NULL, "LDO2" },
878
879 { "HP1L", NULL, "Headphone PGA" },
880 { "HP1R", NULL, "Headphone PGA" },
881
882 { "SPK1L Driver", "DAC1L", "DAC1L" },
883 { "SPK1L Driver", "DAC1R", "DAC1R" },
884 { "SPK1L Driver", "DAC2L", "DAC2L" },
885 { "SPK1L Driver", "DAC2R", "DAC2R" },
886 { "SPK1L Driver", NULL, "CLK_SYS" },
887
888 { "SPK1R Driver", "DAC1L", "DAC1L" },
889 { "SPK1R Driver", "DAC1R", "DAC1R" },
890 { "SPK1R Driver", "DAC2L", "DAC2L" },
891 { "SPK1R Driver", "DAC2R", "DAC2R" },
892 { "SPK1R Driver", NULL, "CLK_SYS" },
893
894 { "SPK2L Driver", "DAC1L", "DAC1L" },
895 { "SPK2L Driver", "DAC1R", "DAC1R" },
896 { "SPK2L Driver", "DAC2L", "DAC2L" },
897 { "SPK2L Driver", "DAC2R", "DAC2R" },
898 { "SPK2L Driver", NULL, "CLK_SYS" },
899
900 { "SPK2R Driver", "DAC1L", "DAC1L" },
901 { "SPK2R Driver", "DAC1R", "DAC1R" },
902 { "SPK2R Driver", "DAC2L", "DAC2L" },
903 { "SPK2R Driver", "DAC2R", "DAC2R" },
904 { "SPK2R Driver", NULL, "CLK_SYS" },
905
906 { "SPK1L", NULL, "SPK1L Driver" },
907 { "SPK1R", NULL, "SPK1R Driver" },
908 { "SPK2L", NULL, "SPK2L Driver" },
909 { "SPK2R", NULL, "SPK2R Driver" }
910};
911
912static int wm8995_volatile(unsigned int reg)
913{
914 /* out of bounds registers are generally considered
915 * volatile to support register banks that are partially
916 * owned by something else for e.g. a DSP
917 */
918 if (reg > WM8995_MAX_CACHED_REGISTER)
919 return 1;
920
921 switch (reg) {
922 case WM8995_SOFTWARE_RESET:
923 case WM8995_DC_SERVO_READBACK_0:
924 case WM8995_INTERRUPT_STATUS_1:
925 case WM8995_INTERRUPT_STATUS_2:
926 case WM8995_INTERRUPT_STATUS_1_MASK:
927 case WM8995_INTERRUPT_STATUS_2_MASK:
928 case WM8995_INTERRUPT_CONTROL:
929 case WM8995_ACCESSORY_DETECT_MODE1:
930 case WM8995_ACCESSORY_DETECT_MODE2:
931 case WM8995_HEADPHONE_DETECT1:
932 case WM8995_HEADPHONE_DETECT2:
933 return 1;
934 }
935
936 return 0;
937}
938
939static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute)
940{
941 struct snd_soc_codec *codec = dai->codec;
942 int mute_reg;
943
944 switch (dai->id) {
945 case 0:
946 mute_reg = WM8995_AIF1_DAC1_FILTERS_1;
947 break;
948 case 1:
949 mute_reg = WM8995_AIF2_DAC_FILTERS_1;
950 break;
951 default:
952 return -EINVAL;
953 }
954
955 snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK,
956 !!mute << WM8995_AIF1DAC1_MUTE_SHIFT);
957 return 0;
958}
959
960static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
961{
962 struct snd_soc_codec *codec;
963 int master;
964 int aif;
965
966 codec = dai->codec;
967
968 master = 0;
969 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
970 case SND_SOC_DAIFMT_CBS_CFS:
971 break;
972 case SND_SOC_DAIFMT_CBM_CFM:
973 master = WM8995_AIF1_MSTR;
974 break;
975 default:
976 dev_err(dai->dev, "Unknown master/slave configuration\n");
977 return -EINVAL;
978 }
979
980 aif = 0;
981 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
982 case SND_SOC_DAIFMT_DSP_B:
983 aif |= WM8995_AIF1_LRCLK_INV;
984 case SND_SOC_DAIFMT_DSP_A:
985 aif |= (0x3 << WM8995_AIF1_FMT_SHIFT);
986 break;
987 case SND_SOC_DAIFMT_I2S:
988 aif |= (0x2 << WM8995_AIF1_FMT_SHIFT);
989 break;
990 case SND_SOC_DAIFMT_RIGHT_J:
991 break;
992 case SND_SOC_DAIFMT_LEFT_J:
993 aif |= (0x1 << WM8995_AIF1_FMT_SHIFT);
994 break;
995 default:
996 dev_err(dai->dev, "Unknown dai format\n");
997 return -EINVAL;
998 }
999
1000 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1001 case SND_SOC_DAIFMT_DSP_A:
1002 case SND_SOC_DAIFMT_DSP_B:
1003 /* frame inversion not valid for DSP modes */
1004 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1005 case SND_SOC_DAIFMT_NB_NF:
1006 break;
1007 case SND_SOC_DAIFMT_IB_NF:
1008 aif |= WM8995_AIF1_BCLK_INV;
1009 break;
1010 default:
1011 return -EINVAL;
1012 }
1013 break;
1014
1015 case SND_SOC_DAIFMT_I2S:
1016 case SND_SOC_DAIFMT_RIGHT_J:
1017 case SND_SOC_DAIFMT_LEFT_J:
1018 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1019 case SND_SOC_DAIFMT_NB_NF:
1020 break;
1021 case SND_SOC_DAIFMT_IB_IF:
1022 aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV;
1023 break;
1024 case SND_SOC_DAIFMT_IB_NF:
1025 aif |= WM8995_AIF1_BCLK_INV;
1026 break;
1027 case SND_SOC_DAIFMT_NB_IF:
1028 aif |= WM8995_AIF1_LRCLK_INV;
1029 break;
1030 default:
1031 return -EINVAL;
1032 }
1033 break;
1034 default:
1035 return -EINVAL;
1036 }
1037
1038 snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1,
1039 WM8995_AIF1_BCLK_INV_MASK |
1040 WM8995_AIF1_LRCLK_INV_MASK |
1041 WM8995_AIF1_FMT_MASK, aif);
1042 snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE,
1043 WM8995_AIF1_MSTR_MASK, master);
1044 return 0;
1045}
1046
1047static const int srs[] = {
1048 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100,
1049 48000, 88200, 96000
1050};
1051
1052static const int fs_ratios[] = {
1053 -1 /* reserved */,
1054 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
1055};
1056
1057static const int bclk_divs[] = {
1058 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480
1059};
1060
1061static int wm8995_hw_params(struct snd_pcm_substream *substream,
1062 struct snd_pcm_hw_params *params,
1063 struct snd_soc_dai *dai)
1064{
1065 struct snd_soc_codec *codec;
1066 struct wm8995_priv *wm8995;
1067 int aif1_reg;
1068 int bclk_reg;
1069 int lrclk_reg;
1070 int rate_reg;
1071 int bclk_rate;
1072 int aif1;
1073 int lrclk, bclk;
1074 int i, rate_val, best, best_val, cur_val;
1075
1076 codec = dai->codec;
1077 wm8995 = snd_soc_codec_get_drvdata(codec);
1078
1079 switch (dai->id) {
1080 case 0:
1081 aif1_reg = WM8995_AIF1_CONTROL_1;
1082 bclk_reg = WM8995_AIF1_BCLK;
1083 rate_reg = WM8995_AIF1_RATE;
1084 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1085 wm8995->lrclk_shared[0] */) {
1086 lrclk_reg = WM8995_AIF1DAC_LRCLK;
1087 } else {
1088 lrclk_reg = WM8995_AIF1ADC_LRCLK;
1089 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
1090 }
1091 break;
1092 case 1:
1093 aif1_reg = WM8995_AIF2_CONTROL_1;
1094 bclk_reg = WM8995_AIF2_BCLK;
1095 rate_reg = WM8995_AIF2_RATE;
1096 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1097 wm8995->lrclk_shared[1] */) {
1098 lrclk_reg = WM8995_AIF2DAC_LRCLK;
1099 } else {
1100 lrclk_reg = WM8995_AIF2ADC_LRCLK;
1101 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
1102 }
1103 break;
1104 default:
1105 return -EINVAL;
1106 }
1107
1108 bclk_rate = snd_soc_params_to_bclk(params);
1109 if (bclk_rate < 0)
1110 return bclk_rate;
1111
1112 aif1 = 0;
1113 switch (params_format(params)) {
1114 case SNDRV_PCM_FORMAT_S16_LE:
1115 break;
1116 case SNDRV_PCM_FORMAT_S20_3LE:
1117 aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT);
1118 break;
1119 case SNDRV_PCM_FORMAT_S24_LE:
1120 aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT);
1121 break;
1122 case SNDRV_PCM_FORMAT_S32_LE:
1123 aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT);
1124 break;
1125 default:
1126 dev_err(dai->dev, "Unsupported word length %u\n",
1127 params_format(params));
1128 return -EINVAL;
1129 }
1130
1131 /* try to find a suitable sample rate */
1132 for (i = 0; i < ARRAY_SIZE(srs); ++i)
1133 if (srs[i] == params_rate(params))
1134 break;
1135 if (i == ARRAY_SIZE(srs)) {
1136 dev_err(dai->dev, "Sample rate %d is not supported\n",
1137 params_rate(params));
1138 return -EINVAL;
1139 }
1140 rate_val = i << WM8995_AIF1_SR_SHIFT;
1141
1142 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]);
1143 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
1144 dai->id + 1, wm8995->aifclk[dai->id], bclk_rate);
1145
1146 /* AIFCLK/fs ratio; look for a close match in either direction */
1147 best = 1;
1148 best_val = abs((fs_ratios[1] * params_rate(params))
1149 - wm8995->aifclk[dai->id]);
1150 for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) {
1151 cur_val = abs((fs_ratios[i] * params_rate(params))
1152 - wm8995->aifclk[dai->id]);
1153 if (cur_val >= best_val)
1154 continue;
1155 best = i;
1156 best_val = cur_val;
1157 }
1158 rate_val |= best;
1159
1160 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
1161 dai->id + 1, fs_ratios[best]);
1162
1163 /*
1164 * We may not get quite the right frequency if using
1165 * approximate clocks so look for the closest match that is
1166 * higher than the target (we need to ensure that there enough
1167 * BCLKs to clock out the samples).
1168 */
1169 best = 0;
1170 bclk = 0;
1171 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1172 cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate;
1173 if (cur_val < 0) /* BCLK table is sorted */
1174 break;
1175 best = i;
1176 }
1177 bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT;
1178
1179 bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best];
1180 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1181 bclk_divs[best], bclk_rate);
1182
1183 lrclk = bclk_rate / params_rate(params);
1184 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1185 lrclk, bclk_rate / lrclk);
1186
1187 snd_soc_update_bits(codec, aif1_reg,
1188 WM8995_AIF1_WL_MASK, aif1);
1189 snd_soc_update_bits(codec, bclk_reg,
1190 WM8995_AIF1_BCLK_DIV_MASK, bclk);
1191 snd_soc_update_bits(codec, lrclk_reg,
1192 WM8995_AIF1DAC_RATE_MASK, lrclk);
1193 snd_soc_update_bits(codec, rate_reg,
1194 WM8995_AIF1_SR_MASK |
1195 WM8995_AIF1CLK_RATE_MASK, rate_val);
1196 return 0;
1197}
1198
1199static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
1200{
1201 struct snd_soc_codec *codec = codec_dai->codec;
1202 int reg, val, mask;
1203
1204 switch (codec_dai->id) {
1205 case 0:
1206 reg = WM8995_AIF1_MASTER_SLAVE;
1207 mask = WM8995_AIF1_TRI;
1208 break;
1209 case 1:
1210 reg = WM8995_AIF2_MASTER_SLAVE;
1211 mask = WM8995_AIF2_TRI;
1212 break;
1213 case 2:
1214 reg = WM8995_POWER_MANAGEMENT_5;
1215 mask = WM8995_AIF3_TRI;
1216 break;
1217 default:
1218 return -EINVAL;
1219 }
1220
1221 if (tristate)
1222 val = mask;
1223 else
1224 val = 0;
1225
1226 return snd_soc_update_bits(codec, reg, mask, reg);
1227}
1228
1229/* The size in bits of the FLL divide multiplied by 10
1230 * to allow rounding later */
1231#define FIXED_FLL_SIZE ((1 << 16) * 10)
1232
1233struct fll_div {
1234 u16 outdiv;
1235 u16 n;
1236 u16 k;
1237 u16 clk_ref_div;
1238 u16 fll_fratio;
1239};
1240
1241static int wm8995_get_fll_config(struct fll_div *fll,
1242 int freq_in, int freq_out)
1243{
1244 u64 Kpart;
1245 unsigned int K, Ndiv, Nmod;
1246
1247 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1248
1249 /* Scale the input frequency down to <= 13.5MHz */
1250 fll->clk_ref_div = 0;
1251 while (freq_in > 13500000) {
1252 fll->clk_ref_div++;
1253 freq_in /= 2;
1254
1255 if (fll->clk_ref_div > 3)
1256 return -EINVAL;
1257 }
1258 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1259
1260 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1261 fll->outdiv = 3;
1262 while (freq_out * (fll->outdiv + 1) < 90000000) {
1263 fll->outdiv++;
1264 if (fll->outdiv > 63)
1265 return -EINVAL;
1266 }
1267 freq_out *= fll->outdiv + 1;
1268 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1269
1270 if (freq_in > 1000000) {
1271 fll->fll_fratio = 0;
1272 } else if (freq_in > 256000) {
1273 fll->fll_fratio = 1;
1274 freq_in *= 2;
1275 } else if (freq_in > 128000) {
1276 fll->fll_fratio = 2;
1277 freq_in *= 4;
1278 } else if (freq_in > 64000) {
1279 fll->fll_fratio = 3;
1280 freq_in *= 8;
1281 } else {
1282 fll->fll_fratio = 4;
1283 freq_in *= 16;
1284 }
1285 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1286
1287 /* Now, calculate N.K */
1288 Ndiv = freq_out / freq_in;
1289
1290 fll->n = Ndiv;
1291 Nmod = freq_out % freq_in;
1292 pr_debug("Nmod=%d\n", Nmod);
1293
1294 /* Calculate fractional part - scale up so we can round. */
1295 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1296
1297 do_div(Kpart, freq_in);
1298
1299 K = Kpart & 0xFFFFFFFF;
1300
1301 if ((K % 10) >= 5)
1302 K += 5;
1303
1304 /* Move down to proper range now rounding is done */
1305 fll->k = K / 10;
1306
1307 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1308
1309 return 0;
1310}
1311
1312static int wm8995_set_fll(struct snd_soc_dai *dai, int id,
1313 int src, unsigned int freq_in,
1314 unsigned int freq_out)
1315{
1316 struct snd_soc_codec *codec;
1317 struct wm8995_priv *wm8995;
1318 int reg_offset, ret;
1319 struct fll_div fll;
1320 u16 reg, aif1, aif2;
1321
1322 codec = dai->codec;
1323 wm8995 = snd_soc_codec_get_drvdata(codec);
1324
1325 aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1)
1326 & WM8995_AIF1CLK_ENA;
1327
1328 aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1)
1329 & WM8995_AIF2CLK_ENA;
1330
1331 switch (id) {
1332 case WM8995_FLL1:
1333 reg_offset = 0;
1334 id = 0;
1335 break;
1336 case WM8995_FLL2:
1337 reg_offset = 0x20;
1338 id = 1;
1339 break;
1340 default:
1341 return -EINVAL;
1342 }
1343
1344 switch (src) {
1345 case 0:
1346 /* Allow no source specification when stopping */
1347 if (freq_out)
1348 return -EINVAL;
1349 break;
1350 case WM8995_FLL_SRC_MCLK1:
1351 case WM8995_FLL_SRC_MCLK2:
1352 case WM8995_FLL_SRC_LRCLK:
1353 case WM8995_FLL_SRC_BCLK:
1354 break;
1355 default:
1356 return -EINVAL;
1357 }
1358
1359 /* Are we changing anything? */
1360 if (wm8995->fll[id].src == src &&
1361 wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out)
1362 return 0;
1363
1364 /* If we're stopping the FLL redo the old config - no
1365 * registers will actually be written but we avoid GCC flow
1366 * analysis bugs spewing warnings.
1367 */
1368 if (freq_out)
1369 ret = wm8995_get_fll_config(&fll, freq_in, freq_out);
1370 else
1371 ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in,
1372 wm8995->fll[id].out);
1373 if (ret < 0)
1374 return ret;
1375
1376 /* Gate the AIF clocks while we reclock */
1377 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1,
1378 WM8995_AIF1CLK_ENA_MASK, 0);
1379 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1,
1380 WM8995_AIF2CLK_ENA_MASK, 0);
1381
1382 /* We always need to disable the FLL while reconfiguring */
1383 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset,
1384 WM8995_FLL1_ENA_MASK, 0);
1385
1386 reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) |
1387 (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT);
1388 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset,
1389 WM8995_FLL1_OUTDIV_MASK |
1390 WM8995_FLL1_FRATIO_MASK, reg);
1391
1392 snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
1393
1394 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset,
1395 WM8995_FLL1_N_MASK,
1396 fll.n << WM8995_FLL1_N_SHIFT);
1397
1398 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset,
1399 WM8995_FLL1_REFCLK_DIV_MASK |
1400 WM8995_FLL1_REFCLK_SRC_MASK,
1401 (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) |
1402 (src - 1));
1403
1404 if (freq_out)
1405 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset,
1406 WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA);
1407
1408 wm8995->fll[id].in = freq_in;
1409 wm8995->fll[id].out = freq_out;
1410 wm8995->fll[id].src = src;
1411
1412 /* Enable any gated AIF clocks */
1413 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1,
1414 WM8995_AIF1CLK_ENA_MASK, aif1);
1415 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1,
1416 WM8995_AIF2CLK_ENA_MASK, aif2);
1417
1418 configure_clock(codec);
1419
1420 return 0;
1421}
1422
1423static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai,
1424 int clk_id, unsigned int freq, int dir)
1425{
1426 struct snd_soc_codec *codec;
1427 struct wm8995_priv *wm8995;
1428
1429 codec = dai->codec;
1430 wm8995 = snd_soc_codec_get_drvdata(codec);
1431
1432 switch (dai->id) {
1433 case 0:
1434 case 1:
1435 break;
1436 default:
1437 /* AIF3 shares clocking with AIF1/2 */
1438 return -EINVAL;
1439 }
1440
1441 switch (clk_id) {
1442 case WM8995_SYSCLK_MCLK1:
1443 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
1444 wm8995->mclk[0] = freq;
1445 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1446 dai->id + 1, freq);
1447 break;
1448 case WM8995_SYSCLK_MCLK2:
1449 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
1450 wm8995->mclk[1] = freq;
1451 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1452 dai->id + 1, freq);
1453 break;
1454 case WM8995_SYSCLK_FLL1:
1455 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1;
1456 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1);
1457 break;
1458 case WM8995_SYSCLK_FLL2:
1459 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2;
1460 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1);
1461 break;
1462 case WM8995_SYSCLK_OPCLK:
1463 default:
1464 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
1465 return -EINVAL;
1466 }
1467
1468 configure_clock(codec);
1469
1470 return 0;
1471}
1472
1473static int wm8995_set_bias_level(struct snd_soc_codec *codec,
1474 enum snd_soc_bias_level level)
1475{
1476 struct wm8995_priv *wm8995;
1477 int ret;
1478
1479 wm8995 = snd_soc_codec_get_drvdata(codec);
1480 switch (level) {
1481 case SND_SOC_BIAS_ON:
1482 case SND_SOC_BIAS_PREPARE:
1483 break;
1484 case SND_SOC_BIAS_STANDBY:
1485 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1486 ret = snd_soc_cache_sync(codec);
1487 if (ret) {
1488 dev_err(codec->dev,
1489 "Failed to sync cache: %d\n", ret);
1490 return ret;
1491 }
1492
1493 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
1494 WM8995_BG_ENA_MASK, WM8995_BG_ENA);
1495
1496 }
1497 break;
1498 case SND_SOC_BIAS_OFF:
1499 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
1500 WM8995_BG_ENA_MASK, 0);
1501 break;
1502 }
1503
1504 codec->dapm.bias_level = level;
1505 return 0;
1506}
1507
1508#ifdef CONFIG_PM
1509static int wm8995_suspend(struct snd_soc_codec *codec, pm_message_t state)
1510{
1511 wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF);
1512 return 0;
1513}
1514
1515static int wm8995_resume(struct snd_soc_codec *codec)
1516{
1517 wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1518 return 0;
1519}
1520#else
1521#define wm8995_suspend NULL
1522#define wm8995_resume NULL
1523#endif
1524
1525static int wm8995_remove(struct snd_soc_codec *codec)
1526{
1527 struct wm8995_priv *wm8995;
1528 struct i2c_client *i2c;
1529
1530 i2c = container_of(codec->dev, struct i2c_client, dev);
1531 wm8995 = snd_soc_codec_get_drvdata(codec);
1532 wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF);
1533 return 0;
1534}
1535
1536static int wm8995_probe(struct snd_soc_codec *codec)
1537{
1538 struct wm8995_priv *wm8995;
1539 int ret;
1540
1541 codec->dapm.idle_bias_off = 1;
1542 wm8995 = snd_soc_codec_get_drvdata(codec);
1543
1544 ret = snd_soc_codec_set_cache_io(codec, 16, 16, wm8995->control_type);
1545 if (ret < 0) {
1546 dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
1547 return ret;
1548 }
1549
1550 ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET);
1551 if (ret < 0) {
1552 dev_err(codec->dev, "Failed to read device ID: %d\n", ret);
1553 return ret;
1554 }
1555
1556 if (ret != 0x8995) {
1557 dev_err(codec->dev, "Invalid device ID: %#x\n", ret);
1558 return -EINVAL;
1559 }
1560
1561 ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0);
1562 if (ret < 0) {
1563 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1564 return ret;
1565 }
1566
1567 wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1568
1569 /* Latch volume updates (right only; we always do left then right). */
1570 snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME,
1571 WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU);
1572 snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME,
1573 WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU);
1574 snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME,
1575 WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU);
1576 snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME,
1577 WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU);
1578 snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME,
1579 WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU);
1580 snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME,
1581 WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU);
1582 snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME,
1583 WM8995_DAC1_VU_MASK, WM8995_DAC1_VU);
1584 snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME,
1585 WM8995_DAC2_VU_MASK, WM8995_DAC2_VU);
1586 snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME,
1587 WM8995_IN1_VU_MASK, WM8995_IN1_VU);
1588
1589 wm8995_update_class_w(codec);
1590
1591 snd_soc_add_controls(codec, wm8995_snd_controls,
1592 ARRAY_SIZE(wm8995_snd_controls));
1593 snd_soc_dapm_new_controls(&codec->dapm, wm8995_dapm_widgets,
1594 ARRAY_SIZE(wm8995_dapm_widgets));
1595 snd_soc_dapm_add_routes(&codec->dapm, wm8995_intercon,
1596 ARRAY_SIZE(wm8995_intercon));
1597
1598 return 0;
1599}
1600
1601#define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1602 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1603
1604static struct snd_soc_dai_ops wm8995_aif1_dai_ops = {
1605 .set_sysclk = wm8995_set_dai_sysclk,
1606 .set_fmt = wm8995_set_dai_fmt,
1607 .hw_params = wm8995_hw_params,
1608 .digital_mute = wm8995_aif_mute,
1609 .set_pll = wm8995_set_fll,
1610 .set_tristate = wm8995_set_tristate,
1611};
1612
1613static struct snd_soc_dai_ops wm8995_aif2_dai_ops = {
1614 .set_sysclk = wm8995_set_dai_sysclk,
1615 .set_fmt = wm8995_set_dai_fmt,
1616 .hw_params = wm8995_hw_params,
1617 .digital_mute = wm8995_aif_mute,
1618 .set_pll = wm8995_set_fll,
1619 .set_tristate = wm8995_set_tristate,
1620};
1621
1622static struct snd_soc_dai_ops wm8995_aif3_dai_ops = {
1623 .set_tristate = wm8995_set_tristate,
1624};
1625
1626static struct snd_soc_dai_driver wm8995_dai[] = {
1627 {
1628 .name = "wm8995-aif1",
1629 .playback = {
1630 .stream_name = "AIF1 Playback",
1631 .channels_min = 2,
1632 .channels_max = 2,
1633 .rates = SNDRV_PCM_RATE_8000_96000,
1634 .formats = WM8995_FORMATS
1635 },
1636 .capture = {
1637 .stream_name = "AIF1 Capture",
1638 .channels_min = 2,
1639 .channels_max = 2,
1640 .rates = SNDRV_PCM_RATE_8000_48000,
1641 .formats = WM8995_FORMATS
1642 },
1643 .ops = &wm8995_aif1_dai_ops
1644 },
1645 {
1646 .name = "wm8995-aif2",
1647 .playback = {
1648 .stream_name = "AIF2 Playback",
1649 .channels_min = 2,
1650 .channels_max = 2,
1651 .rates = SNDRV_PCM_RATE_8000_96000,
1652 .formats = WM8995_FORMATS
1653 },
1654 .capture = {
1655 .stream_name = "AIF2 Capture",
1656 .channels_min = 2,
1657 .channels_max = 2,
1658 .rates = SNDRV_PCM_RATE_8000_48000,
1659 .formats = WM8995_FORMATS
1660 },
1661 .ops = &wm8995_aif2_dai_ops
1662 },
1663 {
1664 .name = "wm8995-aif3",
1665 .playback = {
1666 .stream_name = "AIF3 Playback",
1667 .channels_min = 2,
1668 .channels_max = 2,
1669 .rates = SNDRV_PCM_RATE_8000_96000,
1670 .formats = WM8995_FORMATS
1671 },
1672 .capture = {
1673 .stream_name = "AIF3 Capture",
1674 .channels_min = 2,
1675 .channels_max = 2,
1676 .rates = SNDRV_PCM_RATE_8000_48000,
1677 .formats = WM8995_FORMATS
1678 },
1679 .ops = &wm8995_aif3_dai_ops
1680 }
1681};
1682
1683static struct snd_soc_codec_driver soc_codec_dev_wm8995 = {
1684 .probe = wm8995_probe,
1685 .remove = wm8995_remove,
1686 .suspend = wm8995_suspend,
1687 .resume = wm8995_resume,
1688 .set_bias_level = wm8995_set_bias_level,
1689 .reg_cache_size = ARRAY_SIZE(wm8995_reg_defs),
1690 .reg_word_size = sizeof(u16),
1691 .reg_cache_default = wm8995_reg_defs,
1692 .volatile_register = wm8995_volatile,
1693 .compress_type = SND_SOC_RBTREE_COMPRESSION
1694};
1695
1696#if defined(CONFIG_SPI_MASTER)
1697static int __devinit wm8995_spi_probe(struct spi_device *spi)
1698{
1699 struct wm8995_priv *wm8995;
1700 int ret;
1701
1702 wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL);
1703 if (!wm8995)
1704 return -ENOMEM;
1705
1706 wm8995->control_type = SND_SOC_SPI;
1707 spi_set_drvdata(spi, wm8995);
1708
1709 ret = snd_soc_register_codec(&spi->dev,
1710 &soc_codec_dev_wm8995, wm8995_dai,
1711 ARRAY_SIZE(wm8995_dai));
1712 if (ret < 0)
1713 kfree(wm8995);
1714 return ret;
1715}
1716
1717static int __devexit wm8995_spi_remove(struct spi_device *spi)
1718{
1719 snd_soc_unregister_codec(&spi->dev);
1720 kfree(spi_get_drvdata(spi));
1721 return 0;
1722}
1723
1724static struct spi_driver wm8995_spi_driver = {
1725 .driver = {
1726 .name = "wm8995",
1727 .owner = THIS_MODULE,
1728 },
1729 .probe = wm8995_spi_probe,
1730 .remove = __devexit_p(wm8995_spi_remove)
1731};
1732#endif
1733
1734#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1735static __devinit int wm8995_i2c_probe(struct i2c_client *i2c,
1736 const struct i2c_device_id *id)
1737{
1738 struct wm8995_priv *wm8995;
1739 int ret;
1740
1741 wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL);
1742 if (!wm8995)
1743 return -ENOMEM;
1744
1745 wm8995->control_type = SND_SOC_I2C;
1746 i2c_set_clientdata(i2c, wm8995);
1747
1748 ret = snd_soc_register_codec(&i2c->dev,
1749 &soc_codec_dev_wm8995, wm8995_dai,
1750 ARRAY_SIZE(wm8995_dai));
1751 if (ret < 0)
1752 kfree(wm8995);
1753 return ret;
1754}
1755
1756static __devexit int wm8995_i2c_remove(struct i2c_client *client)
1757{
1758 snd_soc_unregister_codec(&client->dev);
1759 kfree(i2c_get_clientdata(client));
1760 return 0;
1761}
1762
1763static const struct i2c_device_id wm8995_i2c_id[] = {
1764 {"wm8995", 0},
1765 {}
1766};
1767
1768MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id);
1769
1770static struct i2c_driver wm8995_i2c_driver = {
1771 .driver = {
1772 .name = "wm8995",
1773 .owner = THIS_MODULE,
1774 },
1775 .probe = wm8995_i2c_probe,
1776 .remove = __devexit_p(wm8995_i2c_remove),
1777 .id_table = wm8995_i2c_id
1778};
1779#endif
1780
1781static int __init wm8995_modinit(void)
1782{
1783 int ret = 0;
1784
1785#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1786 ret = i2c_add_driver(&wm8995_i2c_driver);
1787 if (ret) {
1788 printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n",
1789 ret);
1790 }
1791#endif
1792#if defined(CONFIG_SPI_MASTER)
1793 ret = spi_register_driver(&wm8995_spi_driver);
1794 if (ret) {
1795 printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n",
1796 ret);
1797 }
1798#endif
1799 return ret;
1800}
1801
1802module_init(wm8995_modinit);
1803
1804static void __exit wm8995_exit(void)
1805{
1806#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1807 i2c_del_driver(&wm8995_i2c_driver);
1808#endif
1809#if defined(CONFIG_SPI_MASTER)
1810 spi_unregister_driver(&wm8995_spi_driver);
1811#endif
1812}
1813
1814module_exit(wm8995_exit);
1815
1816MODULE_DESCRIPTION("ASoC WM8995 driver");
1817MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1818MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8995.h b/sound/soc/codecs/wm8995.h
new file mode 100644
index 00000000000..5642121c497
--- /dev/null
+++ b/sound/soc/codecs/wm8995.h
@@ -0,0 +1,4269 @@
1/*
2 * wm8995.h -- WM8995 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _WM8995_H
14#define _WM8995_H
15
16#include <asm/types.h>
17
18/*
19 * Register values.
20 */
21#define WM8995_SOFTWARE_RESET 0x00
22#define WM8995_POWER_MANAGEMENT_1 0x01
23#define WM8995_POWER_MANAGEMENT_2 0x02
24#define WM8995_POWER_MANAGEMENT_3 0x03
25#define WM8995_POWER_MANAGEMENT_4 0x04
26#define WM8995_POWER_MANAGEMENT_5 0x05
27#define WM8995_LEFT_LINE_INPUT_1_VOLUME 0x10
28#define WM8995_RIGHT_LINE_INPUT_1_VOLUME 0x11
29#define WM8995_LEFT_LINE_INPUT_CONTROL 0x12
30#define WM8995_DAC1_LEFT_VOLUME 0x18
31#define WM8995_DAC1_RIGHT_VOLUME 0x19
32#define WM8995_DAC2_LEFT_VOLUME 0x1A
33#define WM8995_DAC2_RIGHT_VOLUME 0x1B
34#define WM8995_OUTPUT_VOLUME_ZC_1 0x1C
35#define WM8995_MICBIAS_1 0x20
36#define WM8995_MICBIAS_2 0x21
37#define WM8995_LDO_1 0x28
38#define WM8995_LDO_2 0x29
39#define WM8995_ACCESSORY_DETECT_MODE1 0x30
40#define WM8995_ACCESSORY_DETECT_MODE2 0x31
41#define WM8995_HEADPHONE_DETECT1 0x34
42#define WM8995_HEADPHONE_DETECT2 0x35
43#define WM8995_MIC_DETECT_1 0x38
44#define WM8995_MIC_DETECT_2 0x39
45#define WM8995_CHARGE_PUMP_1 0x40
46#define WM8995_CLASS_W_1 0x45
47#define WM8995_DC_SERVO_1 0x50
48#define WM8995_DC_SERVO_2 0x51
49#define WM8995_DC_SERVO_3 0x52
50#define WM8995_DC_SERVO_5 0x54
51#define WM8995_DC_SERVO_6 0x55
52#define WM8995_DC_SERVO_7 0x56
53#define WM8995_DC_SERVO_READBACK_0 0x57
54#define WM8995_ANALOGUE_HP_1 0x60
55#define WM8995_ANALOGUE_HP_2 0x61
56#define WM8995_CHIP_REVISION 0x100
57#define WM8995_CONTROL_INTERFACE_1 0x101
58#define WM8995_CONTROL_INTERFACE_2 0x102
59#define WM8995_WRITE_SEQUENCER_CTRL_1 0x110
60#define WM8995_WRITE_SEQUENCER_CTRL_2 0x111
61#define WM8995_AIF1_CLOCKING_1 0x200
62#define WM8995_AIF1_CLOCKING_2 0x201
63#define WM8995_AIF2_CLOCKING_1 0x204
64#define WM8995_AIF2_CLOCKING_2 0x205
65#define WM8995_CLOCKING_1 0x208
66#define WM8995_CLOCKING_2 0x209
67#define WM8995_AIF1_RATE 0x210
68#define WM8995_AIF2_RATE 0x211
69#define WM8995_RATE_STATUS 0x212
70#define WM8995_FLL1_CONTROL_1 0x220
71#define WM8995_FLL1_CONTROL_2 0x221
72#define WM8995_FLL1_CONTROL_3 0x222
73#define WM8995_FLL1_CONTROL_4 0x223
74#define WM8995_FLL1_CONTROL_5 0x224
75#define WM8995_FLL2_CONTROL_1 0x240
76#define WM8995_FLL2_CONTROL_2 0x241
77#define WM8995_FLL2_CONTROL_3 0x242
78#define WM8995_FLL2_CONTROL_4 0x243
79#define WM8995_FLL2_CONTROL_5 0x244
80#define WM8995_AIF1_CONTROL_1 0x300
81#define WM8995_AIF1_CONTROL_2 0x301
82#define WM8995_AIF1_MASTER_SLAVE 0x302
83#define WM8995_AIF1_BCLK 0x303
84#define WM8995_AIF1ADC_LRCLK 0x304
85#define WM8995_AIF1DAC_LRCLK 0x305
86#define WM8995_AIF1DAC_DATA 0x306
87#define WM8995_AIF1ADC_DATA 0x307
88#define WM8995_AIF2_CONTROL_1 0x310
89#define WM8995_AIF2_CONTROL_2 0x311
90#define WM8995_AIF2_MASTER_SLAVE 0x312
91#define WM8995_AIF2_BCLK 0x313
92#define WM8995_AIF2ADC_LRCLK 0x314
93#define WM8995_AIF2DAC_LRCLK 0x315
94#define WM8995_AIF2DAC_DATA 0x316
95#define WM8995_AIF2ADC_DATA 0x317
96#define WM8995_AIF1_ADC1_LEFT_VOLUME 0x400
97#define WM8995_AIF1_ADC1_RIGHT_VOLUME 0x401
98#define WM8995_AIF1_DAC1_LEFT_VOLUME 0x402
99#define WM8995_AIF1_DAC1_RIGHT_VOLUME 0x403
100#define WM8995_AIF1_ADC2_LEFT_VOLUME 0x404
101#define WM8995_AIF1_ADC2_RIGHT_VOLUME 0x405
102#define WM8995_AIF1_DAC2_LEFT_VOLUME 0x406
103#define WM8995_AIF1_DAC2_RIGHT_VOLUME 0x407
104#define WM8995_AIF1_ADC1_FILTERS 0x410
105#define WM8995_AIF1_ADC2_FILTERS 0x411
106#define WM8995_AIF1_DAC1_FILTERS_1 0x420
107#define WM8995_AIF1_DAC1_FILTERS_2 0x421
108#define WM8995_AIF1_DAC2_FILTERS_1 0x422
109#define WM8995_AIF1_DAC2_FILTERS_2 0x423
110#define WM8995_AIF1_DRC1_1 0x440
111#define WM8995_AIF1_DRC1_2 0x441
112#define WM8995_AIF1_DRC1_3 0x442
113#define WM8995_AIF1_DRC1_4 0x443
114#define WM8995_AIF1_DRC1_5 0x444
115#define WM8995_AIF1_DRC2_1 0x450
116#define WM8995_AIF1_DRC2_2 0x451
117#define WM8995_AIF1_DRC2_3 0x452
118#define WM8995_AIF1_DRC2_4 0x453
119#define WM8995_AIF1_DRC2_5 0x454
120#define WM8995_AIF1_DAC1_EQ_GAINS_1 0x480
121#define WM8995_AIF1_DAC1_EQ_GAINS_2 0x481
122#define WM8995_AIF1_DAC1_EQ_BAND_1_A 0x482
123#define WM8995_AIF1_DAC1_EQ_BAND_1_B 0x483
124#define WM8995_AIF1_DAC1_EQ_BAND_1_PG 0x484
125#define WM8995_AIF1_DAC1_EQ_BAND_2_A 0x485
126#define WM8995_AIF1_DAC1_EQ_BAND_2_B 0x486
127#define WM8995_AIF1_DAC1_EQ_BAND_2_C 0x487
128#define WM8995_AIF1_DAC1_EQ_BAND_2_PG 0x488
129#define WM8995_AIF1_DAC1_EQ_BAND_3_A 0x489
130#define WM8995_AIF1_DAC1_EQ_BAND_3_B 0x48A
131#define WM8995_AIF1_DAC1_EQ_BAND_3_C 0x48B
132#define WM8995_AIF1_DAC1_EQ_BAND_3_PG 0x48C
133#define WM8995_AIF1_DAC1_EQ_BAND_4_A 0x48D
134#define WM8995_AIF1_DAC1_EQ_BAND_4_B 0x48E
135#define WM8995_AIF1_DAC1_EQ_BAND_4_C 0x48F
136#define WM8995_AIF1_DAC1_EQ_BAND_4_PG 0x490
137#define WM8995_AIF1_DAC1_EQ_BAND_5_A 0x491
138#define WM8995_AIF1_DAC1_EQ_BAND_5_B 0x492
139#define WM8995_AIF1_DAC1_EQ_BAND_5_PG 0x493
140#define WM8995_AIF1_DAC2_EQ_GAINS_1 0x4A0
141#define WM8995_AIF1_DAC2_EQ_GAINS_2 0x4A1
142#define WM8995_AIF1_DAC2_EQ_BAND_1_A 0x4A2
143#define WM8995_AIF1_DAC2_EQ_BAND_1_B 0x4A3
144#define WM8995_AIF1_DAC2_EQ_BAND_1_PG 0x4A4
145#define WM8995_AIF1_DAC2_EQ_BAND_2_A 0x4A5
146#define WM8995_AIF1_DAC2_EQ_BAND_2_B 0x4A6
147#define WM8995_AIF1_DAC2_EQ_BAND_2_C 0x4A7
148#define WM8995_AIF1_DAC2_EQ_BAND_2_PG 0x4A8
149#define WM8995_AIF1_DAC2_EQ_BAND_3_A 0x4A9
150#define WM8995_AIF1_DAC2_EQ_BAND_3_B 0x4AA
151#define WM8995_AIF1_DAC2_EQ_BAND_3_C 0x4AB
152#define WM8995_AIF1_DAC2_EQ_BAND_3_PG 0x4AC
153#define WM8995_AIF1_DAC2_EQ_BAND_4_A 0x4AD
154#define WM8995_AIF1_DAC2_EQ_BAND_4_B 0x4AE
155#define WM8995_AIF1_DAC2_EQ_BAND_4_C 0x4AF
156#define WM8995_AIF1_DAC2_EQ_BAND_4_PG 0x4B0
157#define WM8995_AIF1_DAC2_EQ_BAND_5_A 0x4B1
158#define WM8995_AIF1_DAC2_EQ_BAND_5_B 0x4B2
159#define WM8995_AIF1_DAC2_EQ_BAND_5_PG 0x4B3
160#define WM8995_AIF2_ADC_LEFT_VOLUME 0x500
161#define WM8995_AIF2_ADC_RIGHT_VOLUME 0x501
162#define WM8995_AIF2_DAC_LEFT_VOLUME 0x502
163#define WM8995_AIF2_DAC_RIGHT_VOLUME 0x503
164#define WM8995_AIF2_ADC_FILTERS 0x510
165#define WM8995_AIF2_DAC_FILTERS_1 0x520
166#define WM8995_AIF2_DAC_FILTERS_2 0x521
167#define WM8995_AIF2_DRC_1 0x540
168#define WM8995_AIF2_DRC_2 0x541
169#define WM8995_AIF2_DRC_3 0x542
170#define WM8995_AIF2_DRC_4 0x543
171#define WM8995_AIF2_DRC_5 0x544
172#define WM8995_AIF2_EQ_GAINS_1 0x580
173#define WM8995_AIF2_EQ_GAINS_2 0x581
174#define WM8995_AIF2_EQ_BAND_1_A 0x582
175#define WM8995_AIF2_EQ_BAND_1_B 0x583
176#define WM8995_AIF2_EQ_BAND_1_PG 0x584
177#define WM8995_AIF2_EQ_BAND_2_A 0x585
178#define WM8995_AIF2_EQ_BAND_2_B 0x586
179#define WM8995_AIF2_EQ_BAND_2_C 0x587
180#define WM8995_AIF2_EQ_BAND_2_PG 0x588
181#define WM8995_AIF2_EQ_BAND_3_A 0x589
182#define WM8995_AIF2_EQ_BAND_3_B 0x58A
183#define WM8995_AIF2_EQ_BAND_3_C 0x58B
184#define WM8995_AIF2_EQ_BAND_3_PG 0x58C
185#define WM8995_AIF2_EQ_BAND_4_A 0x58D
186#define WM8995_AIF2_EQ_BAND_4_B 0x58E
187#define WM8995_AIF2_EQ_BAND_4_C 0x58F
188#define WM8995_AIF2_EQ_BAND_4_PG 0x590
189#define WM8995_AIF2_EQ_BAND_5_A 0x591
190#define WM8995_AIF2_EQ_BAND_5_B 0x592
191#define WM8995_AIF2_EQ_BAND_5_PG 0x593
192#define WM8995_DAC1_MIXER_VOLUMES 0x600
193#define WM8995_DAC1_LEFT_MIXER_ROUTING 0x601
194#define WM8995_DAC1_RIGHT_MIXER_ROUTING 0x602
195#define WM8995_DAC2_MIXER_VOLUMES 0x603
196#define WM8995_DAC2_LEFT_MIXER_ROUTING 0x604
197#define WM8995_DAC2_RIGHT_MIXER_ROUTING 0x605
198#define WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606
199#define WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607
200#define WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608
201#define WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609
202#define WM8995_DAC_SOFTMUTE 0x610
203#define WM8995_OVERSAMPLING 0x620
204#define WM8995_SIDETONE 0x621
205#define WM8995_GPIO_1 0x700
206#define WM8995_GPIO_2 0x701
207#define WM8995_GPIO_3 0x702
208#define WM8995_GPIO_4 0x703
209#define WM8995_GPIO_5 0x704
210#define WM8995_GPIO_6 0x705
211#define WM8995_GPIO_7 0x706
212#define WM8995_GPIO_8 0x707
213#define WM8995_GPIO_9 0x708
214#define WM8995_GPIO_10 0x709
215#define WM8995_GPIO_11 0x70A
216#define WM8995_GPIO_12 0x70B
217#define WM8995_GPIO_13 0x70C
218#define WM8995_GPIO_14 0x70D
219#define WM8995_PULL_CONTROL_1 0x720
220#define WM8995_PULL_CONTROL_2 0x721
221#define WM8995_INTERRUPT_STATUS_1 0x730
222#define WM8995_INTERRUPT_STATUS_2 0x731
223#define WM8995_INTERRUPT_RAW_STATUS_2 0x732
224#define WM8995_INTERRUPT_STATUS_1_MASK 0x738
225#define WM8995_INTERRUPT_STATUS_2_MASK 0x739
226#define WM8995_INTERRUPT_CONTROL 0x740
227#define WM8995_LEFT_PDM_SPEAKER_1 0x800
228#define WM8995_RIGHT_PDM_SPEAKER_1 0x801
229#define WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE 0x802
230#define WM8995_LEFT_PDM_SPEAKER_2 0x808
231#define WM8995_RIGHT_PDM_SPEAKER_2 0x809
232#define WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE 0x80A
233#define WM8995_WRITE_SEQUENCER_0 0x3000
234#define WM8995_WRITE_SEQUENCER_1 0x3001
235#define WM8995_WRITE_SEQUENCER_2 0x3002
236#define WM8995_WRITE_SEQUENCER_3 0x3003
237#define WM8995_WRITE_SEQUENCER_4 0x3004
238#define WM8995_WRITE_SEQUENCER_5 0x3005
239#define WM8995_WRITE_SEQUENCER_6 0x3006
240#define WM8995_WRITE_SEQUENCER_7 0x3007
241#define WM8995_WRITE_SEQUENCER_8 0x3008
242#define WM8995_WRITE_SEQUENCER_9 0x3009
243#define WM8995_WRITE_SEQUENCER_10 0x300A
244#define WM8995_WRITE_SEQUENCER_11 0x300B
245#define WM8995_WRITE_SEQUENCER_12 0x300C
246#define WM8995_WRITE_SEQUENCER_13 0x300D
247#define WM8995_WRITE_SEQUENCER_14 0x300E
248#define WM8995_WRITE_SEQUENCER_15 0x300F
249#define WM8995_WRITE_SEQUENCER_16 0x3010
250#define WM8995_WRITE_SEQUENCER_17 0x3011
251#define WM8995_WRITE_SEQUENCER_18 0x3012
252#define WM8995_WRITE_SEQUENCER_19 0x3013
253#define WM8995_WRITE_SEQUENCER_20 0x3014
254#define WM8995_WRITE_SEQUENCER_21 0x3015
255#define WM8995_WRITE_SEQUENCER_22 0x3016
256#define WM8995_WRITE_SEQUENCER_23 0x3017
257#define WM8995_WRITE_SEQUENCER_24 0x3018
258#define WM8995_WRITE_SEQUENCER_25 0x3019
259#define WM8995_WRITE_SEQUENCER_26 0x301A
260#define WM8995_WRITE_SEQUENCER_27 0x301B
261#define WM8995_WRITE_SEQUENCER_28 0x301C
262#define WM8995_WRITE_SEQUENCER_29 0x301D
263#define WM8995_WRITE_SEQUENCER_30 0x301E
264#define WM8995_WRITE_SEQUENCER_31 0x301F
265#define WM8995_WRITE_SEQUENCER_32 0x3020
266#define WM8995_WRITE_SEQUENCER_33 0x3021
267#define WM8995_WRITE_SEQUENCER_34 0x3022
268#define WM8995_WRITE_SEQUENCER_35 0x3023
269#define WM8995_WRITE_SEQUENCER_36 0x3024
270#define WM8995_WRITE_SEQUENCER_37 0x3025
271#define WM8995_WRITE_SEQUENCER_38 0x3026
272#define WM8995_WRITE_SEQUENCER_39 0x3027
273#define WM8995_WRITE_SEQUENCER_40 0x3028
274#define WM8995_WRITE_SEQUENCER_41 0x3029
275#define WM8995_WRITE_SEQUENCER_42 0x302A
276#define WM8995_WRITE_SEQUENCER_43 0x302B
277#define WM8995_WRITE_SEQUENCER_44 0x302C
278#define WM8995_WRITE_SEQUENCER_45 0x302D
279#define WM8995_WRITE_SEQUENCER_46 0x302E
280#define WM8995_WRITE_SEQUENCER_47 0x302F
281#define WM8995_WRITE_SEQUENCER_48 0x3030
282#define WM8995_WRITE_SEQUENCER_49 0x3031
283#define WM8995_WRITE_SEQUENCER_50 0x3032
284#define WM8995_WRITE_SEQUENCER_51 0x3033
285#define WM8995_WRITE_SEQUENCER_52 0x3034
286#define WM8995_WRITE_SEQUENCER_53 0x3035
287#define WM8995_WRITE_SEQUENCER_54 0x3036
288#define WM8995_WRITE_SEQUENCER_55 0x3037
289#define WM8995_WRITE_SEQUENCER_56 0x3038
290#define WM8995_WRITE_SEQUENCER_57 0x3039
291#define WM8995_WRITE_SEQUENCER_58 0x303A
292#define WM8995_WRITE_SEQUENCER_59 0x303B
293#define WM8995_WRITE_SEQUENCER_60 0x303C
294#define WM8995_WRITE_SEQUENCER_61 0x303D
295#define WM8995_WRITE_SEQUENCER_62 0x303E
296#define WM8995_WRITE_SEQUENCER_63 0x303F
297#define WM8995_WRITE_SEQUENCER_64 0x3040
298#define WM8995_WRITE_SEQUENCER_65 0x3041
299#define WM8995_WRITE_SEQUENCER_66 0x3042
300#define WM8995_WRITE_SEQUENCER_67 0x3043
301#define WM8995_WRITE_SEQUENCER_68 0x3044
302#define WM8995_WRITE_SEQUENCER_69 0x3045
303#define WM8995_WRITE_SEQUENCER_70 0x3046
304#define WM8995_WRITE_SEQUENCER_71 0x3047
305#define WM8995_WRITE_SEQUENCER_72 0x3048
306#define WM8995_WRITE_SEQUENCER_73 0x3049
307#define WM8995_WRITE_SEQUENCER_74 0x304A
308#define WM8995_WRITE_SEQUENCER_75 0x304B
309#define WM8995_WRITE_SEQUENCER_76 0x304C
310#define WM8995_WRITE_SEQUENCER_77 0x304D
311#define WM8995_WRITE_SEQUENCER_78 0x304E
312#define WM8995_WRITE_SEQUENCER_79 0x304F
313#define WM8995_WRITE_SEQUENCER_80 0x3050
314#define WM8995_WRITE_SEQUENCER_81 0x3051
315#define WM8995_WRITE_SEQUENCER_82 0x3052
316#define WM8995_WRITE_SEQUENCER_83 0x3053
317#define WM8995_WRITE_SEQUENCER_84 0x3054
318#define WM8995_WRITE_SEQUENCER_85 0x3055
319#define WM8995_WRITE_SEQUENCER_86 0x3056
320#define WM8995_WRITE_SEQUENCER_87 0x3057
321#define WM8995_WRITE_SEQUENCER_88 0x3058
322#define WM8995_WRITE_SEQUENCER_89 0x3059
323#define WM8995_WRITE_SEQUENCER_90 0x305A
324#define WM8995_WRITE_SEQUENCER_91 0x305B
325#define WM8995_WRITE_SEQUENCER_92 0x305C
326#define WM8995_WRITE_SEQUENCER_93 0x305D
327#define WM8995_WRITE_SEQUENCER_94 0x305E
328#define WM8995_WRITE_SEQUENCER_95 0x305F
329#define WM8995_WRITE_SEQUENCER_96 0x3060
330#define WM8995_WRITE_SEQUENCER_97 0x3061
331#define WM8995_WRITE_SEQUENCER_98 0x3062
332#define WM8995_WRITE_SEQUENCER_99 0x3063
333#define WM8995_WRITE_SEQUENCER_100 0x3064
334#define WM8995_WRITE_SEQUENCER_101 0x3065
335#define WM8995_WRITE_SEQUENCER_102 0x3066
336#define WM8995_WRITE_SEQUENCER_103 0x3067
337#define WM8995_WRITE_SEQUENCER_104 0x3068
338#define WM8995_WRITE_SEQUENCER_105 0x3069
339#define WM8995_WRITE_SEQUENCER_106 0x306A
340#define WM8995_WRITE_SEQUENCER_107 0x306B
341#define WM8995_WRITE_SEQUENCER_108 0x306C
342#define WM8995_WRITE_SEQUENCER_109 0x306D
343#define WM8995_WRITE_SEQUENCER_110 0x306E
344#define WM8995_WRITE_SEQUENCER_111 0x306F
345#define WM8995_WRITE_SEQUENCER_112 0x3070
346#define WM8995_WRITE_SEQUENCER_113 0x3071
347#define WM8995_WRITE_SEQUENCER_114 0x3072
348#define WM8995_WRITE_SEQUENCER_115 0x3073
349#define WM8995_WRITE_SEQUENCER_116 0x3074
350#define WM8995_WRITE_SEQUENCER_117 0x3075
351#define WM8995_WRITE_SEQUENCER_118 0x3076
352#define WM8995_WRITE_SEQUENCER_119 0x3077
353#define WM8995_WRITE_SEQUENCER_120 0x3078
354#define WM8995_WRITE_SEQUENCER_121 0x3079
355#define WM8995_WRITE_SEQUENCER_122 0x307A
356#define WM8995_WRITE_SEQUENCER_123 0x307B
357#define WM8995_WRITE_SEQUENCER_124 0x307C
358#define WM8995_WRITE_SEQUENCER_125 0x307D
359#define WM8995_WRITE_SEQUENCER_126 0x307E
360#define WM8995_WRITE_SEQUENCER_127 0x307F
361#define WM8995_WRITE_SEQUENCER_128 0x3080
362#define WM8995_WRITE_SEQUENCER_129 0x3081
363#define WM8995_WRITE_SEQUENCER_130 0x3082
364#define WM8995_WRITE_SEQUENCER_131 0x3083
365#define WM8995_WRITE_SEQUENCER_132 0x3084
366#define WM8995_WRITE_SEQUENCER_133 0x3085
367#define WM8995_WRITE_SEQUENCER_134 0x3086
368#define WM8995_WRITE_SEQUENCER_135 0x3087
369#define WM8995_WRITE_SEQUENCER_136 0x3088
370#define WM8995_WRITE_SEQUENCER_137 0x3089
371#define WM8995_WRITE_SEQUENCER_138 0x308A
372#define WM8995_WRITE_SEQUENCER_139 0x308B
373#define WM8995_WRITE_SEQUENCER_140 0x308C
374#define WM8995_WRITE_SEQUENCER_141 0x308D
375#define WM8995_WRITE_SEQUENCER_142 0x308E
376#define WM8995_WRITE_SEQUENCER_143 0x308F
377#define WM8995_WRITE_SEQUENCER_144 0x3090
378#define WM8995_WRITE_SEQUENCER_145 0x3091
379#define WM8995_WRITE_SEQUENCER_146 0x3092
380#define WM8995_WRITE_SEQUENCER_147 0x3093
381#define WM8995_WRITE_SEQUENCER_148 0x3094
382#define WM8995_WRITE_SEQUENCER_149 0x3095
383#define WM8995_WRITE_SEQUENCER_150 0x3096
384#define WM8995_WRITE_SEQUENCER_151 0x3097
385#define WM8995_WRITE_SEQUENCER_152 0x3098
386#define WM8995_WRITE_SEQUENCER_153 0x3099
387#define WM8995_WRITE_SEQUENCER_154 0x309A
388#define WM8995_WRITE_SEQUENCER_155 0x309B
389#define WM8995_WRITE_SEQUENCER_156 0x309C
390#define WM8995_WRITE_SEQUENCER_157 0x309D
391#define WM8995_WRITE_SEQUENCER_158 0x309E
392#define WM8995_WRITE_SEQUENCER_159 0x309F
393#define WM8995_WRITE_SEQUENCER_160 0x30A0
394#define WM8995_WRITE_SEQUENCER_161 0x30A1
395#define WM8995_WRITE_SEQUENCER_162 0x30A2
396#define WM8995_WRITE_SEQUENCER_163 0x30A3
397#define WM8995_WRITE_SEQUENCER_164 0x30A4
398#define WM8995_WRITE_SEQUENCER_165 0x30A5
399#define WM8995_WRITE_SEQUENCER_166 0x30A6
400#define WM8995_WRITE_SEQUENCER_167 0x30A7
401#define WM8995_WRITE_SEQUENCER_168 0x30A8
402#define WM8995_WRITE_SEQUENCER_169 0x30A9
403#define WM8995_WRITE_SEQUENCER_170 0x30AA
404#define WM8995_WRITE_SEQUENCER_171 0x30AB
405#define WM8995_WRITE_SEQUENCER_172 0x30AC
406#define WM8995_WRITE_SEQUENCER_173 0x30AD
407#define WM8995_WRITE_SEQUENCER_174 0x30AE
408#define WM8995_WRITE_SEQUENCER_175 0x30AF
409#define WM8995_WRITE_SEQUENCER_176 0x30B0
410#define WM8995_WRITE_SEQUENCER_177 0x30B1
411#define WM8995_WRITE_SEQUENCER_178 0x30B2
412#define WM8995_WRITE_SEQUENCER_179 0x30B3
413#define WM8995_WRITE_SEQUENCER_180 0x30B4
414#define WM8995_WRITE_SEQUENCER_181 0x30B5
415#define WM8995_WRITE_SEQUENCER_182 0x30B6
416#define WM8995_WRITE_SEQUENCER_183 0x30B7
417#define WM8995_WRITE_SEQUENCER_184 0x30B8
418#define WM8995_WRITE_SEQUENCER_185 0x30B9
419#define WM8995_WRITE_SEQUENCER_186 0x30BA
420#define WM8995_WRITE_SEQUENCER_187 0x30BB
421#define WM8995_WRITE_SEQUENCER_188 0x30BC
422#define WM8995_WRITE_SEQUENCER_189 0x30BD
423#define WM8995_WRITE_SEQUENCER_190 0x30BE
424#define WM8995_WRITE_SEQUENCER_191 0x30BF
425#define WM8995_WRITE_SEQUENCER_192 0x30C0
426#define WM8995_WRITE_SEQUENCER_193 0x30C1
427#define WM8995_WRITE_SEQUENCER_194 0x30C2
428#define WM8995_WRITE_SEQUENCER_195 0x30C3
429#define WM8995_WRITE_SEQUENCER_196 0x30C4
430#define WM8995_WRITE_SEQUENCER_197 0x30C5
431#define WM8995_WRITE_SEQUENCER_198 0x30C6
432#define WM8995_WRITE_SEQUENCER_199 0x30C7
433#define WM8995_WRITE_SEQUENCER_200 0x30C8
434#define WM8995_WRITE_SEQUENCER_201 0x30C9
435#define WM8995_WRITE_SEQUENCER_202 0x30CA
436#define WM8995_WRITE_SEQUENCER_203 0x30CB
437#define WM8995_WRITE_SEQUENCER_204 0x30CC
438#define WM8995_WRITE_SEQUENCER_205 0x30CD
439#define WM8995_WRITE_SEQUENCER_206 0x30CE
440#define WM8995_WRITE_SEQUENCER_207 0x30CF
441#define WM8995_WRITE_SEQUENCER_208 0x30D0
442#define WM8995_WRITE_SEQUENCER_209 0x30D1
443#define WM8995_WRITE_SEQUENCER_210 0x30D2
444#define WM8995_WRITE_SEQUENCER_211 0x30D3
445#define WM8995_WRITE_SEQUENCER_212 0x30D4
446#define WM8995_WRITE_SEQUENCER_213 0x30D5
447#define WM8995_WRITE_SEQUENCER_214 0x30D6
448#define WM8995_WRITE_SEQUENCER_215 0x30D7
449#define WM8995_WRITE_SEQUENCER_216 0x30D8
450#define WM8995_WRITE_SEQUENCER_217 0x30D9
451#define WM8995_WRITE_SEQUENCER_218 0x30DA
452#define WM8995_WRITE_SEQUENCER_219 0x30DB
453#define WM8995_WRITE_SEQUENCER_220 0x30DC
454#define WM8995_WRITE_SEQUENCER_221 0x30DD
455#define WM8995_WRITE_SEQUENCER_222 0x30DE
456#define WM8995_WRITE_SEQUENCER_223 0x30DF
457#define WM8995_WRITE_SEQUENCER_224 0x30E0
458#define WM8995_WRITE_SEQUENCER_225 0x30E1
459#define WM8995_WRITE_SEQUENCER_226 0x30E2
460#define WM8995_WRITE_SEQUENCER_227 0x30E3
461#define WM8995_WRITE_SEQUENCER_228 0x30E4
462#define WM8995_WRITE_SEQUENCER_229 0x30E5
463#define WM8995_WRITE_SEQUENCER_230 0x30E6
464#define WM8995_WRITE_SEQUENCER_231 0x30E7
465#define WM8995_WRITE_SEQUENCER_232 0x30E8
466#define WM8995_WRITE_SEQUENCER_233 0x30E9
467#define WM8995_WRITE_SEQUENCER_234 0x30EA
468#define WM8995_WRITE_SEQUENCER_235 0x30EB
469#define WM8995_WRITE_SEQUENCER_236 0x30EC
470#define WM8995_WRITE_SEQUENCER_237 0x30ED
471#define WM8995_WRITE_SEQUENCER_238 0x30EE
472#define WM8995_WRITE_SEQUENCER_239 0x30EF
473#define WM8995_WRITE_SEQUENCER_240 0x30F0
474#define WM8995_WRITE_SEQUENCER_241 0x30F1
475#define WM8995_WRITE_SEQUENCER_242 0x30F2
476#define WM8995_WRITE_SEQUENCER_243 0x30F3
477#define WM8995_WRITE_SEQUENCER_244 0x30F4
478#define WM8995_WRITE_SEQUENCER_245 0x30F5
479#define WM8995_WRITE_SEQUENCER_246 0x30F6
480#define WM8995_WRITE_SEQUENCER_247 0x30F7
481#define WM8995_WRITE_SEQUENCER_248 0x30F8
482#define WM8995_WRITE_SEQUENCER_249 0x30F9
483#define WM8995_WRITE_SEQUENCER_250 0x30FA
484#define WM8995_WRITE_SEQUENCER_251 0x30FB
485#define WM8995_WRITE_SEQUENCER_252 0x30FC
486#define WM8995_WRITE_SEQUENCER_253 0x30FD
487#define WM8995_WRITE_SEQUENCER_254 0x30FE
488#define WM8995_WRITE_SEQUENCER_255 0x30FF
489#define WM8995_WRITE_SEQUENCER_256 0x3100
490#define WM8995_WRITE_SEQUENCER_257 0x3101
491#define WM8995_WRITE_SEQUENCER_258 0x3102
492#define WM8995_WRITE_SEQUENCER_259 0x3103
493#define WM8995_WRITE_SEQUENCER_260 0x3104
494#define WM8995_WRITE_SEQUENCER_261 0x3105
495#define WM8995_WRITE_SEQUENCER_262 0x3106
496#define WM8995_WRITE_SEQUENCER_263 0x3107
497#define WM8995_WRITE_SEQUENCER_264 0x3108
498#define WM8995_WRITE_SEQUENCER_265 0x3109
499#define WM8995_WRITE_SEQUENCER_266 0x310A
500#define WM8995_WRITE_SEQUENCER_267 0x310B
501#define WM8995_WRITE_SEQUENCER_268 0x310C
502#define WM8995_WRITE_SEQUENCER_269 0x310D
503#define WM8995_WRITE_SEQUENCER_270 0x310E
504#define WM8995_WRITE_SEQUENCER_271 0x310F
505#define WM8995_WRITE_SEQUENCER_272 0x3110
506#define WM8995_WRITE_SEQUENCER_273 0x3111
507#define WM8995_WRITE_SEQUENCER_274 0x3112
508#define WM8995_WRITE_SEQUENCER_275 0x3113
509#define WM8995_WRITE_SEQUENCER_276 0x3114
510#define WM8995_WRITE_SEQUENCER_277 0x3115
511#define WM8995_WRITE_SEQUENCER_278 0x3116
512#define WM8995_WRITE_SEQUENCER_279 0x3117
513#define WM8995_WRITE_SEQUENCER_280 0x3118
514#define WM8995_WRITE_SEQUENCER_281 0x3119
515#define WM8995_WRITE_SEQUENCER_282 0x311A
516#define WM8995_WRITE_SEQUENCER_283 0x311B
517#define WM8995_WRITE_SEQUENCER_284 0x311C
518#define WM8995_WRITE_SEQUENCER_285 0x311D
519#define WM8995_WRITE_SEQUENCER_286 0x311E
520#define WM8995_WRITE_SEQUENCER_287 0x311F
521#define WM8995_WRITE_SEQUENCER_288 0x3120
522#define WM8995_WRITE_SEQUENCER_289 0x3121
523#define WM8995_WRITE_SEQUENCER_290 0x3122
524#define WM8995_WRITE_SEQUENCER_291 0x3123
525#define WM8995_WRITE_SEQUENCER_292 0x3124
526#define WM8995_WRITE_SEQUENCER_293 0x3125
527#define WM8995_WRITE_SEQUENCER_294 0x3126
528#define WM8995_WRITE_SEQUENCER_295 0x3127
529#define WM8995_WRITE_SEQUENCER_296 0x3128
530#define WM8995_WRITE_SEQUENCER_297 0x3129
531#define WM8995_WRITE_SEQUENCER_298 0x312A
532#define WM8995_WRITE_SEQUENCER_299 0x312B
533#define WM8995_WRITE_SEQUENCER_300 0x312C
534#define WM8995_WRITE_SEQUENCER_301 0x312D
535#define WM8995_WRITE_SEQUENCER_302 0x312E
536#define WM8995_WRITE_SEQUENCER_303 0x312F
537#define WM8995_WRITE_SEQUENCER_304 0x3130
538#define WM8995_WRITE_SEQUENCER_305 0x3131
539#define WM8995_WRITE_SEQUENCER_306 0x3132
540#define WM8995_WRITE_SEQUENCER_307 0x3133
541#define WM8995_WRITE_SEQUENCER_308 0x3134
542#define WM8995_WRITE_SEQUENCER_309 0x3135
543#define WM8995_WRITE_SEQUENCER_310 0x3136
544#define WM8995_WRITE_SEQUENCER_311 0x3137
545#define WM8995_WRITE_SEQUENCER_312 0x3138
546#define WM8995_WRITE_SEQUENCER_313 0x3139
547#define WM8995_WRITE_SEQUENCER_314 0x313A
548#define WM8995_WRITE_SEQUENCER_315 0x313B
549#define WM8995_WRITE_SEQUENCER_316 0x313C
550#define WM8995_WRITE_SEQUENCER_317 0x313D
551#define WM8995_WRITE_SEQUENCER_318 0x313E
552#define WM8995_WRITE_SEQUENCER_319 0x313F
553#define WM8995_WRITE_SEQUENCER_320 0x3140
554#define WM8995_WRITE_SEQUENCER_321 0x3141
555#define WM8995_WRITE_SEQUENCER_322 0x3142
556#define WM8995_WRITE_SEQUENCER_323 0x3143
557#define WM8995_WRITE_SEQUENCER_324 0x3144
558#define WM8995_WRITE_SEQUENCER_325 0x3145
559#define WM8995_WRITE_SEQUENCER_326 0x3146
560#define WM8995_WRITE_SEQUENCER_327 0x3147
561#define WM8995_WRITE_SEQUENCER_328 0x3148
562#define WM8995_WRITE_SEQUENCER_329 0x3149
563#define WM8995_WRITE_SEQUENCER_330 0x314A
564#define WM8995_WRITE_SEQUENCER_331 0x314B
565#define WM8995_WRITE_SEQUENCER_332 0x314C
566#define WM8995_WRITE_SEQUENCER_333 0x314D
567#define WM8995_WRITE_SEQUENCER_334 0x314E
568#define WM8995_WRITE_SEQUENCER_335 0x314F
569#define WM8995_WRITE_SEQUENCER_336 0x3150
570#define WM8995_WRITE_SEQUENCER_337 0x3151
571#define WM8995_WRITE_SEQUENCER_338 0x3152
572#define WM8995_WRITE_SEQUENCER_339 0x3153
573#define WM8995_WRITE_SEQUENCER_340 0x3154
574#define WM8995_WRITE_SEQUENCER_341 0x3155
575#define WM8995_WRITE_SEQUENCER_342 0x3156
576#define WM8995_WRITE_SEQUENCER_343 0x3157
577#define WM8995_WRITE_SEQUENCER_344 0x3158
578#define WM8995_WRITE_SEQUENCER_345 0x3159
579#define WM8995_WRITE_SEQUENCER_346 0x315A
580#define WM8995_WRITE_SEQUENCER_347 0x315B
581#define WM8995_WRITE_SEQUENCER_348 0x315C
582#define WM8995_WRITE_SEQUENCER_349 0x315D
583#define WM8995_WRITE_SEQUENCER_350 0x315E
584#define WM8995_WRITE_SEQUENCER_351 0x315F
585#define WM8995_WRITE_SEQUENCER_352 0x3160
586#define WM8995_WRITE_SEQUENCER_353 0x3161
587#define WM8995_WRITE_SEQUENCER_354 0x3162
588#define WM8995_WRITE_SEQUENCER_355 0x3163
589#define WM8995_WRITE_SEQUENCER_356 0x3164
590#define WM8995_WRITE_SEQUENCER_357 0x3165
591#define WM8995_WRITE_SEQUENCER_358 0x3166
592#define WM8995_WRITE_SEQUENCER_359 0x3167
593#define WM8995_WRITE_SEQUENCER_360 0x3168
594#define WM8995_WRITE_SEQUENCER_361 0x3169
595#define WM8995_WRITE_SEQUENCER_362 0x316A
596#define WM8995_WRITE_SEQUENCER_363 0x316B
597#define WM8995_WRITE_SEQUENCER_364 0x316C
598#define WM8995_WRITE_SEQUENCER_365 0x316D
599#define WM8995_WRITE_SEQUENCER_366 0x316E
600#define WM8995_WRITE_SEQUENCER_367 0x316F
601#define WM8995_WRITE_SEQUENCER_368 0x3170
602#define WM8995_WRITE_SEQUENCER_369 0x3171
603#define WM8995_WRITE_SEQUENCER_370 0x3172
604#define WM8995_WRITE_SEQUENCER_371 0x3173
605#define WM8995_WRITE_SEQUENCER_372 0x3174
606#define WM8995_WRITE_SEQUENCER_373 0x3175
607#define WM8995_WRITE_SEQUENCER_374 0x3176
608#define WM8995_WRITE_SEQUENCER_375 0x3177
609#define WM8995_WRITE_SEQUENCER_376 0x3178
610#define WM8995_WRITE_SEQUENCER_377 0x3179
611#define WM8995_WRITE_SEQUENCER_378 0x317A
612#define WM8995_WRITE_SEQUENCER_379 0x317B
613#define WM8995_WRITE_SEQUENCER_380 0x317C
614#define WM8995_WRITE_SEQUENCER_381 0x317D
615#define WM8995_WRITE_SEQUENCER_382 0x317E
616#define WM8995_WRITE_SEQUENCER_383 0x317F
617#define WM8995_WRITE_SEQUENCER_384 0x3180
618#define WM8995_WRITE_SEQUENCER_385 0x3181
619#define WM8995_WRITE_SEQUENCER_386 0x3182
620#define WM8995_WRITE_SEQUENCER_387 0x3183
621#define WM8995_WRITE_SEQUENCER_388 0x3184
622#define WM8995_WRITE_SEQUENCER_389 0x3185
623#define WM8995_WRITE_SEQUENCER_390 0x3186
624#define WM8995_WRITE_SEQUENCER_391 0x3187
625#define WM8995_WRITE_SEQUENCER_392 0x3188
626#define WM8995_WRITE_SEQUENCER_393 0x3189
627#define WM8995_WRITE_SEQUENCER_394 0x318A
628#define WM8995_WRITE_SEQUENCER_395 0x318B
629#define WM8995_WRITE_SEQUENCER_396 0x318C
630#define WM8995_WRITE_SEQUENCER_397 0x318D
631#define WM8995_WRITE_SEQUENCER_398 0x318E
632#define WM8995_WRITE_SEQUENCER_399 0x318F
633#define WM8995_WRITE_SEQUENCER_400 0x3190
634#define WM8995_WRITE_SEQUENCER_401 0x3191
635#define WM8995_WRITE_SEQUENCER_402 0x3192
636#define WM8995_WRITE_SEQUENCER_403 0x3193
637#define WM8995_WRITE_SEQUENCER_404 0x3194
638#define WM8995_WRITE_SEQUENCER_405 0x3195
639#define WM8995_WRITE_SEQUENCER_406 0x3196
640#define WM8995_WRITE_SEQUENCER_407 0x3197
641#define WM8995_WRITE_SEQUENCER_408 0x3198
642#define WM8995_WRITE_SEQUENCER_409 0x3199
643#define WM8995_WRITE_SEQUENCER_410 0x319A
644#define WM8995_WRITE_SEQUENCER_411 0x319B
645#define WM8995_WRITE_SEQUENCER_412 0x319C
646#define WM8995_WRITE_SEQUENCER_413 0x319D
647#define WM8995_WRITE_SEQUENCER_414 0x319E
648#define WM8995_WRITE_SEQUENCER_415 0x319F
649#define WM8995_WRITE_SEQUENCER_416 0x31A0
650#define WM8995_WRITE_SEQUENCER_417 0x31A1
651#define WM8995_WRITE_SEQUENCER_418 0x31A2
652#define WM8995_WRITE_SEQUENCER_419 0x31A3
653#define WM8995_WRITE_SEQUENCER_420 0x31A4
654#define WM8995_WRITE_SEQUENCER_421 0x31A5
655#define WM8995_WRITE_SEQUENCER_422 0x31A6
656#define WM8995_WRITE_SEQUENCER_423 0x31A7
657#define WM8995_WRITE_SEQUENCER_424 0x31A8
658#define WM8995_WRITE_SEQUENCER_425 0x31A9
659#define WM8995_WRITE_SEQUENCER_426 0x31AA
660#define WM8995_WRITE_SEQUENCER_427 0x31AB
661#define WM8995_WRITE_SEQUENCER_428 0x31AC
662#define WM8995_WRITE_SEQUENCER_429 0x31AD
663#define WM8995_WRITE_SEQUENCER_430 0x31AE
664#define WM8995_WRITE_SEQUENCER_431 0x31AF
665#define WM8995_WRITE_SEQUENCER_432 0x31B0
666#define WM8995_WRITE_SEQUENCER_433 0x31B1
667#define WM8995_WRITE_SEQUENCER_434 0x31B2
668#define WM8995_WRITE_SEQUENCER_435 0x31B3
669#define WM8995_WRITE_SEQUENCER_436 0x31B4
670#define WM8995_WRITE_SEQUENCER_437 0x31B5
671#define WM8995_WRITE_SEQUENCER_438 0x31B6
672#define WM8995_WRITE_SEQUENCER_439 0x31B7
673#define WM8995_WRITE_SEQUENCER_440 0x31B8
674#define WM8995_WRITE_SEQUENCER_441 0x31B9
675#define WM8995_WRITE_SEQUENCER_442 0x31BA
676#define WM8995_WRITE_SEQUENCER_443 0x31BB
677#define WM8995_WRITE_SEQUENCER_444 0x31BC
678#define WM8995_WRITE_SEQUENCER_445 0x31BD
679#define WM8995_WRITE_SEQUENCER_446 0x31BE
680#define WM8995_WRITE_SEQUENCER_447 0x31BF
681#define WM8995_WRITE_SEQUENCER_448 0x31C0
682#define WM8995_WRITE_SEQUENCER_449 0x31C1
683#define WM8995_WRITE_SEQUENCER_450 0x31C2
684#define WM8995_WRITE_SEQUENCER_451 0x31C3
685#define WM8995_WRITE_SEQUENCER_452 0x31C4
686#define WM8995_WRITE_SEQUENCER_453 0x31C5
687#define WM8995_WRITE_SEQUENCER_454 0x31C6
688#define WM8995_WRITE_SEQUENCER_455 0x31C7
689#define WM8995_WRITE_SEQUENCER_456 0x31C8
690#define WM8995_WRITE_SEQUENCER_457 0x31C9
691#define WM8995_WRITE_SEQUENCER_458 0x31CA
692#define WM8995_WRITE_SEQUENCER_459 0x31CB
693#define WM8995_WRITE_SEQUENCER_460 0x31CC
694#define WM8995_WRITE_SEQUENCER_461 0x31CD
695#define WM8995_WRITE_SEQUENCER_462 0x31CE
696#define WM8995_WRITE_SEQUENCER_463 0x31CF
697#define WM8995_WRITE_SEQUENCER_464 0x31D0
698#define WM8995_WRITE_SEQUENCER_465 0x31D1
699#define WM8995_WRITE_SEQUENCER_466 0x31D2
700#define WM8995_WRITE_SEQUENCER_467 0x31D3
701#define WM8995_WRITE_SEQUENCER_468 0x31D4
702#define WM8995_WRITE_SEQUENCER_469 0x31D5
703#define WM8995_WRITE_SEQUENCER_470 0x31D6
704#define WM8995_WRITE_SEQUENCER_471 0x31D7
705#define WM8995_WRITE_SEQUENCER_472 0x31D8
706#define WM8995_WRITE_SEQUENCER_473 0x31D9
707#define WM8995_WRITE_SEQUENCER_474 0x31DA
708#define WM8995_WRITE_SEQUENCER_475 0x31DB
709#define WM8995_WRITE_SEQUENCER_476 0x31DC
710#define WM8995_WRITE_SEQUENCER_477 0x31DD
711#define WM8995_WRITE_SEQUENCER_478 0x31DE
712#define WM8995_WRITE_SEQUENCER_479 0x31DF
713#define WM8995_WRITE_SEQUENCER_480 0x31E0
714#define WM8995_WRITE_SEQUENCER_481 0x31E1
715#define WM8995_WRITE_SEQUENCER_482 0x31E2
716#define WM8995_WRITE_SEQUENCER_483 0x31E3
717#define WM8995_WRITE_SEQUENCER_484 0x31E4
718#define WM8995_WRITE_SEQUENCER_485 0x31E5
719#define WM8995_WRITE_SEQUENCER_486 0x31E6
720#define WM8995_WRITE_SEQUENCER_487 0x31E7
721#define WM8995_WRITE_SEQUENCER_488 0x31E8
722#define WM8995_WRITE_SEQUENCER_489 0x31E9
723#define WM8995_WRITE_SEQUENCER_490 0x31EA
724#define WM8995_WRITE_SEQUENCER_491 0x31EB
725#define WM8995_WRITE_SEQUENCER_492 0x31EC
726#define WM8995_WRITE_SEQUENCER_493 0x31ED
727#define WM8995_WRITE_SEQUENCER_494 0x31EE
728#define WM8995_WRITE_SEQUENCER_495 0x31EF
729#define WM8995_WRITE_SEQUENCER_496 0x31F0
730#define WM8995_WRITE_SEQUENCER_497 0x31F1
731#define WM8995_WRITE_SEQUENCER_498 0x31F2
732#define WM8995_WRITE_SEQUENCER_499 0x31F3
733#define WM8995_WRITE_SEQUENCER_500 0x31F4
734#define WM8995_WRITE_SEQUENCER_501 0x31F5
735#define WM8995_WRITE_SEQUENCER_502 0x31F6
736#define WM8995_WRITE_SEQUENCER_503 0x31F7
737#define WM8995_WRITE_SEQUENCER_504 0x31F8
738#define WM8995_WRITE_SEQUENCER_505 0x31F9
739#define WM8995_WRITE_SEQUENCER_506 0x31FA
740#define WM8995_WRITE_SEQUENCER_507 0x31FB
741#define WM8995_WRITE_SEQUENCER_508 0x31FC
742#define WM8995_WRITE_SEQUENCER_509 0x31FD
743#define WM8995_WRITE_SEQUENCER_510 0x31FE
744#define WM8995_WRITE_SEQUENCER_511 0x31FF
745
746#define WM8995_REGISTER_COUNT 725
747#define WM8995_MAX_REGISTER 0x31FF
748
749#define WM8995_MAX_CACHED_REGISTER WM8995_MAX_REGISTER
750
751/*
752 * Field Definitions.
753 */
754
755/*
756 * R0 (0x00) - Software Reset
757 */
758#define WM8995_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
759#define WM8995_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
760#define WM8995_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
761
762/*
763 * R1 (0x01) - Power Management (1)
764 */
765#define WM8995_MICB2_ENA 0x0200 /* MICB2_ENA */
766#define WM8995_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */
767#define WM8995_MICB2_ENA_SHIFT 9 /* MICB2_ENA */
768#define WM8995_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
769#define WM8995_MICB1_ENA 0x0100 /* MICB1_ENA */
770#define WM8995_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */
771#define WM8995_MICB1_ENA_SHIFT 8 /* MICB1_ENA */
772#define WM8995_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
773#define WM8995_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */
774#define WM8995_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */
775#define WM8995_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */
776#define WM8995_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */
777#define WM8995_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */
778#define WM8995_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */
779#define WM8995_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */
780#define WM8995_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */
781#define WM8995_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */
782#define WM8995_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */
783#define WM8995_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */
784#define WM8995_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */
785#define WM8995_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */
786#define WM8995_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */
787#define WM8995_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */
788#define WM8995_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */
789#define WM8995_BG_ENA 0x0001 /* BG_ENA */
790#define WM8995_BG_ENA_MASK 0x0001 /* BG_ENA */
791#define WM8995_BG_ENA_SHIFT 0 /* BG_ENA */
792#define WM8995_BG_ENA_WIDTH 1 /* BG_ENA */
793
794/*
795 * R2 (0x02) - Power Management (2)
796 */
797#define WM8995_OPCLK_ENA 0x0800 /* OPCLK_ENA */
798#define WM8995_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */
799#define WM8995_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */
800#define WM8995_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
801#define WM8995_IN1L_ENA 0x0020 /* IN1L_ENA */
802#define WM8995_IN1L_ENA_MASK 0x0020 /* IN1L_ENA */
803#define WM8995_IN1L_ENA_SHIFT 5 /* IN1L_ENA */
804#define WM8995_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
805#define WM8995_IN1R_ENA 0x0010 /* IN1R_ENA */
806#define WM8995_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */
807#define WM8995_IN1R_ENA_SHIFT 4 /* IN1R_ENA */
808#define WM8995_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
809#define WM8995_LDO2_ENA 0x0002 /* LDO2_ENA */
810#define WM8995_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */
811#define WM8995_LDO2_ENA_SHIFT 1 /* LDO2_ENA */
812#define WM8995_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
813
814/*
815 * R3 (0x03) - Power Management (3)
816 */
817#define WM8995_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */
818#define WM8995_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */
819#define WM8995_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */
820#define WM8995_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */
821#define WM8995_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */
822#define WM8995_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */
823#define WM8995_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */
824#define WM8995_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */
825#define WM8995_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */
826#define WM8995_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */
827#define WM8995_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */
828#define WM8995_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */
829#define WM8995_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */
830#define WM8995_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */
831#define WM8995_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */
832#define WM8995_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */
833#define WM8995_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */
834#define WM8995_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */
835#define WM8995_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */
836#define WM8995_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */
837#define WM8995_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */
838#define WM8995_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */
839#define WM8995_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */
840#define WM8995_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */
841#define WM8995_DMIC3L_ENA 0x0080 /* DMIC3L_ENA */
842#define WM8995_DMIC3L_ENA_MASK 0x0080 /* DMIC3L_ENA */
843#define WM8995_DMIC3L_ENA_SHIFT 7 /* DMIC3L_ENA */
844#define WM8995_DMIC3L_ENA_WIDTH 1 /* DMIC3L_ENA */
845#define WM8995_DMIC3R_ENA 0x0040 /* DMIC3R_ENA */
846#define WM8995_DMIC3R_ENA_MASK 0x0040 /* DMIC3R_ENA */
847#define WM8995_DMIC3R_ENA_SHIFT 6 /* DMIC3R_ENA */
848#define WM8995_DMIC3R_ENA_WIDTH 1 /* DMIC3R_ENA */
849#define WM8995_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */
850#define WM8995_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */
851#define WM8995_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */
852#define WM8995_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */
853#define WM8995_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */
854#define WM8995_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */
855#define WM8995_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */
856#define WM8995_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */
857#define WM8995_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */
858#define WM8995_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */
859#define WM8995_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */
860#define WM8995_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */
861#define WM8995_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */
862#define WM8995_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */
863#define WM8995_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */
864#define WM8995_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */
865#define WM8995_ADCL_ENA 0x0002 /* ADCL_ENA */
866#define WM8995_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
867#define WM8995_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
868#define WM8995_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
869#define WM8995_ADCR_ENA 0x0001 /* ADCR_ENA */
870#define WM8995_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
871#define WM8995_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
872#define WM8995_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
873
874/*
875 * R4 (0x04) - Power Management (4)
876 */
877#define WM8995_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */
878#define WM8995_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */
879#define WM8995_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */
880#define WM8995_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */
881#define WM8995_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */
882#define WM8995_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */
883#define WM8995_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */
884#define WM8995_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */
885#define WM8995_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */
886#define WM8995_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */
887#define WM8995_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */
888#define WM8995_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */
889#define WM8995_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */
890#define WM8995_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */
891#define WM8995_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */
892#define WM8995_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */
893#define WM8995_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */
894#define WM8995_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */
895#define WM8995_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */
896#define WM8995_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */
897#define WM8995_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */
898#define WM8995_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */
899#define WM8995_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */
900#define WM8995_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */
901#define WM8995_DAC2L_ENA 0x0008 /* DAC2L_ENA */
902#define WM8995_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */
903#define WM8995_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */
904#define WM8995_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */
905#define WM8995_DAC2R_ENA 0x0004 /* DAC2R_ENA */
906#define WM8995_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */
907#define WM8995_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */
908#define WM8995_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */
909#define WM8995_DAC1L_ENA 0x0002 /* DAC1L_ENA */
910#define WM8995_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */
911#define WM8995_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */
912#define WM8995_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */
913#define WM8995_DAC1R_ENA 0x0001 /* DAC1R_ENA */
914#define WM8995_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */
915#define WM8995_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */
916#define WM8995_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */
917
918/*
919 * R5 (0x05) - Power Management (5)
920 */
921#define WM8995_DMIC_SRC2_MASK 0x0300 /* DMIC_SRC2 - [9:8] */
922#define WM8995_DMIC_SRC2_SHIFT 8 /* DMIC_SRC2 - [9:8] */
923#define WM8995_DMIC_SRC2_WIDTH 2 /* DMIC_SRC2 - [9:8] */
924#define WM8995_DMIC_SRC1_MASK 0x00C0 /* DMIC_SRC1 - [7:6] */
925#define WM8995_DMIC_SRC1_SHIFT 6 /* DMIC_SRC1 - [7:6] */
926#define WM8995_DMIC_SRC1_WIDTH 2 /* DMIC_SRC1 - [7:6] */
927#define WM8995_AIF3_TRI 0x0020 /* AIF3_TRI */
928#define WM8995_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */
929#define WM8995_AIF3_TRI_SHIFT 5 /* AIF3_TRI */
930#define WM8995_AIF3_TRI_WIDTH 1 /* AIF3_TRI */
931#define WM8995_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */
932#define WM8995_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */
933#define WM8995_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */
934#define WM8995_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */
935#define WM8995_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */
936#define WM8995_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */
937#define WM8995_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */
938#define WM8995_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */
939#define WM8995_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */
940#define WM8995_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */
941#define WM8995_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */
942#define WM8995_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */
943#define WM8995_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */
944#define WM8995_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */
945#define WM8995_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */
946
947/*
948 * R16 (0x10) - Left Line Input 1 Volume
949 */
950#define WM8995_IN1_VU 0x0080 /* IN1_VU */
951#define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */
952#define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */
953#define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */
954#define WM8995_IN1L_ZC 0x0020 /* IN1L_ZC */
955#define WM8995_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */
956#define WM8995_IN1L_ZC_SHIFT 5 /* IN1L_ZC */
957#define WM8995_IN1L_ZC_WIDTH 1 /* IN1L_ZC */
958#define WM8995_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */
959#define WM8995_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */
960#define WM8995_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */
961
962/*
963 * R17 (0x11) - Right Line Input 1 Volume
964 */
965#define WM8995_IN1_VU 0x0080 /* IN1_VU */
966#define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */
967#define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */
968#define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */
969#define WM8995_IN1R_ZC 0x0020 /* IN1R_ZC */
970#define WM8995_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */
971#define WM8995_IN1R_ZC_SHIFT 5 /* IN1R_ZC */
972#define WM8995_IN1R_ZC_WIDTH 1 /* IN1R_ZC */
973#define WM8995_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */
974#define WM8995_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */
975#define WM8995_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */
976
977/*
978 * R18 (0x12) - Left Line Input Control
979 */
980#define WM8995_IN1L_BOOST_MASK 0x0030 /* IN1L_BOOST - [5:4] */
981#define WM8995_IN1L_BOOST_SHIFT 4 /* IN1L_BOOST - [5:4] */
982#define WM8995_IN1L_BOOST_WIDTH 2 /* IN1L_BOOST - [5:4] */
983#define WM8995_IN1L_MODE_MASK 0x000C /* IN1L_MODE - [3:2] */
984#define WM8995_IN1L_MODE_SHIFT 2 /* IN1L_MODE - [3:2] */
985#define WM8995_IN1L_MODE_WIDTH 2 /* IN1L_MODE - [3:2] */
986#define WM8995_IN1R_MODE_MASK 0x0003 /* IN1R_MODE - [1:0] */
987#define WM8995_IN1R_MODE_SHIFT 0 /* IN1R_MODE - [1:0] */
988#define WM8995_IN1R_MODE_WIDTH 2 /* IN1R_MODE - [1:0] */
989
990/*
991 * R24 (0x18) - DAC1 Left Volume
992 */
993#define WM8995_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */
994#define WM8995_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */
995#define WM8995_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */
996#define WM8995_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */
997#define WM8995_DAC1_VU 0x0100 /* DAC1_VU */
998#define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */
999#define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */
1000#define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */
1001#define WM8995_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */
1002#define WM8995_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */
1003#define WM8995_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */
1004
1005/*
1006 * R25 (0x19) - DAC1 Right Volume
1007 */
1008#define WM8995_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */
1009#define WM8995_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */
1010#define WM8995_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */
1011#define WM8995_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */
1012#define WM8995_DAC1_VU 0x0100 /* DAC1_VU */
1013#define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */
1014#define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */
1015#define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */
1016#define WM8995_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */
1017#define WM8995_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */
1018#define WM8995_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */
1019
1020/*
1021 * R26 (0x1A) - DAC2 Left Volume
1022 */
1023#define WM8995_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */
1024#define WM8995_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */
1025#define WM8995_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */
1026#define WM8995_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */
1027#define WM8995_DAC2_VU 0x0100 /* DAC2_VU */
1028#define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1029#define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */
1030#define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */
1031#define WM8995_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */
1032#define WM8995_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */
1033#define WM8995_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */
1034
1035/*
1036 * R27 (0x1B) - DAC2 Right Volume
1037 */
1038#define WM8995_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */
1039#define WM8995_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */
1040#define WM8995_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */
1041#define WM8995_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */
1042#define WM8995_DAC2_VU 0x0100 /* DAC2_VU */
1043#define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1044#define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */
1045#define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */
1046#define WM8995_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */
1047#define WM8995_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */
1048#define WM8995_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */
1049
1050/*
1051 * R28 (0x1C) - Output Volume ZC (1)
1052 */
1053#define WM8995_HPOUT2L_ZC 0x0008 /* HPOUT2L_ZC */
1054#define WM8995_HPOUT2L_ZC_MASK 0x0008 /* HPOUT2L_ZC */
1055#define WM8995_HPOUT2L_ZC_SHIFT 3 /* HPOUT2L_ZC */
1056#define WM8995_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */
1057#define WM8995_HPOUT2R_ZC 0x0004 /* HPOUT2R_ZC */
1058#define WM8995_HPOUT2R_ZC_MASK 0x0004 /* HPOUT2R_ZC */
1059#define WM8995_HPOUT2R_ZC_SHIFT 2 /* HPOUT2R_ZC */
1060#define WM8995_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */
1061#define WM8995_HPOUT1L_ZC 0x0002 /* HPOUT1L_ZC */
1062#define WM8995_HPOUT1L_ZC_MASK 0x0002 /* HPOUT1L_ZC */
1063#define WM8995_HPOUT1L_ZC_SHIFT 1 /* HPOUT1L_ZC */
1064#define WM8995_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */
1065#define WM8995_HPOUT1R_ZC 0x0001 /* HPOUT1R_ZC */
1066#define WM8995_HPOUT1R_ZC_MASK 0x0001 /* HPOUT1R_ZC */
1067#define WM8995_HPOUT1R_ZC_SHIFT 0 /* HPOUT1R_ZC */
1068#define WM8995_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */
1069
1070/*
1071 * R32 (0x20) - MICBIAS (1)
1072 */
1073#define WM8995_MICB1_MODE 0x0008 /* MICB1_MODE */
1074#define WM8995_MICB1_MODE_MASK 0x0008 /* MICB1_MODE */
1075#define WM8995_MICB1_MODE_SHIFT 3 /* MICB1_MODE */
1076#define WM8995_MICB1_MODE_WIDTH 1 /* MICB1_MODE */
1077#define WM8995_MICB1_LVL_MASK 0x0006 /* MICB1_LVL - [2:1] */
1078#define WM8995_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [2:1] */
1079#define WM8995_MICB1_LVL_WIDTH 2 /* MICB1_LVL - [2:1] */
1080#define WM8995_MICB1_DISCH 0x0001 /* MICB1_DISCH */
1081#define WM8995_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */
1082#define WM8995_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */
1083#define WM8995_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
1084
1085/*
1086 * R33 (0x21) - MICBIAS (2)
1087 */
1088#define WM8995_MICB2_MODE 0x0008 /* MICB2_MODE */
1089#define WM8995_MICB2_MODE_MASK 0x0008 /* MICB2_MODE */
1090#define WM8995_MICB2_MODE_SHIFT 3 /* MICB2_MODE */
1091#define WM8995_MICB2_MODE_WIDTH 1 /* MICB2_MODE */
1092#define WM8995_MICB2_LVL_MASK 0x0006 /* MICB2_LVL - [2:1] */
1093#define WM8995_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [2:1] */
1094#define WM8995_MICB2_LVL_WIDTH 2 /* MICB2_LVL - [2:1] */
1095#define WM8995_MICB2_DISCH 0x0001 /* MICB2_DISCH */
1096#define WM8995_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */
1097#define WM8995_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */
1098#define WM8995_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
1099
1100/*
1101 * R40 (0x28) - LDO 1
1102 */
1103#define WM8995_LDO1_MODE 0x0020 /* LDO1_MODE */
1104#define WM8995_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */
1105#define WM8995_LDO1_MODE_SHIFT 5 /* LDO1_MODE */
1106#define WM8995_LDO1_MODE_WIDTH 1 /* LDO1_MODE */
1107#define WM8995_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */
1108#define WM8995_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */
1109#define WM8995_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */
1110#define WM8995_LDO1_DISCH 0x0001 /* LDO1_DISCH */
1111#define WM8995_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */
1112#define WM8995_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */
1113#define WM8995_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
1114
1115/*
1116 * R41 (0x29) - LDO 2
1117 */
1118#define WM8995_LDO2_MODE 0x0020 /* LDO2_MODE */
1119#define WM8995_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */
1120#define WM8995_LDO2_MODE_SHIFT 5 /* LDO2_MODE */
1121#define WM8995_LDO2_MODE_WIDTH 1 /* LDO2_MODE */
1122#define WM8995_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */
1123#define WM8995_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */
1124#define WM8995_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */
1125#define WM8995_LDO2_DISCH 0x0001 /* LDO2_DISCH */
1126#define WM8995_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */
1127#define WM8995_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */
1128#define WM8995_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
1129
1130/*
1131 * R48 (0x30) - Accessory Detect Mode1
1132 */
1133#define WM8995_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */
1134#define WM8995_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */
1135#define WM8995_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */
1136
1137/*
1138 * R49 (0x31) - Accessory Detect Mode2
1139 */
1140#define WM8995_VID_ENA 0x0001 /* VID_ENA */
1141#define WM8995_VID_ENA_MASK 0x0001 /* VID_ENA */
1142#define WM8995_VID_ENA_SHIFT 0 /* VID_ENA */
1143#define WM8995_VID_ENA_WIDTH 1 /* VID_ENA */
1144
1145/*
1146 * R52 (0x34) - Headphone Detect1
1147 */
1148#define WM8995_HP_RAMPRATE 0x0002 /* HP_RAMPRATE */
1149#define WM8995_HP_RAMPRATE_MASK 0x0002 /* HP_RAMPRATE */
1150#define WM8995_HP_RAMPRATE_SHIFT 1 /* HP_RAMPRATE */
1151#define WM8995_HP_RAMPRATE_WIDTH 1 /* HP_RAMPRATE */
1152#define WM8995_HP_POLL 0x0001 /* HP_POLL */
1153#define WM8995_HP_POLL_MASK 0x0001 /* HP_POLL */
1154#define WM8995_HP_POLL_SHIFT 0 /* HP_POLL */
1155#define WM8995_HP_POLL_WIDTH 1 /* HP_POLL */
1156
1157/*
1158 * R53 (0x35) - Headphone Detect2
1159 */
1160#define WM8995_HP_DONE 0x0080 /* HP_DONE */
1161#define WM8995_HP_DONE_MASK 0x0080 /* HP_DONE */
1162#define WM8995_HP_DONE_SHIFT 7 /* HP_DONE */
1163#define WM8995_HP_DONE_WIDTH 1 /* HP_DONE */
1164#define WM8995_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */
1165#define WM8995_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
1166#define WM8995_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
1167
1168/*
1169 * R56 (0x38) - Mic Detect (1)
1170 */
1171#define WM8995_MICD_RATE_MASK 0x7800 /* MICD_RATE - [14:11] */
1172#define WM8995_MICD_RATE_SHIFT 11 /* MICD_RATE - [14:11] */
1173#define WM8995_MICD_RATE_WIDTH 4 /* MICD_RATE - [14:11] */
1174#define WM8995_MICD_LVL_SEL_MASK 0x01F8 /* MICD_LVL_SEL - [8:3] */
1175#define WM8995_MICD_LVL_SEL_SHIFT 3 /* MICD_LVL_SEL - [8:3] */
1176#define WM8995_MICD_LVL_SEL_WIDTH 6 /* MICD_LVL_SEL - [8:3] */
1177#define WM8995_MICD_DBTIME 0x0002 /* MICD_DBTIME */
1178#define WM8995_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */
1179#define WM8995_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
1180#define WM8995_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
1181#define WM8995_MICD_ENA 0x0001 /* MICD_ENA */
1182#define WM8995_MICD_ENA_MASK 0x0001 /* MICD_ENA */
1183#define WM8995_MICD_ENA_SHIFT 0 /* MICD_ENA */
1184#define WM8995_MICD_ENA_WIDTH 1 /* MICD_ENA */
1185
1186/*
1187 * R57 (0x39) - Mic Detect (2)
1188 */
1189#define WM8995_MICD_LVL_MASK 0x01FC /* MICD_LVL - [8:2] */
1190#define WM8995_MICD_LVL_SHIFT 2 /* MICD_LVL - [8:2] */
1191#define WM8995_MICD_LVL_WIDTH 7 /* MICD_LVL - [8:2] */
1192#define WM8995_MICD_VALID 0x0002 /* MICD_VALID */
1193#define WM8995_MICD_VALID_MASK 0x0002 /* MICD_VALID */
1194#define WM8995_MICD_VALID_SHIFT 1 /* MICD_VALID */
1195#define WM8995_MICD_VALID_WIDTH 1 /* MICD_VALID */
1196#define WM8995_MICD_STS 0x0001 /* MICD_STS */
1197#define WM8995_MICD_STS_MASK 0x0001 /* MICD_STS */
1198#define WM8995_MICD_STS_SHIFT 0 /* MICD_STS */
1199#define WM8995_MICD_STS_WIDTH 1 /* MICD_STS */
1200
1201/*
1202 * R64 (0x40) - Charge Pump (1)
1203 */
1204#define WM8995_CP_ENA 0x8000 /* CP_ENA */
1205#define WM8995_CP_ENA_MASK 0x8000 /* CP_ENA */
1206#define WM8995_CP_ENA_SHIFT 15 /* CP_ENA */
1207#define WM8995_CP_ENA_WIDTH 1 /* CP_ENA */
1208
1209/*
1210 * R69 (0x45) - Class W (1)
1211 */
1212#define WM8995_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */
1213#define WM8995_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */
1214#define WM8995_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */
1215#define WM8995_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */
1216#define WM8995_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */
1217#define WM8995_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */
1218#define WM8995_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */
1219
1220/*
1221 * R80 (0x50) - DC Servo (1)
1222 */
1223#define WM8995_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */
1224#define WM8995_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */
1225#define WM8995_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */
1226#define WM8995_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */
1227#define WM8995_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */
1228#define WM8995_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */
1229#define WM8995_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */
1230#define WM8995_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */
1231#define WM8995_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */
1232#define WM8995_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */
1233#define WM8995_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */
1234#define WM8995_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */
1235#define WM8995_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
1236#define WM8995_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
1237#define WM8995_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */
1238#define WM8995_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */
1239
1240/*
1241 * R81 (0x51) - DC Servo (2)
1242 */
1243#define WM8995_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */
1244#define WM8995_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */
1245#define WM8995_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */
1246#define WM8995_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */
1247#define WM8995_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */
1248#define WM8995_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */
1249#define WM8995_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */
1250#define WM8995_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */
1251#define WM8995_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */
1252#define WM8995_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */
1253#define WM8995_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */
1254#define WM8995_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */
1255#define WM8995_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */
1256#define WM8995_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */
1257#define WM8995_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */
1258#define WM8995_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */
1259#define WM8995_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */
1260#define WM8995_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */
1261#define WM8995_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */
1262#define WM8995_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */
1263#define WM8995_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */
1264#define WM8995_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */
1265#define WM8995_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */
1266#define WM8995_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */
1267#define WM8995_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */
1268#define WM8995_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */
1269#define WM8995_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */
1270#define WM8995_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */
1271#define WM8995_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */
1272#define WM8995_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */
1273#define WM8995_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */
1274#define WM8995_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */
1275#define WM8995_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */
1276#define WM8995_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */
1277#define WM8995_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */
1278#define WM8995_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */
1279#define WM8995_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */
1280#define WM8995_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */
1281#define WM8995_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */
1282#define WM8995_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */
1283#define WM8995_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */
1284#define WM8995_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */
1285#define WM8995_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */
1286#define WM8995_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */
1287#define WM8995_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */
1288#define WM8995_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */
1289#define WM8995_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */
1290#define WM8995_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */
1291#define WM8995_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */
1292#define WM8995_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */
1293#define WM8995_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */
1294#define WM8995_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */
1295#define WM8995_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */
1296#define WM8995_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */
1297#define WM8995_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */
1298#define WM8995_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */
1299#define WM8995_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */
1300#define WM8995_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */
1301#define WM8995_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */
1302#define WM8995_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */
1303#define WM8995_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */
1304#define WM8995_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */
1305#define WM8995_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */
1306#define WM8995_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */
1307
1308/*
1309 * R82 (0x52) - DC Servo (3)
1310 */
1311#define WM8995_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */
1312#define WM8995_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */
1313#define WM8995_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */
1314#define WM8995_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
1315#define WM8995_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
1316#define WM8995_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
1317
1318/*
1319 * R84 (0x54) - DC Servo (5)
1320 */
1321#define WM8995_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */
1322#define WM8995_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */
1323#define WM8995_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */
1324#define WM8995_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */
1325#define WM8995_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */
1326#define WM8995_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */
1327
1328/*
1329 * R85 (0x55) - DC Servo (6)
1330 */
1331#define WM8995_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */
1332#define WM8995_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */
1333#define WM8995_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */
1334#define WM8995_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */
1335#define WM8995_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */
1336#define WM8995_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */
1337
1338/*
1339 * R86 (0x56) - DC Servo (7)
1340 */
1341#define WM8995_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */
1342#define WM8995_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
1343#define WM8995_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
1344#define WM8995_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
1345#define WM8995_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
1346#define WM8995_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
1347
1348/*
1349 * R87 (0x57) - DC Servo Readback 0
1350 */
1351#define WM8995_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */
1352#define WM8995_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */
1353#define WM8995_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */
1354#define WM8995_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */
1355#define WM8995_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
1356#define WM8995_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
1357#define WM8995_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */
1358#define WM8995_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */
1359#define WM8995_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */
1360
1361/*
1362 * R96 (0x60) - Analogue HP (1)
1363 */
1364#define WM8995_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */
1365#define WM8995_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */
1366#define WM8995_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */
1367#define WM8995_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */
1368#define WM8995_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */
1369#define WM8995_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */
1370#define WM8995_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */
1371#define WM8995_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */
1372#define WM8995_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */
1373#define WM8995_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */
1374#define WM8995_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */
1375#define WM8995_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */
1376#define WM8995_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */
1377#define WM8995_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */
1378#define WM8995_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */
1379#define WM8995_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */
1380#define WM8995_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */
1381#define WM8995_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */
1382#define WM8995_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */
1383#define WM8995_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */
1384#define WM8995_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */
1385#define WM8995_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */
1386#define WM8995_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */
1387#define WM8995_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
1388
1389/*
1390 * R97 (0x61) - Analogue HP (2)
1391 */
1392#define WM8995_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */
1393#define WM8995_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */
1394#define WM8995_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */
1395#define WM8995_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */
1396#define WM8995_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */
1397#define WM8995_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */
1398#define WM8995_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */
1399#define WM8995_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */
1400#define WM8995_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */
1401#define WM8995_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */
1402#define WM8995_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */
1403#define WM8995_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */
1404#define WM8995_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */
1405#define WM8995_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */
1406#define WM8995_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */
1407#define WM8995_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */
1408#define WM8995_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */
1409#define WM8995_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */
1410#define WM8995_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */
1411#define WM8995_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */
1412#define WM8995_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */
1413#define WM8995_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */
1414#define WM8995_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */
1415#define WM8995_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */
1416
1417/*
1418 * R256 (0x100) - Chip Revision
1419 */
1420#define WM8995_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */
1421#define WM8995_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */
1422#define WM8995_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */
1423
1424/*
1425 * R257 (0x101) - Control Interface (1)
1426 */
1427#define WM8995_REG_SYNC 0x8000 /* REG_SYNC */
1428#define WM8995_REG_SYNC_MASK 0x8000 /* REG_SYNC */
1429#define WM8995_REG_SYNC_SHIFT 15 /* REG_SYNC */
1430#define WM8995_REG_SYNC_WIDTH 1 /* REG_SYNC */
1431#define WM8995_SPI_CONTRD 0x0040 /* SPI_CONTRD */
1432#define WM8995_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */
1433#define WM8995_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */
1434#define WM8995_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */
1435#define WM8995_SPI_4WIRE 0x0020 /* SPI_4WIRE */
1436#define WM8995_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */
1437#define WM8995_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */
1438#define WM8995_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
1439#define WM8995_SPI_CFG 0x0010 /* SPI_CFG */
1440#define WM8995_SPI_CFG_MASK 0x0010 /* SPI_CFG */
1441#define WM8995_SPI_CFG_SHIFT 4 /* SPI_CFG */
1442#define WM8995_SPI_CFG_WIDTH 1 /* SPI_CFG */
1443#define WM8995_AUTO_INC 0x0004 /* AUTO_INC */
1444#define WM8995_AUTO_INC_MASK 0x0004 /* AUTO_INC */
1445#define WM8995_AUTO_INC_SHIFT 2 /* AUTO_INC */
1446#define WM8995_AUTO_INC_WIDTH 1 /* AUTO_INC */
1447
1448/*
1449 * R258 (0x102) - Control Interface (2)
1450 */
1451#define WM8995_CTRL_IF_SRC 0x0001 /* CTRL_IF_SRC */
1452#define WM8995_CTRL_IF_SRC_MASK 0x0001 /* CTRL_IF_SRC */
1453#define WM8995_CTRL_IF_SRC_SHIFT 0 /* CTRL_IF_SRC */
1454#define WM8995_CTRL_IF_SRC_WIDTH 1 /* CTRL_IF_SRC */
1455
1456/*
1457 * R272 (0x110) - Write Sequencer Ctrl (1)
1458 */
1459#define WM8995_WSEQ_ENA 0x8000 /* WSEQ_ENA */
1460#define WM8995_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
1461#define WM8995_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
1462#define WM8995_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
1463#define WM8995_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
1464#define WM8995_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
1465#define WM8995_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
1466#define WM8995_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
1467#define WM8995_WSEQ_START 0x0100 /* WSEQ_START */
1468#define WM8995_WSEQ_START_MASK 0x0100 /* WSEQ_START */
1469#define WM8995_WSEQ_START_SHIFT 8 /* WSEQ_START */
1470#define WM8995_WSEQ_START_WIDTH 1 /* WSEQ_START */
1471#define WM8995_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
1472#define WM8995_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
1473#define WM8995_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
1474
1475/*
1476 * R273 (0x111) - Write Sequencer Ctrl (2)
1477 */
1478#define WM8995_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */
1479#define WM8995_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */
1480#define WM8995_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */
1481#define WM8995_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
1482#define WM8995_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */
1483#define WM8995_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */
1484#define WM8995_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */
1485
1486/*
1487 * R512 (0x200) - AIF1 Clocking (1)
1488 */
1489#define WM8995_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */
1490#define WM8995_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */
1491#define WM8995_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */
1492#define WM8995_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */
1493#define WM8995_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */
1494#define WM8995_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */
1495#define WM8995_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */
1496#define WM8995_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */
1497#define WM8995_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */
1498#define WM8995_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */
1499#define WM8995_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */
1500#define WM8995_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */
1501#define WM8995_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */
1502#define WM8995_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */
1503#define WM8995_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */
1504
1505/*
1506 * R513 (0x201) - AIF1 Clocking (2)
1507 */
1508#define WM8995_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */
1509#define WM8995_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */
1510#define WM8995_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */
1511#define WM8995_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */
1512#define WM8995_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */
1513#define WM8995_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */
1514
1515/*
1516 * R516 (0x204) - AIF2 Clocking (1)
1517 */
1518#define WM8995_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */
1519#define WM8995_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */
1520#define WM8995_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */
1521#define WM8995_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */
1522#define WM8995_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */
1523#define WM8995_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */
1524#define WM8995_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */
1525#define WM8995_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */
1526#define WM8995_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */
1527#define WM8995_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */
1528#define WM8995_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */
1529#define WM8995_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */
1530#define WM8995_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */
1531#define WM8995_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */
1532#define WM8995_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */
1533
1534/*
1535 * R517 (0x205) - AIF2 Clocking (2)
1536 */
1537#define WM8995_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */
1538#define WM8995_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */
1539#define WM8995_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */
1540#define WM8995_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */
1541#define WM8995_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */
1542#define WM8995_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */
1543
1544/*
1545 * R520 (0x208) - Clocking (1)
1546 */
1547#define WM8995_LFCLK_ENA 0x0020 /* LFCLK_ENA */
1548#define WM8995_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */
1549#define WM8995_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */
1550#define WM8995_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */
1551#define WM8995_TOCLK_ENA 0x0010 /* TOCLK_ENA */
1552#define WM8995_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */
1553#define WM8995_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */
1554#define WM8995_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
1555#define WM8995_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */
1556#define WM8995_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */
1557#define WM8995_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */
1558#define WM8995_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */
1559#define WM8995_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */
1560#define WM8995_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */
1561#define WM8995_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */
1562#define WM8995_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */
1563#define WM8995_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */
1564#define WM8995_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */
1565#define WM8995_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */
1566#define WM8995_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */
1567#define WM8995_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */
1568#define WM8995_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */
1569#define WM8995_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */
1570#define WM8995_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */
1571
1572/*
1573 * R521 (0x209) - Clocking (2)
1574 */
1575#define WM8995_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */
1576#define WM8995_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */
1577#define WM8995_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */
1578#define WM8995_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */
1579#define WM8995_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */
1580#define WM8995_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */
1581#define WM8995_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */
1582#define WM8995_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */
1583#define WM8995_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */
1584
1585/*
1586 * R528 (0x210) - AIF1 Rate
1587 */
1588#define WM8995_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */
1589#define WM8995_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */
1590#define WM8995_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */
1591#define WM8995_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */
1592#define WM8995_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */
1593#define WM8995_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */
1594
1595/*
1596 * R529 (0x211) - AIF2 Rate
1597 */
1598#define WM8995_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */
1599#define WM8995_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */
1600#define WM8995_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */
1601#define WM8995_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */
1602#define WM8995_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */
1603#define WM8995_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */
1604
1605/*
1606 * R530 (0x212) - Rate Status
1607 */
1608#define WM8995_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */
1609#define WM8995_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */
1610#define WM8995_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */
1611
1612/*
1613 * R544 (0x220) - FLL1 Control (1)
1614 */
1615#define WM8995_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */
1616#define WM8995_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */
1617#define WM8995_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */
1618#define WM8995_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */
1619#define WM8995_FLL1_ENA 0x0001 /* FLL1_ENA */
1620#define WM8995_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */
1621#define WM8995_FLL1_ENA_SHIFT 0 /* FLL1_ENA */
1622#define WM8995_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
1623
1624/*
1625 * R545 (0x221) - FLL1 Control (2)
1626 */
1627#define WM8995_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */
1628#define WM8995_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */
1629#define WM8995_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */
1630#define WM8995_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */
1631#define WM8995_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */
1632#define WM8995_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */
1633#define WM8995_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */
1634#define WM8995_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */
1635#define WM8995_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */
1636
1637/*
1638 * R546 (0x222) - FLL1 Control (3)
1639 */
1640#define WM8995_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */
1641#define WM8995_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */
1642#define WM8995_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */
1643
1644/*
1645 * R547 (0x223) - FLL1 Control (4)
1646 */
1647#define WM8995_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */
1648#define WM8995_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */
1649#define WM8995_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */
1650#define WM8995_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */
1651#define WM8995_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */
1652#define WM8995_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */
1653
1654/*
1655 * R548 (0x224) - FLL1 Control (5)
1656 */
1657#define WM8995_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */
1658#define WM8995_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */
1659#define WM8995_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */
1660#define WM8995_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */
1661#define WM8995_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */
1662#define WM8995_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */
1663#define WM8995_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */
1664#define WM8995_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */
1665#define WM8995_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */
1666#define WM8995_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */
1667#define WM8995_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */
1668#define WM8995_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */
1669#define WM8995_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */
1670
1671/*
1672 * R576 (0x240) - FLL2 Control (1)
1673 */
1674#define WM8995_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */
1675#define WM8995_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */
1676#define WM8995_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */
1677#define WM8995_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */
1678#define WM8995_FLL2_ENA 0x0001 /* FLL2_ENA */
1679#define WM8995_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */
1680#define WM8995_FLL2_ENA_SHIFT 0 /* FLL2_ENA */
1681#define WM8995_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
1682
1683/*
1684 * R577 (0x241) - FLL2 Control (2)
1685 */
1686#define WM8995_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */
1687#define WM8995_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */
1688#define WM8995_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */
1689#define WM8995_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */
1690#define WM8995_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */
1691#define WM8995_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */
1692#define WM8995_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */
1693#define WM8995_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */
1694#define WM8995_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */
1695
1696/*
1697 * R578 (0x242) - FLL2 Control (3)
1698 */
1699#define WM8995_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */
1700#define WM8995_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */
1701#define WM8995_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */
1702
1703/*
1704 * R579 (0x243) - FLL2 Control (4)
1705 */
1706#define WM8995_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */
1707#define WM8995_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */
1708#define WM8995_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */
1709#define WM8995_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */
1710#define WM8995_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */
1711#define WM8995_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */
1712
1713/*
1714 * R580 (0x244) - FLL2 Control (5)
1715 */
1716#define WM8995_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */
1717#define WM8995_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */
1718#define WM8995_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */
1719#define WM8995_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */
1720#define WM8995_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */
1721#define WM8995_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */
1722#define WM8995_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */
1723#define WM8995_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */
1724#define WM8995_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */
1725#define WM8995_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */
1726#define WM8995_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */
1727#define WM8995_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */
1728#define WM8995_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */
1729
1730/*
1731 * R768 (0x300) - AIF1 Control (1)
1732 */
1733#define WM8995_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */
1734#define WM8995_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */
1735#define WM8995_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */
1736#define WM8995_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */
1737#define WM8995_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */
1738#define WM8995_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */
1739#define WM8995_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */
1740#define WM8995_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */
1741#define WM8995_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */
1742#define WM8995_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */
1743#define WM8995_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */
1744#define WM8995_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */
1745#define WM8995_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */
1746#define WM8995_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */
1747#define WM8995_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */
1748#define WM8995_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
1749#define WM8995_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */
1750#define WM8995_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */
1751#define WM8995_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */
1752#define WM8995_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */
1753#define WM8995_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */
1754#define WM8995_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */
1755#define WM8995_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */
1756#define WM8995_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */
1757#define WM8995_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */
1758#define WM8995_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */
1759
1760/*
1761 * R769 (0x301) - AIF1 Control (2)
1762 */
1763#define WM8995_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */
1764#define WM8995_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */
1765#define WM8995_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */
1766#define WM8995_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */
1767#define WM8995_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */
1768#define WM8995_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */
1769#define WM8995_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */
1770#define WM8995_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */
1771#define WM8995_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */
1772#define WM8995_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */
1773#define WM8995_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */
1774#define WM8995_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */
1775#define WM8995_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */
1776#define WM8995_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */
1777#define WM8995_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */
1778#define WM8995_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */
1779#define WM8995_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */
1780#define WM8995_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */
1781#define WM8995_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */
1782#define WM8995_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */
1783#define WM8995_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */
1784#define WM8995_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */
1785#define WM8995_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */
1786#define WM8995_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */
1787#define WM8995_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */
1788#define WM8995_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */
1789#define WM8995_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */
1790#define WM8995_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */
1791#define WM8995_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */
1792#define WM8995_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */
1793#define WM8995_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */
1794
1795/*
1796 * R770 (0x302) - AIF1 Master/Slave
1797 */
1798#define WM8995_AIF1_TRI 0x8000 /* AIF1_TRI */
1799#define WM8995_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */
1800#define WM8995_AIF1_TRI_SHIFT 15 /* AIF1_TRI */
1801#define WM8995_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
1802#define WM8995_AIF1_MSTR 0x4000 /* AIF1_MSTR */
1803#define WM8995_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */
1804#define WM8995_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */
1805#define WM8995_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */
1806#define WM8995_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */
1807#define WM8995_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */
1808#define WM8995_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */
1809#define WM8995_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */
1810#define WM8995_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */
1811#define WM8995_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */
1812#define WM8995_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */
1813#define WM8995_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */
1814
1815/*
1816 * R771 (0x303) - AIF1 BCLK
1817 */
1818#define WM8995_AIF1_BCLK_DIV_MASK 0x00F0 /* AIF1_BCLK_DIV - [7:4] */
1819#define WM8995_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [7:4] */
1820#define WM8995_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [7:4] */
1821
1822/*
1823 * R772 (0x304) - AIF1ADC LRCLK
1824 */
1825#define WM8995_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */
1826#define WM8995_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */
1827#define WM8995_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */
1828#define WM8995_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */
1829#define WM8995_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */
1830#define WM8995_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */
1831#define WM8995_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */
1832
1833/*
1834 * R773 (0x305) - AIF1DAC LRCLK
1835 */
1836#define WM8995_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */
1837#define WM8995_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */
1838#define WM8995_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */
1839#define WM8995_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */
1840#define WM8995_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */
1841#define WM8995_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */
1842#define WM8995_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */
1843
1844/*
1845 * R774 (0x306) - AIF1DAC Data
1846 */
1847#define WM8995_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */
1848#define WM8995_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */
1849#define WM8995_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */
1850#define WM8995_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */
1851#define WM8995_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */
1852#define WM8995_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */
1853#define WM8995_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */
1854#define WM8995_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */
1855
1856/*
1857 * R775 (0x307) - AIF1ADC Data
1858 */
1859#define WM8995_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */
1860#define WM8995_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */
1861#define WM8995_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */
1862#define WM8995_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */
1863#define WM8995_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */
1864#define WM8995_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */
1865#define WM8995_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */
1866#define WM8995_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */
1867
1868/*
1869 * R784 (0x310) - AIF2 Control (1)
1870 */
1871#define WM8995_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */
1872#define WM8995_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */
1873#define WM8995_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */
1874#define WM8995_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */
1875#define WM8995_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */
1876#define WM8995_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */
1877#define WM8995_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */
1878#define WM8995_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */
1879#define WM8995_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */
1880#define WM8995_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */
1881#define WM8995_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */
1882#define WM8995_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */
1883#define WM8995_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */
1884#define WM8995_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */
1885#define WM8995_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */
1886#define WM8995_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */
1887#define WM8995_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */
1888#define WM8995_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */
1889#define WM8995_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */
1890#define WM8995_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
1891#define WM8995_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */
1892#define WM8995_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */
1893#define WM8995_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */
1894#define WM8995_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */
1895#define WM8995_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */
1896#define WM8995_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */
1897#define WM8995_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */
1898#define WM8995_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */
1899#define WM8995_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */
1900#define WM8995_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */
1901
1902/*
1903 * R785 (0x311) - AIF2 Control (2)
1904 */
1905#define WM8995_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */
1906#define WM8995_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */
1907#define WM8995_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */
1908#define WM8995_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */
1909#define WM8995_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */
1910#define WM8995_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */
1911#define WM8995_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */
1912#define WM8995_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */
1913#define WM8995_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */
1914#define WM8995_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */
1915#define WM8995_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */
1916#define WM8995_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */
1917#define WM8995_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */
1918#define WM8995_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */
1919#define WM8995_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */
1920#define WM8995_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */
1921#define WM8995_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */
1922#define WM8995_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */
1923#define WM8995_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */
1924#define WM8995_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */
1925#define WM8995_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */
1926#define WM8995_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */
1927#define WM8995_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */
1928#define WM8995_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */
1929#define WM8995_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */
1930#define WM8995_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */
1931#define WM8995_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */
1932#define WM8995_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */
1933#define WM8995_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */
1934#define WM8995_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */
1935#define WM8995_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */
1936#define WM8995_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */
1937#define WM8995_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */
1938#define WM8995_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */
1939#define WM8995_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */
1940#define WM8995_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */
1941#define WM8995_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */
1942#define WM8995_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */
1943#define WM8995_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */
1944
1945/*
1946 * R786 (0x312) - AIF2 Master/Slave
1947 */
1948#define WM8995_AIF2_TRI 0x8000 /* AIF2_TRI */
1949#define WM8995_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */
1950#define WM8995_AIF2_TRI_SHIFT 15 /* AIF2_TRI */
1951#define WM8995_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
1952#define WM8995_AIF2_MSTR 0x4000 /* AIF2_MSTR */
1953#define WM8995_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */
1954#define WM8995_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */
1955#define WM8995_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */
1956#define WM8995_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */
1957#define WM8995_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */
1958#define WM8995_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */
1959#define WM8995_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */
1960#define WM8995_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */
1961#define WM8995_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */
1962#define WM8995_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */
1963#define WM8995_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */
1964
1965/*
1966 * R787 (0x313) - AIF2 BCLK
1967 */
1968#define WM8995_AIF2_BCLK_DIV_MASK 0x00F0 /* AIF2_BCLK_DIV - [7:4] */
1969#define WM8995_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [7:4] */
1970#define WM8995_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [7:4] */
1971
1972/*
1973 * R788 (0x314) - AIF2ADC LRCLK
1974 */
1975#define WM8995_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */
1976#define WM8995_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */
1977#define WM8995_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */
1978#define WM8995_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */
1979#define WM8995_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */
1980#define WM8995_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */
1981#define WM8995_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */
1982
1983/*
1984 * R789 (0x315) - AIF2DAC LRCLK
1985 */
1986#define WM8995_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */
1987#define WM8995_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */
1988#define WM8995_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */
1989#define WM8995_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */
1990#define WM8995_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */
1991#define WM8995_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */
1992#define WM8995_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */
1993
1994/*
1995 * R790 (0x316) - AIF2DAC Data
1996 */
1997#define WM8995_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */
1998#define WM8995_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */
1999#define WM8995_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */
2000#define WM8995_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */
2001#define WM8995_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */
2002#define WM8995_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */
2003#define WM8995_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */
2004#define WM8995_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */
2005
2006/*
2007 * R791 (0x317) - AIF2ADC Data
2008 */
2009#define WM8995_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */
2010#define WM8995_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */
2011#define WM8995_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */
2012#define WM8995_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */
2013#define WM8995_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */
2014#define WM8995_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */
2015#define WM8995_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */
2016#define WM8995_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */
2017
2018/*
2019 * R1024 (0x400) - AIF1 ADC1 Left Volume
2020 */
2021#define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
2022#define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */
2023#define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */
2024#define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
2025#define WM8995_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */
2026#define WM8995_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */
2027#define WM8995_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */
2028
2029/*
2030 * R1025 (0x401) - AIF1 ADC1 Right Volume
2031 */
2032#define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
2033#define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */
2034#define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */
2035#define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
2036#define WM8995_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */
2037#define WM8995_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */
2038#define WM8995_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */
2039
2040/*
2041 * R1026 (0x402) - AIF1 DAC1 Left Volume
2042 */
2043#define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */
2044#define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */
2045#define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */
2046#define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
2047#define WM8995_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */
2048#define WM8995_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */
2049#define WM8995_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */
2050
2051/*
2052 * R1027 (0x403) - AIF1 DAC1 Right Volume
2053 */
2054#define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */
2055#define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */
2056#define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */
2057#define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
2058#define WM8995_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */
2059#define WM8995_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */
2060#define WM8995_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */
2061
2062/*
2063 * R1028 (0x404) - AIF1 ADC2 Left Volume
2064 */
2065#define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */
2066#define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */
2067#define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */
2068#define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
2069#define WM8995_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */
2070#define WM8995_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */
2071#define WM8995_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */
2072
2073/*
2074 * R1029 (0x405) - AIF1 ADC2 Right Volume
2075 */
2076#define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */
2077#define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */
2078#define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */
2079#define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
2080#define WM8995_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */
2081#define WM8995_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */
2082#define WM8995_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */
2083
2084/*
2085 * R1030 (0x406) - AIF1 DAC2 Left Volume
2086 */
2087#define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */
2088#define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */
2089#define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */
2090#define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
2091#define WM8995_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */
2092#define WM8995_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */
2093#define WM8995_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */
2094
2095/*
2096 * R1031 (0x407) - AIF1 DAC2 Right Volume
2097 */
2098#define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */
2099#define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */
2100#define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */
2101#define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
2102#define WM8995_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */
2103#define WM8995_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */
2104#define WM8995_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */
2105
2106/*
2107 * R1040 (0x410) - AIF1 ADC1 Filters
2108 */
2109#define WM8995_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */
2110#define WM8995_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */
2111#define WM8995_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */
2112#define WM8995_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */
2113#define WM8995_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */
2114#define WM8995_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */
2115#define WM8995_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */
2116#define WM8995_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */
2117#define WM8995_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */
2118#define WM8995_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */
2119#define WM8995_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */
2120#define WM8995_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */
2121#define WM8995_AIF1ADC1_HPF_MODE 0x0008 /* AIF1ADC1_HPF_MODE */
2122#define WM8995_AIF1ADC1_HPF_MODE_MASK 0x0008 /* AIF1ADC1_HPF_MODE */
2123#define WM8995_AIF1ADC1_HPF_MODE_SHIFT 3 /* AIF1ADC1_HPF_MODE */
2124#define WM8995_AIF1ADC1_HPF_MODE_WIDTH 1 /* AIF1ADC1_HPF_MODE */
2125#define WM8995_AIF1ADC1_HPF_CUT_MASK 0x0007 /* AIF1ADC1_HPF_CUT - [2:0] */
2126#define WM8995_AIF1ADC1_HPF_CUT_SHIFT 0 /* AIF1ADC1_HPF_CUT - [2:0] */
2127#define WM8995_AIF1ADC1_HPF_CUT_WIDTH 3 /* AIF1ADC1_HPF_CUT - [2:0] */
2128
2129/*
2130 * R1041 (0x411) - AIF1 ADC2 Filters
2131 */
2132#define WM8995_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */
2133#define WM8995_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */
2134#define WM8995_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */
2135#define WM8995_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */
2136#define WM8995_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */
2137#define WM8995_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */
2138#define WM8995_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */
2139#define WM8995_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */
2140#define WM8995_AIF1ADC2_HPF_MODE 0x0008 /* AIF1ADC2_HPF_MODE */
2141#define WM8995_AIF1ADC2_HPF_MODE_MASK 0x0008 /* AIF1ADC2_HPF_MODE */
2142#define WM8995_AIF1ADC2_HPF_MODE_SHIFT 3 /* AIF1ADC2_HPF_MODE */
2143#define WM8995_AIF1ADC2_HPF_MODE_WIDTH 1 /* AIF1ADC2_HPF_MODE */
2144#define WM8995_AIF1ADC2_HPF_CUT_MASK 0x0007 /* AIF1ADC2_HPF_CUT - [2:0] */
2145#define WM8995_AIF1ADC2_HPF_CUT_SHIFT 0 /* AIF1ADC2_HPF_CUT - [2:0] */
2146#define WM8995_AIF1ADC2_HPF_CUT_WIDTH 3 /* AIF1ADC2_HPF_CUT - [2:0] */
2147
2148/*
2149 * R1056 (0x420) - AIF1 DAC1 Filters (1)
2150 */
2151#define WM8995_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */
2152#define WM8995_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */
2153#define WM8995_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */
2154#define WM8995_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */
2155#define WM8995_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */
2156#define WM8995_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */
2157#define WM8995_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */
2158#define WM8995_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */
2159#define WM8995_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */
2160#define WM8995_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */
2161#define WM8995_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */
2162#define WM8995_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */
2163#define WM8995_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */
2164#define WM8995_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */
2165#define WM8995_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */
2166#define WM8995_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */
2167#define WM8995_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */
2168#define WM8995_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */
2169#define WM8995_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */
2170
2171/*
2172 * R1057 (0x421) - AIF1 DAC1 Filters (2)
2173 */
2174#define WM8995_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */
2175#define WM8995_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */
2176#define WM8995_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */
2177#define WM8995_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */
2178#define WM8995_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */
2179#define WM8995_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */
2180#define WM8995_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */
2181
2182/*
2183 * R1058 (0x422) - AIF1 DAC2 Filters (1)
2184 */
2185#define WM8995_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */
2186#define WM8995_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */
2187#define WM8995_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */
2188#define WM8995_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */
2189#define WM8995_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */
2190#define WM8995_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */
2191#define WM8995_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */
2192#define WM8995_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */
2193#define WM8995_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */
2194#define WM8995_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */
2195#define WM8995_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */
2196#define WM8995_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */
2197#define WM8995_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */
2198#define WM8995_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */
2199#define WM8995_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */
2200#define WM8995_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */
2201#define WM8995_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */
2202#define WM8995_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */
2203#define WM8995_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */
2204
2205/*
2206 * R1059 (0x423) - AIF1 DAC2 Filters (2)
2207 */
2208#define WM8995_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */
2209#define WM8995_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */
2210#define WM8995_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */
2211#define WM8995_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */
2212#define WM8995_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */
2213#define WM8995_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */
2214#define WM8995_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */
2215
2216/*
2217 * R1088 (0x440) - AIF1 DRC1 (1)
2218 */
2219#define WM8995_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
2220#define WM8995_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
2221#define WM8995_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
2222#define WM8995_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */
2223#define WM8995_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */
2224#define WM8995_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */
2225#define WM8995_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */
2226#define WM8995_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */
2227#define WM8995_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */
2228#define WM8995_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */
2229#define WM8995_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */
2230#define WM8995_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */
2231#define WM8995_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */
2232#define WM8995_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */
2233#define WM8995_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */
2234#define WM8995_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */
2235#define WM8995_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */
2236#define WM8995_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */
2237#define WM8995_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */
2238#define WM8995_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */
2239#define WM8995_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */
2240#define WM8995_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */
2241#define WM8995_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */
2242#define WM8995_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */
2243#define WM8995_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */
2244#define WM8995_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */
2245#define WM8995_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */
2246#define WM8995_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */
2247#define WM8995_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */
2248#define WM8995_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */
2249#define WM8995_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */
2250#define WM8995_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */
2251#define WM8995_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */
2252#define WM8995_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */
2253#define WM8995_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */
2254#define WM8995_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */
2255#define WM8995_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */
2256#define WM8995_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */
2257#define WM8995_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */
2258#define WM8995_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */
2259#define WM8995_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */
2260#define WM8995_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */
2261
2262/*
2263 * R1089 (0x441) - AIF1 DRC1 (2)
2264 */
2265#define WM8995_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */
2266#define WM8995_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */
2267#define WM8995_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */
2268#define WM8995_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */
2269#define WM8995_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */
2270#define WM8995_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */
2271#define WM8995_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */
2272#define WM8995_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */
2273#define WM8995_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */
2274#define WM8995_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */
2275#define WM8995_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */
2276#define WM8995_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */
2277
2278/*
2279 * R1090 (0x442) - AIF1 DRC1 (3)
2280 */
2281#define WM8995_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */
2282#define WM8995_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */
2283#define WM8995_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */
2284#define WM8995_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */
2285#define WM8995_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */
2286#define WM8995_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */
2287#define WM8995_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */
2288#define WM8995_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */
2289#define WM8995_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */
2290#define WM8995_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */
2291#define WM8995_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */
2292#define WM8995_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */
2293#define WM8995_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */
2294#define WM8995_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */
2295#define WM8995_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */
2296#define WM8995_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */
2297#define WM8995_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */
2298#define WM8995_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */
2299
2300/*
2301 * R1091 (0x443) - AIF1 DRC1 (4)
2302 */
2303#define WM8995_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */
2304#define WM8995_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */
2305#define WM8995_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */
2306#define WM8995_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */
2307#define WM8995_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */
2308#define WM8995_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */
2309
2310/*
2311 * R1092 (0x444) - AIF1 DRC1 (5)
2312 */
2313#define WM8995_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */
2314#define WM8995_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
2315#define WM8995_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
2316#define WM8995_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */
2317#define WM8995_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */
2318#define WM8995_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */
2319
2320/*
2321 * R1104 (0x450) - AIF1 DRC2 (1)
2322 */
2323#define WM8995_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
2324#define WM8995_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
2325#define WM8995_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
2326#define WM8995_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */
2327#define WM8995_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */
2328#define WM8995_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */
2329#define WM8995_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */
2330#define WM8995_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */
2331#define WM8995_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */
2332#define WM8995_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */
2333#define WM8995_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */
2334#define WM8995_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */
2335#define WM8995_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */
2336#define WM8995_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */
2337#define WM8995_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */
2338#define WM8995_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */
2339#define WM8995_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */
2340#define WM8995_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */
2341#define WM8995_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */
2342#define WM8995_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */
2343#define WM8995_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */
2344#define WM8995_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */
2345#define WM8995_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */
2346#define WM8995_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */
2347#define WM8995_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */
2348#define WM8995_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */
2349#define WM8995_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */
2350#define WM8995_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */
2351#define WM8995_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */
2352#define WM8995_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */
2353#define WM8995_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */
2354#define WM8995_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */
2355#define WM8995_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */
2356#define WM8995_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */
2357#define WM8995_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */
2358#define WM8995_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */
2359#define WM8995_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */
2360#define WM8995_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */
2361#define WM8995_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */
2362#define WM8995_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */
2363#define WM8995_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */
2364#define WM8995_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */
2365
2366/*
2367 * R1105 (0x451) - AIF1 DRC2 (2)
2368 */
2369#define WM8995_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */
2370#define WM8995_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */
2371#define WM8995_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */
2372#define WM8995_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */
2373#define WM8995_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */
2374#define WM8995_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */
2375#define WM8995_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */
2376#define WM8995_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */
2377#define WM8995_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */
2378#define WM8995_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */
2379#define WM8995_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */
2380#define WM8995_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */
2381
2382/*
2383 * R1106 (0x452) - AIF1 DRC2 (3)
2384 */
2385#define WM8995_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */
2386#define WM8995_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */
2387#define WM8995_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */
2388#define WM8995_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */
2389#define WM8995_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */
2390#define WM8995_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */
2391#define WM8995_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */
2392#define WM8995_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */
2393#define WM8995_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */
2394#define WM8995_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */
2395#define WM8995_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */
2396#define WM8995_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */
2397#define WM8995_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */
2398#define WM8995_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */
2399#define WM8995_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */
2400#define WM8995_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */
2401#define WM8995_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */
2402#define WM8995_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */
2403
2404/*
2405 * R1107 (0x453) - AIF1 DRC2 (4)
2406 */
2407#define WM8995_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */
2408#define WM8995_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */
2409#define WM8995_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */
2410#define WM8995_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */
2411#define WM8995_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */
2412#define WM8995_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */
2413
2414/*
2415 * R1108 (0x454) - AIF1 DRC2 (5)
2416 */
2417#define WM8995_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */
2418#define WM8995_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
2419#define WM8995_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
2420#define WM8995_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */
2421#define WM8995_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */
2422#define WM8995_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */
2423
2424/*
2425 * R1152 (0x480) - AIF1 DAC1 EQ Gains (1)
2426 */
2427#define WM8995_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
2428#define WM8995_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
2429#define WM8995_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
2430#define WM8995_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
2431#define WM8995_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
2432#define WM8995_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
2433#define WM8995_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
2434#define WM8995_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
2435#define WM8995_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
2436#define WM8995_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */
2437#define WM8995_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */
2438#define WM8995_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */
2439#define WM8995_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */
2440
2441/*
2442 * R1153 (0x481) - AIF1 DAC1 EQ Gains (2)
2443 */
2444#define WM8995_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
2445#define WM8995_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
2446#define WM8995_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
2447#define WM8995_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
2448#define WM8995_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
2449#define WM8995_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
2450
2451/*
2452 * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A
2453 */
2454#define WM8995_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */
2455#define WM8995_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */
2456#define WM8995_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */
2457
2458/*
2459 * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B
2460 */
2461#define WM8995_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */
2462#define WM8995_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */
2463#define WM8995_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */
2464
2465/*
2466 * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG
2467 */
2468#define WM8995_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */
2469#define WM8995_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */
2470#define WM8995_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */
2471
2472/*
2473 * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A
2474 */
2475#define WM8995_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */
2476#define WM8995_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */
2477#define WM8995_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */
2478
2479/*
2480 * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B
2481 */
2482#define WM8995_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */
2483#define WM8995_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */
2484#define WM8995_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */
2485
2486/*
2487 * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C
2488 */
2489#define WM8995_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */
2490#define WM8995_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */
2491#define WM8995_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */
2492
2493/*
2494 * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG
2495 */
2496#define WM8995_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */
2497#define WM8995_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */
2498#define WM8995_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */
2499
2500/*
2501 * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A
2502 */
2503#define WM8995_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */
2504#define WM8995_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */
2505#define WM8995_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */
2506
2507/*
2508 * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B
2509 */
2510#define WM8995_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */
2511#define WM8995_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */
2512#define WM8995_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */
2513
2514/*
2515 * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C
2516 */
2517#define WM8995_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */
2518#define WM8995_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */
2519#define WM8995_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */
2520
2521/*
2522 * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG
2523 */
2524#define WM8995_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */
2525#define WM8995_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */
2526#define WM8995_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */
2527
2528/*
2529 * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A
2530 */
2531#define WM8995_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */
2532#define WM8995_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */
2533#define WM8995_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */
2534
2535/*
2536 * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B
2537 */
2538#define WM8995_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */
2539#define WM8995_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */
2540#define WM8995_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */
2541
2542/*
2543 * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C
2544 */
2545#define WM8995_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */
2546#define WM8995_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */
2547#define WM8995_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */
2548
2549/*
2550 * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG
2551 */
2552#define WM8995_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */
2553#define WM8995_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */
2554#define WM8995_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */
2555
2556/*
2557 * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A
2558 */
2559#define WM8995_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */
2560#define WM8995_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */
2561#define WM8995_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */
2562
2563/*
2564 * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B
2565 */
2566#define WM8995_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */
2567#define WM8995_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */
2568#define WM8995_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */
2569
2570/*
2571 * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG
2572 */
2573#define WM8995_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */
2574#define WM8995_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */
2575#define WM8995_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */
2576
2577/*
2578 * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1)
2579 */
2580#define WM8995_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
2581#define WM8995_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
2582#define WM8995_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
2583#define WM8995_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
2584#define WM8995_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
2585#define WM8995_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
2586#define WM8995_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
2587#define WM8995_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
2588#define WM8995_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
2589#define WM8995_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */
2590#define WM8995_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */
2591#define WM8995_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */
2592#define WM8995_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */
2593
2594/*
2595 * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2)
2596 */
2597#define WM8995_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
2598#define WM8995_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
2599#define WM8995_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
2600#define WM8995_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
2601#define WM8995_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
2602#define WM8995_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
2603
2604/*
2605 * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A
2606 */
2607#define WM8995_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */
2608#define WM8995_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */
2609#define WM8995_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */
2610
2611/*
2612 * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B
2613 */
2614#define WM8995_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */
2615#define WM8995_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */
2616#define WM8995_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */
2617
2618/*
2619 * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG
2620 */
2621#define WM8995_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */
2622#define WM8995_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */
2623#define WM8995_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */
2624
2625/*
2626 * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A
2627 */
2628#define WM8995_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */
2629#define WM8995_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */
2630#define WM8995_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */
2631
2632/*
2633 * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B
2634 */
2635#define WM8995_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */
2636#define WM8995_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */
2637#define WM8995_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */
2638
2639/*
2640 * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C
2641 */
2642#define WM8995_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */
2643#define WM8995_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */
2644#define WM8995_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */
2645
2646/*
2647 * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG
2648 */
2649#define WM8995_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */
2650#define WM8995_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */
2651#define WM8995_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */
2652
2653/*
2654 * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A
2655 */
2656#define WM8995_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */
2657#define WM8995_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */
2658#define WM8995_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */
2659
2660/*
2661 * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B
2662 */
2663#define WM8995_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */
2664#define WM8995_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */
2665#define WM8995_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */
2666
2667/*
2668 * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C
2669 */
2670#define WM8995_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */
2671#define WM8995_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */
2672#define WM8995_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */
2673
2674/*
2675 * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG
2676 */
2677#define WM8995_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */
2678#define WM8995_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */
2679#define WM8995_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */
2680
2681/*
2682 * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A
2683 */
2684#define WM8995_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */
2685#define WM8995_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */
2686#define WM8995_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */
2687
2688/*
2689 * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B
2690 */
2691#define WM8995_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */
2692#define WM8995_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */
2693#define WM8995_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */
2694
2695/*
2696 * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C
2697 */
2698#define WM8995_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */
2699#define WM8995_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */
2700#define WM8995_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */
2701
2702/*
2703 * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG
2704 */
2705#define WM8995_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */
2706#define WM8995_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */
2707#define WM8995_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */
2708
2709/*
2710 * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A
2711 */
2712#define WM8995_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */
2713#define WM8995_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */
2714#define WM8995_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */
2715
2716/*
2717 * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B
2718 */
2719#define WM8995_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */
2720#define WM8995_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */
2721#define WM8995_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */
2722
2723/*
2724 * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG
2725 */
2726#define WM8995_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */
2727#define WM8995_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */
2728#define WM8995_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */
2729
2730/*
2731 * R1280 (0x500) - AIF2 ADC Left Volume
2732 */
2733#define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */
2734#define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */
2735#define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */
2736#define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
2737#define WM8995_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */
2738#define WM8995_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */
2739#define WM8995_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */
2740
2741/*
2742 * R1281 (0x501) - AIF2 ADC Right Volume
2743 */
2744#define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */
2745#define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */
2746#define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */
2747#define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
2748#define WM8995_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */
2749#define WM8995_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */
2750#define WM8995_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */
2751
2752/*
2753 * R1282 (0x502) - AIF2 DAC Left Volume
2754 */
2755#define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */
2756#define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */
2757#define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */
2758#define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
2759#define WM8995_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */
2760#define WM8995_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */
2761#define WM8995_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */
2762
2763/*
2764 * R1283 (0x503) - AIF2 DAC Right Volume
2765 */
2766#define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */
2767#define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */
2768#define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */
2769#define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
2770#define WM8995_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */
2771#define WM8995_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */
2772#define WM8995_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */
2773
2774/*
2775 * R1296 (0x510) - AIF2 ADC Filters
2776 */
2777#define WM8995_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */
2778#define WM8995_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */
2779#define WM8995_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */
2780#define WM8995_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */
2781#define WM8995_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */
2782#define WM8995_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */
2783#define WM8995_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */
2784#define WM8995_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */
2785#define WM8995_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */
2786#define WM8995_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */
2787#define WM8995_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */
2788#define WM8995_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */
2789#define WM8995_AIF2ADC_HPF_MODE 0x0008 /* AIF2ADC_HPF_MODE */
2790#define WM8995_AIF2ADC_HPF_MODE_MASK 0x0008 /* AIF2ADC_HPF_MODE */
2791#define WM8995_AIF2ADC_HPF_MODE_SHIFT 3 /* AIF2ADC_HPF_MODE */
2792#define WM8995_AIF2ADC_HPF_MODE_WIDTH 1 /* AIF2ADC_HPF_MODE */
2793#define WM8995_AIF2ADC_HPF_CUT_MASK 0x0007 /* AIF2ADC_HPF_CUT - [2:0] */
2794#define WM8995_AIF2ADC_HPF_CUT_SHIFT 0 /* AIF2ADC_HPF_CUT - [2:0] */
2795#define WM8995_AIF2ADC_HPF_CUT_WIDTH 3 /* AIF2ADC_HPF_CUT - [2:0] */
2796
2797/*
2798 * R1312 (0x520) - AIF2 DAC Filters (1)
2799 */
2800#define WM8995_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */
2801#define WM8995_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */
2802#define WM8995_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */
2803#define WM8995_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */
2804#define WM8995_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */
2805#define WM8995_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */
2806#define WM8995_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */
2807#define WM8995_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */
2808#define WM8995_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */
2809#define WM8995_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */
2810#define WM8995_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */
2811#define WM8995_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */
2812#define WM8995_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */
2813#define WM8995_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */
2814#define WM8995_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */
2815#define WM8995_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */
2816#define WM8995_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */
2817#define WM8995_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */
2818#define WM8995_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */
2819
2820/*
2821 * R1313 (0x521) - AIF2 DAC Filters (2)
2822 */
2823#define WM8995_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */
2824#define WM8995_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */
2825#define WM8995_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */
2826#define WM8995_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */
2827#define WM8995_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */
2828#define WM8995_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */
2829#define WM8995_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */
2830
2831/*
2832 * R1344 (0x540) - AIF2 DRC (1)
2833 */
2834#define WM8995_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */
2835#define WM8995_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */
2836#define WM8995_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */
2837#define WM8995_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */
2838#define WM8995_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */
2839#define WM8995_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */
2840#define WM8995_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */
2841#define WM8995_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */
2842#define WM8995_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */
2843#define WM8995_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */
2844#define WM8995_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */
2845#define WM8995_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */
2846#define WM8995_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */
2847#define WM8995_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */
2848#define WM8995_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */
2849#define WM8995_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */
2850#define WM8995_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */
2851#define WM8995_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */
2852#define WM8995_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */
2853#define WM8995_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */
2854#define WM8995_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */
2855#define WM8995_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */
2856#define WM8995_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */
2857#define WM8995_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */
2858#define WM8995_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */
2859#define WM8995_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */
2860#define WM8995_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */
2861#define WM8995_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */
2862#define WM8995_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */
2863#define WM8995_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */
2864#define WM8995_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */
2865#define WM8995_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */
2866#define WM8995_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */
2867#define WM8995_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */
2868#define WM8995_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */
2869#define WM8995_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */
2870#define WM8995_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */
2871#define WM8995_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */
2872#define WM8995_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */
2873#define WM8995_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */
2874#define WM8995_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */
2875#define WM8995_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */
2876
2877/*
2878 * R1345 (0x541) - AIF2 DRC (2)
2879 */
2880#define WM8995_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */
2881#define WM8995_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */
2882#define WM8995_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */
2883#define WM8995_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */
2884#define WM8995_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */
2885#define WM8995_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */
2886#define WM8995_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */
2887#define WM8995_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */
2888#define WM8995_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */
2889#define WM8995_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */
2890#define WM8995_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */
2891#define WM8995_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */
2892
2893/*
2894 * R1346 (0x542) - AIF2 DRC (3)
2895 */
2896#define WM8995_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */
2897#define WM8995_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */
2898#define WM8995_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */
2899#define WM8995_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */
2900#define WM8995_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */
2901#define WM8995_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */
2902#define WM8995_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */
2903#define WM8995_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */
2904#define WM8995_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */
2905#define WM8995_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */
2906#define WM8995_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */
2907#define WM8995_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */
2908#define WM8995_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */
2909#define WM8995_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */
2910#define WM8995_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */
2911#define WM8995_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */
2912#define WM8995_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */
2913#define WM8995_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */
2914
2915/*
2916 * R1347 (0x543) - AIF2 DRC (4)
2917 */
2918#define WM8995_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */
2919#define WM8995_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */
2920#define WM8995_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */
2921#define WM8995_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */
2922#define WM8995_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */
2923#define WM8995_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */
2924
2925/*
2926 * R1348 (0x544) - AIF2 DRC (5)
2927 */
2928#define WM8995_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */
2929#define WM8995_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */
2930#define WM8995_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */
2931#define WM8995_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */
2932#define WM8995_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */
2933#define WM8995_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */
2934
2935/*
2936 * R1408 (0x580) - AIF2 EQ Gains (1)
2937 */
2938#define WM8995_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
2939#define WM8995_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
2940#define WM8995_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
2941#define WM8995_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
2942#define WM8995_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
2943#define WM8995_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
2944#define WM8995_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */
2945#define WM8995_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
2946#define WM8995_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
2947#define WM8995_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */
2948#define WM8995_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */
2949#define WM8995_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */
2950#define WM8995_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */
2951
2952/*
2953 * R1409 (0x581) - AIF2 EQ Gains (2)
2954 */
2955#define WM8995_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
2956#define WM8995_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
2957#define WM8995_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
2958#define WM8995_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
2959#define WM8995_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
2960#define WM8995_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
2961
2962/*
2963 * R1410 (0x582) - AIF2 EQ Band 1 A
2964 */
2965#define WM8995_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */
2966#define WM8995_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */
2967#define WM8995_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */
2968
2969/*
2970 * R1411 (0x583) - AIF2 EQ Band 1 B
2971 */
2972#define WM8995_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */
2973#define WM8995_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */
2974#define WM8995_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */
2975
2976/*
2977 * R1412 (0x584) - AIF2 EQ Band 1 PG
2978 */
2979#define WM8995_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */
2980#define WM8995_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */
2981#define WM8995_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */
2982
2983/*
2984 * R1413 (0x585) - AIF2 EQ Band 2 A
2985 */
2986#define WM8995_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */
2987#define WM8995_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */
2988#define WM8995_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */
2989
2990/*
2991 * R1414 (0x586) - AIF2 EQ Band 2 B
2992 */
2993#define WM8995_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */
2994#define WM8995_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */
2995#define WM8995_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */
2996
2997/*
2998 * R1415 (0x587) - AIF2 EQ Band 2 C
2999 */
3000#define WM8995_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */
3001#define WM8995_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */
3002#define WM8995_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */
3003
3004/*
3005 * R1416 (0x588) - AIF2 EQ Band 2 PG
3006 */
3007#define WM8995_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */
3008#define WM8995_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */
3009#define WM8995_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */
3010
3011/*
3012 * R1417 (0x589) - AIF2 EQ Band 3 A
3013 */
3014#define WM8995_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */
3015#define WM8995_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */
3016#define WM8995_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */
3017
3018/*
3019 * R1418 (0x58A) - AIF2 EQ Band 3 B
3020 */
3021#define WM8995_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */
3022#define WM8995_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */
3023#define WM8995_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */
3024
3025/*
3026 * R1419 (0x58B) - AIF2 EQ Band 3 C
3027 */
3028#define WM8995_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */
3029#define WM8995_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */
3030#define WM8995_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */
3031
3032/*
3033 * R1420 (0x58C) - AIF2 EQ Band 3 PG
3034 */
3035#define WM8995_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */
3036#define WM8995_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */
3037#define WM8995_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */
3038
3039/*
3040 * R1421 (0x58D) - AIF2 EQ Band 4 A
3041 */
3042#define WM8995_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */
3043#define WM8995_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */
3044#define WM8995_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */
3045
3046/*
3047 * R1422 (0x58E) - AIF2 EQ Band 4 B
3048 */
3049#define WM8995_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */
3050#define WM8995_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */
3051#define WM8995_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */
3052
3053/*
3054 * R1423 (0x58F) - AIF2 EQ Band 4 C
3055 */
3056#define WM8995_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */
3057#define WM8995_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */
3058#define WM8995_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */
3059
3060/*
3061 * R1424 (0x590) - AIF2 EQ Band 4 PG
3062 */
3063#define WM8995_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */
3064#define WM8995_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */
3065#define WM8995_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */
3066
3067/*
3068 * R1425 (0x591) - AIF2 EQ Band 5 A
3069 */
3070#define WM8995_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */
3071#define WM8995_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */
3072#define WM8995_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */
3073
3074/*
3075 * R1426 (0x592) - AIF2 EQ Band 5 B
3076 */
3077#define WM8995_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */
3078#define WM8995_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */
3079#define WM8995_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */
3080
3081/*
3082 * R1427 (0x593) - AIF2 EQ Band 5 PG
3083 */
3084#define WM8995_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */
3085#define WM8995_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */
3086#define WM8995_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */
3087
3088/*
3089 * R1536 (0x600) - DAC1 Mixer Volumes
3090 */
3091#define WM8995_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */
3092#define WM8995_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */
3093#define WM8995_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */
3094#define WM8995_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */
3095#define WM8995_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */
3096#define WM8995_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */
3097
3098/*
3099 * R1537 (0x601) - DAC1 Left Mixer Routing
3100 */
3101#define WM8995_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */
3102#define WM8995_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */
3103#define WM8995_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */
3104#define WM8995_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */
3105#define WM8995_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */
3106#define WM8995_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */
3107#define WM8995_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */
3108#define WM8995_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */
3109#define WM8995_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */
3110#define WM8995_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */
3111#define WM8995_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */
3112#define WM8995_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */
3113#define WM8995_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */
3114#define WM8995_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */
3115#define WM8995_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */
3116#define WM8995_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */
3117#define WM8995_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */
3118#define WM8995_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */
3119#define WM8995_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */
3120#define WM8995_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */
3121
3122/*
3123 * R1538 (0x602) - DAC1 Right Mixer Routing
3124 */
3125#define WM8995_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */
3126#define WM8995_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */
3127#define WM8995_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */
3128#define WM8995_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */
3129#define WM8995_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */
3130#define WM8995_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */
3131#define WM8995_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */
3132#define WM8995_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */
3133#define WM8995_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */
3134#define WM8995_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */
3135#define WM8995_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */
3136#define WM8995_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */
3137#define WM8995_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */
3138#define WM8995_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */
3139#define WM8995_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */
3140#define WM8995_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */
3141#define WM8995_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */
3142#define WM8995_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */
3143#define WM8995_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */
3144#define WM8995_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */
3145
3146/*
3147 * R1539 (0x603) - DAC2 Mixer Volumes
3148 */
3149#define WM8995_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */
3150#define WM8995_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */
3151#define WM8995_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */
3152#define WM8995_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */
3153#define WM8995_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */
3154#define WM8995_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */
3155
3156/*
3157 * R1540 (0x604) - DAC2 Left Mixer Routing
3158 */
3159#define WM8995_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */
3160#define WM8995_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */
3161#define WM8995_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */
3162#define WM8995_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */
3163#define WM8995_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */
3164#define WM8995_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */
3165#define WM8995_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */
3166#define WM8995_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */
3167#define WM8995_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */
3168#define WM8995_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */
3169#define WM8995_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */
3170#define WM8995_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */
3171#define WM8995_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */
3172#define WM8995_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */
3173#define WM8995_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */
3174#define WM8995_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */
3175#define WM8995_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */
3176#define WM8995_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */
3177#define WM8995_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */
3178#define WM8995_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */
3179
3180/*
3181 * R1541 (0x605) - DAC2 Right Mixer Routing
3182 */
3183#define WM8995_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */
3184#define WM8995_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */
3185#define WM8995_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */
3186#define WM8995_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */
3187#define WM8995_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */
3188#define WM8995_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */
3189#define WM8995_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */
3190#define WM8995_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */
3191#define WM8995_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */
3192#define WM8995_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */
3193#define WM8995_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */
3194#define WM8995_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */
3195#define WM8995_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */
3196#define WM8995_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */
3197#define WM8995_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */
3198#define WM8995_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */
3199#define WM8995_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */
3200#define WM8995_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */
3201#define WM8995_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */
3202#define WM8995_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */
3203
3204/*
3205 * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing
3206 */
3207#define WM8995_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */
3208#define WM8995_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */
3209#define WM8995_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */
3210#define WM8995_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */
3211#define WM8995_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */
3212#define WM8995_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */
3213#define WM8995_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */
3214#define WM8995_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */
3215
3216/*
3217 * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing
3218 */
3219#define WM8995_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */
3220#define WM8995_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */
3221#define WM8995_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */
3222#define WM8995_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */
3223#define WM8995_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */
3224#define WM8995_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */
3225#define WM8995_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */
3226#define WM8995_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */
3227
3228/*
3229 * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing
3230 */
3231#define WM8995_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */
3232#define WM8995_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */
3233#define WM8995_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */
3234#define WM8995_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */
3235#define WM8995_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */
3236#define WM8995_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */
3237#define WM8995_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */
3238#define WM8995_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */
3239
3240/*
3241 * R1545 (0x609) - AIF1 ADC2 Right mixer Routing
3242 */
3243#define WM8995_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */
3244#define WM8995_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */
3245#define WM8995_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */
3246#define WM8995_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */
3247#define WM8995_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */
3248#define WM8995_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */
3249#define WM8995_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */
3250#define WM8995_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */
3251
3252/*
3253 * R1552 (0x610) - DAC Softmute
3254 */
3255#define WM8995_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */
3256#define WM8995_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */
3257#define WM8995_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */
3258#define WM8995_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */
3259#define WM8995_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */
3260#define WM8995_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */
3261#define WM8995_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */
3262#define WM8995_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
3263
3264/*
3265 * R1568 (0x620) - Oversampling
3266 */
3267#define WM8995_ADC_OSR128 0x0002 /* ADC_OSR128 */
3268#define WM8995_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */
3269#define WM8995_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */
3270#define WM8995_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */
3271#define WM8995_DAC_OSR128 0x0001 /* DAC_OSR128 */
3272#define WM8995_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */
3273#define WM8995_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */
3274#define WM8995_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */
3275
3276/*
3277 * R1569 (0x621) - Sidetone
3278 */
3279#define WM8995_ST_LPF 0x1000 /* ST_LPF */
3280#define WM8995_ST_LPF_MASK 0x1000 /* ST_LPF */
3281#define WM8995_ST_LPF_SHIFT 12 /* ST_LPF */
3282#define WM8995_ST_LPF_WIDTH 1 /* ST_LPF */
3283#define WM8995_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */
3284#define WM8995_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */
3285#define WM8995_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */
3286#define WM8995_ST_HPF 0x0040 /* ST_HPF */
3287#define WM8995_ST_HPF_MASK 0x0040 /* ST_HPF */
3288#define WM8995_ST_HPF_SHIFT 6 /* ST_HPF */
3289#define WM8995_ST_HPF_WIDTH 1 /* ST_HPF */
3290#define WM8995_STR_SEL 0x0002 /* STR_SEL */
3291#define WM8995_STR_SEL_MASK 0x0002 /* STR_SEL */
3292#define WM8995_STR_SEL_SHIFT 1 /* STR_SEL */
3293#define WM8995_STR_SEL_WIDTH 1 /* STR_SEL */
3294#define WM8995_STL_SEL 0x0001 /* STL_SEL */
3295#define WM8995_STL_SEL_MASK 0x0001 /* STL_SEL */
3296#define WM8995_STL_SEL_SHIFT 0 /* STL_SEL */
3297#define WM8995_STL_SEL_WIDTH 1 /* STL_SEL */
3298
3299/*
3300 * R1792 (0x700) - GPIO 1
3301 */
3302#define WM8995_GP1_DIR 0x8000 /* GP1_DIR */
3303#define WM8995_GP1_DIR_MASK 0x8000 /* GP1_DIR */
3304#define WM8995_GP1_DIR_SHIFT 15 /* GP1_DIR */
3305#define WM8995_GP1_DIR_WIDTH 1 /* GP1_DIR */
3306#define WM8995_GP1_PU 0x4000 /* GP1_PU */
3307#define WM8995_GP1_PU_MASK 0x4000 /* GP1_PU */
3308#define WM8995_GP1_PU_SHIFT 14 /* GP1_PU */
3309#define WM8995_GP1_PU_WIDTH 1 /* GP1_PU */
3310#define WM8995_GP1_PD 0x2000 /* GP1_PD */
3311#define WM8995_GP1_PD_MASK 0x2000 /* GP1_PD */
3312#define WM8995_GP1_PD_SHIFT 13 /* GP1_PD */
3313#define WM8995_GP1_PD_WIDTH 1 /* GP1_PD */
3314#define WM8995_GP1_POL 0x0400 /* GP1_POL */
3315#define WM8995_GP1_POL_MASK 0x0400 /* GP1_POL */
3316#define WM8995_GP1_POL_SHIFT 10 /* GP1_POL */
3317#define WM8995_GP1_POL_WIDTH 1 /* GP1_POL */
3318#define WM8995_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */
3319#define WM8995_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */
3320#define WM8995_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */
3321#define WM8995_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
3322#define WM8995_GP1_DB 0x0100 /* GP1_DB */
3323#define WM8995_GP1_DB_MASK 0x0100 /* GP1_DB */
3324#define WM8995_GP1_DB_SHIFT 8 /* GP1_DB */
3325#define WM8995_GP1_DB_WIDTH 1 /* GP1_DB */
3326#define WM8995_GP1_LVL 0x0040 /* GP1_LVL */
3327#define WM8995_GP1_LVL_MASK 0x0040 /* GP1_LVL */
3328#define WM8995_GP1_LVL_SHIFT 6 /* GP1_LVL */
3329#define WM8995_GP1_LVL_WIDTH 1 /* GP1_LVL */
3330#define WM8995_GP1_FN_MASK 0x001F /* GP1_FN - [4:0] */
3331#define WM8995_GP1_FN_SHIFT 0 /* GP1_FN - [4:0] */
3332#define WM8995_GP1_FN_WIDTH 5 /* GP1_FN - [4:0] */
3333
3334/*
3335 * R1793 (0x701) - GPIO 2
3336 */
3337#define WM8995_GP2_DIR 0x8000 /* GP2_DIR */
3338#define WM8995_GP2_DIR_MASK 0x8000 /* GP2_DIR */
3339#define WM8995_GP2_DIR_SHIFT 15 /* GP2_DIR */
3340#define WM8995_GP2_DIR_WIDTH 1 /* GP2_DIR */
3341#define WM8995_GP2_PU 0x4000 /* GP2_PU */
3342#define WM8995_GP2_PU_MASK 0x4000 /* GP2_PU */
3343#define WM8995_GP2_PU_SHIFT 14 /* GP2_PU */
3344#define WM8995_GP2_PU_WIDTH 1 /* GP2_PU */
3345#define WM8995_GP2_PD 0x2000 /* GP2_PD */
3346#define WM8995_GP2_PD_MASK 0x2000 /* GP2_PD */
3347#define WM8995_GP2_PD_SHIFT 13 /* GP2_PD */
3348#define WM8995_GP2_PD_WIDTH 1 /* GP2_PD */
3349#define WM8995_GP2_POL 0x0400 /* GP2_POL */
3350#define WM8995_GP2_POL_MASK 0x0400 /* GP2_POL */
3351#define WM8995_GP2_POL_SHIFT 10 /* GP2_POL */
3352#define WM8995_GP2_POL_WIDTH 1 /* GP2_POL */
3353#define WM8995_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */
3354#define WM8995_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */
3355#define WM8995_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */
3356#define WM8995_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
3357#define WM8995_GP2_DB 0x0100 /* GP2_DB */
3358#define WM8995_GP2_DB_MASK 0x0100 /* GP2_DB */
3359#define WM8995_GP2_DB_SHIFT 8 /* GP2_DB */
3360#define WM8995_GP2_DB_WIDTH 1 /* GP2_DB */
3361#define WM8995_GP2_LVL 0x0040 /* GP2_LVL */
3362#define WM8995_GP2_LVL_MASK 0x0040 /* GP2_LVL */
3363#define WM8995_GP2_LVL_SHIFT 6 /* GP2_LVL */
3364#define WM8995_GP2_LVL_WIDTH 1 /* GP2_LVL */
3365#define WM8995_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */
3366#define WM8995_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */
3367#define WM8995_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */
3368
3369/*
3370 * R1794 (0x702) - GPIO 3
3371 */
3372#define WM8995_GP3_DIR 0x8000 /* GP3_DIR */
3373#define WM8995_GP3_DIR_MASK 0x8000 /* GP3_DIR */
3374#define WM8995_GP3_DIR_SHIFT 15 /* GP3_DIR */
3375#define WM8995_GP3_DIR_WIDTH 1 /* GP3_DIR */
3376#define WM8995_GP3_PU 0x4000 /* GP3_PU */
3377#define WM8995_GP3_PU_MASK 0x4000 /* GP3_PU */
3378#define WM8995_GP3_PU_SHIFT 14 /* GP3_PU */
3379#define WM8995_GP3_PU_WIDTH 1 /* GP3_PU */
3380#define WM8995_GP3_PD 0x2000 /* GP3_PD */
3381#define WM8995_GP3_PD_MASK 0x2000 /* GP3_PD */
3382#define WM8995_GP3_PD_SHIFT 13 /* GP3_PD */
3383#define WM8995_GP3_PD_WIDTH 1 /* GP3_PD */
3384#define WM8995_GP3_POL 0x0400 /* GP3_POL */
3385#define WM8995_GP3_POL_MASK 0x0400 /* GP3_POL */
3386#define WM8995_GP3_POL_SHIFT 10 /* GP3_POL */
3387#define WM8995_GP3_POL_WIDTH 1 /* GP3_POL */
3388#define WM8995_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */
3389#define WM8995_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */
3390#define WM8995_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */
3391#define WM8995_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
3392#define WM8995_GP3_DB 0x0100 /* GP3_DB */
3393#define WM8995_GP3_DB_MASK 0x0100 /* GP3_DB */
3394#define WM8995_GP3_DB_SHIFT 8 /* GP3_DB */
3395#define WM8995_GP3_DB_WIDTH 1 /* GP3_DB */
3396#define WM8995_GP3_LVL 0x0040 /* GP3_LVL */
3397#define WM8995_GP3_LVL_MASK 0x0040 /* GP3_LVL */
3398#define WM8995_GP3_LVL_SHIFT 6 /* GP3_LVL */
3399#define WM8995_GP3_LVL_WIDTH 1 /* GP3_LVL */
3400#define WM8995_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */
3401#define WM8995_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */
3402#define WM8995_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */
3403
3404/*
3405 * R1795 (0x703) - GPIO 4
3406 */
3407#define WM8995_GP4_DIR 0x8000 /* GP4_DIR */
3408#define WM8995_GP4_DIR_MASK 0x8000 /* GP4_DIR */
3409#define WM8995_GP4_DIR_SHIFT 15 /* GP4_DIR */
3410#define WM8995_GP4_DIR_WIDTH 1 /* GP4_DIR */
3411#define WM8995_GP4_PU 0x4000 /* GP4_PU */
3412#define WM8995_GP4_PU_MASK 0x4000 /* GP4_PU */
3413#define WM8995_GP4_PU_SHIFT 14 /* GP4_PU */
3414#define WM8995_GP4_PU_WIDTH 1 /* GP4_PU */
3415#define WM8995_GP4_PD 0x2000 /* GP4_PD */
3416#define WM8995_GP4_PD_MASK 0x2000 /* GP4_PD */
3417#define WM8995_GP4_PD_SHIFT 13 /* GP4_PD */
3418#define WM8995_GP4_PD_WIDTH 1 /* GP4_PD */
3419#define WM8995_GP4_POL 0x0400 /* GP4_POL */
3420#define WM8995_GP4_POL_MASK 0x0400 /* GP4_POL */
3421#define WM8995_GP4_POL_SHIFT 10 /* GP4_POL */
3422#define WM8995_GP4_POL_WIDTH 1 /* GP4_POL */
3423#define WM8995_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */
3424#define WM8995_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */
3425#define WM8995_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */
3426#define WM8995_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
3427#define WM8995_GP4_DB 0x0100 /* GP4_DB */
3428#define WM8995_GP4_DB_MASK 0x0100 /* GP4_DB */
3429#define WM8995_GP4_DB_SHIFT 8 /* GP4_DB */
3430#define WM8995_GP4_DB_WIDTH 1 /* GP4_DB */
3431#define WM8995_GP4_LVL 0x0040 /* GP4_LVL */
3432#define WM8995_GP4_LVL_MASK 0x0040 /* GP4_LVL */
3433#define WM8995_GP4_LVL_SHIFT 6 /* GP4_LVL */
3434#define WM8995_GP4_LVL_WIDTH 1 /* GP4_LVL */
3435#define WM8995_GP4_FN_MASK 0x001F /* GP4_FN - [4:0] */
3436#define WM8995_GP4_FN_SHIFT 0 /* GP4_FN - [4:0] */
3437#define WM8995_GP4_FN_WIDTH 5 /* GP4_FN - [4:0] */
3438
3439/*
3440 * R1796 (0x704) - GPIO 5
3441 */
3442#define WM8995_GP5_DIR 0x8000 /* GP5_DIR */
3443#define WM8995_GP5_DIR_MASK 0x8000 /* GP5_DIR */
3444#define WM8995_GP5_DIR_SHIFT 15 /* GP5_DIR */
3445#define WM8995_GP5_DIR_WIDTH 1 /* GP5_DIR */
3446#define WM8995_GP5_PU 0x4000 /* GP5_PU */
3447#define WM8995_GP5_PU_MASK 0x4000 /* GP5_PU */
3448#define WM8995_GP5_PU_SHIFT 14 /* GP5_PU */
3449#define WM8995_GP5_PU_WIDTH 1 /* GP5_PU */
3450#define WM8995_GP5_PD 0x2000 /* GP5_PD */
3451#define WM8995_GP5_PD_MASK 0x2000 /* GP5_PD */
3452#define WM8995_GP5_PD_SHIFT 13 /* GP5_PD */
3453#define WM8995_GP5_PD_WIDTH 1 /* GP5_PD */
3454#define WM8995_GP5_POL 0x0400 /* GP5_POL */
3455#define WM8995_GP5_POL_MASK 0x0400 /* GP5_POL */
3456#define WM8995_GP5_POL_SHIFT 10 /* GP5_POL */
3457#define WM8995_GP5_POL_WIDTH 1 /* GP5_POL */
3458#define WM8995_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */
3459#define WM8995_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */
3460#define WM8995_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */
3461#define WM8995_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
3462#define WM8995_GP5_DB 0x0100 /* GP5_DB */
3463#define WM8995_GP5_DB_MASK 0x0100 /* GP5_DB */
3464#define WM8995_GP5_DB_SHIFT 8 /* GP5_DB */
3465#define WM8995_GP5_DB_WIDTH 1 /* GP5_DB */
3466#define WM8995_GP5_LVL 0x0040 /* GP5_LVL */
3467#define WM8995_GP5_LVL_MASK 0x0040 /* GP5_LVL */
3468#define WM8995_GP5_LVL_SHIFT 6 /* GP5_LVL */
3469#define WM8995_GP5_LVL_WIDTH 1 /* GP5_LVL */
3470#define WM8995_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */
3471#define WM8995_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */
3472#define WM8995_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */
3473
3474/*
3475 * R1797 (0x705) - GPIO 6
3476 */
3477#define WM8995_GP6_DIR 0x8000 /* GP6_DIR */
3478#define WM8995_GP6_DIR_MASK 0x8000 /* GP6_DIR */
3479#define WM8995_GP6_DIR_SHIFT 15 /* GP6_DIR */
3480#define WM8995_GP6_DIR_WIDTH 1 /* GP6_DIR */
3481#define WM8995_GP6_PU 0x4000 /* GP6_PU */
3482#define WM8995_GP6_PU_MASK 0x4000 /* GP6_PU */
3483#define WM8995_GP6_PU_SHIFT 14 /* GP6_PU */
3484#define WM8995_GP6_PU_WIDTH 1 /* GP6_PU */
3485#define WM8995_GP6_PD 0x2000 /* GP6_PD */
3486#define WM8995_GP6_PD_MASK 0x2000 /* GP6_PD */
3487#define WM8995_GP6_PD_SHIFT 13 /* GP6_PD */
3488#define WM8995_GP6_PD_WIDTH 1 /* GP6_PD */
3489#define WM8995_GP6_POL 0x0400 /* GP6_POL */
3490#define WM8995_GP6_POL_MASK 0x0400 /* GP6_POL */
3491#define WM8995_GP6_POL_SHIFT 10 /* GP6_POL */
3492#define WM8995_GP6_POL_WIDTH 1 /* GP6_POL */
3493#define WM8995_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */
3494#define WM8995_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */
3495#define WM8995_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */
3496#define WM8995_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */
3497#define WM8995_GP6_DB 0x0100 /* GP6_DB */
3498#define WM8995_GP6_DB_MASK 0x0100 /* GP6_DB */
3499#define WM8995_GP6_DB_SHIFT 8 /* GP6_DB */
3500#define WM8995_GP6_DB_WIDTH 1 /* GP6_DB */
3501#define WM8995_GP6_LVL 0x0040 /* GP6_LVL */
3502#define WM8995_GP6_LVL_MASK 0x0040 /* GP6_LVL */
3503#define WM8995_GP6_LVL_SHIFT 6 /* GP6_LVL */
3504#define WM8995_GP6_LVL_WIDTH 1 /* GP6_LVL */
3505#define WM8995_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */
3506#define WM8995_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */
3507#define WM8995_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */
3508
3509/*
3510 * R1798 (0x706) - GPIO 7
3511 */
3512#define WM8995_GP7_DIR 0x8000 /* GP7_DIR */
3513#define WM8995_GP7_DIR_MASK 0x8000 /* GP7_DIR */
3514#define WM8995_GP7_DIR_SHIFT 15 /* GP7_DIR */
3515#define WM8995_GP7_DIR_WIDTH 1 /* GP7_DIR */
3516#define WM8995_GP7_PU 0x4000 /* GP7_PU */
3517#define WM8995_GP7_PU_MASK 0x4000 /* GP7_PU */
3518#define WM8995_GP7_PU_SHIFT 14 /* GP7_PU */
3519#define WM8995_GP7_PU_WIDTH 1 /* GP7_PU */
3520#define WM8995_GP7_PD 0x2000 /* GP7_PD */
3521#define WM8995_GP7_PD_MASK 0x2000 /* GP7_PD */
3522#define WM8995_GP7_PD_SHIFT 13 /* GP7_PD */
3523#define WM8995_GP7_PD_WIDTH 1 /* GP7_PD */
3524#define WM8995_GP7_POL 0x0400 /* GP7_POL */
3525#define WM8995_GP7_POL_MASK 0x0400 /* GP7_POL */
3526#define WM8995_GP7_POL_SHIFT 10 /* GP7_POL */
3527#define WM8995_GP7_POL_WIDTH 1 /* GP7_POL */
3528#define WM8995_GP7_OP_CFG 0x0200 /* GP7_OP_CFG */
3529#define WM8995_GP7_OP_CFG_MASK 0x0200 /* GP7_OP_CFG */
3530#define WM8995_GP7_OP_CFG_SHIFT 9 /* GP7_OP_CFG */
3531#define WM8995_GP7_OP_CFG_WIDTH 1 /* GP7_OP_CFG */
3532#define WM8995_GP7_DB 0x0100 /* GP7_DB */
3533#define WM8995_GP7_DB_MASK 0x0100 /* GP7_DB */
3534#define WM8995_GP7_DB_SHIFT 8 /* GP7_DB */
3535#define WM8995_GP7_DB_WIDTH 1 /* GP7_DB */
3536#define WM8995_GP7_LVL 0x0040 /* GP7_LVL */
3537#define WM8995_GP7_LVL_MASK 0x0040 /* GP7_LVL */
3538#define WM8995_GP7_LVL_SHIFT 6 /* GP7_LVL */
3539#define WM8995_GP7_LVL_WIDTH 1 /* GP7_LVL */
3540#define WM8995_GP7_FN_MASK 0x001F /* GP7_FN - [4:0] */
3541#define WM8995_GP7_FN_SHIFT 0 /* GP7_FN - [4:0] */
3542#define WM8995_GP7_FN_WIDTH 5 /* GP7_FN - [4:0] */
3543
3544/*
3545 * R1799 (0x707) - GPIO 8
3546 */
3547#define WM8995_GP8_DIR 0x8000 /* GP8_DIR */
3548#define WM8995_GP8_DIR_MASK 0x8000 /* GP8_DIR */
3549#define WM8995_GP8_DIR_SHIFT 15 /* GP8_DIR */
3550#define WM8995_GP8_DIR_WIDTH 1 /* GP8_DIR */
3551#define WM8995_GP8_PU 0x4000 /* GP8_PU */
3552#define WM8995_GP8_PU_MASK 0x4000 /* GP8_PU */
3553#define WM8995_GP8_PU_SHIFT 14 /* GP8_PU */
3554#define WM8995_GP8_PU_WIDTH 1 /* GP8_PU */
3555#define WM8995_GP8_PD 0x2000 /* GP8_PD */
3556#define WM8995_GP8_PD_MASK 0x2000 /* GP8_PD */
3557#define WM8995_GP8_PD_SHIFT 13 /* GP8_PD */
3558#define WM8995_GP8_PD_WIDTH 1 /* GP8_PD */
3559#define WM8995_GP8_POL 0x0400 /* GP8_POL */
3560#define WM8995_GP8_POL_MASK 0x0400 /* GP8_POL */
3561#define WM8995_GP8_POL_SHIFT 10 /* GP8_POL */
3562#define WM8995_GP8_POL_WIDTH 1 /* GP8_POL */
3563#define WM8995_GP8_OP_CFG 0x0200 /* GP8_OP_CFG */
3564#define WM8995_GP8_OP_CFG_MASK 0x0200 /* GP8_OP_CFG */
3565#define WM8995_GP8_OP_CFG_SHIFT 9 /* GP8_OP_CFG */
3566#define WM8995_GP8_OP_CFG_WIDTH 1 /* GP8_OP_CFG */
3567#define WM8995_GP8_DB 0x0100 /* GP8_DB */
3568#define WM8995_GP8_DB_MASK 0x0100 /* GP8_DB */
3569#define WM8995_GP8_DB_SHIFT 8 /* GP8_DB */
3570#define WM8995_GP8_DB_WIDTH 1 /* GP8_DB */
3571#define WM8995_GP8_LVL 0x0040 /* GP8_LVL */
3572#define WM8995_GP8_LVL_MASK 0x0040 /* GP8_LVL */
3573#define WM8995_GP8_LVL_SHIFT 6 /* GP8_LVL */
3574#define WM8995_GP8_LVL_WIDTH 1 /* GP8_LVL */
3575#define WM8995_GP8_FN_MASK 0x001F /* GP8_FN - [4:0] */
3576#define WM8995_GP8_FN_SHIFT 0 /* GP8_FN - [4:0] */
3577#define WM8995_GP8_FN_WIDTH 5 /* GP8_FN - [4:0] */
3578
3579/*
3580 * R1800 (0x708) - GPIO 9
3581 */
3582#define WM8995_GP9_DIR 0x8000 /* GP9_DIR */
3583#define WM8995_GP9_DIR_MASK 0x8000 /* GP9_DIR */
3584#define WM8995_GP9_DIR_SHIFT 15 /* GP9_DIR */
3585#define WM8995_GP9_DIR_WIDTH 1 /* GP9_DIR */
3586#define WM8995_GP9_PU 0x4000 /* GP9_PU */
3587#define WM8995_GP9_PU_MASK 0x4000 /* GP9_PU */
3588#define WM8995_GP9_PU_SHIFT 14 /* GP9_PU */
3589#define WM8995_GP9_PU_WIDTH 1 /* GP9_PU */
3590#define WM8995_GP9_PD 0x2000 /* GP9_PD */
3591#define WM8995_GP9_PD_MASK 0x2000 /* GP9_PD */
3592#define WM8995_GP9_PD_SHIFT 13 /* GP9_PD */
3593#define WM8995_GP9_PD_WIDTH 1 /* GP9_PD */
3594#define WM8995_GP9_POL 0x0400 /* GP9_POL */
3595#define WM8995_GP9_POL_MASK 0x0400 /* GP9_POL */
3596#define WM8995_GP9_POL_SHIFT 10 /* GP9_POL */
3597#define WM8995_GP9_POL_WIDTH 1 /* GP9_POL */
3598#define WM8995_GP9_OP_CFG 0x0200 /* GP9_OP_CFG */
3599#define WM8995_GP9_OP_CFG_MASK 0x0200 /* GP9_OP_CFG */
3600#define WM8995_GP9_OP_CFG_SHIFT 9 /* GP9_OP_CFG */
3601#define WM8995_GP9_OP_CFG_WIDTH 1 /* GP9_OP_CFG */
3602#define WM8995_GP9_DB 0x0100 /* GP9_DB */
3603#define WM8995_GP9_DB_MASK 0x0100 /* GP9_DB */
3604#define WM8995_GP9_DB_SHIFT 8 /* GP9_DB */
3605#define WM8995_GP9_DB_WIDTH 1 /* GP9_DB */
3606#define WM8995_GP9_LVL 0x0040 /* GP9_LVL */
3607#define WM8995_GP9_LVL_MASK 0x0040 /* GP9_LVL */
3608#define WM8995_GP9_LVL_SHIFT 6 /* GP9_LVL */
3609#define WM8995_GP9_LVL_WIDTH 1 /* GP9_LVL */
3610#define WM8995_GP9_FN_MASK 0x001F /* GP9_FN - [4:0] */
3611#define WM8995_GP9_FN_SHIFT 0 /* GP9_FN - [4:0] */
3612#define WM8995_GP9_FN_WIDTH 5 /* GP9_FN - [4:0] */
3613
3614/*
3615 * R1801 (0x709) - GPIO 10
3616 */
3617#define WM8995_GP10_DIR 0x8000 /* GP10_DIR */
3618#define WM8995_GP10_DIR_MASK 0x8000 /* GP10_DIR */
3619#define WM8995_GP10_DIR_SHIFT 15 /* GP10_DIR */
3620#define WM8995_GP10_DIR_WIDTH 1 /* GP10_DIR */
3621#define WM8995_GP10_PU 0x4000 /* GP10_PU */
3622#define WM8995_GP10_PU_MASK 0x4000 /* GP10_PU */
3623#define WM8995_GP10_PU_SHIFT 14 /* GP10_PU */
3624#define WM8995_GP10_PU_WIDTH 1 /* GP10_PU */
3625#define WM8995_GP10_PD 0x2000 /* GP10_PD */
3626#define WM8995_GP10_PD_MASK 0x2000 /* GP10_PD */
3627#define WM8995_GP10_PD_SHIFT 13 /* GP10_PD */
3628#define WM8995_GP10_PD_WIDTH 1 /* GP10_PD */
3629#define WM8995_GP10_POL 0x0400 /* GP10_POL */
3630#define WM8995_GP10_POL_MASK 0x0400 /* GP10_POL */
3631#define WM8995_GP10_POL_SHIFT 10 /* GP10_POL */
3632#define WM8995_GP10_POL_WIDTH 1 /* GP10_POL */
3633#define WM8995_GP10_OP_CFG 0x0200 /* GP10_OP_CFG */
3634#define WM8995_GP10_OP_CFG_MASK 0x0200 /* GP10_OP_CFG */
3635#define WM8995_GP10_OP_CFG_SHIFT 9 /* GP10_OP_CFG */
3636#define WM8995_GP10_OP_CFG_WIDTH 1 /* GP10_OP_CFG */
3637#define WM8995_GP10_DB 0x0100 /* GP10_DB */
3638#define WM8995_GP10_DB_MASK 0x0100 /* GP10_DB */
3639#define WM8995_GP10_DB_SHIFT 8 /* GP10_DB */
3640#define WM8995_GP10_DB_WIDTH 1 /* GP10_DB */
3641#define WM8995_GP10_LVL 0x0040 /* GP10_LVL */
3642#define WM8995_GP10_LVL_MASK 0x0040 /* GP10_LVL */
3643#define WM8995_GP10_LVL_SHIFT 6 /* GP10_LVL */
3644#define WM8995_GP10_LVL_WIDTH 1 /* GP10_LVL */
3645#define WM8995_GP10_FN_MASK 0x001F /* GP10_FN - [4:0] */
3646#define WM8995_GP10_FN_SHIFT 0 /* GP10_FN - [4:0] */
3647#define WM8995_GP10_FN_WIDTH 5 /* GP10_FN - [4:0] */
3648
3649/*
3650 * R1802 (0x70A) - GPIO 11
3651 */
3652#define WM8995_GP11_DIR 0x8000 /* GP11_DIR */
3653#define WM8995_GP11_DIR_MASK 0x8000 /* GP11_DIR */
3654#define WM8995_GP11_DIR_SHIFT 15 /* GP11_DIR */
3655#define WM8995_GP11_DIR_WIDTH 1 /* GP11_DIR */
3656#define WM8995_GP11_PU 0x4000 /* GP11_PU */
3657#define WM8995_GP11_PU_MASK 0x4000 /* GP11_PU */
3658#define WM8995_GP11_PU_SHIFT 14 /* GP11_PU */
3659#define WM8995_GP11_PU_WIDTH 1 /* GP11_PU */
3660#define WM8995_GP11_PD 0x2000 /* GP11_PD */
3661#define WM8995_GP11_PD_MASK 0x2000 /* GP11_PD */
3662#define WM8995_GP11_PD_SHIFT 13 /* GP11_PD */
3663#define WM8995_GP11_PD_WIDTH 1 /* GP11_PD */
3664#define WM8995_GP11_POL 0x0400 /* GP11_POL */
3665#define WM8995_GP11_POL_MASK 0x0400 /* GP11_POL */
3666#define WM8995_GP11_POL_SHIFT 10 /* GP11_POL */
3667#define WM8995_GP11_POL_WIDTH 1 /* GP11_POL */
3668#define WM8995_GP11_OP_CFG 0x0200 /* GP11_OP_CFG */
3669#define WM8995_GP11_OP_CFG_MASK 0x0200 /* GP11_OP_CFG */
3670#define WM8995_GP11_OP_CFG_SHIFT 9 /* GP11_OP_CFG */
3671#define WM8995_GP11_OP_CFG_WIDTH 1 /* GP11_OP_CFG */
3672#define WM8995_GP11_DB 0x0100 /* GP11_DB */
3673#define WM8995_GP11_DB_MASK 0x0100 /* GP11_DB */
3674#define WM8995_GP11_DB_SHIFT 8 /* GP11_DB */
3675#define WM8995_GP11_DB_WIDTH 1 /* GP11_DB */
3676#define WM8995_GP11_LVL 0x0040 /* GP11_LVL */
3677#define WM8995_GP11_LVL_MASK 0x0040 /* GP11_LVL */
3678#define WM8995_GP11_LVL_SHIFT 6 /* GP11_LVL */
3679#define WM8995_GP11_LVL_WIDTH 1 /* GP11_LVL */
3680#define WM8995_GP11_FN_MASK 0x001F /* GP11_FN - [4:0] */
3681#define WM8995_GP11_FN_SHIFT 0 /* GP11_FN - [4:0] */
3682#define WM8995_GP11_FN_WIDTH 5 /* GP11_FN - [4:0] */
3683
3684/*
3685 * R1803 (0x70B) - GPIO 12
3686 */
3687#define WM8995_GP12_DIR 0x8000 /* GP12_DIR */
3688#define WM8995_GP12_DIR_MASK 0x8000 /* GP12_DIR */
3689#define WM8995_GP12_DIR_SHIFT 15 /* GP12_DIR */
3690#define WM8995_GP12_DIR_WIDTH 1 /* GP12_DIR */
3691#define WM8995_GP12_PU 0x4000 /* GP12_PU */
3692#define WM8995_GP12_PU_MASK 0x4000 /* GP12_PU */
3693#define WM8995_GP12_PU_SHIFT 14 /* GP12_PU */
3694#define WM8995_GP12_PU_WIDTH 1 /* GP12_PU */
3695#define WM8995_GP12_PD 0x2000 /* GP12_PD */
3696#define WM8995_GP12_PD_MASK 0x2000 /* GP12_PD */
3697#define WM8995_GP12_PD_SHIFT 13 /* GP12_PD */
3698#define WM8995_GP12_PD_WIDTH 1 /* GP12_PD */
3699#define WM8995_GP12_POL 0x0400 /* GP12_POL */
3700#define WM8995_GP12_POL_MASK 0x0400 /* GP12_POL */
3701#define WM8995_GP12_POL_SHIFT 10 /* GP12_POL */
3702#define WM8995_GP12_POL_WIDTH 1 /* GP12_POL */
3703#define WM8995_GP12_OP_CFG 0x0200 /* GP12_OP_CFG */
3704#define WM8995_GP12_OP_CFG_MASK 0x0200 /* GP12_OP_CFG */
3705#define WM8995_GP12_OP_CFG_SHIFT 9 /* GP12_OP_CFG */
3706#define WM8995_GP12_OP_CFG_WIDTH 1 /* GP12_OP_CFG */
3707#define WM8995_GP12_DB 0x0100 /* GP12_DB */
3708#define WM8995_GP12_DB_MASK 0x0100 /* GP12_DB */
3709#define WM8995_GP12_DB_SHIFT 8 /* GP12_DB */
3710#define WM8995_GP12_DB_WIDTH 1 /* GP12_DB */
3711#define WM8995_GP12_LVL 0x0040 /* GP12_LVL */
3712#define WM8995_GP12_LVL_MASK 0x0040 /* GP12_LVL */
3713#define WM8995_GP12_LVL_SHIFT 6 /* GP12_LVL */
3714#define WM8995_GP12_LVL_WIDTH 1 /* GP12_LVL */
3715#define WM8995_GP12_FN_MASK 0x001F /* GP12_FN - [4:0] */
3716#define WM8995_GP12_FN_SHIFT 0 /* GP12_FN - [4:0] */
3717#define WM8995_GP12_FN_WIDTH 5 /* GP12_FN - [4:0] */
3718
3719/*
3720 * R1804 (0x70C) - GPIO 13
3721 */
3722#define WM8995_GP13_DIR 0x8000 /* GP13_DIR */
3723#define WM8995_GP13_DIR_MASK 0x8000 /* GP13_DIR */
3724#define WM8995_GP13_DIR_SHIFT 15 /* GP13_DIR */
3725#define WM8995_GP13_DIR_WIDTH 1 /* GP13_DIR */
3726#define WM8995_GP13_PU 0x4000 /* GP13_PU */
3727#define WM8995_GP13_PU_MASK 0x4000 /* GP13_PU */
3728#define WM8995_GP13_PU_SHIFT 14 /* GP13_PU */
3729#define WM8995_GP13_PU_WIDTH 1 /* GP13_PU */
3730#define WM8995_GP13_PD 0x2000 /* GP13_PD */
3731#define WM8995_GP13_PD_MASK 0x2000 /* GP13_PD */
3732#define WM8995_GP13_PD_SHIFT 13 /* GP13_PD */
3733#define WM8995_GP13_PD_WIDTH 1 /* GP13_PD */
3734#define WM8995_GP13_POL 0x0400 /* GP13_POL */
3735#define WM8995_GP13_POL_MASK 0x0400 /* GP13_POL */
3736#define WM8995_GP13_POL_SHIFT 10 /* GP13_POL */
3737#define WM8995_GP13_POL_WIDTH 1 /* GP13_POL */
3738#define WM8995_GP13_OP_CFG 0x0200 /* GP13_OP_CFG */
3739#define WM8995_GP13_OP_CFG_MASK 0x0200 /* GP13_OP_CFG */
3740#define WM8995_GP13_OP_CFG_SHIFT 9 /* GP13_OP_CFG */
3741#define WM8995_GP13_OP_CFG_WIDTH 1 /* GP13_OP_CFG */
3742#define WM8995_GP13_DB 0x0100 /* GP13_DB */
3743#define WM8995_GP13_DB_MASK 0x0100 /* GP13_DB */
3744#define WM8995_GP13_DB_SHIFT 8 /* GP13_DB */
3745#define WM8995_GP13_DB_WIDTH 1 /* GP13_DB */
3746#define WM8995_GP13_LVL 0x0040 /* GP13_LVL */
3747#define WM8995_GP13_LVL_MASK 0x0040 /* GP13_LVL */
3748#define WM8995_GP13_LVL_SHIFT 6 /* GP13_LVL */
3749#define WM8995_GP13_LVL_WIDTH 1 /* GP13_LVL */
3750#define WM8995_GP13_FN_MASK 0x001F /* GP13_FN - [4:0] */
3751#define WM8995_GP13_FN_SHIFT 0 /* GP13_FN - [4:0] */
3752#define WM8995_GP13_FN_WIDTH 5 /* GP13_FN - [4:0] */
3753
3754/*
3755 * R1805 (0x70D) - GPIO 14
3756 */
3757#define WM8995_GP14_DIR 0x8000 /* GP14_DIR */
3758#define WM8995_GP14_DIR_MASK 0x8000 /* GP14_DIR */
3759#define WM8995_GP14_DIR_SHIFT 15 /* GP14_DIR */
3760#define WM8995_GP14_DIR_WIDTH 1 /* GP14_DIR */
3761#define WM8995_GP14_PU 0x4000 /* GP14_PU */
3762#define WM8995_GP14_PU_MASK 0x4000 /* GP14_PU */
3763#define WM8995_GP14_PU_SHIFT 14 /* GP14_PU */
3764#define WM8995_GP14_PU_WIDTH 1 /* GP14_PU */
3765#define WM8995_GP14_PD 0x2000 /* GP14_PD */
3766#define WM8995_GP14_PD_MASK 0x2000 /* GP14_PD */
3767#define WM8995_GP14_PD_SHIFT 13 /* GP14_PD */
3768#define WM8995_GP14_PD_WIDTH 1 /* GP14_PD */
3769#define WM8995_GP14_POL 0x0400 /* GP14_POL */
3770#define WM8995_GP14_POL_MASK 0x0400 /* GP14_POL */
3771#define WM8995_GP14_POL_SHIFT 10 /* GP14_POL */
3772#define WM8995_GP14_POL_WIDTH 1 /* GP14_POL */
3773#define WM8995_GP14_OP_CFG 0x0200 /* GP14_OP_CFG */
3774#define WM8995_GP14_OP_CFG_MASK 0x0200 /* GP14_OP_CFG */
3775#define WM8995_GP14_OP_CFG_SHIFT 9 /* GP14_OP_CFG */
3776#define WM8995_GP14_OP_CFG_WIDTH 1 /* GP14_OP_CFG */
3777#define WM8995_GP14_DB 0x0100 /* GP14_DB */
3778#define WM8995_GP14_DB_MASK 0x0100 /* GP14_DB */
3779#define WM8995_GP14_DB_SHIFT 8 /* GP14_DB */
3780#define WM8995_GP14_DB_WIDTH 1 /* GP14_DB */
3781#define WM8995_GP14_LVL 0x0040 /* GP14_LVL */
3782#define WM8995_GP14_LVL_MASK 0x0040 /* GP14_LVL */
3783#define WM8995_GP14_LVL_SHIFT 6 /* GP14_LVL */
3784#define WM8995_GP14_LVL_WIDTH 1 /* GP14_LVL */
3785#define WM8995_GP14_FN_MASK 0x001F /* GP14_FN - [4:0] */
3786#define WM8995_GP14_FN_SHIFT 0 /* GP14_FN - [4:0] */
3787#define WM8995_GP14_FN_WIDTH 5 /* GP14_FN - [4:0] */
3788
3789/*
3790 * R1824 (0x720) - Pull Control (1)
3791 */
3792#define WM8995_DMICDAT3_PD 0x4000 /* DMICDAT3_PD */
3793#define WM8995_DMICDAT3_PD_MASK 0x4000 /* DMICDAT3_PD */
3794#define WM8995_DMICDAT3_PD_SHIFT 14 /* DMICDAT3_PD */
3795#define WM8995_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */
3796#define WM8995_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */
3797#define WM8995_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */
3798#define WM8995_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */
3799#define WM8995_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
3800#define WM8995_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */
3801#define WM8995_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */
3802#define WM8995_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */
3803#define WM8995_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
3804#define WM8995_MCLK2_PU 0x0200 /* MCLK2_PU */
3805#define WM8995_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */
3806#define WM8995_MCLK2_PU_SHIFT 9 /* MCLK2_PU */
3807#define WM8995_MCLK2_PU_WIDTH 1 /* MCLK2_PU */
3808#define WM8995_MCLK2_PD 0x0100 /* MCLK2_PD */
3809#define WM8995_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */
3810#define WM8995_MCLK2_PD_SHIFT 8 /* MCLK2_PD */
3811#define WM8995_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
3812#define WM8995_MCLK1_PU 0x0080 /* MCLK1_PU */
3813#define WM8995_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */
3814#define WM8995_MCLK1_PU_SHIFT 7 /* MCLK1_PU */
3815#define WM8995_MCLK1_PU_WIDTH 1 /* MCLK1_PU */
3816#define WM8995_MCLK1_PD 0x0040 /* MCLK1_PD */
3817#define WM8995_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */
3818#define WM8995_MCLK1_PD_SHIFT 6 /* MCLK1_PD */
3819#define WM8995_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
3820#define WM8995_DACDAT1_PU 0x0020 /* DACDAT1_PU */
3821#define WM8995_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */
3822#define WM8995_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */
3823#define WM8995_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */
3824#define WM8995_DACDAT1_PD 0x0010 /* DACDAT1_PD */
3825#define WM8995_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */
3826#define WM8995_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */
3827#define WM8995_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */
3828#define WM8995_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */
3829#define WM8995_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */
3830#define WM8995_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */
3831#define WM8995_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */
3832#define WM8995_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */
3833#define WM8995_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */
3834#define WM8995_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */
3835#define WM8995_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */
3836#define WM8995_BCLK1_PU 0x0002 /* BCLK1_PU */
3837#define WM8995_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */
3838#define WM8995_BCLK1_PU_SHIFT 1 /* BCLK1_PU */
3839#define WM8995_BCLK1_PU_WIDTH 1 /* BCLK1_PU */
3840#define WM8995_BCLK1_PD 0x0001 /* BCLK1_PD */
3841#define WM8995_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */
3842#define WM8995_BCLK1_PD_SHIFT 0 /* BCLK1_PD */
3843#define WM8995_BCLK1_PD_WIDTH 1 /* BCLK1_PD */
3844
3845/*
3846 * R1825 (0x721) - Pull Control (2)
3847 */
3848#define WM8995_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */
3849#define WM8995_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */
3850#define WM8995_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */
3851#define WM8995_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
3852#define WM8995_MODE_PD 0x0004 /* MODE_PD */
3853#define WM8995_MODE_PD_MASK 0x0004 /* MODE_PD */
3854#define WM8995_MODE_PD_SHIFT 2 /* MODE_PD */
3855#define WM8995_MODE_PD_WIDTH 1 /* MODE_PD */
3856#define WM8995_CSNADDR_PD 0x0001 /* CSNADDR_PD */
3857#define WM8995_CSNADDR_PD_MASK 0x0001 /* CSNADDR_PD */
3858#define WM8995_CSNADDR_PD_SHIFT 0 /* CSNADDR_PD */
3859#define WM8995_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */
3860
3861/*
3862 * R1840 (0x730) - Interrupt Status 1
3863 */
3864#define WM8995_GP14_EINT 0x2000 /* GP14_EINT */
3865#define WM8995_GP14_EINT_MASK 0x2000 /* GP14_EINT */
3866#define WM8995_GP14_EINT_SHIFT 13 /* GP14_EINT */
3867#define WM8995_GP14_EINT_WIDTH 1 /* GP14_EINT */
3868#define WM8995_GP13_EINT 0x1000 /* GP13_EINT */
3869#define WM8995_GP13_EINT_MASK 0x1000 /* GP13_EINT */
3870#define WM8995_GP13_EINT_SHIFT 12 /* GP13_EINT */
3871#define WM8995_GP13_EINT_WIDTH 1 /* GP13_EINT */
3872#define WM8995_GP12_EINT 0x0800 /* GP12_EINT */
3873#define WM8995_GP12_EINT_MASK 0x0800 /* GP12_EINT */
3874#define WM8995_GP12_EINT_SHIFT 11 /* GP12_EINT */
3875#define WM8995_GP12_EINT_WIDTH 1 /* GP12_EINT */
3876#define WM8995_GP11_EINT 0x0400 /* GP11_EINT */
3877#define WM8995_GP11_EINT_MASK 0x0400 /* GP11_EINT */
3878#define WM8995_GP11_EINT_SHIFT 10 /* GP11_EINT */
3879#define WM8995_GP11_EINT_WIDTH 1 /* GP11_EINT */
3880#define WM8995_GP10_EINT 0x0200 /* GP10_EINT */
3881#define WM8995_GP10_EINT_MASK 0x0200 /* GP10_EINT */
3882#define WM8995_GP10_EINT_SHIFT 9 /* GP10_EINT */
3883#define WM8995_GP10_EINT_WIDTH 1 /* GP10_EINT */
3884#define WM8995_GP9_EINT 0x0100 /* GP9_EINT */
3885#define WM8995_GP9_EINT_MASK 0x0100 /* GP9_EINT */
3886#define WM8995_GP9_EINT_SHIFT 8 /* GP9_EINT */
3887#define WM8995_GP9_EINT_WIDTH 1 /* GP9_EINT */
3888#define WM8995_GP8_EINT 0x0080 /* GP8_EINT */
3889#define WM8995_GP8_EINT_MASK 0x0080 /* GP8_EINT */
3890#define WM8995_GP8_EINT_SHIFT 7 /* GP8_EINT */
3891#define WM8995_GP8_EINT_WIDTH 1 /* GP8_EINT */
3892#define WM8995_GP7_EINT 0x0040 /* GP7_EINT */
3893#define WM8995_GP7_EINT_MASK 0x0040 /* GP7_EINT */
3894#define WM8995_GP7_EINT_SHIFT 6 /* GP7_EINT */
3895#define WM8995_GP7_EINT_WIDTH 1 /* GP7_EINT */
3896#define WM8995_GP6_EINT 0x0020 /* GP6_EINT */
3897#define WM8995_GP6_EINT_MASK 0x0020 /* GP6_EINT */
3898#define WM8995_GP6_EINT_SHIFT 5 /* GP6_EINT */
3899#define WM8995_GP6_EINT_WIDTH 1 /* GP6_EINT */
3900#define WM8995_GP5_EINT 0x0010 /* GP5_EINT */
3901#define WM8995_GP5_EINT_MASK 0x0010 /* GP5_EINT */
3902#define WM8995_GP5_EINT_SHIFT 4 /* GP5_EINT */
3903#define WM8995_GP5_EINT_WIDTH 1 /* GP5_EINT */
3904#define WM8995_GP4_EINT 0x0008 /* GP4_EINT */
3905#define WM8995_GP4_EINT_MASK 0x0008 /* GP4_EINT */
3906#define WM8995_GP4_EINT_SHIFT 3 /* GP4_EINT */
3907#define WM8995_GP4_EINT_WIDTH 1 /* GP4_EINT */
3908#define WM8995_GP3_EINT 0x0004 /* GP3_EINT */
3909#define WM8995_GP3_EINT_MASK 0x0004 /* GP3_EINT */
3910#define WM8995_GP3_EINT_SHIFT 2 /* GP3_EINT */
3911#define WM8995_GP3_EINT_WIDTH 1 /* GP3_EINT */
3912#define WM8995_GP2_EINT 0x0002 /* GP2_EINT */
3913#define WM8995_GP2_EINT_MASK 0x0002 /* GP2_EINT */
3914#define WM8995_GP2_EINT_SHIFT 1 /* GP2_EINT */
3915#define WM8995_GP2_EINT_WIDTH 1 /* GP2_EINT */
3916#define WM8995_GP1_EINT 0x0001 /* GP1_EINT */
3917#define WM8995_GP1_EINT_MASK 0x0001 /* GP1_EINT */
3918#define WM8995_GP1_EINT_SHIFT 0 /* GP1_EINT */
3919#define WM8995_GP1_EINT_WIDTH 1 /* GP1_EINT */
3920
3921/*
3922 * R1841 (0x731) - Interrupt Status 2
3923 */
3924#define WM8995_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */
3925#define WM8995_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */
3926#define WM8995_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */
3927#define WM8995_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */
3928#define WM8995_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */
3929#define WM8995_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */
3930#define WM8995_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */
3931#define WM8995_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */
3932#define WM8995_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */
3933#define WM8995_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */
3934#define WM8995_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */
3935#define WM8995_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */
3936#define WM8995_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */
3937#define WM8995_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */
3938#define WM8995_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */
3939#define WM8995_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */
3940#define WM8995_AIF2DRC_SIG_DET_EINT 0x0100 /* AIF2DRC_SIG_DET_EINT */
3941#define WM8995_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* AIF2DRC_SIG_DET_EINT */
3942#define WM8995_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* AIF2DRC_SIG_DET_EINT */
3943#define WM8995_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */
3944#define WM8995_AIF1DRC2_SIG_DET_EINT 0x0080 /* AIF1DRC2_SIG_DET_EINT */
3945#define WM8995_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* AIF1DRC2_SIG_DET_EINT */
3946#define WM8995_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* AIF1DRC2_SIG_DET_EINT */
3947#define WM8995_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */
3948#define WM8995_AIF1DRC1_SIG_DET_EINT 0x0040 /* AIF1DRC1_SIG_DET_EINT */
3949#define WM8995_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* AIF1DRC1_SIG_DET_EINT */
3950#define WM8995_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* AIF1DRC1_SIG_DET_EINT */
3951#define WM8995_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */
3952#define WM8995_SRC2_LOCK_EINT 0x0020 /* SRC2_LOCK_EINT */
3953#define WM8995_SRC2_LOCK_EINT_MASK 0x0020 /* SRC2_LOCK_EINT */
3954#define WM8995_SRC2_LOCK_EINT_SHIFT 5 /* SRC2_LOCK_EINT */
3955#define WM8995_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */
3956#define WM8995_SRC1_LOCK_EINT 0x0010 /* SRC1_LOCK_EINT */
3957#define WM8995_SRC1_LOCK_EINT_MASK 0x0010 /* SRC1_LOCK_EINT */
3958#define WM8995_SRC1_LOCK_EINT_SHIFT 4 /* SRC1_LOCK_EINT */
3959#define WM8995_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */
3960#define WM8995_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */
3961#define WM8995_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */
3962#define WM8995_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */
3963#define WM8995_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */
3964#define WM8995_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */
3965#define WM8995_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */
3966#define WM8995_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */
3967#define WM8995_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */
3968#define WM8995_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */
3969#define WM8995_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */
3970#define WM8995_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */
3971#define WM8995_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */
3972#define WM8995_MICD_EINT 0x0001 /* MICD_EINT */
3973#define WM8995_MICD_EINT_MASK 0x0001 /* MICD_EINT */
3974#define WM8995_MICD_EINT_SHIFT 0 /* MICD_EINT */
3975#define WM8995_MICD_EINT_WIDTH 1 /* MICD_EINT */
3976
3977/*
3978 * R1842 (0x732) - Interrupt Raw Status 2
3979 */
3980#define WM8995_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */
3981#define WM8995_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */
3982#define WM8995_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */
3983#define WM8995_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */
3984#define WM8995_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */
3985#define WM8995_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */
3986#define WM8995_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */
3987#define WM8995_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */
3988#define WM8995_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */
3989#define WM8995_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */
3990#define WM8995_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */
3991#define WM8995_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */
3992#define WM8995_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */
3993#define WM8995_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */
3994#define WM8995_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */
3995#define WM8995_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */
3996#define WM8995_AIF2DRC_SIG_DET_STS 0x0100 /* AIF2DRC_SIG_DET_STS */
3997#define WM8995_AIF2DRC_SIG_DET_STS_MASK 0x0100 /* AIF2DRC_SIG_DET_STS */
3998#define WM8995_AIF2DRC_SIG_DET_STS_SHIFT 8 /* AIF2DRC_SIG_DET_STS */
3999#define WM8995_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */
4000#define WM8995_AIF1DRC2_SIG_DET_STS 0x0080 /* AIF1DRC2_SIG_DET_STS */
4001#define WM8995_AIF1DRC2_SIG_DET_STS_MASK 0x0080 /* AIF1DRC2_SIG_DET_STS */
4002#define WM8995_AIF1DRC2_SIG_DET_STS_SHIFT 7 /* AIF1DRC2_SIG_DET_STS */
4003#define WM8995_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */
4004#define WM8995_AIF1DRC1_SIG_DET_STS 0x0040 /* AIF1DRC1_SIG_DET_STS */
4005#define WM8995_AIF1DRC1_SIG_DET_STS_MASK 0x0040 /* AIF1DRC1_SIG_DET_STS */
4006#define WM8995_AIF1DRC1_SIG_DET_STS_SHIFT 6 /* AIF1DRC1_SIG_DET_STS */
4007#define WM8995_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */
4008#define WM8995_SRC2_LOCK_STS 0x0020 /* SRC2_LOCK_STS */
4009#define WM8995_SRC2_LOCK_STS_MASK 0x0020 /* SRC2_LOCK_STS */
4010#define WM8995_SRC2_LOCK_STS_SHIFT 5 /* SRC2_LOCK_STS */
4011#define WM8995_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */
4012#define WM8995_SRC1_LOCK_STS 0x0010 /* SRC1_LOCK_STS */
4013#define WM8995_SRC1_LOCK_STS_MASK 0x0010 /* SRC1_LOCK_STS */
4014#define WM8995_SRC1_LOCK_STS_SHIFT 4 /* SRC1_LOCK_STS */
4015#define WM8995_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */
4016#define WM8995_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */
4017#define WM8995_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */
4018#define WM8995_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */
4019#define WM8995_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */
4020#define WM8995_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */
4021#define WM8995_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */
4022#define WM8995_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */
4023#define WM8995_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */
4024
4025/*
4026 * R1848 (0x738) - Interrupt Status 1 Mask
4027 */
4028#define WM8995_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */
4029#define WM8995_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */
4030#define WM8995_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */
4031#define WM8995_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */
4032#define WM8995_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */
4033#define WM8995_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */
4034#define WM8995_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */
4035#define WM8995_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */
4036#define WM8995_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */
4037#define WM8995_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */
4038#define WM8995_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */
4039#define WM8995_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */
4040#define WM8995_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
4041#define WM8995_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
4042#define WM8995_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */
4043#define WM8995_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
4044#define WM8995_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
4045#define WM8995_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
4046#define WM8995_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */
4047#define WM8995_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
4048#define WM8995_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
4049#define WM8995_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
4050#define WM8995_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */
4051#define WM8995_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
4052#define WM8995_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
4053#define WM8995_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
4054#define WM8995_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */
4055#define WM8995_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
4056#define WM8995_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
4057#define WM8995_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
4058#define WM8995_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */
4059#define WM8995_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
4060#define WM8995_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
4061#define WM8995_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
4062#define WM8995_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
4063#define WM8995_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
4064#define WM8995_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
4065#define WM8995_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
4066#define WM8995_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
4067#define WM8995_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
4068#define WM8995_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
4069#define WM8995_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
4070#define WM8995_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
4071#define WM8995_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
4072#define WM8995_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
4073#define WM8995_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
4074#define WM8995_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
4075#define WM8995_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
4076#define WM8995_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
4077#define WM8995_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
4078#define WM8995_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
4079#define WM8995_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
4080#define WM8995_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
4081#define WM8995_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
4082#define WM8995_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
4083#define WM8995_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
4084
4085/*
4086 * R1849 (0x739) - Interrupt Status 2 Mask
4087 */
4088#define WM8995_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */
4089#define WM8995_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */
4090#define WM8995_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */
4091#define WM8995_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */
4092#define WM8995_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */
4093#define WM8995_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */
4094#define WM8995_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */
4095#define WM8995_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */
4096#define WM8995_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */
4097#define WM8995_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */
4098#define WM8995_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */
4099#define WM8995_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */
4100#define WM8995_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */
4101#define WM8995_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */
4102#define WM8995_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */
4103#define WM8995_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */
4104#define WM8995_IM_AIF2DRC_SIG_DET_EINT 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */
4105#define WM8995_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */
4106#define WM8995_IM_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* IM_AIF2DRC_SIG_DET_EINT */
4107#define WM8995_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */
4108#define WM8995_IM_AIF1DRC2_SIG_DET_EINT 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */
4109#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */
4110#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* IM_AIF1DRC2_SIG_DET_EINT */
4111#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */
4112#define WM8995_IM_AIF1DRC1_SIG_DET_EINT 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */
4113#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */
4114#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* IM_AIF1DRC1_SIG_DET_EINT */
4115#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */
4116#define WM8995_IM_SRC2_LOCK_EINT 0x0020 /* IM_SRC2_LOCK_EINT */
4117#define WM8995_IM_SRC2_LOCK_EINT_MASK 0x0020 /* IM_SRC2_LOCK_EINT */
4118#define WM8995_IM_SRC2_LOCK_EINT_SHIFT 5 /* IM_SRC2_LOCK_EINT */
4119#define WM8995_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */
4120#define WM8995_IM_SRC1_LOCK_EINT 0x0010 /* IM_SRC1_LOCK_EINT */
4121#define WM8995_IM_SRC1_LOCK_EINT_MASK 0x0010 /* IM_SRC1_LOCK_EINT */
4122#define WM8995_IM_SRC1_LOCK_EINT_SHIFT 4 /* IM_SRC1_LOCK_EINT */
4123#define WM8995_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */
4124#define WM8995_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */
4125#define WM8995_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */
4126#define WM8995_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */
4127#define WM8995_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */
4128#define WM8995_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */
4129#define WM8995_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */
4130#define WM8995_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */
4131#define WM8995_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */
4132#define WM8995_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */
4133#define WM8995_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */
4134#define WM8995_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */
4135#define WM8995_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */
4136#define WM8995_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */
4137#define WM8995_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */
4138#define WM8995_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */
4139#define WM8995_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */
4140
4141/*
4142 * R1856 (0x740) - Interrupt Control
4143 */
4144#define WM8995_IM_IRQ 0x0001 /* IM_IRQ */
4145#define WM8995_IM_IRQ_MASK 0x0001 /* IM_IRQ */
4146#define WM8995_IM_IRQ_SHIFT 0 /* IM_IRQ */
4147#define WM8995_IM_IRQ_WIDTH 1 /* IM_IRQ */
4148
4149/*
4150 * R2048 (0x800) - Left PDM Speaker 1
4151 */
4152#define WM8995_SPK1L_ENA 0x0010 /* SPK1L_ENA */
4153#define WM8995_SPK1L_ENA_MASK 0x0010 /* SPK1L_ENA */
4154#define WM8995_SPK1L_ENA_SHIFT 4 /* SPK1L_ENA */
4155#define WM8995_SPK1L_ENA_WIDTH 1 /* SPK1L_ENA */
4156#define WM8995_SPK1L_MUTE 0x0008 /* SPK1L_MUTE */
4157#define WM8995_SPK1L_MUTE_MASK 0x0008 /* SPK1L_MUTE */
4158#define WM8995_SPK1L_MUTE_SHIFT 3 /* SPK1L_MUTE */
4159#define WM8995_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */
4160#define WM8995_SPK1L_MUTE_ZC 0x0004 /* SPK1L_MUTE_ZC */
4161#define WM8995_SPK1L_MUTE_ZC_MASK 0x0004 /* SPK1L_MUTE_ZC */
4162#define WM8995_SPK1L_MUTE_ZC_SHIFT 2 /* SPK1L_MUTE_ZC */
4163#define WM8995_SPK1L_MUTE_ZC_WIDTH 1 /* SPK1L_MUTE_ZC */
4164#define WM8995_SPK1L_SRC_MASK 0x0003 /* SPK1L_SRC - [1:0] */
4165#define WM8995_SPK1L_SRC_SHIFT 0 /* SPK1L_SRC - [1:0] */
4166#define WM8995_SPK1L_SRC_WIDTH 2 /* SPK1L_SRC - [1:0] */
4167
4168/*
4169 * R2049 (0x801) - Right PDM Speaker 1
4170 */
4171#define WM8995_SPK1R_ENA 0x0010 /* SPK1R_ENA */
4172#define WM8995_SPK1R_ENA_MASK 0x0010 /* SPK1R_ENA */
4173#define WM8995_SPK1R_ENA_SHIFT 4 /* SPK1R_ENA */
4174#define WM8995_SPK1R_ENA_WIDTH 1 /* SPK1R_ENA */
4175#define WM8995_SPK1R_MUTE 0x0008 /* SPK1R_MUTE */
4176#define WM8995_SPK1R_MUTE_MASK 0x0008 /* SPK1R_MUTE */
4177#define WM8995_SPK1R_MUTE_SHIFT 3 /* SPK1R_MUTE */
4178#define WM8995_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */
4179#define WM8995_SPK1R_MUTE_ZC 0x0004 /* SPK1R_MUTE_ZC */
4180#define WM8995_SPK1R_MUTE_ZC_MASK 0x0004 /* SPK1R_MUTE_ZC */
4181#define WM8995_SPK1R_MUTE_ZC_SHIFT 2 /* SPK1R_MUTE_ZC */
4182#define WM8995_SPK1R_MUTE_ZC_WIDTH 1 /* SPK1R_MUTE_ZC */
4183#define WM8995_SPK1R_SRC_MASK 0x0003 /* SPK1R_SRC - [1:0] */
4184#define WM8995_SPK1R_SRC_SHIFT 0 /* SPK1R_SRC - [1:0] */
4185#define WM8995_SPK1R_SRC_WIDTH 2 /* SPK1R_SRC - [1:0] */
4186
4187/*
4188 * R2050 (0x802) - PDM Speaker 1 Mute Sequence
4189 */
4190#define WM8995_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */
4191#define WM8995_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */
4192#define WM8995_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */
4193
4194/*
4195 * R2056 (0x808) - Left PDM Speaker 2
4196 */
4197#define WM8995_SPK2L_ENA 0x0010 /* SPK2L_ENA */
4198#define WM8995_SPK2L_ENA_MASK 0x0010 /* SPK2L_ENA */
4199#define WM8995_SPK2L_ENA_SHIFT 4 /* SPK2L_ENA */
4200#define WM8995_SPK2L_ENA_WIDTH 1 /* SPK2L_ENA */
4201#define WM8995_SPK2L_MUTE 0x0008 /* SPK2L_MUTE */
4202#define WM8995_SPK2L_MUTE_MASK 0x0008 /* SPK2L_MUTE */
4203#define WM8995_SPK2L_MUTE_SHIFT 3 /* SPK2L_MUTE */
4204#define WM8995_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */
4205#define WM8995_SPK2L_MUTE_ZC 0x0004 /* SPK2L_MUTE_ZC */
4206#define WM8995_SPK2L_MUTE_ZC_MASK 0x0004 /* SPK2L_MUTE_ZC */
4207#define WM8995_SPK2L_MUTE_ZC_SHIFT 2 /* SPK2L_MUTE_ZC */
4208#define WM8995_SPK2L_MUTE_ZC_WIDTH 1 /* SPK2L_MUTE_ZC */
4209#define WM8995_SPK2L_SRC_MASK 0x0003 /* SPK2L_SRC - [1:0] */
4210#define WM8995_SPK2L_SRC_SHIFT 0 /* SPK2L_SRC - [1:0] */
4211#define WM8995_SPK2L_SRC_WIDTH 2 /* SPK2L_SRC - [1:0] */
4212
4213/*
4214 * R2057 (0x809) - Right PDM Speaker 2
4215 */
4216#define WM8995_SPK2R_ENA 0x0010 /* SPK2R_ENA */
4217#define WM8995_SPK2R_ENA_MASK 0x0010 /* SPK2R_ENA */
4218#define WM8995_SPK2R_ENA_SHIFT 4 /* SPK2R_ENA */
4219#define WM8995_SPK2R_ENA_WIDTH 1 /* SPK2R_ENA */
4220#define WM8995_SPK2R_MUTE 0x0008 /* SPK2R_MUTE */
4221#define WM8995_SPK2R_MUTE_MASK 0x0008 /* SPK2R_MUTE */
4222#define WM8995_SPK2R_MUTE_SHIFT 3 /* SPK2R_MUTE */
4223#define WM8995_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */
4224#define WM8995_SPK2R_MUTE_ZC 0x0004 /* SPK2R_MUTE_ZC */
4225#define WM8995_SPK2R_MUTE_ZC_MASK 0x0004 /* SPK2R_MUTE_ZC */
4226#define WM8995_SPK2R_MUTE_ZC_SHIFT 2 /* SPK2R_MUTE_ZC */
4227#define WM8995_SPK2R_MUTE_ZC_WIDTH 1 /* SPK2R_MUTE_ZC */
4228#define WM8995_SPK2R_SRC_MASK 0x0003 /* SPK2R_SRC - [1:0] */
4229#define WM8995_SPK2R_SRC_SHIFT 0 /* SPK2R_SRC - [1:0] */
4230#define WM8995_SPK2R_SRC_WIDTH 2 /* SPK2R_SRC - [1:0] */
4231
4232/*
4233 * R2058 (0x80A) - PDM Speaker 2 Mute Sequence
4234 */
4235#define WM8995_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */
4236#define WM8995_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */
4237#define WM8995_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */
4238
4239#define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
4240{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
4241 .info = snd_soc_info_volsw, \
4242 .get = snd_soc_dapm_get_volsw, .put = wm8995_put_class_w, \
4243 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) \
4244}
4245
4246struct wm8995_reg_access {
4247 u16 read;
4248 u16 write;
4249 u16 vol;
4250};
4251
4252/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
4253enum clk_src {
4254 WM8995_SYSCLK_MCLK1 = 1,
4255 WM8995_SYSCLK_MCLK2,
4256 WM8995_SYSCLK_FLL1,
4257 WM8995_SYSCLK_FLL2,
4258 WM8995_SYSCLK_OPCLK
4259};
4260
4261#define WM8995_FLL1 1
4262#define WM8995_FLL2 2
4263
4264#define WM8995_FLL_SRC_MCLK1 1
4265#define WM8995_FLL_SRC_MCLK2 2
4266#define WM8995_FLL_SRC_LRCLK 3
4267#define WM8995_FLL_SRC_BCLK 4
4268
4269#endif /* _WM8995_H */
diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c
index e5055b28c63..43825b2102a 100644
--- a/sound/soc/codecs/wm9081.c
+++ b/sound/soc/codecs/wm9081.c
@@ -157,7 +157,6 @@ static struct {
157struct wm9081_priv { 157struct wm9081_priv {
158 enum snd_soc_control_type control_type; 158 enum snd_soc_control_type control_type;
159 void *control_data; 159 void *control_data;
160 u16 reg_cache[WM9081_MAX_REGISTER + 1];
161 int sysclk_source; 160 int sysclk_source;
162 int mclk_rate; 161 int mclk_rate;
163 int sysclk_rate; 162 int sysclk_rate;
@@ -1339,6 +1338,7 @@ static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1339 return -ENOMEM; 1338 return -ENOMEM;
1340 1339
1341 i2c_set_clientdata(i2c, wm9081); 1340 i2c_set_clientdata(i2c, wm9081);
1341 wm9081->control_type = SND_SOC_I2C;
1342 wm9081->control_data = i2c; 1342 wm9081->control_data = i2c;
1343 1343
1344 ret = snd_soc_register_codec(&i2c->dev, 1344 ret = snd_soc_register_codec(&i2c->dev,
diff --git a/sound/soc/codecs/wm9090.c b/sound/soc/codecs/wm9090.c
index 7ba5807cac3..a788c429704 100644
--- a/sound/soc/codecs/wm9090.c
+++ b/sound/soc/codecs/wm9090.c
@@ -140,7 +140,6 @@ static const u16 wm9090_reg_defaults[] = {
140/* This struct is used to save the context */ 140/* This struct is used to save the context */
141struct wm9090_priv { 141struct wm9090_priv {
142 struct mutex mutex; 142 struct mutex mutex;
143 u16 reg_cache[WM9090_MAX_REGISTER + 1];
144 struct wm9090_platform_data pdata; 143 struct wm9090_platform_data pdata;
145 void *control_data; 144 void *control_data;
146}; 145};
@@ -552,6 +551,7 @@ static int wm9090_set_bias_level(struct snd_soc_codec *codec,
552static int wm9090_probe(struct snd_soc_codec *codec) 551static int wm9090_probe(struct snd_soc_codec *codec)
553{ 552{
554 struct wm9090_priv *wm9090 = snd_soc_codec_get_drvdata(codec); 553 struct wm9090_priv *wm9090 = snd_soc_codec_get_drvdata(codec);
554 u16 *reg_cache = codec->reg_cache;
555 int ret; 555 int ret;
556 556
557 codec->control_data = wm9090->control_data; 557 codec->control_data = wm9090->control_data;
@@ -576,22 +576,22 @@ static int wm9090_probe(struct snd_soc_codec *codec)
576 /* Configure some defaults; they will be written out when we 576 /* Configure some defaults; they will be written out when we
577 * bring the bias up. 577 * bring the bias up.
578 */ 578 */
579 wm9090->reg_cache[WM9090_IN1_LINE_INPUT_A_VOLUME] |= WM9090_IN1_VU 579 reg_cache[WM9090_IN1_LINE_INPUT_A_VOLUME] |= WM9090_IN1_VU
580 | WM9090_IN1A_ZC; 580 | WM9090_IN1A_ZC;
581 wm9090->reg_cache[WM9090_IN1_LINE_INPUT_B_VOLUME] |= WM9090_IN1_VU 581 reg_cache[WM9090_IN1_LINE_INPUT_B_VOLUME] |= WM9090_IN1_VU
582 | WM9090_IN1B_ZC; 582 | WM9090_IN1B_ZC;
583 wm9090->reg_cache[WM9090_IN2_LINE_INPUT_A_VOLUME] |= WM9090_IN2_VU 583 reg_cache[WM9090_IN2_LINE_INPUT_A_VOLUME] |= WM9090_IN2_VU
584 | WM9090_IN2A_ZC; 584 | WM9090_IN2A_ZC;
585 wm9090->reg_cache[WM9090_IN2_LINE_INPUT_B_VOLUME] |= WM9090_IN2_VU 585 reg_cache[WM9090_IN2_LINE_INPUT_B_VOLUME] |= WM9090_IN2_VU
586 | WM9090_IN2B_ZC; 586 | WM9090_IN2B_ZC;
587 wm9090->reg_cache[WM9090_SPEAKER_VOLUME_LEFT] |= 587 reg_cache[WM9090_SPEAKER_VOLUME_LEFT] |=
588 WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC; 588 WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC;
589 wm9090->reg_cache[WM9090_LEFT_OUTPUT_VOLUME] |= 589 reg_cache[WM9090_LEFT_OUTPUT_VOLUME] |=
590 WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC; 590 WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC;
591 wm9090->reg_cache[WM9090_RIGHT_OUTPUT_VOLUME] |= 591 reg_cache[WM9090_RIGHT_OUTPUT_VOLUME] |=
592 WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC; 592 WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC;
593 593
594 wm9090->reg_cache[WM9090_CLOCKING_1] |= WM9090_TOCLK_ENA; 594 reg_cache[WM9090_CLOCKING_1] |= WM9090_TOCLK_ENA;
595 595
596 wm9090_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 596 wm9090_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
597 597
diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index 24b031e2634..0c2d6bacc68 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -26,7 +26,6 @@
26#include <mach/edma.h> 26#include <mach/edma.h>
27#include <mach/mux.h> 27#include <mach/mux.h>
28 28
29#include "../codecs/tlv320aic3x.h"
30#include "davinci-pcm.h" 29#include "davinci-pcm.h"
31#include "davinci-i2s.h" 30#include "davinci-i2s.h"
32#include "davinci-mcasp.h" 31#include "davinci-mcasp.h"
diff --git a/sound/soc/omap/n810.c b/sound/soc/omap/n810.c
index fe215f3e8af..83d213bfd3d 100644
--- a/sound/soc/omap/n810.c
+++ b/sound/soc/omap/n810.c
@@ -35,7 +35,6 @@
35 35
36#include "omap-mcbsp.h" 36#include "omap-mcbsp.h"
37#include "omap-pcm.h" 37#include "omap-pcm.h"
38#include "../codecs/tlv320aic3x.h"
39 38
40#define N810_HEADSET_AMP_GPIO 10 39#define N810_HEADSET_AMP_GPIO 10
41#define N810_SPEAKER_AMP_GPIO 101 40#define N810_SPEAKER_AMP_GPIO 101
diff --git a/sound/soc/omap/rx51.c b/sound/soc/omap/rx51.c
index 150042a785d..09fb0df8d41 100644
--- a/sound/soc/omap/rx51.c
+++ b/sound/soc/omap/rx51.c
@@ -36,7 +36,6 @@
36 36
37#include "omap-mcbsp.h" 37#include "omap-mcbsp.h"
38#include "omap-pcm.h" 38#include "omap-pcm.h"
39#include "../codecs/tlv320aic3x.h"
40 39
41#define RX51_TVOUT_SEL_GPIO 40 40#define RX51_TVOUT_SEL_GPIO 40
42#define RX51_JACK_DETECT_GPIO 177 41#define RX51_JACK_DETECT_GPIO 177
diff --git a/sound/soc/s6000/s6105-ipcam.c b/sound/soc/s6000/s6105-ipcam.c
index bf3f3f9165e..5890e431852 100644
--- a/sound/soc/s6000/s6105-ipcam.c
+++ b/sound/soc/s6000/s6105-ipcam.c
@@ -21,7 +21,6 @@
21 21
22#include <variant/dmac.h> 22#include <variant/dmac.h>
23 23
24#include "../codecs/tlv320aic3x.h"
25#include "s6000-pcm.h" 24#include "s6000-pcm.h"
26#include "s6000-i2s.h" 25#include "s6000-i2s.h"
27 26
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index 67cdad4ee53..a6a6b5fa2f2 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -1,6 +1,6 @@
1config ASOC_SAMSUNG 1config SND_SOC_SAMSUNG
2 tristate "ASoC support for Samsung" 2 tristate "ASoC support for Samsung"
3 depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 3 depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PV310
4 select S3C64XX_DMA if ARCH_S3C64XX 4 select S3C64XX_DMA if ARCH_S3C64XX
5 select S3C2410_DMA if ARCH_S3C2410 5 select S3C2410_DMA if ARCH_S3C2410
6 help 6 help
@@ -34,43 +34,51 @@ config SND_SAMSUNG_SPDIF
34config SND_SAMSUNG_I2S 34config SND_SAMSUNG_I2S
35 tristate 35 tristate
36 36
37config ASOC_SAMSUNG_NEO1973_WM8753 37config SND_SOC_SAMSUNG_NEO1973_WM8753
38 tristate "SoC I2S Audio support for NEO1973 - WM8753" 38 tristate "SoC I2S Audio support for NEO1973 - WM8753"
39 depends on ASOC_SAMSUNG && MACH_NEO1973_GTA01 39 depends on SND_SOC_SAMSUNG && MACH_NEO1973_GTA01
40 select SND_S3C24XX_I2S 40 select SND_S3C24XX_I2S
41 select SND_SOC_WM8753 41 select SND_SOC_WM8753
42 help 42 help
43 Say Y if you want to add support for SoC audio on smdk2440 43 Say Y if you want to add support for SoC audio on smdk2440
44 with the WM8753. 44 with the WM8753.
45 45
46config ASOC_SAMSUNG_NEO1973_GTA02_WM8753 46config SND_SOC_SAMSUNG_NEO1973_GTA02_WM8753
47 tristate "Audio support for the Openmoko Neo FreeRunner (GTA02)" 47 tristate "Audio support for the Openmoko Neo FreeRunner (GTA02)"
48 depends on ASOC_SAMSUNG && MACH_NEO1973_GTA02 48 depends on SND_SOC_SAMSUNG && MACH_NEO1973_GTA02
49 select SND_S3C24XX_I2S 49 select SND_S3C24XX_I2S
50 select SND_SOC_WM8753 50 select SND_SOC_WM8753
51 help 51 help
52 This driver provides audio support for the Openmoko Neo FreeRunner 52 This driver provides audio support for the Openmoko Neo FreeRunner
53 smartphone. 53 smartphone.
54 54
55config ASOC_SAMSUNG_JIVE_WM8750 55config SND_SOC_SAMSUNG_JIVE_WM8750
56 tristate "SoC I2S Audio support for Jive" 56 tristate "SoC I2S Audio support for Jive"
57 depends on ASOC_SAMSUNG && MACH_JIVE 57 depends on SND_SOC_SAMSUNG && MACH_JIVE
58 select SND_SOC_WM8750 58 select SND_SOC_WM8750
59 select SND_S3C2412_SOC_I2S 59 select SND_S3C2412_SOC_I2S
60 help 60 help
61 Sat Y if you want to add support for SoC audio on the Jive. 61 Sat Y if you want to add support for SoC audio on the Jive.
62 62
63config ASOC_SAMSUNG_SMDK_WM8580 63config SND_SOC_SAMSUNG_SMDK_WM8580
64 tristate "SoC I2S Audio support for WM8580 on SMDK" 64 tristate "SoC I2S Audio support for WM8580 on SMDK"
65 depends on ASOC_SAMSUNG && (MACH_SMDK6410 || MACH_SMDKC100) 65 depends on SND_SOC_SAMSUNG && (MACH_SMDK6410 || MACH_SMDKC100 || MACH_SMDK6440 || MACH_SMDK6450 || MACH_SMDK6442 || MACH_SMDKV210 || MACH_SMDKC110)
66 select SND_SOC_WM8580 66 select SND_SOC_WM8580
67 select SND_SAMSUNG_I2S 67 select SND_SAMSUNG_I2S
68 help 68 help
69 Say Y if you want to add support for SoC audio on the SMDKs. 69 Say Y if you want to add support for SoC audio on the SMDKs.
70 70
71config ASOC_SAMSUNG_SMDK2443_WM9710 71config SND_SOC_SAMSUNG_SMDK_WM8994
72 tristate "SoC I2S Audio support for WM8994 on SMDK"
73 depends on SND_SOC_SAMSUNG && (MACH_SMDKV310 || MACH_SMDKC210)
74 select SND_SOC_WM8994
75 select SND_SAMSUNG_I2S
76 help
77 Say Y if you want to add support for SoC audio on the SMDKs.
78
79config SND_SOC_SAMSUNG_SMDK2443_WM9710
72 tristate "SoC AC97 Audio support for SMDK2443 - WM9710" 80 tristate "SoC AC97 Audio support for SMDK2443 - WM9710"
73 depends on ASOC_SAMSUNG && MACH_SMDK2443 81 depends on SND_SOC_SAMSUNG && MACH_SMDK2443
74 select S3C2410_DMA 82 select S3C2410_DMA
75 select AC97_BUS 83 select AC97_BUS
76 select SND_SOC_AC97_CODEC 84 select SND_SOC_AC97_CODEC
@@ -79,9 +87,9 @@ config ASOC_SAMSUNG_SMDK2443_WM9710
79 Say Y if you want to add support for SoC audio on smdk2443 87 Say Y if you want to add support for SoC audio on smdk2443
80 with the WM9710. 88 with the WM9710.
81 89
82config ASOC_SAMSUNG_LN2440SBC_ALC650 90config SND_SOC_SAMSUNG_LN2440SBC_ALC650
83 tristate "SoC AC97 Audio support for LN2440SBC - ALC650" 91 tristate "SoC AC97 Audio support for LN2440SBC - ALC650"
84 depends on ASOC_SAMSUNG && ARCH_S3C2410 92 depends on SND_SOC_SAMSUNG && ARCH_S3C2410
85 select S3C2410_DMA 93 select S3C2410_DMA
86 select AC97_BUS 94 select AC97_BUS
87 select SND_SOC_AC97_CODEC 95 select SND_SOC_AC97_CODEC
@@ -90,74 +98,74 @@ config ASOC_SAMSUNG_LN2440SBC_ALC650
90 Say Y if you want to add support for SoC audio on ln2440sbc 98 Say Y if you want to add support for SoC audio on ln2440sbc
91 with the ALC650. 99 with the ALC650.
92 100
93config ASOC_SAMSUNG_S3C24XX_UDA134X 101config SND_SOC_SAMSUNG_S3C24XX_UDA134X
94 tristate "SoC I2S Audio support UDA134X wired to a S3C24XX" 102 tristate "SoC I2S Audio support UDA134X wired to a S3C24XX"
95 depends on ASOC_SAMSUNG && ARCH_S3C2410 103 depends on SND_SOC_SAMSUNG && ARCH_S3C2410
96 select SND_S3C24XX_I2S 104 select SND_S3C24XX_I2S
97 select SND_SOC_L3 105 select SND_SOC_L3
98 select SND_SOC_UDA134X 106 select SND_SOC_UDA134X
99 107
100config ASOC_SAMSUNG_SIMTEC 108config SND_SOC_SAMSUNG_SIMTEC
101 tristate 109 tristate
102 help 110 help
103 Internal node for common S3C24XX/Simtec suppor 111 Internal node for common S3C24XX/Simtec suppor
104 112
105config ASOC_SAMSUNG_SIMTEC_TLV320AIC23 113config SND_SOC_SAMSUNG_SIMTEC_TLV320AIC23
106 tristate "SoC I2S Audio support for TLV320AIC23 on Simtec boards" 114 tristate "SoC I2S Audio support for TLV320AIC23 on Simtec boards"
107 depends on ASOC_SAMSUNG && ARCH_S3C2410 115 depends on SND_SOC_SAMSUNG && ARCH_S3C2410
108 select SND_S3C24XX_I2S 116 select SND_S3C24XX_I2S
109 select SND_SOC_TLV320AIC23 117 select SND_SOC_TLV320AIC23
110 select ASOC_SAMSUNG_SIMTEC 118 select SND_SOC_SAMSUNG_SIMTEC
111 119
112config ASOC_SAMSUNG_SIMTEC_HERMES 120config SND_SOC_SAMSUNG_SIMTEC_HERMES
113 tristate "SoC I2S Audio support for Simtec Hermes board" 121 tristate "SoC I2S Audio support for Simtec Hermes board"
114 depends on ASOC_SAMSUNG && ARCH_S3C2410 122 depends on SND_SOC_SAMSUNG && ARCH_S3C2410
115 select SND_S3C24XX_I2S 123 select SND_S3C24XX_I2S
116 select SND_SOC_TLV320AIC3X 124 select SND_SOC_TLV320AIC3X
117 select ASOC_SAMSUNG_SIMTEC 125 select SND_SOC_SAMSUNG_SIMTEC
118 126
119config ASOC_SAMSUNG_H1940_UDA1380 127config SND_SOC_SAMSUNG_H1940_UDA1380
120 tristate "Audio support for the HP iPAQ H1940" 128 tristate "Audio support for the HP iPAQ H1940"
121 depends on ASOC_SAMSUNG && ARCH_H1940 129 depends on SND_SOC_SAMSUNG && ARCH_H1940
122 select SND_S3C24XX_I2S 130 select SND_S3C24XX_I2S
123 select SND_SOC_UDA1380 131 select SND_SOC_UDA1380
124 help 132 help
125 This driver provides audio support for HP iPAQ h1940 PDA. 133 This driver provides audio support for HP iPAQ h1940 PDA.
126 134
127config ASOC_SAMSUNG_RX1950_UDA1380 135config SND_SOC_SAMSUNG_RX1950_UDA1380
128 tristate "Audio support for the HP iPAQ RX1950" 136 tristate "Audio support for the HP iPAQ RX1950"
129 depends on ASOC_SAMSUNG && MACH_RX1950 137 depends on SND_SOC_SAMSUNG && MACH_RX1950
130 select SND_S3C24XX_I2S 138 select SND_S3C24XX_I2S
131 select SND_SOC_UDA1380 139 select SND_SOC_UDA1380
132 help 140 help
133 This driver provides audio support for HP iPAQ RX1950 PDA. 141 This driver provides audio support for HP iPAQ RX1950 PDA.
134 142
135config ASOC_SAMSUNG_SMDK_WM9713 143config SND_SOC_SAMSUNG_SMDK_WM9713
136 tristate "SoC AC97 Audio support for SMDK with WM9713" 144 tristate "SoC AC97 Audio support for SMDK with WM9713"
137 depends on ASOC_SAMSUNG && (MACH_SMDK6410 || MACH_SMDKC100 || MACH_SMDKV210 || MACH_SMDKC110) 145 depends on SND_SOC_SAMSUNG && (MACH_SMDK6410 || MACH_SMDKC100 || MACH_SMDKV210 || MACH_SMDKC110 || MACH_SMDKV310 || MACH_SMDKC210)
138 select SND_SOC_WM9713 146 select SND_SOC_WM9713
139 select SND_SAMSUNG_AC97 147 select SND_SAMSUNG_AC97
140 help 148 help
141 Sat Y if you want to add support for SoC audio on the SMDK. 149 Sat Y if you want to add support for SoC audio on the SMDK.
142 150
143config ASOC_SMARTQ 151config SND_SOC_SMARTQ
144 tristate "SoC I2S Audio support for SmartQ board" 152 tristate "SoC I2S Audio support for SmartQ board"
145 depends on ASOC_SAMSUNG && MACH_SMARTQ 153 depends on SND_SOC_SAMSUNG && MACH_SMARTQ
146 select SND_SAMSUNG_I2S 154 select SND_SAMSUNG_I2S
147 select SND_SOC_WM8750 155 select SND_SOC_WM8750
148 156
149config ASOC_GONI_AQUILA_WM8994 157config SND_SOC_GONI_AQUILA_WM8994
150 tristate "SoC I2S Audio support for AQUILA/GONI - WM8994" 158 tristate "SoC I2S Audio support for AQUILA/GONI - WM8994"
151 depends on ASOC_SAMSUNG && (MACH_GONI || MACH_AQUILA) 159 depends on SND_SOC_SAMSUNG && (MACH_GONI || MACH_AQUILA)
152 select SND_SAMSUNG_I2S 160 select SND_SAMSUNG_I2S
153 select SND_SOC_WM8994 161 select SND_SOC_WM8994
154 help 162 help
155 Say Y if you want to add support for SoC audio on goni or aquila 163 Say Y if you want to add support for SoC audio on goni or aquila
156 with the WM8994. 164 with the WM8994.
157 165
158config ASOC_SAMSUNG_SMDK_SPDIF 166config SND_SOC_SAMSUNG_SMDK_SPDIF
159 tristate "SoC S/PDIF Audio support for SMDK" 167 tristate "SoC S/PDIF Audio support for SMDK"
160 depends on ASOC_SAMSUNG && (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210) 168 depends on SND_SOC_SAMSUNG && (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210)
161 select SND_SAMSUNG_SPDIF 169 select SND_SAMSUNG_SPDIF
162 help 170 help
163 Say Y if you want to add support for SoC S/PDIF audio on the SMDK. 171 Say Y if you want to add support for SoC S/PDIF audio on the SMDK.
diff --git a/sound/soc/samsung/Makefile b/sound/soc/samsung/Makefile
index 622e76eb977..705d4e8a672 100644
--- a/sound/soc/samsung/Makefile
+++ b/sound/soc/samsung/Makefile
@@ -8,7 +8,7 @@ snd-soc-samsung-spdif-objs := spdif.o
8snd-soc-pcm-objs := pcm.o 8snd-soc-pcm-objs := pcm.o
9snd-soc-i2s-objs := i2s.o 9snd-soc-i2s-objs := i2s.o
10 10
11obj-$(CONFIG_ASOC_SAMSUNG) += snd-soc-s3c24xx.o 11obj-$(CONFIG_SND_SOC_SAMSUNG) += snd-soc-s3c24xx.o
12obj-$(CONFIG_SND_S3C24XX_I2S) += snd-soc-s3c24xx-i2s.o 12obj-$(CONFIG_SND_S3C24XX_I2S) += snd-soc-s3c24xx-i2s.o
13obj-$(CONFIG_SND_SAMSUNG_AC97) += snd-soc-ac97.o 13obj-$(CONFIG_SND_SAMSUNG_AC97) += snd-soc-ac97.o
14obj-$(CONFIG_SND_S3C2412_SOC_I2S) += snd-soc-s3c2412-i2s.o 14obj-$(CONFIG_SND_S3C2412_SOC_I2S) += snd-soc-s3c2412-i2s.o
@@ -30,24 +30,26 @@ snd-soc-s3c24xx-simtec-tlv320aic23-objs := s3c24xx_simtec_tlv320aic23.o
30snd-soc-h1940-uda1380-objs := h1940_uda1380.o 30snd-soc-h1940-uda1380-objs := h1940_uda1380.o
31snd-soc-rx1950-uda1380-objs := rx1950_uda1380.o 31snd-soc-rx1950-uda1380-objs := rx1950_uda1380.o
32snd-soc-smdk-wm8580-objs := smdk_wm8580.o 32snd-soc-smdk-wm8580-objs := smdk_wm8580.o
33snd-soc-smdk-wm8994-objs := smdk_wm8994.o
33snd-soc-smdk-wm9713-objs := smdk_wm9713.o 34snd-soc-smdk-wm9713-objs := smdk_wm9713.o
34snd-soc-s3c64xx-smartq-wm8987-objs := smartq_wm8987.o 35snd-soc-s3c64xx-smartq-wm8987-objs := smartq_wm8987.o
35snd-soc-goni-wm8994-objs := goni_wm8994.o 36snd-soc-goni-wm8994-objs := goni_wm8994.o
36snd-soc-smdk-spdif-objs := smdk_spdif.o 37snd-soc-smdk-spdif-objs := smdk_spdif.o
37 38
38obj-$(CONFIG_ASOC_SAMSUNG_JIVE_WM8750) += snd-soc-jive-wm8750.o 39obj-$(CONFIG_SND_SOC_SAMSUNG_JIVE_WM8750) += snd-soc-jive-wm8750.o
39obj-$(CONFIG_ASOC_SAMSUNG_NEO1973_WM8753) += snd-soc-neo1973-wm8753.o 40obj-$(CONFIG_SND_SOC_SAMSUNG_NEO1973_WM8753) += snd-soc-neo1973-wm8753.o
40obj-$(CONFIG_ASOC_SAMSUNG_NEO1973_GTA02_WM8753) += snd-soc-neo1973-gta02-wm8753.o 41obj-$(CONFIG_SND_SOC_SAMSUNG_NEO1973_GTA02_WM8753) += snd-soc-neo1973-gta02-wm8753.o
41obj-$(CONFIG_ASOC_SAMSUNG_SMDK2443_WM9710) += snd-soc-smdk2443-wm9710.o 42obj-$(CONFIG_SND_SOC_SAMSUNG_SMDK2443_WM9710) += snd-soc-smdk2443-wm9710.o
42obj-$(CONFIG_ASOC_SAMSUNG_LN2440SBC_ALC650) += snd-soc-ln2440sbc-alc650.o 43obj-$(CONFIG_SND_SOC_SAMSUNG_LN2440SBC_ALC650) += snd-soc-ln2440sbc-alc650.o
43obj-$(CONFIG_ASOC_SAMSUNG_S3C24XX_UDA134X) += snd-soc-s3c24xx-uda134x.o 44obj-$(CONFIG_SND_SOC_SAMSUNG_S3C24XX_UDA134X) += snd-soc-s3c24xx-uda134x.o
44obj-$(CONFIG_ASOC_SAMSUNG_SIMTEC) += snd-soc-s3c24xx-simtec.o 45obj-$(CONFIG_SND_SOC_SAMSUNG_SIMTEC) += snd-soc-s3c24xx-simtec.o
45obj-$(CONFIG_ASOC_SAMSUNG_SIMTEC_HERMES) += snd-soc-s3c24xx-simtec-hermes.o 46obj-$(CONFIG_SND_SOC_SAMSUNG_SIMTEC_HERMES) += snd-soc-s3c24xx-simtec-hermes.o
46obj-$(CONFIG_ASOC_SAMSUNG_SIMTEC_TLV320AIC23) += snd-soc-s3c24xx-simtec-tlv320aic23.o 47obj-$(CONFIG_SND_SOC_SAMSUNG_SIMTEC_TLV320AIC23) += snd-soc-s3c24xx-simtec-tlv320aic23.o
47obj-$(CONFIG_ASOC_SAMSUNG_H1940_UDA1380) += snd-soc-h1940-uda1380.o 48obj-$(CONFIG_SND_SOC_SAMSUNG_H1940_UDA1380) += snd-soc-h1940-uda1380.o
48obj-$(CONFIG_ASOC_SAMSUNG_RX1950_UDA1380) += snd-soc-rx1950-uda1380.o 49obj-$(CONFIG_SND_SOC_SAMSUNG_RX1950_UDA1380) += snd-soc-rx1950-uda1380.o
49obj-$(CONFIG_ASOC_SAMSUNG_SMDK_WM8580) += snd-soc-smdk-wm8580.o 50obj-$(CONFIG_SND_SOC_SAMSUNG_SMDK_WM8580) += snd-soc-smdk-wm8580.o
50obj-$(CONFIG_ASOC_SAMSUNG_SMDK_WM9713) += snd-soc-smdk-wm9713.o 51obj-$(CONFIG_SND_SOC_SAMSUNG_SMDK_WM8994) += snd-soc-smdk-wm8994.o
51obj-$(CONFIG_ASOC_SMARTQ) += snd-soc-s3c64xx-smartq-wm8987.o 52obj-$(CONFIG_SND_SOC_SAMSUNG_SMDK_WM9713) += snd-soc-smdk-wm9713.o
52obj-$(CONFIG_ASOC_SAMSUNG_SMDK_SPDIF) += snd-soc-smdk-spdif.o 53obj-$(CONFIG_SND_SOC_SMARTQ) += snd-soc-s3c64xx-smartq-wm8987.o
53obj-$(CONFIG_ASOC_GONI_AQUILA_WM8994) += snd-soc-goni-wm8994.o 54obj-$(CONFIG_SND_SOC_SAMSUNG_SMDK_SPDIF) += snd-soc-smdk-spdif.o
55obj-$(CONFIG_SND_SOC_GONI_AQUILA_WM8994) += snd-soc-goni-wm8994.o
diff --git a/sound/soc/samsung/goni_wm8994.c b/sound/soc/samsung/goni_wm8994.c
index cc8528c0a49..34dd9ef1b9c 100644
--- a/sound/soc/samsung/goni_wm8994.c
+++ b/sound/soc/samsung/goni_wm8994.c
@@ -131,7 +131,7 @@ static int goni_wm8994_init(struct snd_soc_pcm_runtime *rtd)
131 snd_soc_dapm_sync(dapm); 131 snd_soc_dapm_sync(dapm);
132 132
133 /* Headset jack detection */ 133 /* Headset jack detection */
134 ret = snd_soc_jack_new(&goni, "Headset Jack", 134 ret = snd_soc_jack_new(codec, "Headset Jack",
135 SND_JACK_HEADSET | SND_JACK_MECHANICAL | SND_JACK_AVOUT, 135 SND_JACK_HEADSET | SND_JACK_MECHANICAL | SND_JACK_AVOUT,
136 &jack); 136 &jack);
137 if (ret) 137 if (ret)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index d6de3f0eeff..d00ac3a7102 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -525,6 +525,8 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai,
525 clk_disable(i2s->op_clk); 525 clk_disable(i2s->op_clk);
526 clk_put(i2s->op_clk); 526 clk_put(i2s->op_clk);
527 } else { 527 } else {
528 i2s->rclk_srcrate =
529 clk_get_rate(i2s->op_clk);
528 return 0; 530 return 0;
529 } 531 }
530 } 532 }
@@ -841,11 +843,6 @@ static int i2s_trigger(struct snd_pcm_substream *substream,
841 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 843 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
842 local_irq_save(flags); 844 local_irq_save(flags);
843 845
844 if (capture)
845 i2s_fifo(i2s, FIC_RXFLUSH);
846 else
847 i2s_fifo(i2s, FIC_TXFLUSH);
848
849 if (config_setup(i2s)) { 846 if (config_setup(i2s)) {
850 local_irq_restore(flags); 847 local_irq_restore(flags);
851 return -EINVAL; 848 return -EINVAL;
@@ -868,6 +865,11 @@ static int i2s_trigger(struct snd_pcm_substream *substream,
868 else 865 else
869 i2s_txctrl(i2s, 0); 866 i2s_txctrl(i2s, 0);
870 867
868 if (capture)
869 i2s_fifo(i2s, FIC_RXFLUSH);
870 else
871 i2s_fifo(i2s, FIC_TXFLUSH);
872
871 local_irq_restore(flags); 873 local_irq_restore(flags);
872 break; 874 break;
873 } 875 }
diff --git a/sound/soc/samsung/s3c24xx_simtec_hermes.c b/sound/soc/samsung/s3c24xx_simtec_hermes.c
index 0083aff5a83..bb4292e3596 100644
--- a/sound/soc/samsung/s3c24xx_simtec_hermes.c
+++ b/sound/soc/samsung/s3c24xx_simtec_hermes.c
@@ -21,8 +21,6 @@
21#include "s3c24xx-i2s.h" 21#include "s3c24xx-i2s.h"
22#include "s3c24xx_simtec.h" 22#include "s3c24xx_simtec.h"
23 23
24#include "../codecs/tlv320aic3x.h"
25
26static const struct snd_soc_dapm_widget dapm_widgets[] = { 24static const struct snd_soc_dapm_widget dapm_widgets[] = {
27 SND_SOC_DAPM_LINE("GSM Out", NULL), 25 SND_SOC_DAPM_LINE("GSM Out", NULL),
28 SND_SOC_DAPM_LINE("GSM In", NULL), 26 SND_SOC_DAPM_LINE("GSM In", NULL),
diff --git a/sound/soc/samsung/smdk_wm8580.c b/sound/soc/samsung/smdk_wm8580.c
index e2d56b9bac5..b2cff1a44ae 100644
--- a/sound/soc/samsung/smdk_wm8580.c
+++ b/sound/soc/samsung/smdk_wm8580.c
@@ -212,7 +212,7 @@ static struct snd_soc_dai_link smdk_dai[] = {
212 [PRI_PLAYBACK] = { /* Primary Playback i/f */ 212 [PRI_PLAYBACK] = { /* Primary Playback i/f */
213 .name = "WM8580 PAIF RX", 213 .name = "WM8580 PAIF RX",
214 .stream_name = "Playback", 214 .stream_name = "Playback",
215 .cpu_dai_name = "samsung-i2s.2", 215 .cpu_dai_name = "samsung-i2s.0",
216 .codec_dai_name = "wm8580-hifi-playback", 216 .codec_dai_name = "wm8580-hifi-playback",
217 .platform_name = "samsung-audio", 217 .platform_name = "samsung-audio",
218 .codec_name = "wm8580-codec.0-001b", 218 .codec_name = "wm8580-codec.0-001b",
@@ -222,7 +222,7 @@ static struct snd_soc_dai_link smdk_dai[] = {
222 [PRI_CAPTURE] = { /* Primary Capture i/f */ 222 [PRI_CAPTURE] = { /* Primary Capture i/f */
223 .name = "WM8580 PAIF TX", 223 .name = "WM8580 PAIF TX",
224 .stream_name = "Capture", 224 .stream_name = "Capture",
225 .cpu_dai_name = "samsung-i2s.2", 225 .cpu_dai_name = "samsung-i2s.0",
226 .codec_dai_name = "wm8580-hifi-capture", 226 .codec_dai_name = "wm8580-hifi-capture",
227 .platform_name = "samsung-audio", 227 .platform_name = "samsung-audio",
228 .codec_name = "wm8580-codec.0-001b", 228 .codec_name = "wm8580-codec.0-001b",
@@ -254,16 +254,17 @@ static int __init smdk_audio_init(void)
254 int ret; 254 int ret;
255 char *str; 255 char *str;
256 256
257 if (machine_is_smdkc100()) { 257 if (machine_is_smdkc100() || machine_is_smdk6442()
258 || machine_is_smdkv210() || machine_is_smdkc110()) {
258 smdk.num_links = 3; 259 smdk.num_links = 3;
259 /* S5PC100 has I2S0 as v5 */
260 str = (char *)smdk_dai[PRI_PLAYBACK].cpu_dai_name;
261 str[strlen(str) - 1] = '0';
262 str = (char *)smdk_dai[PRI_CAPTURE].cpu_dai_name;
263 str[strlen(str) - 1] = '0';
264 /* Secondary is at offset SAMSUNG_I2S_SECOFF from Primary */ 260 /* Secondary is at offset SAMSUNG_I2S_SECOFF from Primary */
265 str = (char *)smdk_dai[SEC_PLAYBACK].cpu_dai_name; 261 str = (char *)smdk_dai[SEC_PLAYBACK].cpu_dai_name;
266 str[strlen(str) - 1] = '0' + SAMSUNG_I2S_SECOFF; 262 str[strlen(str) - 1] = '0' + SAMSUNG_I2S_SECOFF;
263 } else if (machine_is_smdk6410()) {
264 str = (char *)smdk_dai[PRI_PLAYBACK].cpu_dai_name;
265 str[strlen(str) - 1] = '2';
266 str = (char *)smdk_dai[PRI_CAPTURE].cpu_dai_name;
267 str[strlen(str) - 1] = '2';
267 } 268 }
268 269
269 smdk_snd_device = platform_device_alloc("soc-audio", -1); 270 smdk_snd_device = platform_device_alloc("soc-audio", -1);
diff --git a/sound/soc/samsung/smdk_wm8994.c b/sound/soc/samsung/smdk_wm8994.c
new file mode 100644
index 00000000000..e7c1009a1e1
--- /dev/null
+++ b/sound/soc/samsung/smdk_wm8994.c
@@ -0,0 +1,176 @@
1/*
2 * smdk_wm8994.c
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include "../codecs/wm8994.h"
11
12 /*
13 * Default CFG switch settings to use this driver:
14 * SMDKV310: CFG5-1000, CFG7-111111
15 */
16
17 /*
18 * Configure audio route as :-
19 * $ amixer sset 'DAC1' on,on
20 * $ amixer sset 'Right Headphone Mux' 'DAC'
21 * $ amixer sset 'Left Headphone Mux' 'DAC'
22 * $ amixer sset 'DAC1R Mixer AIF1.1' on
23 * $ amixer sset 'DAC1L Mixer AIF1.1' on
24 * $ amixer sset 'IN2L' on
25 * $ amixer sset 'IN2L PGA IN2LN' on
26 * $ amixer sset 'MIXINL IN2L' on
27 * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
28 * $ amixer sset 'IN2R' on
29 * $ amixer sset 'IN2R PGA IN2RN' on
30 * $ amixer sset 'MIXINR IN2R' on
31 * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
32 */
33
34/* SMDK has a 16.934MHZ crystal attached to WM8994 */
35#define SMDK_WM8994_FREQ 16934000
36
37static int smdk_hw_params(struct snd_pcm_substream *substream,
38 struct snd_pcm_hw_params *params)
39{
40 struct snd_soc_pcm_runtime *rtd = substream->private_data;
41 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
42 struct snd_soc_dai *codec_dai = rtd->codec_dai;
43 unsigned int pll_out;
44 int ret;
45
46 /* AIF1CLK should be >=3MHz for optimal performance */
47 if (params_rate(params) == 8000 || params_rate(params) == 11025)
48 pll_out = params_rate(params) * 512;
49 else
50 pll_out = params_rate(params) * 256;
51
52 ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
53 | SND_SOC_DAIFMT_NB_NF
54 | SND_SOC_DAIFMT_CBM_CFM);
55 if (ret < 0)
56 return ret;
57
58 ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
59 | SND_SOC_DAIFMT_NB_NF
60 | SND_SOC_DAIFMT_CBM_CFM);
61 if (ret < 0)
62 return ret;
63
64 ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL1, WM8994_FLL_SRC_MCLK1,
65 SMDK_WM8994_FREQ, pll_out);
66 if (ret < 0)
67 return ret;
68
69 ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL1,
70 pll_out, SND_SOC_CLOCK_IN);
71 if (ret < 0)
72 return ret;
73
74 return 0;
75}
76
77/*
78 * SMDK WM8994 DAI operations.
79 */
80static struct snd_soc_ops smdk_ops = {
81 .hw_params = smdk_hw_params,
82};
83
84static int smdk_wm8994_init_paiftx(struct snd_soc_pcm_runtime *rtd)
85{
86 struct snd_soc_codec *codec = rtd->codec;
87 struct snd_soc_dapm_context *dapm = &codec->dapm;
88
89 /* HeadPhone */
90 snd_soc_dapm_enable_pin(dapm, "HPOUT1R");
91 snd_soc_dapm_enable_pin(dapm, "HPOUT1L");
92
93 /* MicIn */
94 snd_soc_dapm_enable_pin(dapm, "IN1LN");
95 snd_soc_dapm_enable_pin(dapm, "IN1RN");
96
97 /* LineIn */
98 snd_soc_dapm_enable_pin(dapm, "IN2LN");
99 snd_soc_dapm_enable_pin(dapm, "IN2RN");
100
101 /* Other pins NC */
102 snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
103 snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
104 snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
105 snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
106 snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
107 snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
108 snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
109 snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
110 snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
111 snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
112 snd_soc_dapm_nc_pin(dapm, "IN1LP");
113 snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
114 snd_soc_dapm_nc_pin(dapm, "IN1RP");
115 snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
116
117 snd_soc_dapm_sync(dapm);
118
119 return 0;
120}
121
122static struct snd_soc_dai_link smdk_dai[] = {
123 { /* Primary DAI i/f */
124 .name = "WM8994 AIF1",
125 .stream_name = "Pri_Dai",
126 .cpu_dai_name = "samsung-i2s.0",
127 .codec_dai_name = "wm8994-aif1",
128 .platform_name = "samsung-audio",
129 .codec_name = "wm8994-codec",
130 .init = smdk_wm8994_init_paiftx,
131 .ops = &smdk_ops,
132 }, { /* Sec_Fifo Playback i/f */
133 .name = "Sec_FIFO TX",
134 .stream_name = "Sec_Dai",
135 .cpu_dai_name = "samsung-i2s.4",
136 .codec_dai_name = "wm8994-aif1",
137 .platform_name = "samsung-audio",
138 .codec_name = "wm8994-codec",
139 .ops = &smdk_ops,
140 },
141};
142
143static struct snd_soc_card smdk = {
144 .name = "SMDK-I2S",
145 .dai_link = smdk_dai,
146 .num_links = ARRAY_SIZE(smdk_dai),
147};
148
149static struct platform_device *smdk_snd_device;
150
151static int __init smdk_audio_init(void)
152{
153 int ret;
154
155 smdk_snd_device = platform_device_alloc("soc-audio", -1);
156 if (!smdk_snd_device)
157 return -ENOMEM;
158
159 platform_set_drvdata(smdk_snd_device, &smdk);
160
161 ret = platform_device_add(smdk_snd_device);
162 if (ret)
163 platform_device_put(smdk_snd_device);
164
165 return ret;
166}
167module_init(smdk_audio_init);
168
169static void __exit smdk_audio_exit(void)
170{
171 platform_device_unregister(smdk_snd_device);
172}
173module_exit(smdk_audio_exit);
174
175MODULE_DESCRIPTION("ALSA SoC SMDK WM8994");
176MODULE_LICENSE("GPL");
diff --git a/sound/soc/samsung/smdk_wm9713.c b/sound/soc/samsung/smdk_wm9713.c
index 238cb3a38c5..ae5fed6f772 100644
--- a/sound/soc/samsung/smdk_wm9713.c
+++ b/sound/soc/samsung/smdk_wm9713.c
@@ -27,6 +27,7 @@ static struct snd_soc_card smdk;
27 * SMDKC100: Set CFG6 1-3 On, CFG7 1 On 27 * SMDKC100: Set CFG6 1-3 On, CFG7 1 On
28 * SMDKC110: Set CFGB10 1-2 Off, CFGB12 1-3 On 28 * SMDKC110: Set CFGB10 1-2 Off, CFGB12 1-3 On
29 * SMDKV210: Set CFGB10 1-2 Off, CFGB12 1-3 On 29 * SMDKV210: Set CFGB10 1-2 Off, CFGB12 1-3 On
30 * SMDKV310: Set CFG2 1-2 Off, CFG4 All On, CFG7 All Off, CFG8 1-On
30 */ 31 */
31 32
32/* 33/*
diff --git a/sound/soc/sh/Kconfig b/sound/soc/sh/Kconfig
index 7f0a496e07c..d8e06a607a2 100644
--- a/sound/soc/sh/Kconfig
+++ b/sound/soc/sh/Kconfig
@@ -48,7 +48,7 @@ config SND_SH7760_AC97
48 48
49config SND_FSI_AK4642 49config SND_FSI_AK4642
50 tristate "FSI-AK4642 sound support" 50 tristate "FSI-AK4642 sound support"
51 depends on SND_SOC_SH4_FSI && I2C_SH_MOBILE 51 depends on SND_SOC_SH4_FSI && I2C
52 select SND_SOC_AK4642 52 select SND_SOC_AK4642
53 help 53 help
54 This option enables generic sound support for the 54 This option enables generic sound support for the
@@ -56,7 +56,7 @@ config SND_FSI_AK4642
56 56
57config SND_FSI_DA7210 57config SND_FSI_DA7210
58 tristate "FSI-DA7210 sound support" 58 tristate "FSI-DA7210 sound support"
59 depends on SND_SOC_SH4_FSI && I2C_SH_MOBILE 59 depends on SND_SOC_SH4_FSI && I2C
60 select SND_SOC_DA7210 60 select SND_SOC_DA7210
61 help 61 help
62 This option enables generic sound support for the 62 This option enables generic sound support for the
diff --git a/sound/soc/sh/fsi-da7210.c b/sound/soc/sh/fsi-da7210.c
index a6adb6e4325..e8df9da92f7 100644
--- a/sound/soc/sh/fsi-da7210.c
+++ b/sound/soc/sh/fsi-da7210.c
@@ -18,7 +18,7 @@ static int fsi_da7210_init(struct snd_soc_pcm_runtime *rtd)
18 struct snd_soc_dai *dai = rtd->codec_dai; 18 struct snd_soc_dai *dai = rtd->codec_dai;
19 19
20 return snd_soc_dai_set_fmt(dai, 20 return snd_soc_dai_set_fmt(dai,
21 SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | 21 SND_SOC_DAIFMT_I2S |
22 SND_SOC_DAIFMT_CBM_CFM); 22 SND_SOC_DAIFMT_CBM_CFM);
23} 23}
24 24
diff --git a/sound/soc/sh/fsi.c b/sound/soc/sh/fsi.c
index 97c5394aa7d..2b06402801e 100644
--- a/sound/soc/sh/fsi.c
+++ b/sound/soc/sh/fsi.c
@@ -134,6 +134,9 @@ struct fsi_stream {
134 int buff_len; 134 int buff_len;
135 int period_len; 135 int period_len;
136 int period_num; 136 int period_num;
137
138 int uerr_num;
139 int oerr_num;
137}; 140};
138 141
139struct fsi_priv { 142struct fsi_priv {
@@ -326,17 +329,29 @@ static void fsi_stream_push(struct fsi_priv *fsi,
326 io->buff_offset = 0; 329 io->buff_offset = 0;
327 io->period_len = period_len; 330 io->period_len = period_len;
328 io->period_num = 0; 331 io->period_num = 0;
332 io->oerr_num = -1; /* ignore 1st err */
333 io->uerr_num = -1; /* ignore 1st err */
329} 334}
330 335
331static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) 336static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
332{ 337{
333 struct fsi_stream *io = fsi_get_stream(fsi, is_play); 338 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
339 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
340
341
342 if (io->oerr_num > 0)
343 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
344
345 if (io->uerr_num > 0)
346 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
334 347
335 io->substream = NULL; 348 io->substream = NULL;
336 io->buff_len = 0; 349 io->buff_len = 0;
337 io->buff_offset = 0; 350 io->buff_offset = 0;
338 io->period_len = 0; 351 io->period_len = 0;
339 io->period_num = 0; 352 io->period_num = 0;
353 io->oerr_num = 0;
354 io->uerr_num = 0;
340} 355}
341 356
342static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play) 357static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
@@ -375,6 +390,27 @@ static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play)
375 return frames_to_bytes(runtime, 1) / io->chan_num; 390 return frames_to_bytes(runtime, 1) / io->chan_num;
376} 391}
377 392
393static void fsi_count_fifo_err(struct fsi_priv *fsi)
394{
395 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
396 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
397
398 if (ostatus & ERR_OVER)
399 fsi->playback.oerr_num++;
400
401 if (ostatus & ERR_UNDER)
402 fsi->playback.uerr_num++;
403
404 if (istatus & ERR_OVER)
405 fsi->capture.oerr_num++;
406
407 if (istatus & ERR_UNDER)
408 fsi->capture.uerr_num++;
409
410 fsi_reg_write(fsi, DOFF_ST, 0);
411 fsi_reg_write(fsi, DIFF_ST, 0);
412}
413
378/* 414/*
379 * dma function 415 * dma function
380 */ 416 */
@@ -574,7 +610,7 @@ static void fsi_soft_all_reset(struct fsi_master *master)
574 mdelay(10); 610 mdelay(10);
575} 611}
576 612
577static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream) 613static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream)
578{ 614{
579 struct snd_pcm_runtime *runtime; 615 struct snd_pcm_runtime *runtime;
580 struct snd_pcm_substream *substream = NULL; 616 struct snd_pcm_substream *substream = NULL;
@@ -667,40 +703,20 @@ static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream)
667 /* update buff_offset */ 703 /* update buff_offset */
668 io->buff_offset += fsi_num2offset(data_num, ch_width); 704 io->buff_offset += fsi_num2offset(data_num, ch_width);
669 705
670 /* check fifo status */
671 if (!startup) {
672 struct snd_soc_dai *dai = fsi_get_dai(substream);
673 u32 status = is_play ?
674 fsi_reg_read(fsi, DOFF_ST) :
675 fsi_reg_read(fsi, DIFF_ST);
676
677 if (status & ERR_OVER)
678 dev_err(dai->dev, "over run\n");
679 if (status & ERR_UNDER)
680 dev_err(dai->dev, "under run\n");
681 }
682
683 is_play ?
684 fsi_reg_write(fsi, DOFF_ST, 0) :
685 fsi_reg_write(fsi, DIFF_ST, 0);
686
687 /* re-enable irq */
688 fsi_irq_enable(fsi, is_play);
689
690 if (over_period) 706 if (over_period)
691 snd_pcm_period_elapsed(substream); 707 snd_pcm_period_elapsed(substream);
692 708
693 return 0; 709 return 0;
694} 710}
695 711
696static int fsi_data_pop(struct fsi_priv *fsi, int startup) 712static int fsi_data_pop(struct fsi_priv *fsi)
697{ 713{
698 return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_CAPTURE); 714 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE);
699} 715}
700 716
701static int fsi_data_push(struct fsi_priv *fsi, int startup) 717static int fsi_data_push(struct fsi_priv *fsi)
702{ 718{
703 return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_PLAYBACK); 719 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK);
704} 720}
705 721
706static irqreturn_t fsi_interrupt(int irq, void *data) 722static irqreturn_t fsi_interrupt(int irq, void *data)
@@ -713,13 +729,16 @@ static irqreturn_t fsi_interrupt(int irq, void *data)
713 fsi_master_mask_set(master, SOFT_RST, IR, IR); 729 fsi_master_mask_set(master, SOFT_RST, IR, IR);
714 730
715 if (int_st & AB_IO(1, AO_SHIFT)) 731 if (int_st & AB_IO(1, AO_SHIFT))
716 fsi_data_push(&master->fsia, 0); 732 fsi_data_push(&master->fsia);
717 if (int_st & AB_IO(1, BO_SHIFT)) 733 if (int_st & AB_IO(1, BO_SHIFT))
718 fsi_data_push(&master->fsib, 0); 734 fsi_data_push(&master->fsib);
719 if (int_st & AB_IO(1, AI_SHIFT)) 735 if (int_st & AB_IO(1, AI_SHIFT))
720 fsi_data_pop(&master->fsia, 0); 736 fsi_data_pop(&master->fsia);
721 if (int_st & AB_IO(1, BI_SHIFT)) 737 if (int_st & AB_IO(1, BI_SHIFT))
722 fsi_data_pop(&master->fsib, 0); 738 fsi_data_pop(&master->fsib);
739
740 fsi_count_fifo_err(&master->fsia);
741 fsi_count_fifo_err(&master->fsib);
723 742
724 fsi_irq_clear_status(&master->fsia); 743 fsi_irq_clear_status(&master->fsia);
725 fsi_irq_clear_status(&master->fsib); 744 fsi_irq_clear_status(&master->fsib);
@@ -858,7 +877,8 @@ static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
858 fsi_stream_push(fsi, is_play, substream, 877 fsi_stream_push(fsi, is_play, substream,
859 frames_to_bytes(runtime, runtime->buffer_size), 878 frames_to_bytes(runtime, runtime->buffer_size),
860 frames_to_bytes(runtime, runtime->period_size)); 879 frames_to_bytes(runtime, runtime->period_size));
861 ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1); 880 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi);
881 fsi_irq_enable(fsi, is_play);
862 break; 882 break;
863 case SNDRV_PCM_TRIGGER_STOP: 883 case SNDRV_PCM_TRIGGER_STOP:
864 fsi_irq_disable(fsi, is_play); 884 fsi_irq_disable(fsi, is_play);
diff --git a/sound/soc/soc-cache.c b/sound/soc/soc-cache.c
index 0e17b405042..a9ebc078bea 100644
--- a/sound/soc/soc-cache.c
+++ b/sound/soc/soc-cache.c
@@ -988,6 +988,7 @@ static int snd_soc_rbtree_cache_init(struct snd_soc_codec *codec)
988 return 0; 988 return 0;
989} 989}
990 990
991#ifdef CONFIG_SND_SOC_CACHE_LZO
991struct snd_soc_lzo_ctx { 992struct snd_soc_lzo_ctx {
992 void *wmem; 993 void *wmem;
993 void *dst; 994 void *dst;
@@ -1399,6 +1400,7 @@ err_tofree:
1399 } 1400 }
1400 return ret; 1401 return ret;
1401} 1402}
1403#endif
1402 1404
1403static int snd_soc_flat_cache_sync(struct snd_soc_codec *codec) 1405static int snd_soc_flat_cache_sync(struct snd_soc_codec *codec)
1404{ 1406{
@@ -1531,6 +1533,7 @@ static int snd_soc_flat_cache_init(struct snd_soc_codec *codec)
1531 1533
1532/* an array of all supported compression types */ 1534/* an array of all supported compression types */
1533static const struct snd_soc_cache_ops cache_types[] = { 1535static const struct snd_soc_cache_ops cache_types[] = {
1536 /* Flat *must* be the first entry for fallback */
1534 { 1537 {
1535 .id = SND_SOC_FLAT_COMPRESSION, 1538 .id = SND_SOC_FLAT_COMPRESSION,
1536 .name = "flat", 1539 .name = "flat",
@@ -1540,6 +1543,7 @@ static const struct snd_soc_cache_ops cache_types[] = {
1540 .write = snd_soc_flat_cache_write, 1543 .write = snd_soc_flat_cache_write,
1541 .sync = snd_soc_flat_cache_sync 1544 .sync = snd_soc_flat_cache_sync
1542 }, 1545 },
1546#ifdef CONFIG_SND_SOC_CACHE_LZO
1543 { 1547 {
1544 .id = SND_SOC_LZO_COMPRESSION, 1548 .id = SND_SOC_LZO_COMPRESSION,
1545 .name = "LZO", 1549 .name = "LZO",
@@ -1549,6 +1553,7 @@ static const struct snd_soc_cache_ops cache_types[] = {
1549 .write = snd_soc_lzo_cache_write, 1553 .write = snd_soc_lzo_cache_write,
1550 .sync = snd_soc_lzo_cache_sync 1554 .sync = snd_soc_lzo_cache_sync
1551 }, 1555 },
1556#endif
1552 { 1557 {
1553 .id = SND_SOC_RBTREE_COMPRESSION, 1558 .id = SND_SOC_RBTREE_COMPRESSION,
1554 .name = "rbtree", 1559 .name = "rbtree",
@@ -1567,10 +1572,12 @@ int snd_soc_cache_init(struct snd_soc_codec *codec)
1567 for (i = 0; i < ARRAY_SIZE(cache_types); ++i) 1572 for (i = 0; i < ARRAY_SIZE(cache_types); ++i)
1568 if (cache_types[i].id == codec->compress_type) 1573 if (cache_types[i].id == codec->compress_type)
1569 break; 1574 break;
1575
1576 /* Fall back to flat compression */
1570 if (i == ARRAY_SIZE(cache_types)) { 1577 if (i == ARRAY_SIZE(cache_types)) {
1571 dev_err(codec->dev, "Could not match compress type: %d\n", 1578 dev_warn(codec->dev, "Could not match compress type: %d\n",
1572 codec->compress_type); 1579 codec->compress_type);
1573 return -EINVAL; 1580 i = 0;
1574 } 1581 }
1575 1582
1576 mutex_init(&codec->cache_rw_mutex); 1583 mutex_init(&codec->cache_rw_mutex);
diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index 1dc4b11c198..bac7291b6ff 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -1259,9 +1259,6 @@ find_codec:
1259 if (!strcmp(codec->name, dai_link->codec_name)) { 1259 if (!strcmp(codec->name, dai_link->codec_name)) {
1260 rtd->codec = codec; 1260 rtd->codec = codec;
1261 1261
1262 if (!try_module_get(codec->dev->driver->owner))
1263 return -ENODEV;
1264
1265 /* CODEC found, so find CODEC DAI from registered DAIs from this CODEC*/ 1262 /* CODEC found, so find CODEC DAI from registered DAIs from this CODEC*/
1266 list_for_each_entry(codec_dai, &dai_list, list) { 1263 list_for_each_entry(codec_dai, &dai_list, list) {
1267 if (codec->dev == codec_dai->dev && 1264 if (codec->dev == codec_dai->dev &&
@@ -1287,10 +1284,6 @@ find_platform:
1287 /* no, then find CPU DAI from registered DAIs*/ 1284 /* no, then find CPU DAI from registered DAIs*/
1288 list_for_each_entry(platform, &platform_list, list) { 1285 list_for_each_entry(platform, &platform_list, list) {
1289 if (!strcmp(platform->name, dai_link->platform_name)) { 1286 if (!strcmp(platform->name, dai_link->platform_name)) {
1290
1291 if (!try_module_get(platform->dev->driver->owner))
1292 return -ENODEV;
1293
1294 rtd->platform = platform; 1287 rtd->platform = platform;
1295 goto out; 1288 goto out;
1296 } 1289 }
@@ -1425,8 +1418,12 @@ static int soc_probe_codec(struct snd_soc_card *card,
1425 soc_init_codec_debugfs(codec); 1418 soc_init_codec_debugfs(codec);
1426 1419
1427 /* mark codec as probed and add to card codec list */ 1420 /* mark codec as probed and add to card codec list */
1421 if (!try_module_get(codec->dev->driver->owner))
1422 return -ENODEV;
1423
1428 codec->probed = 1; 1424 codec->probed = 1;
1429 list_add(&codec->card_list, &card->codec_dev_list); 1425 list_add(&codec->card_list, &card->codec_dev_list);
1426 list_add(&codec->dapm.list, &card->dapm_list);
1430 1427
1431 return ret; 1428 return ret;
1432} 1429}
@@ -1555,6 +1552,10 @@ static int soc_probe_dai_link(struct snd_soc_card *card, int num)
1555 } 1552 }
1556 } 1553 }
1557 /* mark platform as probed and add to card platform list */ 1554 /* mark platform as probed and add to card platform list */
1555
1556 if (!try_module_get(platform->dev->driver->owner))
1557 return -ENODEV;
1558
1558 platform->probed = 1; 1559 platform->probed = 1;
1559 list_add(&platform->card_list, &card->platform_dev_list); 1560 list_add(&platform->card_list, &card->platform_dev_list);
1560 } 1561 }
@@ -1879,6 +1880,9 @@ static int soc_probe(struct platform_device *pdev)
1879 INIT_LIST_HEAD(&card->dai_dev_list); 1880 INIT_LIST_HEAD(&card->dai_dev_list);
1880 INIT_LIST_HEAD(&card->codec_dev_list); 1881 INIT_LIST_HEAD(&card->codec_dev_list);
1881 INIT_LIST_HEAD(&card->platform_dev_list); 1882 INIT_LIST_HEAD(&card->platform_dev_list);
1883 INIT_LIST_HEAD(&card->widgets);
1884 INIT_LIST_HEAD(&card->paths);
1885 INIT_LIST_HEAD(&card->dapm_list);
1882 1886
1883 soc_init_card_debugfs(card); 1887 soc_init_card_debugfs(card);
1884 1888
@@ -3480,8 +3484,6 @@ int snd_soc_register_codec(struct device *dev,
3480 else 3484 else
3481 codec->compress_type = SND_SOC_FLAT_COMPRESSION; 3485 codec->compress_type = SND_SOC_FLAT_COMPRESSION;
3482 3486
3483 INIT_LIST_HEAD(&codec->dapm.widgets);
3484 INIT_LIST_HEAD(&codec->dapm.paths);
3485 codec->write = codec_drv->write; 3487 codec->write = codec_drv->write;
3486 codec->read = codec_drv->read; 3488 codec->read = codec_drv->read;
3487 codec->dapm.bias_level = SND_SOC_BIAS_OFF; 3489 codec->dapm.bias_level = SND_SOC_BIAS_OFF;
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 3d310af2890..499730ab563 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -56,6 +56,7 @@ static int dapm_up_seq[] = {
56 [snd_soc_dapm_aif_out] = 3, 56 [snd_soc_dapm_aif_out] = 3,
57 [snd_soc_dapm_mic] = 4, 57 [snd_soc_dapm_mic] = 4,
58 [snd_soc_dapm_mux] = 5, 58 [snd_soc_dapm_mux] = 5,
59 [snd_soc_dapm_virt_mux] = 5,
59 [snd_soc_dapm_value_mux] = 5, 60 [snd_soc_dapm_value_mux] = 5,
60 [snd_soc_dapm_dac] = 6, 61 [snd_soc_dapm_dac] = 6,
61 [snd_soc_dapm_mixer] = 7, 62 [snd_soc_dapm_mixer] = 7,
@@ -81,6 +82,7 @@ static int dapm_down_seq[] = {
81 [snd_soc_dapm_mic] = 7, 82 [snd_soc_dapm_mic] = 7,
82 [snd_soc_dapm_micbias] = 8, 83 [snd_soc_dapm_micbias] = 8,
83 [snd_soc_dapm_mux] = 9, 84 [snd_soc_dapm_mux] = 9,
85 [snd_soc_dapm_virt_mux] = 9,
84 [snd_soc_dapm_value_mux] = 9, 86 [snd_soc_dapm_value_mux] = 9,
85 [snd_soc_dapm_aif_in] = 10, 87 [snd_soc_dapm_aif_in] = 10,
86 [snd_soc_dapm_aif_out] = 10, 88 [snd_soc_dapm_aif_out] = 10,
@@ -108,7 +110,7 @@ static void pop_dbg(struct device *dev, u32 pop_time, const char *fmt, ...)
108 110
109 va_start(args, fmt); 111 va_start(args, fmt);
110 vsnprintf(buf, PAGE_SIZE, fmt, args); 112 vsnprintf(buf, PAGE_SIZE, fmt, args);
111 dev_info(dev, buf); 113 dev_info(dev, "%s", buf);
112 va_end(args); 114 va_end(args);
113 115
114 kfree(buf); 116 kfree(buf);
@@ -216,6 +218,20 @@ static void dapm_set_path_status(struct snd_soc_dapm_widget *w,
216 } 218 }
217 } 219 }
218 break; 220 break;
221 case snd_soc_dapm_virt_mux: {
222 struct soc_enum *e = (struct soc_enum *)w->kcontrols[i].private_value;
223
224 p->connect = 0;
225 /* since a virtual mux has no backing registers to
226 * decide which path to connect, it will try to match
227 * with the first enumeration. This is to ensure
228 * that the default mux choice (the first) will be
229 * correctly powered up during initialization.
230 */
231 if (!strcmp(p->name, e->texts[0]))
232 p->connect = 1;
233 }
234 break;
219 case snd_soc_dapm_value_mux: { 235 case snd_soc_dapm_value_mux: {
220 struct soc_enum *e = (struct soc_enum *) 236 struct soc_enum *e = (struct soc_enum *)
221 w->kcontrols[i].private_value; 237 w->kcontrols[i].private_value;
@@ -272,7 +288,7 @@ static int dapm_connect_mux(struct snd_soc_dapm_context *dapm,
272 288
273 for (i = 0; i < e->max; i++) { 289 for (i = 0; i < e->max; i++) {
274 if (!(strcmp(control_name, e->texts[i]))) { 290 if (!(strcmp(control_name, e->texts[i]))) {
275 list_add(&path->list, &dapm->paths); 291 list_add(&path->list, &dapm->card->paths);
276 list_add(&path->list_sink, &dest->sources); 292 list_add(&path->list_sink, &dest->sources);
277 list_add(&path->list_source, &src->sinks); 293 list_add(&path->list_source, &src->sinks);
278 path->name = (char*)e->texts[i]; 294 path->name = (char*)e->texts[i];
@@ -294,7 +310,7 @@ static int dapm_connect_mixer(struct snd_soc_dapm_context *dapm,
294 /* search for mixer kcontrol */ 310 /* search for mixer kcontrol */
295 for (i = 0; i < dest->num_kcontrols; i++) { 311 for (i = 0; i < dest->num_kcontrols; i++) {
296 if (!strcmp(control_name, dest->kcontrols[i].name)) { 312 if (!strcmp(control_name, dest->kcontrols[i].name)) {
297 list_add(&path->list, &dapm->paths); 313 list_add(&path->list, &dapm->card->paths);
298 list_add(&path->list_sink, &dest->sources); 314 list_add(&path->list_sink, &dest->sources);
299 list_add(&path->list_source, &src->sinks); 315 list_add(&path->list_source, &src->sinks);
300 path->name = dest->kcontrols[i].name; 316 path->name = dest->kcontrols[i].name;
@@ -453,7 +469,7 @@ static inline void dapm_clear_walk(struct snd_soc_dapm_context *dapm)
453{ 469{
454 struct snd_soc_dapm_path *p; 470 struct snd_soc_dapm_path *p;
455 471
456 list_for_each_entry(p, &dapm->paths, list) 472 list_for_each_entry(p, &dapm->card->paths, list)
457 p->walked = 0; 473 p->walked = 0;
458} 474}
459 475
@@ -847,19 +863,22 @@ static void dapm_seq_run(struct snd_soc_dapm_context *dapm,
847 LIST_HEAD(pending); 863 LIST_HEAD(pending);
848 int cur_sort = -1; 864 int cur_sort = -1;
849 int cur_reg = SND_SOC_NOPM; 865 int cur_reg = SND_SOC_NOPM;
866 struct snd_soc_dapm_context *cur_dapm = NULL;
850 int ret; 867 int ret;
851 868
852 list_for_each_entry_safe(w, n, list, power_list) { 869 list_for_each_entry_safe(w, n, list, power_list) {
853 ret = 0; 870 ret = 0;
854 871
855 /* Do we need to apply any queued changes? */ 872 /* Do we need to apply any queued changes? */
856 if (sort[w->id] != cur_sort || w->reg != cur_reg) { 873 if (sort[w->id] != cur_sort || w->reg != cur_reg ||
874 w->dapm != cur_dapm) {
857 if (!list_empty(&pending)) 875 if (!list_empty(&pending))
858 dapm_seq_run_coalesced(dapm, &pending); 876 dapm_seq_run_coalesced(cur_dapm, &pending);
859 877
860 INIT_LIST_HEAD(&pending); 878 INIT_LIST_HEAD(&pending);
861 cur_sort = -1; 879 cur_sort = -1;
862 cur_reg = SND_SOC_NOPM; 880 cur_reg = SND_SOC_NOPM;
881 cur_dapm = NULL;
863 } 882 }
864 883
865 switch (w->id) { 884 switch (w->id) {
@@ -903,6 +922,7 @@ static void dapm_seq_run(struct snd_soc_dapm_context *dapm,
903 /* Queue it up for application */ 922 /* Queue it up for application */
904 cur_sort = sort[w->id]; 923 cur_sort = sort[w->id];
905 cur_reg = w->reg; 924 cur_reg = w->reg;
925 cur_dapm = w->dapm;
906 list_move(&w->power_list, &pending); 926 list_move(&w->power_list, &pending);
907 break; 927 break;
908 } 928 }
@@ -916,6 +936,41 @@ static void dapm_seq_run(struct snd_soc_dapm_context *dapm,
916 dapm_seq_run_coalesced(dapm, &pending); 936 dapm_seq_run_coalesced(dapm, &pending);
917} 937}
918 938
939static void dapm_widget_update(struct snd_soc_dapm_context *dapm)
940{
941 struct snd_soc_dapm_update *update = dapm->update;
942 struct snd_soc_dapm_widget *w;
943 int ret;
944
945 if (!update)
946 return;
947
948 w = update->widget;
949
950 if (w->event &&
951 (w->event_flags & SND_SOC_DAPM_PRE_REG)) {
952 ret = w->event(w, update->kcontrol, SND_SOC_DAPM_PRE_REG);
953 if (ret != 0)
954 pr_err("%s DAPM pre-event failed: %d\n",
955 w->name, ret);
956 }
957
958 ret = snd_soc_update_bits(w->codec, update->reg, update->mask,
959 update->val);
960 if (ret < 0)
961 pr_err("%s DAPM update failed: %d\n", w->name, ret);
962
963 if (w->event &&
964 (w->event_flags & SND_SOC_DAPM_POST_REG)) {
965 ret = w->event(w, update->kcontrol, SND_SOC_DAPM_POST_REG);
966 if (ret != 0)
967 pr_err("%s DAPM post-event failed: %d\n",
968 w->name, ret);
969 }
970}
971
972
973
919/* 974/*
920 * Scan each dapm widget for complete audio path. 975 * Scan each dapm widget for complete audio path.
921 * A complete path is a route that has valid endpoints i.e.:- 976 * A complete path is a route that has valid endpoints i.e.:-
@@ -929,18 +984,22 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event)
929{ 984{
930 struct snd_soc_card *card = dapm->codec->card; 985 struct snd_soc_card *card = dapm->codec->card;
931 struct snd_soc_dapm_widget *w; 986 struct snd_soc_dapm_widget *w;
987 struct snd_soc_dapm_context *d;
932 LIST_HEAD(up_list); 988 LIST_HEAD(up_list);
933 LIST_HEAD(down_list); 989 LIST_HEAD(down_list);
934 int ret = 0; 990 int ret = 0;
935 int power; 991 int power;
936 int sys_power = 0;
937 992
938 trace_snd_soc_dapm_start(card); 993 trace_snd_soc_dapm_start(card);
939 994
995 list_for_each_entry(d, &card->dapm_list, list)
996 if (d->n_widgets)
997 d->dev_power = 0;
998
940 /* Check which widgets we need to power and store them in 999 /* Check which widgets we need to power and store them in
941 * lists indicating if they should be powered up or down. 1000 * lists indicating if they should be powered up or down.
942 */ 1001 */
943 list_for_each_entry(w, &dapm->widgets, list) { 1002 list_for_each_entry(w, &card->widgets, list) {
944 switch (w->id) { 1003 switch (w->id) {
945 case snd_soc_dapm_pre: 1004 case snd_soc_dapm_pre:
946 dapm_seq_insert(w, &down_list, dapm_down_seq); 1005 dapm_seq_insert(w, &down_list, dapm_down_seq);
@@ -958,7 +1017,7 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event)
958 else 1017 else
959 power = 1; 1018 power = 1;
960 if (power) 1019 if (power)
961 sys_power = 1; 1020 w->dapm->dev_power = 1;
962 1021
963 if (w->power == power) 1022 if (w->power == power)
964 continue; 1023 continue;
@@ -978,26 +1037,26 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event)
978 /* If there are no DAPM widgets then try to figure out power from the 1037 /* If there are no DAPM widgets then try to figure out power from the
979 * event type. 1038 * event type.
980 */ 1039 */
981 if (list_empty(&dapm->widgets)) { 1040 if (!dapm->n_widgets) {
982 switch (event) { 1041 switch (event) {
983 case SND_SOC_DAPM_STREAM_START: 1042 case SND_SOC_DAPM_STREAM_START:
984 case SND_SOC_DAPM_STREAM_RESUME: 1043 case SND_SOC_DAPM_STREAM_RESUME:
985 sys_power = 1; 1044 dapm->dev_power = 1;
986 break; 1045 break;
987 case SND_SOC_DAPM_STREAM_STOP: 1046 case SND_SOC_DAPM_STREAM_STOP:
988 sys_power = !!dapm->codec->active; 1047 dapm->dev_power = !!dapm->codec->active;
989 break; 1048 break;
990 case SND_SOC_DAPM_STREAM_SUSPEND: 1049 case SND_SOC_DAPM_STREAM_SUSPEND:
991 sys_power = 0; 1050 dapm->dev_power = 0;
992 break; 1051 break;
993 case SND_SOC_DAPM_STREAM_NOP: 1052 case SND_SOC_DAPM_STREAM_NOP:
994 switch (dapm->bias_level) { 1053 switch (dapm->bias_level) {
995 case SND_SOC_BIAS_STANDBY: 1054 case SND_SOC_BIAS_STANDBY:
996 case SND_SOC_BIAS_OFF: 1055 case SND_SOC_BIAS_OFF:
997 sys_power = 0; 1056 dapm->dev_power = 0;
998 break; 1057 break;
999 default: 1058 default:
1000 sys_power = 1; 1059 dapm->dev_power = 1;
1001 break; 1060 break;
1002 } 1061 }
1003 break; 1062 break;
@@ -1006,52 +1065,64 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event)
1006 } 1065 }
1007 } 1066 }
1008 1067
1009 if (sys_power && dapm->bias_level == SND_SOC_BIAS_OFF) { 1068 list_for_each_entry(d, &dapm->card->dapm_list, list) {
1010 ret = snd_soc_dapm_set_bias_level(card, dapm, 1069 if (d->dev_power && d->bias_level == SND_SOC_BIAS_OFF) {
1011 SND_SOC_BIAS_STANDBY); 1070 ret = snd_soc_dapm_set_bias_level(card, d,
1012 if (ret != 0) 1071 SND_SOC_BIAS_STANDBY);
1013 dev_err(dapm->dev, 1072 if (ret != 0)
1014 "Failed to turn on bias: %d\n", ret); 1073 dev_err(d->dev,
1015 } 1074 "Failed to turn on bias: %d\n", ret);
1075 }
1016 1076
1017 /* If we're changing to all on or all off then prepare */ 1077 /* If we're changing to all on or all off then prepare */
1018 if ((sys_power && dapm->bias_level == SND_SOC_BIAS_STANDBY) || 1078 if ((d->dev_power && d->bias_level == SND_SOC_BIAS_STANDBY) ||
1019 (!sys_power && dapm->bias_level == SND_SOC_BIAS_ON)) { 1079 (!d->dev_power && d->bias_level == SND_SOC_BIAS_ON)) {
1020 ret = snd_soc_dapm_set_bias_level(card, dapm, SND_SOC_BIAS_PREPARE); 1080 ret = snd_soc_dapm_set_bias_level(card, d,
1021 if (ret != 0) 1081 SND_SOC_BIAS_PREPARE);
1022 dev_err(dapm->dev, 1082 if (ret != 0)
1023 "Failed to prepare bias: %d\n", ret); 1083 dev_err(d->dev,
1084 "Failed to prepare bias: %d\n", ret);
1085 }
1024 } 1086 }
1025 1087
1026 /* Power down widgets first; try to avoid amplifying pops. */ 1088 /* Power down widgets first; try to avoid amplifying pops. */
1027 dapm_seq_run(dapm, &down_list, event, dapm_down_seq); 1089 dapm_seq_run(dapm, &down_list, event, dapm_down_seq);
1028 1090
1091 dapm_widget_update(dapm);
1092
1029 /* Now power up. */ 1093 /* Now power up. */
1030 dapm_seq_run(dapm, &up_list, event, dapm_up_seq); 1094 dapm_seq_run(dapm, &up_list, event, dapm_up_seq);
1031 1095
1032 /* If we just powered the last thing off drop to standby bias */ 1096 list_for_each_entry(d, &dapm->card->dapm_list, list) {
1033 if (dapm->bias_level == SND_SOC_BIAS_PREPARE && !sys_power) { 1097 /* If we just powered the last thing off drop to standby bias */
1034 ret = snd_soc_dapm_set_bias_level(card, dapm, SND_SOC_BIAS_STANDBY); 1098 if (d->bias_level == SND_SOC_BIAS_PREPARE && !d->dev_power) {
1035 if (ret != 0) 1099 ret = snd_soc_dapm_set_bias_level(card, d,
1036 dev_err(dapm->dev, 1100 SND_SOC_BIAS_STANDBY);
1037 "Failed to apply standby bias: %d\n", ret); 1101 if (ret != 0)
1038 } 1102 dev_err(d->dev,
1103 "Failed to apply standby bias: %d\n",
1104 ret);
1105 }
1039 1106
1040 /* If we're in standby and can support bias off then do that */ 1107 /* If we're in standby and can support bias off then do that */
1041 if (dapm->bias_level == SND_SOC_BIAS_STANDBY && 1108 if (d->bias_level == SND_SOC_BIAS_STANDBY &&
1042 dapm->idle_bias_off) { 1109 d->idle_bias_off) {
1043 ret = snd_soc_dapm_set_bias_level(card, dapm, SND_SOC_BIAS_OFF); 1110 ret = snd_soc_dapm_set_bias_level(card, d,
1044 if (ret != 0) 1111 SND_SOC_BIAS_OFF);
1045 dev_err(dapm->dev, 1112 if (ret != 0)
1046 "Failed to turn off bias: %d\n", ret); 1113 dev_err(d->dev,
1047 } 1114 "Failed to turn off bias: %d\n", ret);
1115 }
1048 1116
1049 /* If we just powered up then move to active bias */ 1117 /* If we just powered up then move to active bias */
1050 if (dapm->bias_level == SND_SOC_BIAS_PREPARE && sys_power) { 1118 if (d->bias_level == SND_SOC_BIAS_PREPARE && d->dev_power) {
1051 ret = snd_soc_dapm_set_bias_level(card, dapm, SND_SOC_BIAS_ON); 1119 ret = snd_soc_dapm_set_bias_level(card, d,
1052 if (ret != 0) 1120 SND_SOC_BIAS_ON);
1053 dev_err(dapm->dev, 1121 if (ret != 0)
1054 "Failed to apply active bias: %d\n", ret); 1122 dev_err(d->dev,
1123 "Failed to apply active bias: %d\n",
1124 ret);
1125 }
1055 } 1126 }
1056 1127
1057 pop_dbg(dapm->dev, card->pop_time, 1128 pop_dbg(dapm->dev, card->pop_time,
@@ -1145,8 +1216,8 @@ void snd_soc_dapm_debugfs_init(struct snd_soc_dapm_context *dapm)
1145 if (!dapm->debugfs_dapm) 1216 if (!dapm->debugfs_dapm)
1146 return; 1217 return;
1147 1218
1148 list_for_each_entry(w, &dapm->widgets, list) { 1219 list_for_each_entry(w, &dapm->card->widgets, list) {
1149 if (!w->name) 1220 if (!w->name || w->dapm != dapm)
1150 continue; 1221 continue;
1151 1222
1152 d = debugfs_create_file(w->name, 0444, 1223 d = debugfs_create_file(w->name, 0444,
@@ -1173,6 +1244,7 @@ static int dapm_mux_update_power(struct snd_soc_dapm_widget *widget,
1173 int found = 0; 1244 int found = 0;
1174 1245
1175 if (widget->id != snd_soc_dapm_mux && 1246 if (widget->id != snd_soc_dapm_mux &&
1247 widget->id != snd_soc_dapm_virt_mux &&
1176 widget->id != snd_soc_dapm_value_mux) 1248 widget->id != snd_soc_dapm_value_mux)
1177 return -ENODEV; 1249 return -ENODEV;
1178 1250
@@ -1180,7 +1252,7 @@ static int dapm_mux_update_power(struct snd_soc_dapm_widget *widget,
1180 return 0; 1252 return 0;
1181 1253
1182 /* find dapm widget path assoc with kcontrol */ 1254 /* find dapm widget path assoc with kcontrol */
1183 list_for_each_entry(path, &widget->dapm->paths, list) { 1255 list_for_each_entry(path, &widget->dapm->card->paths, list) {
1184 if (path->kcontrol != kcontrol) 1256 if (path->kcontrol != kcontrol)
1185 continue; 1257 continue;
1186 1258
@@ -1214,7 +1286,7 @@ static int dapm_mixer_update_power(struct snd_soc_dapm_widget *widget,
1214 return -ENODEV; 1286 return -ENODEV;
1215 1287
1216 /* find dapm widget path assoc with kcontrol */ 1288 /* find dapm widget path assoc with kcontrol */
1217 list_for_each_entry(path, &widget->dapm->paths, list) { 1289 list_for_each_entry(path, &widget->dapm->card->paths, list) {
1218 if (path->kcontrol != kcontrol) 1290 if (path->kcontrol != kcontrol)
1219 continue; 1291 continue;
1220 1292
@@ -1241,7 +1313,9 @@ static ssize_t dapm_widget_show(struct device *dev,
1241 int count = 0; 1313 int count = 0;
1242 char *state = "not set"; 1314 char *state = "not set";
1243 1315
1244 list_for_each_entry(w, &codec->dapm.widgets, list) { 1316 list_for_each_entry(w, &codec->card->widgets, list) {
1317 if (w->dapm != &codec->dapm)
1318 continue;
1245 1319
1246 /* only display widgets that burnm power */ 1320 /* only display widgets that burnm power */
1247 switch (w->id) { 1321 switch (w->id) {
@@ -1303,17 +1377,32 @@ static void dapm_free_widgets(struct snd_soc_dapm_context *dapm)
1303 struct snd_soc_dapm_widget *w, *next_w; 1377 struct snd_soc_dapm_widget *w, *next_w;
1304 struct snd_soc_dapm_path *p, *next_p; 1378 struct snd_soc_dapm_path *p, *next_p;
1305 1379
1306 list_for_each_entry_safe(w, next_w, &dapm->widgets, list) { 1380 list_for_each_entry_safe(w, next_w, &dapm->card->widgets, list) {
1381 if (w->dapm != dapm)
1382 continue;
1307 list_del(&w->list); 1383 list_del(&w->list);
1384 /*
1385 * remove source and sink paths associated to this widget.
1386 * While removing the path, remove reference to it from both
1387 * source and sink widgets so that path is removed only once.
1388 */
1389 list_for_each_entry_safe(p, next_p, &w->sources, list_sink) {
1390 list_del(&p->list_sink);
1391 list_del(&p->list_source);
1392 list_del(&p->list);
1393 kfree(p->long_name);
1394 kfree(p);
1395 }
1396 list_for_each_entry_safe(p, next_p, &w->sinks, list_source) {
1397 list_del(&p->list_sink);
1398 list_del(&p->list_source);
1399 list_del(&p->list);
1400 kfree(p->long_name);
1401 kfree(p);
1402 }
1308 kfree(w->name); 1403 kfree(w->name);
1309 kfree(w); 1404 kfree(w);
1310 } 1405 }
1311
1312 list_for_each_entry_safe(p, next_p, &dapm->paths, list) {
1313 list_del(&p->list);
1314 kfree(p->long_name);
1315 kfree(p);
1316 }
1317} 1406}
1318 1407
1319static int snd_soc_dapm_set_pin(struct snd_soc_dapm_context *dapm, 1408static int snd_soc_dapm_set_pin(struct snd_soc_dapm_context *dapm,
@@ -1321,7 +1410,9 @@ static int snd_soc_dapm_set_pin(struct snd_soc_dapm_context *dapm,
1321{ 1410{
1322 struct snd_soc_dapm_widget *w; 1411 struct snd_soc_dapm_widget *w;
1323 1412
1324 list_for_each_entry(w, &dapm->widgets, list) { 1413 list_for_each_entry(w, &dapm->card->widgets, list) {
1414 if (w->dapm != dapm)
1415 continue;
1325 if (!strcmp(w->name, pin)) { 1416 if (!strcmp(w->name, pin)) {
1326 dev_dbg(w->dapm->dev, "dapm: pin %s = %d\n", 1417 dev_dbg(w->dapm->dev, "dapm: pin %s = %d\n",
1327 pin, status); 1418 pin, status);
@@ -1357,6 +1448,7 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm,
1357{ 1448{
1358 struct snd_soc_dapm_path *path; 1449 struct snd_soc_dapm_path *path;
1359 struct snd_soc_dapm_widget *wsource = NULL, *wsink = NULL, *w; 1450 struct snd_soc_dapm_widget *wsource = NULL, *wsink = NULL, *w;
1451 struct snd_soc_dapm_widget *wtsource = NULL, *wtsink = NULL;
1360 const char *sink; 1452 const char *sink;
1361 const char *control = route->control; 1453 const char *control = route->control;
1362 const char *source; 1454 const char *source;
@@ -1376,17 +1468,28 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm,
1376 source = route->source; 1468 source = route->source;
1377 } 1469 }
1378 1470
1379 /* find src and dest widgets */ 1471 /*
1380 list_for_each_entry(w, &dapm->widgets, list) { 1472 * find src and dest widgets over all widgets but favor a widget from
1381 1473 * current DAPM context
1474 */
1475 list_for_each_entry(w, &dapm->card->widgets, list) {
1382 if (!wsink && !(strcmp(w->name, sink))) { 1476 if (!wsink && !(strcmp(w->name, sink))) {
1383 wsink = w; 1477 wtsink = w;
1478 if (w->dapm == dapm)
1479 wsink = w;
1384 continue; 1480 continue;
1385 } 1481 }
1386 if (!wsource && !(strcmp(w->name, source))) { 1482 if (!wsource && !(strcmp(w->name, source))) {
1387 wsource = w; 1483 wtsource = w;
1484 if (w->dapm == dapm)
1485 wsource = w;
1388 } 1486 }
1389 } 1487 }
1488 /* use widget from another DAPM context if not found from this */
1489 if (!wsink)
1490 wsink = wtsink;
1491 if (!wsource)
1492 wsource = wtsource;
1390 1493
1391 if (wsource == NULL || wsink == NULL) 1494 if (wsource == NULL || wsink == NULL)
1392 return -ENODEV; 1495 return -ENODEV;
@@ -1420,7 +1523,7 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm,
1420 1523
1421 /* connect static paths */ 1524 /* connect static paths */
1422 if (control == NULL) { 1525 if (control == NULL) {
1423 list_add(&path->list, &dapm->paths); 1526 list_add(&path->list, &dapm->card->paths);
1424 list_add(&path->list_sink, &wsink->sources); 1527 list_add(&path->list_sink, &wsink->sources);
1425 list_add(&path->list_source, &wsource->sinks); 1528 list_add(&path->list_source, &wsource->sinks);
1426 path->connect = 1; 1529 path->connect = 1;
@@ -1442,12 +1545,13 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm,
1442 case snd_soc_dapm_supply: 1545 case snd_soc_dapm_supply:
1443 case snd_soc_dapm_aif_in: 1546 case snd_soc_dapm_aif_in:
1444 case snd_soc_dapm_aif_out: 1547 case snd_soc_dapm_aif_out:
1445 list_add(&path->list, &dapm->paths); 1548 list_add(&path->list, &dapm->card->paths);
1446 list_add(&path->list_sink, &wsink->sources); 1549 list_add(&path->list_sink, &wsink->sources);
1447 list_add(&path->list_source, &wsource->sinks); 1550 list_add(&path->list_source, &wsource->sinks);
1448 path->connect = 1; 1551 path->connect = 1;
1449 return 0; 1552 return 0;
1450 case snd_soc_dapm_mux: 1553 case snd_soc_dapm_mux:
1554 case snd_soc_dapm_virt_mux:
1451 case snd_soc_dapm_value_mux: 1555 case snd_soc_dapm_value_mux:
1452 ret = dapm_connect_mux(dapm, wsource, wsink, path, control, 1556 ret = dapm_connect_mux(dapm, wsource, wsink, path, control,
1453 &wsink->kcontrols[0]); 1557 &wsink->kcontrols[0]);
@@ -1465,7 +1569,7 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm,
1465 case snd_soc_dapm_mic: 1569 case snd_soc_dapm_mic:
1466 case snd_soc_dapm_line: 1570 case snd_soc_dapm_line:
1467 case snd_soc_dapm_spk: 1571 case snd_soc_dapm_spk:
1468 list_add(&path->list, &dapm->paths); 1572 list_add(&path->list, &dapm->card->paths);
1469 list_add(&path->list_sink, &wsink->sources); 1573 list_add(&path->list_sink, &wsink->sources);
1470 list_add(&path->list_source, &wsource->sinks); 1574 list_add(&path->list_source, &wsource->sinks);
1471 path->connect = 0; 1575 path->connect = 0;
@@ -1524,7 +1628,7 @@ int snd_soc_dapm_new_widgets(struct snd_soc_dapm_context *dapm)
1524{ 1628{
1525 struct snd_soc_dapm_widget *w; 1629 struct snd_soc_dapm_widget *w;
1526 1630
1527 list_for_each_entry(w, &dapm->widgets, list) 1631 list_for_each_entry(w, &dapm->card->widgets, list)
1528 { 1632 {
1529 if (w->new) 1633 if (w->new)
1530 continue; 1634 continue;
@@ -1537,6 +1641,7 @@ int snd_soc_dapm_new_widgets(struct snd_soc_dapm_context *dapm)
1537 dapm_new_mixer(dapm, w); 1641 dapm_new_mixer(dapm, w);
1538 break; 1642 break;
1539 case snd_soc_dapm_mux: 1643 case snd_soc_dapm_mux:
1644 case snd_soc_dapm_virt_mux:
1540 case snd_soc_dapm_value_mux: 1645 case snd_soc_dapm_value_mux:
1541 w->power_check = dapm_generic_check_power; 1646 w->power_check = dapm_generic_check_power;
1542 dapm_new_mux(dapm, w); 1647 dapm_new_mux(dapm, w);
@@ -1634,13 +1739,12 @@ int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol,
1634 (struct soc_mixer_control *)kcontrol->private_value; 1739 (struct soc_mixer_control *)kcontrol->private_value;
1635 unsigned int reg = mc->reg; 1740 unsigned int reg = mc->reg;
1636 unsigned int shift = mc->shift; 1741 unsigned int shift = mc->shift;
1637 unsigned int rshift = mc->rshift;
1638 int max = mc->max; 1742 int max = mc->max;
1639 unsigned int mask = (1 << fls(max)) - 1; 1743 unsigned int mask = (1 << fls(max)) - 1;
1640 unsigned int invert = mc->invert; 1744 unsigned int invert = mc->invert;
1641 unsigned int val, val2, val_mask; 1745 unsigned int val, val_mask;
1642 int connect; 1746 int connect, change;
1643 int ret; 1747 struct snd_soc_dapm_update update;
1644 1748
1645 val = (ucontrol->value.integer.value[0] & mask); 1749 val = (ucontrol->value.integer.value[0] & mask);
1646 1750
@@ -1648,18 +1752,12 @@ int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol,
1648 val = max - val; 1752 val = max - val;
1649 val_mask = mask << shift; 1753 val_mask = mask << shift;
1650 val = val << shift; 1754 val = val << shift;
1651 if (shift != rshift) {
1652 val2 = (ucontrol->value.integer.value[1] & mask);
1653 if (invert)
1654 val2 = max - val2;
1655 val_mask |= mask << rshift;
1656 val |= val2 << rshift;
1657 }
1658 1755
1659 mutex_lock(&widget->codec->mutex); 1756 mutex_lock(&widget->codec->mutex);
1660 widget->value = val; 1757 widget->value = val;
1661 1758
1662 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { 1759 change = snd_soc_test_bits(widget->codec, reg, val_mask, val);
1760 if (change) {
1663 if (val) 1761 if (val)
1664 /* new connection */ 1762 /* new connection */
1665 connect = invert ? 0:1; 1763 connect = invert ? 0:1;
@@ -1667,28 +1765,20 @@ int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol,
1667 /* old connection must be powered down */ 1765 /* old connection must be powered down */
1668 connect = invert ? 1:0; 1766 connect = invert ? 1:0;
1669 1767
1768 update.kcontrol = kcontrol;
1769 update.widget = widget;
1770 update.reg = reg;
1771 update.mask = mask;
1772 update.val = val;
1773 widget->dapm->update = &update;
1774
1670 dapm_mixer_update_power(widget, kcontrol, connect); 1775 dapm_mixer_update_power(widget, kcontrol, connect);
1776
1777 widget->dapm->update = NULL;
1671 } 1778 }
1672 1779
1673 if (widget->event) {
1674 if (widget->event_flags & SND_SOC_DAPM_PRE_REG) {
1675 ret = widget->event(widget, kcontrol,
1676 SND_SOC_DAPM_PRE_REG);
1677 if (ret < 0) {
1678 ret = 1;
1679 goto out;
1680 }
1681 }
1682 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
1683 if (widget->event_flags & SND_SOC_DAPM_POST_REG)
1684 ret = widget->event(widget, kcontrol,
1685 SND_SOC_DAPM_POST_REG);
1686 } else
1687 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
1688
1689out:
1690 mutex_unlock(&widget->codec->mutex); 1780 mutex_unlock(&widget->codec->mutex);
1691 return ret; 1781 return 0;
1692} 1782}
1693EXPORT_SYMBOL_GPL(snd_soc_dapm_put_volsw); 1783EXPORT_SYMBOL_GPL(snd_soc_dapm_put_volsw);
1694 1784
@@ -1736,7 +1826,7 @@ int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol,
1736 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1826 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1737 unsigned int val, mux, change; 1827 unsigned int val, mux, change;
1738 unsigned int mask, bitmask; 1828 unsigned int mask, bitmask;
1739 int ret = 0; 1829 struct snd_soc_dapm_update update;
1740 1830
1741 for (bitmask = 1; bitmask < e->max; bitmask <<= 1) 1831 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
1742 ; 1832 ;
@@ -1755,24 +1845,20 @@ int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol,
1755 mutex_lock(&widget->codec->mutex); 1845 mutex_lock(&widget->codec->mutex);
1756 widget->value = val; 1846 widget->value = val;
1757 change = snd_soc_test_bits(widget->codec, e->reg, mask, val); 1847 change = snd_soc_test_bits(widget->codec, e->reg, mask, val);
1758 dapm_mux_update_power(widget, kcontrol, change, mux, e);
1759 1848
1760 if (widget->event_flags & SND_SOC_DAPM_PRE_REG) { 1849 update.kcontrol = kcontrol;
1761 ret = widget->event(widget, 1850 update.widget = widget;
1762 kcontrol, SND_SOC_DAPM_PRE_REG); 1851 update.reg = e->reg;
1763 if (ret < 0) 1852 update.mask = mask;
1764 goto out; 1853 update.val = val;
1765 } 1854 widget->dapm->update = &update;
1766 1855
1767 ret = snd_soc_update_bits(widget->codec, e->reg, mask, val); 1856 dapm_mux_update_power(widget, kcontrol, change, mux, e);
1768 1857
1769 if (widget->event_flags & SND_SOC_DAPM_POST_REG) 1858 widget->dapm->update = NULL;
1770 ret = widget->event(widget,
1771 kcontrol, SND_SOC_DAPM_POST_REG);
1772 1859
1773out:
1774 mutex_unlock(&widget->codec->mutex); 1860 mutex_unlock(&widget->codec->mutex);
1775 return ret; 1861 return change;
1776} 1862}
1777EXPORT_SYMBOL_GPL(snd_soc_dapm_put_enum_double); 1863EXPORT_SYMBOL_GPL(snd_soc_dapm_put_enum_double);
1778 1864
@@ -1884,7 +1970,7 @@ int snd_soc_dapm_put_value_enum_double(struct snd_kcontrol *kcontrol,
1884 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1970 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1885 unsigned int val, mux, change; 1971 unsigned int val, mux, change;
1886 unsigned int mask; 1972 unsigned int mask;
1887 int ret = 0; 1973 struct snd_soc_dapm_update update;
1888 1974
1889 if (ucontrol->value.enumerated.item[0] > e->max - 1) 1975 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1890 return -EINVAL; 1976 return -EINVAL;
@@ -1901,24 +1987,20 @@ int snd_soc_dapm_put_value_enum_double(struct snd_kcontrol *kcontrol,
1901 mutex_lock(&widget->codec->mutex); 1987 mutex_lock(&widget->codec->mutex);
1902 widget->value = val; 1988 widget->value = val;
1903 change = snd_soc_test_bits(widget->codec, e->reg, mask, val); 1989 change = snd_soc_test_bits(widget->codec, e->reg, mask, val);
1904 dapm_mux_update_power(widget, kcontrol, change, mux, e);
1905 1990
1906 if (widget->event_flags & SND_SOC_DAPM_PRE_REG) { 1991 update.kcontrol = kcontrol;
1907 ret = widget->event(widget, 1992 update.widget = widget;
1908 kcontrol, SND_SOC_DAPM_PRE_REG); 1993 update.reg = e->reg;
1909 if (ret < 0) 1994 update.mask = mask;
1910 goto out; 1995 update.val = val;
1911 } 1996 widget->dapm->update = &update;
1912 1997
1913 ret = snd_soc_update_bits(widget->codec, e->reg, mask, val); 1998 dapm_mux_update_power(widget, kcontrol, change, mux, e);
1914 1999
1915 if (widget->event_flags & SND_SOC_DAPM_POST_REG) 2000 widget->dapm->update = NULL;
1916 ret = widget->event(widget,
1917 kcontrol, SND_SOC_DAPM_POST_REG);
1918 2001
1919out:
1920 mutex_unlock(&widget->codec->mutex); 2002 mutex_unlock(&widget->codec->mutex);
1921 return ret; 2003 return change;
1922} 2004}
1923EXPORT_SYMBOL_GPL(snd_soc_dapm_put_value_enum_double); 2005EXPORT_SYMBOL_GPL(snd_soc_dapm_put_value_enum_double);
1924 2006
@@ -2024,12 +2106,13 @@ int snd_soc_dapm_new_control(struct snd_soc_dapm_context *dapm,
2024 else 2106 else
2025 snprintf(w->name, name_len, "%s", widget->name); 2107 snprintf(w->name, name_len, "%s", widget->name);
2026 2108
2109 dapm->n_widgets++;
2027 w->dapm = dapm; 2110 w->dapm = dapm;
2028 w->codec = dapm->codec; 2111 w->codec = dapm->codec;
2029 INIT_LIST_HEAD(&w->sources); 2112 INIT_LIST_HEAD(&w->sources);
2030 INIT_LIST_HEAD(&w->sinks); 2113 INIT_LIST_HEAD(&w->sinks);
2031 INIT_LIST_HEAD(&w->list); 2114 INIT_LIST_HEAD(&w->list);
2032 list_add(&w->list, &dapm->widgets); 2115 list_add(&w->list, &dapm->card->widgets);
2033 2116
2034 /* machine layer set ups unconnected pins and insertions */ 2117 /* machine layer set ups unconnected pins and insertions */
2035 w->connected = 1; 2118 w->connected = 1;
@@ -2072,9 +2155,9 @@ static void soc_dapm_stream_event(struct snd_soc_dapm_context *dapm,
2072{ 2155{
2073 struct snd_soc_dapm_widget *w; 2156 struct snd_soc_dapm_widget *w;
2074 2157
2075 list_for_each_entry(w, &dapm->widgets, list) 2158 list_for_each_entry(w, &dapm->card->widgets, list)
2076 { 2159 {
2077 if (!w->sname) 2160 if (!w->sname || w->dapm != dapm)
2078 continue; 2161 continue;
2079 dev_dbg(w->dapm->dev, "widget %s\n %s stream %s event %d\n", 2162 dev_dbg(w->dapm->dev, "widget %s\n %s stream %s event %d\n",
2080 w->name, w->sname, stream, event); 2163 w->name, w->sname, stream, event);
@@ -2157,7 +2240,9 @@ int snd_soc_dapm_force_enable_pin(struct snd_soc_dapm_context *dapm,
2157{ 2240{
2158 struct snd_soc_dapm_widget *w; 2241 struct snd_soc_dapm_widget *w;
2159 2242
2160 list_for_each_entry(w, &dapm->widgets, list) { 2243 list_for_each_entry(w, &dapm->card->widgets, list) {
2244 if (w->dapm != dapm)
2245 continue;
2161 if (!strcmp(w->name, pin)) { 2246 if (!strcmp(w->name, pin)) {
2162 dev_dbg(w->dapm->dev, 2247 dev_dbg(w->dapm->dev,
2163 "dapm: force enable pin %s\n", pin); 2248 "dapm: force enable pin %s\n", pin);
@@ -2222,7 +2307,9 @@ int snd_soc_dapm_get_pin_status(struct snd_soc_dapm_context *dapm,
2222{ 2307{
2223 struct snd_soc_dapm_widget *w; 2308 struct snd_soc_dapm_widget *w;
2224 2309
2225 list_for_each_entry(w, &dapm->widgets, list) { 2310 list_for_each_entry(w, &dapm->card->widgets, list) {
2311 if (w->dapm != dapm)
2312 continue;
2226 if (!strcmp(w->name, pin)) 2313 if (!strcmp(w->name, pin))
2227 return w->connected; 2314 return w->connected;
2228 } 2315 }
@@ -2247,7 +2334,9 @@ int snd_soc_dapm_ignore_suspend(struct snd_soc_dapm_context *dapm,
2247{ 2334{
2248 struct snd_soc_dapm_widget *w; 2335 struct snd_soc_dapm_widget *w;
2249 2336
2250 list_for_each_entry(w, &dapm->widgets, list) { 2337 list_for_each_entry(w, &dapm->card->widgets, list) {
2338 if (w->dapm != dapm)
2339 continue;
2251 if (!strcmp(w->name, pin)) { 2340 if (!strcmp(w->name, pin)) {
2252 w->ignore_suspend = 1; 2341 w->ignore_suspend = 1;
2253 return 0; 2342 return 0;
@@ -2269,6 +2358,7 @@ void snd_soc_dapm_free(struct snd_soc_dapm_context *dapm)
2269{ 2358{
2270 snd_soc_dapm_sys_remove(dapm->dev); 2359 snd_soc_dapm_sys_remove(dapm->dev);
2271 dapm_free_widgets(dapm); 2360 dapm_free_widgets(dapm);
2361 list_del(&dapm->list);
2272} 2362}
2273EXPORT_SYMBOL_GPL(snd_soc_dapm_free); 2363EXPORT_SYMBOL_GPL(snd_soc_dapm_free);
2274 2364
@@ -2278,7 +2368,9 @@ static void soc_dapm_shutdown_codec(struct snd_soc_dapm_context *dapm)
2278 LIST_HEAD(down_list); 2368 LIST_HEAD(down_list);
2279 int powerdown = 0; 2369 int powerdown = 0;
2280 2370
2281 list_for_each_entry(w, &dapm->widgets, list) { 2371 list_for_each_entry(w, &dapm->card->widgets, list) {
2372 if (w->dapm != dapm)
2373 continue;
2282 if (w->power) { 2374 if (w->power) {
2283 dapm_seq_insert(w, &down_list, dapm_down_seq); 2375 dapm_seq_insert(w, &down_list, dapm_down_seq);
2284 w->power = 0; 2376 w->power = 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 02:45:19 -0500