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-rw-r--r--drivers/isdn/hardware/mISDN/Kconfig13
-rw-r--r--drivers/isdn/hardware/mISDN/Makefile6
-rw-r--r--drivers/isdn/hardware/mISDN/hfc_pci.h228
-rw-r--r--drivers/isdn/hardware/mISDN/hfcpci.c2256
4 files changed, 2503 insertions, 0 deletions
diff --git a/drivers/isdn/hardware/mISDN/Kconfig b/drivers/isdn/hardware/mISDN/Kconfig
new file mode 100644
index 00000000000..f62dc8752be
--- /dev/null
+++ b/drivers/isdn/hardware/mISDN/Kconfig
@@ -0,0 +1,13 @@
1#
2# Hardware for mISDN
3#
4comment "mISDN hardware drivers"
5
6config MISDN_HFCPCI
7 tristate "Support for HFC PCI cards"
8 depends on MISDN
9 depends on PCI
10 help
11 Enable support for cards with Cologne Chip AG's
12 HFC PCI chip.
13
diff --git a/drivers/isdn/hardware/mISDN/Makefile b/drivers/isdn/hardware/mISDN/Makefile
new file mode 100644
index 00000000000..6f20a40b9d5
--- /dev/null
+++ b/drivers/isdn/hardware/mISDN/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for the modular ISDN hardware drivers
3#
4#
5
6obj-$(CONFIG_MISDN_HFCPCI) += hfcpci.o
diff --git a/drivers/isdn/hardware/mISDN/hfc_pci.h b/drivers/isdn/hardware/mISDN/hfc_pci.h
new file mode 100644
index 00000000000..fd2c9be6d84
--- /dev/null
+++ b/drivers/isdn/hardware/mISDN/hfc_pci.h
@@ -0,0 +1,228 @@
1/*
2 * specific defines for CCD's HFC 2BDS0 PCI chips
3 *
4 * Author Werner Cornelius (werner@isdn4linux.de)
5 *
6 * Copyright 1999 by Werner Cornelius (werner@isdn4linux.de)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24/*
25 * thresholds for transparent B-channel mode
26 * change mask and threshold simultaneously
27 */
28#define HFCPCI_BTRANS_THRESHOLD 128
29#define HFCPCI_BTRANS_MAX 256
30#define HFCPCI_BTRANS_THRESMASK 0x00
31
32/* defines for PCI config */
33#define PCI_ENA_MEMIO 0x02
34#define PCI_ENA_MASTER 0x04
35
36/* GCI/IOM bus monitor registers */
37#define HCFPCI_C_I 0x08
38#define HFCPCI_TRxR 0x0C
39#define HFCPCI_MON1_D 0x28
40#define HFCPCI_MON2_D 0x2C
41
42/* GCI/IOM bus timeslot registers */
43#define HFCPCI_B1_SSL 0x80
44#define HFCPCI_B2_SSL 0x84
45#define HFCPCI_AUX1_SSL 0x88
46#define HFCPCI_AUX2_SSL 0x8C
47#define HFCPCI_B1_RSL 0x90
48#define HFCPCI_B2_RSL 0x94
49#define HFCPCI_AUX1_RSL 0x98
50#define HFCPCI_AUX2_RSL 0x9C
51
52/* GCI/IOM bus data registers */
53#define HFCPCI_B1_D 0xA0
54#define HFCPCI_B2_D 0xA4
55#define HFCPCI_AUX1_D 0xA8
56#define HFCPCI_AUX2_D 0xAC
57
58/* GCI/IOM bus configuration registers */
59#define HFCPCI_MST_EMOD 0xB4
60#define HFCPCI_MST_MODE 0xB8
61#define HFCPCI_CONNECT 0xBC
62
63
64/* Interrupt and status registers */
65#define HFCPCI_FIFO_EN 0x44
66#define HFCPCI_TRM 0x48
67#define HFCPCI_B_MODE 0x4C
68#define HFCPCI_CHIP_ID 0x58
69#define HFCPCI_CIRM 0x60
70#define HFCPCI_CTMT 0x64
71#define HFCPCI_INT_M1 0x68
72#define HFCPCI_INT_M2 0x6C
73#define HFCPCI_INT_S1 0x78
74#define HFCPCI_INT_S2 0x7C
75#define HFCPCI_STATUS 0x70
76
77/* S/T section registers */
78#define HFCPCI_STATES 0xC0
79#define HFCPCI_SCTRL 0xC4
80#define HFCPCI_SCTRL_E 0xC8
81#define HFCPCI_SCTRL_R 0xCC
82#define HFCPCI_SQ 0xD0
83#define HFCPCI_CLKDEL 0xDC
84#define HFCPCI_B1_REC 0xF0
85#define HFCPCI_B1_SEND 0xF0
86#define HFCPCI_B2_REC 0xF4
87#define HFCPCI_B2_SEND 0xF4
88#define HFCPCI_D_REC 0xF8
89#define HFCPCI_D_SEND 0xF8
90#define HFCPCI_E_REC 0xFC
91
92
93/* bits in status register (READ) */
94#define HFCPCI_PCI_PROC 0x02
95#define HFCPCI_NBUSY 0x04
96#define HFCPCI_TIMER_ELAP 0x10
97#define HFCPCI_STATINT 0x20
98#define HFCPCI_FRAMEINT 0x40
99#define HFCPCI_ANYINT 0x80
100
101/* bits in CTMT (Write) */
102#define HFCPCI_CLTIMER 0x80
103#define HFCPCI_TIM3_125 0x04
104#define HFCPCI_TIM25 0x10
105#define HFCPCI_TIM50 0x14
106#define HFCPCI_TIM400 0x18
107#define HFCPCI_TIM800 0x1C
108#define HFCPCI_AUTO_TIMER 0x20
109#define HFCPCI_TRANSB2 0x02
110#define HFCPCI_TRANSB1 0x01
111
112/* bits in CIRM (Write) */
113#define HFCPCI_AUX_MSK 0x07
114#define HFCPCI_RESET 0x08
115#define HFCPCI_B1_REV 0x40
116#define HFCPCI_B2_REV 0x80
117
118/* bits in INT_M1 and INT_S1 */
119#define HFCPCI_INTS_B1TRANS 0x01
120#define HFCPCI_INTS_B2TRANS 0x02
121#define HFCPCI_INTS_DTRANS 0x04
122#define HFCPCI_INTS_B1REC 0x08
123#define HFCPCI_INTS_B2REC 0x10
124#define HFCPCI_INTS_DREC 0x20
125#define HFCPCI_INTS_L1STATE 0x40
126#define HFCPCI_INTS_TIMER 0x80
127
128/* bits in INT_M2 */
129#define HFCPCI_PROC_TRANS 0x01
130#define HFCPCI_GCI_I_CHG 0x02
131#define HFCPCI_GCI_MON_REC 0x04
132#define HFCPCI_IRQ_ENABLE 0x08
133#define HFCPCI_PMESEL 0x80
134
135/* bits in STATES */
136#define HFCPCI_STATE_MSK 0x0F
137#define HFCPCI_LOAD_STATE 0x10
138#define HFCPCI_ACTIVATE 0x20
139#define HFCPCI_DO_ACTION 0x40
140#define HFCPCI_NT_G2_G3 0x80
141
142/* bits in HFCD_MST_MODE */
143#define HFCPCI_MASTER 0x01
144#define HFCPCI_SLAVE 0x00
145#define HFCPCI_F0IO_POSITIV 0x02
146#define HFCPCI_F0_NEGATIV 0x04
147#define HFCPCI_F0_2C4 0x08
148/* remaining bits are for codecs control */
149
150/* bits in HFCD_SCTRL */
151#define SCTRL_B1_ENA 0x01
152#define SCTRL_B2_ENA 0x02
153#define SCTRL_MODE_TE 0x00
154#define SCTRL_MODE_NT 0x04
155#define SCTRL_LOW_PRIO 0x08
156#define SCTRL_SQ_ENA 0x10
157#define SCTRL_TEST 0x20
158#define SCTRL_NONE_CAP 0x40
159#define SCTRL_PWR_DOWN 0x80
160
161/* bits in SCTRL_E */
162#define HFCPCI_AUTO_AWAKE 0x01
163#define HFCPCI_DBIT_1 0x04
164#define HFCPCI_IGNORE_COL 0x08
165#define HFCPCI_CHG_B1_B2 0x80
166
167/* bits in FIFO_EN register */
168#define HFCPCI_FIFOEN_B1 0x03
169#define HFCPCI_FIFOEN_B2 0x0C
170#define HFCPCI_FIFOEN_DTX 0x10
171#define HFCPCI_FIFOEN_B1TX 0x01
172#define HFCPCI_FIFOEN_B1RX 0x02
173#define HFCPCI_FIFOEN_B2TX 0x04
174#define HFCPCI_FIFOEN_B2RX 0x08
175
176
177/* definitions of fifo memory area */
178#define MAX_D_FRAMES 15
179#define MAX_B_FRAMES 31
180#define B_SUB_VAL 0x200
181#define B_FIFO_SIZE (0x2000 - B_SUB_VAL)
182#define D_FIFO_SIZE 512
183#define D_FREG_MASK 0xF
184
185struct zt {
186 unsigned short z1; /* Z1 pointer 16 Bit */
187 unsigned short z2; /* Z2 pointer 16 Bit */
188};
189
190struct dfifo {
191 u_char data[D_FIFO_SIZE]; /* FIFO data space */
192 u_char fill1[0x20A0-D_FIFO_SIZE]; /* reserved, do not use */
193 u_char f1, f2; /* f pointers */
194 u_char fill2[0x20C0-0x20A2]; /* reserved, do not use */
195 /* mask index with D_FREG_MASK for access */
196 struct zt za[MAX_D_FRAMES+1];
197 u_char fill3[0x4000-0x2100]; /* align 16K */
198};
199
200struct bzfifo {
201 struct zt za[MAX_B_FRAMES+1]; /* only range 0x0..0x1F allowed */
202 u_char f1, f2; /* f pointers */
203 u_char fill[0x2100-0x2082]; /* alignment */
204};
205
206
207union fifo_area {
208 struct {
209 struct dfifo d_tx; /* D-send channel */
210 struct dfifo d_rx; /* D-receive channel */
211 } d_chan;
212 struct {
213 u_char fill1[0x200];
214 u_char txdat_b1[B_FIFO_SIZE];
215 struct bzfifo txbz_b1;
216 struct bzfifo txbz_b2;
217 u_char txdat_b2[B_FIFO_SIZE];
218 u_char fill2[D_FIFO_SIZE];
219 u_char rxdat_b1[B_FIFO_SIZE];
220 struct bzfifo rxbz_b1;
221 struct bzfifo rxbz_b2;
222 u_char rxdat_b2[B_FIFO_SIZE];
223 } b_chans;
224 u_char fill[32768];
225};
226
227#define Write_hfc(a, b, c) (writeb(c, (a->hw.pci_io)+b))
228#define Read_hfc(a, b) (readb((a->hw.pci_io)+b))
diff --git a/drivers/isdn/hardware/mISDN/hfcpci.c b/drivers/isdn/hardware/mISDN/hfcpci.c
new file mode 100644
index 00000000000..917968530e1
--- /dev/null
+++ b/drivers/isdn/hardware/mISDN/hfcpci.c
@@ -0,0 +1,2256 @@
1/*
2 *
3 * hfcpci.c low level driver for CCD's hfc-pci based cards
4 *
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 * based on existing driver for CCD hfc ISA cards
7 * type approval valid for HFC-S PCI A based card
8 *
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil <kkeil@novell.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/mISDNhw.h>
32
33#include "hfc_pci.h"
34
35static const char *hfcpci_revision = "2.0";
36
37#define MAX_CARDS 8
38static int HFC_cnt;
39static uint debug;
40
41MODULE_AUTHOR("Karsten Keil");
42MODULE_LICENSE("GPL");
43module_param(debug, uint, 0);
44
45static LIST_HEAD(HFClist);
46DEFINE_RWLOCK(HFClock);
47
48enum {
49 HFC_CCD_2BD0,
50 HFC_CCD_B000,
51 HFC_CCD_B006,
52 HFC_CCD_B007,
53 HFC_CCD_B008,
54 HFC_CCD_B009,
55 HFC_CCD_B00A,
56 HFC_CCD_B00B,
57 HFC_CCD_B00C,
58 HFC_CCD_B100,
59 HFC_CCD_B700,
60 HFC_CCD_B701,
61 HFC_ASUS_0675,
62 HFC_BERKOM_A1T,
63 HFC_BERKOM_TCONCEPT,
64 HFC_ANIGMA_MC145575,
65 HFC_ZOLTRIX_2BD0,
66 HFC_DIGI_DF_M_IOM2_E,
67 HFC_DIGI_DF_M_E,
68 HFC_DIGI_DF_M_IOM2_A,
69 HFC_DIGI_DF_M_A,
70 HFC_ABOCOM_2BD1,
71 HFC_SITECOM_DC105V2,
72};
73
74struct hfcPCI_hw {
75 unsigned char cirm;
76 unsigned char ctmt;
77 unsigned char clkdel;
78 unsigned char states;
79 unsigned char conn;
80 unsigned char mst_m;
81 unsigned char int_m1;
82 unsigned char int_m2;
83 unsigned char sctrl;
84 unsigned char sctrl_r;
85 unsigned char sctrl_e;
86 unsigned char trm;
87 unsigned char fifo_en;
88 unsigned char bswapped;
89 unsigned char protocol;
90 int nt_timer;
91 unsigned char *pci_io; /* start of PCI IO memory */
92 dma_addr_t dmahandle;
93 void *fifos; /* FIFO memory */
94 int last_bfifo_cnt[2];
95 /* marker saving last b-fifo frame count */
96 struct timer_list timer;
97};
98
99#define HFC_CFG_MASTER 1
100#define HFC_CFG_SLAVE 2
101#define HFC_CFG_PCM 3
102#define HFC_CFG_2HFC 4
103#define HFC_CFG_SLAVEHFC 5
104#define HFC_CFG_NEG_F0 6
105#define HFC_CFG_SW_DD_DU 7
106
107#define FLG_HFC_TIMER_T1 16
108#define FLG_HFC_TIMER_T3 17
109
110#define NT_T1_COUNT 1120 /* number of 3.125ms interrupts (3.5s) */
111#define NT_T3_COUNT 31 /* number of 3.125ms interrupts (97 ms) */
112#define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
113#define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
114
115
116struct hfc_pci {
117 struct list_head list;
118 u_char subtype;
119 u_char chanlimit;
120 u_char initdone;
121 u_long cfg;
122 u_int irq;
123 u_int irqcnt;
124 struct pci_dev *pdev;
125 struct hfcPCI_hw hw;
126 spinlock_t lock; /* card lock */
127 struct dchannel dch;
128 struct bchannel bch[2];
129};
130
131/* Interface functions */
132static void
133enable_hwirq(struct hfc_pci *hc)
134{
135 hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
136 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
137}
138
139static void
140disable_hwirq(struct hfc_pci *hc)
141{
142 hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
143 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
144}
145
146/*
147 * free hardware resources used by driver
148 */
149static void
150release_io_hfcpci(struct hfc_pci *hc)
151{
152 /* disable memory mapped ports + busmaster */
153 pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
154 del_timer(&hc->hw.timer);
155 pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
156 iounmap((void *)hc->hw.pci_io);
157}
158
159/*
160 * set mode (NT or TE)
161 */
162static void
163hfcpci_setmode(struct hfc_pci *hc)
164{
165 if (hc->hw.protocol == ISDN_P_NT_S0) {
166 hc->hw.clkdel = CLKDEL_NT; /* ST-Bit delay for NT-Mode */
167 hc->hw.sctrl |= SCTRL_MODE_NT; /* NT-MODE */
168 hc->hw.states = 1; /* G1 */
169 } else {
170 hc->hw.clkdel = CLKDEL_TE; /* ST-Bit delay for TE-Mode */
171 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
172 hc->hw.states = 2; /* F2 */
173 }
174 Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
175 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
176 udelay(10);
177 Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
178 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
179}
180
181/*
182 * function called to reset the HFC PCI chip. A complete software reset of chip
183 * and fifos is done.
184 */
185static void
186reset_hfcpci(struct hfc_pci *hc)
187{
188 u_char val;
189 int cnt = 0;
190
191 printk(KERN_DEBUG "reset_hfcpci: entered\n");
192 val = Read_hfc(hc, HFCPCI_CHIP_ID);
193 printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
194 /* enable memory mapped ports, disable busmaster */
195 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
196 disable_hwirq(hc);
197 /* enable memory ports + busmaster */
198 pci_write_config_word(hc->pdev, PCI_COMMAND,
199 PCI_ENA_MEMIO + PCI_ENA_MASTER);
200 val = Read_hfc(hc, HFCPCI_STATUS);
201 printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
202 hc->hw.cirm = HFCPCI_RESET; /* Reset On */
203 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
204 set_current_state(TASK_UNINTERRUPTIBLE);
205 mdelay(10); /* Timeout 10ms */
206 hc->hw.cirm = 0; /* Reset Off */
207 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
208 val = Read_hfc(hc, HFCPCI_STATUS);
209 printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
210 while (cnt < 50000) { /* max 50000 us */
211 udelay(5);
212 cnt += 5;
213 val = Read_hfc(hc, HFCPCI_STATUS);
214 if (!(val & 2))
215 break;
216 }
217 printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
218
219 hc->hw.fifo_en = 0x30; /* only D fifos enabled */
220
221 hc->hw.bswapped = 0; /* no exchange */
222 hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
223 hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
224 hc->hw.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
225 hc->hw.sctrl_r = 0;
226 hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE; /* S/T Auto awake */
227 hc->hw.mst_m = 0;
228 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
229 hc->hw.mst_m |= HFCPCI_MASTER; /* HFC Master Mode */
230 if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
231 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
232 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
233 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
234 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
235 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
236
237 hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
238 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
239 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
240
241 /* Clear already pending ints */
242 if (Read_hfc(hc, HFCPCI_INT_S1));
243
244 /* set NT/TE mode */
245 hfcpci_setmode(hc);
246
247 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
248 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
249
250 /*
251 * Init GCI/IOM2 in master mode
252 * Slots 0 and 1 are set for B-chan 1 and 2
253 * D- and monitor/CI channel are not enabled
254 * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
255 * STIO2 is used as data input, B1+B2 from IOM->ST
256 * ST B-channel send disabled -> continous 1s
257 * The IOM slots are always enabled
258 */
259 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
260 /* set data flow directions: connect B1,B2: HFC to/from PCM */
261 hc->hw.conn = 0x09;
262 } else {
263 hc->hw.conn = 0x36; /* set data flow directions */
264 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
265 Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
266 Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
267 Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
268 Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
269 } else {
270 Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
271 Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
272 Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
273 Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
274 }
275 }
276 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
277 val = Read_hfc(hc, HFCPCI_INT_S2);
278}
279
280/*
281 * Timer function called when kernel timer expires
282 */
283static void
284hfcpci_Timer(struct hfc_pci *hc)
285{
286 hc->hw.timer.expires = jiffies + 75;
287 /* WD RESET */
288/*
289 * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
290 * add_timer(&hc->hw.timer);
291 */
292}
293
294
295/*
296 * select a b-channel entry matching and active
297 */
298static struct bchannel *
299Sel_BCS(struct hfc_pci *hc, int channel)
300{
301 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
302 (hc->bch[0].nr & channel))
303 return &hc->bch[0];
304 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
305 (hc->bch[1].nr & channel))
306 return &hc->bch[1];
307 else
308 return NULL;
309}
310
311/*
312 * clear the desired B-channel rx fifo
313 */
314static void
315hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
316{
317 u_char fifo_state;
318 struct bzfifo *bzr;
319
320 if (fifo) {
321 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
322 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
323 } else {
324 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
325 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
326 }
327 if (fifo_state)
328 hc->hw.fifo_en ^= fifo_state;
329 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
330 hc->hw.last_bfifo_cnt[fifo] = 0;
331 bzr->f1 = MAX_B_FRAMES;
332 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
333 bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
334 bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
335 le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
336 if (fifo_state)
337 hc->hw.fifo_en |= fifo_state;
338 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
339}
340
341/*
342 * clear the desired B-channel tx fifo
343 */
344static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
345{
346 u_char fifo_state;
347 struct bzfifo *bzt;
348
349 if (fifo) {
350 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
351 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
352 } else {
353 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
354 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
355 }
356 if (fifo_state)
357 hc->hw.fifo_en ^= fifo_state;
358 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
359 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
360 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
361 "z1(%x) z2(%x) state(%x)\n",
362 fifo, bzt->f1, bzt->f2,
363 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
364 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
365 fifo_state);
366 bzt->f2 = MAX_B_FRAMES;
367 bzt->f1 = bzt->f2; /* init F pointers to remain constant */
368 bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
369 bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(
370 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1 - 1));
371 if (fifo_state)
372 hc->hw.fifo_en |= fifo_state;
373 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
374 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
375 printk(KERN_DEBUG
376 "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
377 fifo, bzt->f1, bzt->f2,
378 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
379 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
380}
381
382/*
383 * read a complete B-frame out of the buffer
384 */
385static void
386hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
387 u_char *bdata, int count)
388{
389 u_char *ptr, *ptr1, new_f2;
390 int total, maxlen, new_z2;
391 struct zt *zp;
392
393 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
394 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
395 zp = &bz->za[bz->f2]; /* point to Z-Regs */
396 new_z2 = le16_to_cpu(zp->z2) + count; /* new position in fifo */
397 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
398 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
399 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
400 if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
401 (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
402 if (bch->debug & DEBUG_HW)
403 printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
404 "invalid length %d or crc\n", count);
405#ifdef ERROR_STATISTIC
406 bch->err_inv++;
407#endif
408 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
409 bz->f2 = new_f2; /* next buffer */
410 } else {
411 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
412 if (!bch->rx_skb) {
413 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
414 return;
415 }
416 total = count;
417 count -= 3;
418 ptr = skb_put(bch->rx_skb, count);
419
420 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
421 maxlen = count; /* complete transfer */
422 else
423 maxlen = B_FIFO_SIZE + B_SUB_VAL -
424 le16_to_cpu(zp->z2); /* maximum */
425
426 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
427 /* start of data */
428 memcpy(ptr, ptr1, maxlen); /* copy data */
429 count -= maxlen;
430
431 if (count) { /* rest remaining */
432 ptr += maxlen;
433 ptr1 = bdata; /* start of buffer */
434 memcpy(ptr, ptr1, count); /* rest */
435 }
436 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
437 bz->f2 = new_f2; /* next buffer */
438 recv_Bchannel(bch);
439 }
440}
441
442/*
443 * D-channel receive procedure
444 */
445static int
446receive_dmsg(struct hfc_pci *hc)
447{
448 struct dchannel *dch = &hc->dch;
449 int maxlen;
450 int rcnt, total;
451 int count = 5;
452 u_char *ptr, *ptr1;
453 struct dfifo *df;
454 struct zt *zp;
455
456 df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
457 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
458 zp = &df->za[df->f2 & D_FREG_MASK];
459 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
460 if (rcnt < 0)
461 rcnt += D_FIFO_SIZE;
462 rcnt++;
463 if (dch->debug & DEBUG_HW_DCHANNEL)
464 printk(KERN_DEBUG
465 "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
466 df->f1, df->f2,
467 le16_to_cpu(zp->z1),
468 le16_to_cpu(zp->z2),
469 rcnt);
470
471 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
472 (df->data[le16_to_cpu(zp->z1)])) {
473 if (dch->debug & DEBUG_HW)
474 printk(KERN_DEBUG
475 "empty_fifo hfcpci paket inv. len "
476 "%d or crc %d\n",
477 rcnt,
478 df->data[le16_to_cpu(zp->z1)]);
479#ifdef ERROR_STATISTIC
480 cs->err_rx++;
481#endif
482 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
483 (MAX_D_FRAMES + 1); /* next buffer */
484 df->za[df->f2 & D_FREG_MASK].z2 =
485 cpu_to_le16((zp->z2 + rcnt) & (D_FIFO_SIZE - 1));
486 } else {
487 dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
488 if (!dch->rx_skb) {
489 printk(KERN_WARNING
490 "HFC-PCI: D receive out of memory\n");
491 break;
492 }
493 total = rcnt;
494 rcnt -= 3;
495 ptr = skb_put(dch->rx_skb, rcnt);
496
497 if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
498 maxlen = rcnt; /* complete transfer */
499 else
500 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
501 /* maximum */
502
503 ptr1 = df->data + le16_to_cpu(zp->z2);
504 /* start of data */
505 memcpy(ptr, ptr1, maxlen); /* copy data */
506 rcnt -= maxlen;
507
508 if (rcnt) { /* rest remaining */
509 ptr += maxlen;
510 ptr1 = df->data; /* start of buffer */
511 memcpy(ptr, ptr1, rcnt); /* rest */
512 }
513 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
514 (MAX_D_FRAMES + 1); /* next buffer */
515 df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
516 le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
517 recv_Dchannel(dch);
518 }
519 }
520 return 1;
521}
522
523/*
524 * check for transparent receive data and read max one threshold size if avail
525 */
526int
527hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *bz, u_char *bdata)
528{
529 unsigned short *z1r, *z2r;
530 int new_z2, fcnt, maxlen;
531 u_char *ptr, *ptr1;
532
533 z1r = &bz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
534 z2r = z1r + 1;
535
536 fcnt = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
537 if (!fcnt)
538 return 0; /* no data avail */
539
540 if (fcnt <= 0)
541 fcnt += B_FIFO_SIZE; /* bytes actually buffered */
542 if (fcnt > HFCPCI_BTRANS_THRESHOLD)
543 fcnt = HFCPCI_BTRANS_THRESHOLD; /* limit size */
544
545 new_z2 = le16_to_cpu(*z2r) + fcnt; /* new position in fifo */
546 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
547 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
548
549 bch->rx_skb = mI_alloc_skb(fcnt, GFP_ATOMIC);
550 if (bch->rx_skb) {
551 ptr = skb_put(bch->rx_skb, fcnt);
552 if (le16_to_cpu(*z2r) + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
553 maxlen = fcnt; /* complete transfer */
554 else
555 maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
556 /* maximum */
557
558 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
559 /* start of data */
560 memcpy(ptr, ptr1, maxlen); /* copy data */
561 fcnt -= maxlen;
562
563 if (fcnt) { /* rest remaining */
564 ptr += maxlen;
565 ptr1 = bdata; /* start of buffer */
566 memcpy(ptr, ptr1, fcnt); /* rest */
567 }
568 recv_Bchannel(bch);
569 } else
570 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
571
572 *z2r = cpu_to_le16(new_z2); /* new position */
573 return 1;
574}
575
576/*
577 * B-channel main receive routine
578 */
579void
580main_rec_hfcpci(struct bchannel *bch)
581{
582 struct hfc_pci *hc = bch->hw;
583 int rcnt, real_fifo;
584 int receive, count = 5;
585 struct bzfifo *bz;
586 u_char *bdata;
587 struct zt *zp;
588
589
590 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
591 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
592 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
593 real_fifo = 1;
594 } else {
595 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
596 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
597 real_fifo = 0;
598 }
599Begin:
600 count--;
601 if (bz->f1 != bz->f2) {
602 if (bch->debug & DEBUG_HW_BCHANNEL)
603 printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
604 bch->nr, bz->f1, bz->f2);
605 zp = &bz->za[bz->f2];
606
607 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
608 if (rcnt < 0)
609 rcnt += B_FIFO_SIZE;
610 rcnt++;
611 if (bch->debug & DEBUG_HW_BCHANNEL)
612 printk(KERN_DEBUG
613 "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
614 bch->nr, le16_to_cpu(zp->z1),
615 le16_to_cpu(zp->z2), rcnt);
616 hfcpci_empty_bfifo(bch, bz, bdata, rcnt);
617 rcnt = bz->f1 - bz->f2;
618 if (rcnt < 0)
619 rcnt += MAX_B_FRAMES + 1;
620 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
621 rcnt = 0;
622 hfcpci_clear_fifo_rx(hc, real_fifo);
623 }
624 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
625 if (rcnt > 1)
626 receive = 1;
627 else
628 receive = 0;
629 } else if (test_bit(FLG_TRANSPARENT, &bch->Flags))
630 receive = hfcpci_empty_fifo_trans(bch, bz, bdata);
631 else
632 receive = 0;
633 if (count && receive)
634 goto Begin;
635
636}
637
638/*
639 * D-channel send routine
640 */
641static void
642hfcpci_fill_dfifo(struct hfc_pci *hc)
643{
644 struct dchannel *dch = &hc->dch;
645 int fcnt;
646 int count, new_z1, maxlen;
647 struct dfifo *df;
648 u_char *src, *dst, new_f1;
649
650 if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
651 printk(KERN_DEBUG "%s\n", __func__);
652
653 if (!dch->tx_skb)
654 return;
655 count = dch->tx_skb->len - dch->tx_idx;
656 if (count <= 0)
657 return;
658 df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
659
660 if (dch->debug & DEBUG_HW_DFIFO)
661 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
662 df->f1, df->f2,
663 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
664 fcnt = df->f1 - df->f2; /* frame count actually buffered */
665 if (fcnt < 0)
666 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
667 if (fcnt > (MAX_D_FRAMES - 1)) {
668 if (dch->debug & DEBUG_HW_DCHANNEL)
669 printk(KERN_DEBUG
670 "hfcpci_fill_Dfifo more as 14 frames\n");
671#ifdef ERROR_STATISTIC
672 cs->err_tx++;
673#endif
674 return;
675 }
676 /* now determine free bytes in FIFO buffer */
677 maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
678 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
679 if (maxlen <= 0)
680 maxlen += D_FIFO_SIZE; /* count now contains available bytes */
681
682 if (dch->debug & DEBUG_HW_DCHANNEL)
683 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
684 count, maxlen);
685 if (count > maxlen) {
686 if (dch->debug & DEBUG_HW_DCHANNEL)
687 printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
688 return;
689 }
690 new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
691 (D_FIFO_SIZE - 1);
692 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
693 src = dch->tx_skb->data + dch->tx_idx; /* source pointer */
694 dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
695 maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
696 /* end fifo */
697 if (maxlen > count)
698 maxlen = count; /* limit size */
699 memcpy(dst, src, maxlen); /* first copy */
700
701 count -= maxlen; /* remaining bytes */
702 if (count) {
703 dst = df->data; /* start of buffer */
704 src += maxlen; /* new position */
705 memcpy(dst, src, count);
706 }
707 df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
708 /* for next buffer */
709 df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
710 /* new pos actual buffer */
711 df->f1 = new_f1; /* next frame */
712 dch->tx_idx = dch->tx_skb->len;
713}
714
715/*
716 * B-channel send routine
717 */
718static void
719hfcpci_fill_fifo(struct bchannel *bch)
720{
721 struct hfc_pci *hc = bch->hw;
722 int maxlen, fcnt;
723 int count, new_z1;
724 struct bzfifo *bz;
725 u_char *bdata;
726 u_char new_f1, *src, *dst;
727 unsigned short *z1t, *z2t;
728
729 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
730 printk(KERN_DEBUG "%s\n", __func__);
731 if ((!bch->tx_skb) || bch->tx_skb->len <= 0)
732 return;
733 count = bch->tx_skb->len - bch->tx_idx;
734 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
735 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
736 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
737 } else {
738 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
739 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
740 }
741
742 if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
743 z1t = &bz->za[MAX_B_FRAMES].z1;
744 z2t = z1t + 1;
745 if (bch->debug & DEBUG_HW_BCHANNEL)
746 printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
747 "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
748 le16_to_cpu(*z1t), le16_to_cpu(*z2t));
749 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
750 if (fcnt <= 0)
751 fcnt += B_FIFO_SIZE;
752 /* fcnt contains available bytes in fifo */
753 fcnt = B_FIFO_SIZE - fcnt;
754 /* remaining bytes to send (bytes in fifo) */
755next_t_frame:
756 count = bch->tx_skb->len - bch->tx_idx;
757 /* maximum fill shall be HFCPCI_BTRANS_MAX */
758 if (count > HFCPCI_BTRANS_MAX - fcnt)
759 count = HFCPCI_BTRANS_MAX - fcnt;
760 if (count <= 0)
761 return;
762 /* data is suitable for fifo */
763 new_z1 = le16_to_cpu(*z1t) + count;
764 /* new buffer Position */
765 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
766 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
767 src = bch->tx_skb->data + bch->tx_idx;
768 /* source pointer */
769 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
770 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
771 /* end of fifo */
772 if (bch->debug & DEBUG_HW_BFIFO)
773 printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
774 "maxl(%d) nz1(%x) dst(%p)\n",
775 fcnt, maxlen, new_z1, dst);
776 fcnt += count;
777 bch->tx_idx += count;
778 if (maxlen > count)
779 maxlen = count; /* limit size */
780 memcpy(dst, src, maxlen); /* first copy */
781 count -= maxlen; /* remaining bytes */
782 if (count) {
783 dst = bdata; /* start of buffer */
784 src += maxlen; /* new position */
785 memcpy(dst, src, count);
786 }
787 *z1t = cpu_to_le16(new_z1); /* now send data */
788 if (bch->tx_idx < bch->tx_skb->len)
789 return;
790 /* send confirm, on trans, free on hdlc. */
791 if (test_bit(FLG_TRANSPARENT, &bch->Flags))
792 confirm_Bsend(bch);
793 dev_kfree_skb(bch->tx_skb);
794 if (get_next_bframe(bch))
795 goto next_t_frame;
796 return;
797 }
798 if (bch->debug & DEBUG_HW_BCHANNEL)
799 printk(KERN_DEBUG
800 "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
801 __func__, bch->nr, bz->f1, bz->f2,
802 bz->za[bz->f1].z1);
803 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
804 if (fcnt < 0)
805 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
806 if (fcnt > (MAX_B_FRAMES - 1)) {
807 if (bch->debug & DEBUG_HW_BCHANNEL)
808 printk(KERN_DEBUG
809 "hfcpci_fill_Bfifo more as 14 frames\n");
810 return;
811 }
812 /* now determine free bytes in FIFO buffer */
813 maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
814 le16_to_cpu(bz->za[bz->f1].z1) - 1;
815 if (maxlen <= 0)
816 maxlen += B_FIFO_SIZE; /* count now contains available bytes */
817
818 if (bch->debug & DEBUG_HW_BCHANNEL)
819 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
820 bch->nr, count, maxlen);
821
822 if (maxlen < count) {
823 if (bch->debug & DEBUG_HW_BCHANNEL)
824 printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
825 return;
826 }
827 new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
828 /* new buffer Position */
829 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
830 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
831
832 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
833 src = bch->tx_skb->data + bch->tx_idx; /* source pointer */
834 dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
835 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
836 /* end fifo */
837 if (maxlen > count)
838 maxlen = count; /* limit size */
839 memcpy(dst, src, maxlen); /* first copy */
840
841 count -= maxlen; /* remaining bytes */
842 if (count) {
843 dst = bdata; /* start of buffer */
844 src += maxlen; /* new position */
845 memcpy(dst, src, count);
846 }
847 bz->za[new_f1].z1 = cpu_to_le16(new_z1); /* for next buffer */
848 bz->f1 = new_f1; /* next frame */
849 dev_kfree_skb(bch->tx_skb);
850 get_next_bframe(bch);
851}
852
853
854
855/*
856 * handle L1 state changes TE
857 */
858
859static void
860ph_state_te(struct dchannel *dch)
861{
862 if (dch->debug)
863 printk(KERN_DEBUG "%s: TE newstate %x\n",
864 __func__, dch->state);
865 switch (dch->state) {
866 case 0:
867 l1_event(dch->l1, HW_RESET_IND);
868 break;
869 case 3:
870 l1_event(dch->l1, HW_DEACT_IND);
871 break;
872 case 5:
873 case 8:
874 l1_event(dch->l1, ANYSIGNAL);
875 break;
876 case 6:
877 l1_event(dch->l1, INFO2);
878 break;
879 case 7:
880 l1_event(dch->l1, INFO4_P8);
881 break;
882 }
883}
884
885/*
886 * handle L1 state changes NT
887 */
888
889static void
890handle_nt_timer3(struct dchannel *dch) {
891 struct hfc_pci *hc = dch->hw;
892
893 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
894 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
895 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
896 hc->hw.nt_timer = 0;
897 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
898 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
899 hc->hw.mst_m |= HFCPCI_MASTER;
900 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
901 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
902 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
903}
904
905static void
906ph_state_nt(struct dchannel *dch)
907{
908 struct hfc_pci *hc = dch->hw;
909
910 if (dch->debug)
911 printk(KERN_DEBUG "%s: NT newstate %x\n",
912 __func__, dch->state);
913 switch (dch->state) {
914 case 2:
915 if (hc->hw.nt_timer < 0) {
916 hc->hw.nt_timer = 0;
917 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
918 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
919 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
920 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
921 /* Clear already pending ints */
922 if (Read_hfc(hc, HFCPCI_INT_S1));
923 Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
924 udelay(10);
925 Write_hfc(hc, HFCPCI_STATES, 4);
926 dch->state = 4;
927 } else if (hc->hw.nt_timer == 0) {
928 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
929 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
930 hc->hw.nt_timer = NT_T1_COUNT;
931 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
932 hc->hw.ctmt |= HFCPCI_TIM3_125;
933 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
934 HFCPCI_CLTIMER);
935 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
936 test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
937 /* allow G2 -> G3 transition */
938 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
939 } else {
940 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
941 }
942 break;
943 case 1:
944 hc->hw.nt_timer = 0;
945 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
946 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
947 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
948 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
949 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
950 hc->hw.mst_m &= ~HFCPCI_MASTER;
951 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
952 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
953 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
954 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
955 break;
956 case 4:
957 hc->hw.nt_timer = 0;
958 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
959 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
960 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
961 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
962 break;
963 case 3:
964 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
965 if (!test_and_clear_bit(FLG_L2_ACTIVATED,
966 &dch->Flags)) {
967 handle_nt_timer3(dch);
968 break;
969 }
970 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
971 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
972 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
973 hc->hw.nt_timer = NT_T3_COUNT;
974 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
975 hc->hw.ctmt |= HFCPCI_TIM3_125;
976 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
977 HFCPCI_CLTIMER);
978 }
979 break;
980 }
981}
982
983static void
984ph_state(struct dchannel *dch)
985{
986 struct hfc_pci *hc = dch->hw;
987
988 if (hc->hw.protocol == ISDN_P_NT_S0) {
989 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
990 hc->hw.nt_timer < 0)
991 handle_nt_timer3(dch);
992 else
993 ph_state_nt(dch);
994 } else
995 ph_state_te(dch);
996}
997
998/*
999 * Layer 1 callback function
1000 */
1001static int
1002hfc_l1callback(struct dchannel *dch, u_int cmd)
1003{
1004 struct hfc_pci *hc = dch->hw;
1005
1006 switch (cmd) {
1007 case INFO3_P8:
1008 case INFO3_P10:
1009 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1010 hc->hw.mst_m |= HFCPCI_MASTER;
1011 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1012 break;
1013 case HW_RESET_REQ:
1014 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1015 /* HFC ST 3 */
1016 udelay(6);
1017 Write_hfc(hc, HFCPCI_STATES, 3); /* HFC ST 2 */
1018 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1019 hc->hw.mst_m |= HFCPCI_MASTER;
1020 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1021 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1022 HFCPCI_DO_ACTION);
1023 l1_event(dch->l1, HW_POWERUP_IND);
1024 break;
1025 case HW_DEACT_REQ:
1026 hc->hw.mst_m &= ~HFCPCI_MASTER;
1027 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1028 skb_queue_purge(&dch->squeue);
1029 if (dch->tx_skb) {
1030 dev_kfree_skb(dch->tx_skb);
1031 dch->tx_skb = NULL;
1032 }
1033 dch->tx_idx = 0;
1034 if (dch->rx_skb) {
1035 dev_kfree_skb(dch->rx_skb);
1036 dch->rx_skb = NULL;
1037 }
1038 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1039 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1040 del_timer(&dch->timer);
1041 break;
1042 case HW_POWERUP_REQ:
1043 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1044 break;
1045 case PH_ACTIVATE_IND:
1046 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1047 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1048 GFP_ATOMIC);
1049 break;
1050 case PH_DEACTIVATE_IND:
1051 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1052 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1053 GFP_ATOMIC);
1054 break;
1055 default:
1056 if (dch->debug & DEBUG_HW)
1057 printk(KERN_DEBUG "%s: unknown command %x\n",
1058 __func__, cmd);
1059 return -1;
1060 }
1061 return 0;
1062}
1063
1064/*
1065 * Interrupt handler
1066 */
1067static inline void
1068tx_birq(struct bchannel *bch)
1069{
1070 if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1071 hfcpci_fill_fifo(bch);
1072 else {
1073 if (bch->tx_skb)
1074 dev_kfree_skb(bch->tx_skb);
1075 if (get_next_bframe(bch))
1076 hfcpci_fill_fifo(bch);
1077 }
1078}
1079
1080static inline void
1081tx_dirq(struct dchannel *dch)
1082{
1083 if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1084 hfcpci_fill_dfifo(dch->hw);
1085 else {
1086 if (dch->tx_skb)
1087 dev_kfree_skb(dch->tx_skb);
1088 if (get_next_dframe(dch))
1089 hfcpci_fill_dfifo(dch->hw);
1090 }
1091}
1092
1093static irqreturn_t
1094hfcpci_int(int intno, void *dev_id)
1095{
1096 struct hfc_pci *hc = dev_id;
1097 u_char exval;
1098 struct bchannel *bch;
1099 u_char val, stat;
1100
1101 spin_lock(&hc->lock);
1102 if (!(hc->hw.int_m2 & 0x08)) {
1103 spin_unlock(&hc->lock);
1104 return IRQ_NONE; /* not initialised */
1105 }
1106 stat = Read_hfc(hc, HFCPCI_STATUS);
1107 if (HFCPCI_ANYINT & stat) {
1108 val = Read_hfc(hc, HFCPCI_INT_S1);
1109 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1110 printk(KERN_DEBUG
1111 "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1112 } else {
1113 /* shared */
1114 spin_unlock(&hc->lock);
1115 return IRQ_NONE;
1116 }
1117 hc->irqcnt++;
1118
1119 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1120 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1121 val &= hc->hw.int_m1;
1122 if (val & 0x40) { /* state machine irq */
1123 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1124 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1125 printk(KERN_DEBUG "ph_state chg %d->%d\n",
1126 hc->dch.state, exval);
1127 hc->dch.state = exval;
1128 schedule_event(&hc->dch, FLG_PHCHANGE);
1129 val &= ~0x40;
1130 }
1131 if (val & 0x80) { /* timer irq */
1132 if (hc->hw.protocol == ISDN_P_NT_S0) {
1133 if ((--hc->hw.nt_timer) < 0)
1134 schedule_event(&hc->dch, FLG_PHCHANGE);
1135 }
1136 val &= ~0x80;
1137 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1138 }
1139 if (val & 0x08) {
1140 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1141 if (bch)
1142 main_rec_hfcpci(bch);
1143 else if (hc->dch.debug)
1144 printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1145 }
1146 if (val & 0x10) {
1147 bch = Sel_BCS(hc, 2);
1148 if (bch)
1149 main_rec_hfcpci(bch);
1150 else if (hc->dch.debug)
1151 printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1152 }
1153 if (val & 0x01) {
1154 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1155 if (bch)
1156 tx_birq(bch);
1157 else if (hc->dch.debug)
1158 printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1159 }
1160 if (val & 0x02) {
1161 bch = Sel_BCS(hc, 2);
1162 if (bch)
1163 tx_birq(bch);
1164 else if (hc->dch.debug)
1165 printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1166 }
1167 if (val & 0x20)
1168 receive_dmsg(hc);
1169 if (val & 0x04) { /* dframe transmitted */
1170 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1171 del_timer(&hc->dch.timer);
1172 tx_dirq(&hc->dch);
1173 }
1174 spin_unlock(&hc->lock);
1175 return IRQ_HANDLED;
1176}
1177
1178/*
1179 * timer callback for D-chan busy resolution. Currently no function
1180 */
1181static void
1182hfcpci_dbusy_timer(struct hfc_pci *hc)
1183{
1184}
1185
1186/*
1187 * activate/deactivate hardware for selected channels and mode
1188 */
1189static int
1190mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1191{
1192 struct hfc_pci *hc = bch->hw;
1193 int fifo2;
1194 u_char rx_slot = 0, tx_slot = 0, pcm_mode;
1195
1196 if (bch->debug & DEBUG_HW_BCHANNEL)
1197 printk(KERN_DEBUG
1198 "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1199 bch->state, protocol, bch->nr, bc);
1200
1201 fifo2 = bc;
1202 pcm_mode = (bc>>24) & 0xff;
1203 if (pcm_mode) { /* PCM SLOT USE */
1204 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1205 printk(KERN_WARNING
1206 "%s: pcm channel id without HFC_CFG_PCM\n",
1207 __func__);
1208 rx_slot = (bc>>8) & 0xff;
1209 tx_slot = (bc>>16) & 0xff;
1210 bc = bc & 0xff;
1211 } else if (test_bit(HFC_CFG_PCM, &hc->cfg) &&
1212 (protocol > ISDN_P_NONE))
1213 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1214 __func__);
1215 if (hc->chanlimit > 1) {
1216 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1217 hc->hw.sctrl_e &= ~0x80;
1218 } else {
1219 if (bc & 2) {
1220 if (protocol != ISDN_P_NONE) {
1221 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1222 hc->hw.sctrl_e |= 0x80;
1223 } else {
1224 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1225 hc->hw.sctrl_e &= ~0x80;
1226 }
1227 fifo2 = 1;
1228 } else {
1229 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1230 hc->hw.sctrl_e &= ~0x80;
1231 }
1232 }
1233 switch (protocol) {
1234 case (-1): /* used for init */
1235 bch->state = -1;
1236 bch->nr = bc;
1237 case (ISDN_P_NONE):
1238 if (bch->state == ISDN_P_NONE)
1239 return 0;
1240 if (bc & 2) {
1241 hc->hw.sctrl &= ~SCTRL_B2_ENA;
1242 hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1243 } else {
1244 hc->hw.sctrl &= ~SCTRL_B1_ENA;
1245 hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1246 }
1247 if (fifo2 & 2) {
1248 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1249 hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS +
1250 HFCPCI_INTS_B2REC);
1251 } else {
1252 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1253 hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS +
1254 HFCPCI_INTS_B1REC);
1255 }
1256#ifdef REVERSE_BITORDER
1257 if (bch->nr & 2)
1258 hc->hw.cirm &= 0x7f;
1259 else
1260 hc->hw.cirm &= 0xbf;
1261#endif
1262 bch->state = ISDN_P_NONE;
1263 bch->nr = bc;
1264 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1265 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1266 break;
1267 case (ISDN_P_B_RAW):
1268 bch->state = protocol;
1269 bch->nr = bc;
1270 hfcpci_clear_fifo_rx(hc, (fifo2 & 2)?1:0);
1271 hfcpci_clear_fifo_tx(hc, (fifo2 & 2)?1:0);
1272 if (bc & 2) {
1273 hc->hw.sctrl |= SCTRL_B2_ENA;
1274 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1275#ifdef REVERSE_BITORDER
1276 hc->hw.cirm |= 0x80;
1277#endif
1278 } else {
1279 hc->hw.sctrl |= SCTRL_B1_ENA;
1280 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1281#ifdef REVERSE_BITORDER
1282 hc->hw.cirm |= 0x40;
1283#endif
1284 }
1285 if (fifo2 & 2) {
1286 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1287 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1288 HFCPCI_INTS_B2REC);
1289 hc->hw.ctmt |= 2;
1290 hc->hw.conn &= ~0x18;
1291 } else {
1292 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1293 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1294 HFCPCI_INTS_B1REC);
1295 hc->hw.ctmt |= 1;
1296 hc->hw.conn &= ~0x03;
1297 }
1298 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1299 break;
1300 case (ISDN_P_B_HDLC):
1301 bch->state = protocol;
1302 bch->nr = bc;
1303 hfcpci_clear_fifo_rx(hc, (fifo2 & 2)?1:0);
1304 hfcpci_clear_fifo_tx(hc, (fifo2 & 2)?1:0);
1305 if (bc & 2) {
1306 hc->hw.sctrl |= SCTRL_B2_ENA;
1307 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1308 } else {
1309 hc->hw.sctrl |= SCTRL_B1_ENA;
1310 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1311 }
1312 if (fifo2 & 2) {
1313 hc->hw.last_bfifo_cnt[1] = 0;
1314 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1315 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1316 HFCPCI_INTS_B2REC);
1317 hc->hw.ctmt &= ~2;
1318 hc->hw.conn &= ~0x18;
1319 } else {
1320 hc->hw.last_bfifo_cnt[0] = 0;
1321 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1322 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1323 HFCPCI_INTS_B1REC);
1324 hc->hw.ctmt &= ~1;
1325 hc->hw.conn &= ~0x03;
1326 }
1327 test_and_set_bit(FLG_HDLC, &bch->Flags);
1328 break;
1329 default:
1330 printk(KERN_DEBUG "prot not known %x\n", protocol);
1331 return -ENOPROTOOPT;
1332 }
1333 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1334 if ((protocol == ISDN_P_NONE) ||
1335 (protocol == -1)) { /* init case */
1336 rx_slot = 0;
1337 tx_slot = 0;
1338 } else {
1339 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1340 rx_slot |= 0xC0;
1341 tx_slot |= 0xC0;
1342 } else {
1343 rx_slot |= 0x80;
1344 tx_slot |= 0x80;
1345 }
1346 }
1347 if (bc & 2) {
1348 hc->hw.conn &= 0xc7;
1349 hc->hw.conn |= 0x08;
1350 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1351 __func__, tx_slot);
1352 printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1353 __func__, rx_slot);
1354 Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1355 Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1356 } else {
1357 hc->hw.conn &= 0xf8;
1358 hc->hw.conn |= 0x01;
1359 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1360 __func__, tx_slot);
1361 printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1362 __func__, rx_slot);
1363 Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1364 Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1365 }
1366 }
1367 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1368 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1369 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1370 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1371 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1372 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1373 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1374#ifdef REVERSE_BITORDER
1375 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1376#endif
1377 return 0;
1378}
1379
1380static int
1381set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1382{
1383 struct hfc_pci *hc = bch->hw;
1384
1385 if (bch->debug & DEBUG_HW_BCHANNEL)
1386 printk(KERN_DEBUG
1387 "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1388 bch->state, protocol, bch->nr, chan);
1389 if (bch->nr != chan) {
1390 printk(KERN_DEBUG
1391 "HFCPCI rxtest wrong channel parameter %x/%x\n",
1392 bch->nr, chan);
1393 return -EINVAL;
1394 }
1395 switch (protocol) {
1396 case (ISDN_P_B_RAW):
1397 bch->state = protocol;
1398 hfcpci_clear_fifo_rx(hc, (chan & 2)?1:0);
1399 if (chan & 2) {
1400 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1401 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1402 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1403 hc->hw.ctmt |= 2;
1404 hc->hw.conn &= ~0x18;
1405#ifdef REVERSE_BITORDER
1406 hc->hw.cirm |= 0x80;
1407#endif
1408 } else {
1409 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1410 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1411 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1412 hc->hw.ctmt |= 1;
1413 hc->hw.conn &= ~0x03;
1414#ifdef REVERSE_BITORDER
1415 hc->hw.cirm |= 0x40;
1416#endif
1417 }
1418 break;
1419 case (ISDN_P_B_HDLC):
1420 bch->state = protocol;
1421 hfcpci_clear_fifo_rx(hc, (chan & 2)?1:0);
1422 if (chan & 2) {
1423 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1424 hc->hw.last_bfifo_cnt[1] = 0;
1425 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1426 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1427 hc->hw.ctmt &= ~2;
1428 hc->hw.conn &= ~0x18;
1429 } else {
1430 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1431 hc->hw.last_bfifo_cnt[0] = 0;
1432 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1433 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1434 hc->hw.ctmt &= ~1;
1435 hc->hw.conn &= ~0x03;
1436 }
1437 break;
1438 default:
1439 printk(KERN_DEBUG "prot not known %x\n", protocol);
1440 return -ENOPROTOOPT;
1441 }
1442 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1443 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1444 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1445 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1446 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1447#ifdef REVERSE_BITORDER
1448 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1449#endif
1450 return 0;
1451}
1452
1453static void
1454deactivate_bchannel(struct bchannel *bch)
1455{
1456 struct hfc_pci *hc = bch->hw;
1457 u_long flags;
1458
1459 spin_lock_irqsave(&hc->lock, flags);
1460 if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
1461 dev_kfree_skb(bch->next_skb);
1462 bch->next_skb = NULL;
1463 }
1464 if (bch->tx_skb) {
1465 dev_kfree_skb(bch->tx_skb);
1466 bch->tx_skb = NULL;
1467 }
1468 bch->tx_idx = 0;
1469 if (bch->rx_skb) {
1470 dev_kfree_skb(bch->rx_skb);
1471 bch->rx_skb = NULL;
1472 }
1473 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1474 test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
1475 test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
1476 spin_unlock_irqrestore(&hc->lock, flags);
1477}
1478
1479/*
1480 * Layer 1 B-channel hardware access
1481 */
1482static int
1483channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1484{
1485 int ret = 0;
1486
1487 switch (cq->op) {
1488 case MISDN_CTRL_GETOP:
1489 cq->op = 0;
1490 break;
1491 default:
1492 printk(KERN_WARNING "%s: unknown Op %x\n", __func__, cq->op);
1493 ret = -EINVAL;
1494 break;
1495 }
1496 return ret;
1497}
1498static int
1499hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1500{
1501 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1502 struct hfc_pci *hc = bch->hw;
1503 int ret = -EINVAL;
1504 u_long flags;
1505
1506 if (bch->debug & DEBUG_HW)
1507 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1508 switch (cmd) {
1509 case HW_TESTRX_RAW:
1510 spin_lock_irqsave(&hc->lock, flags);
1511 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1512 spin_unlock_irqrestore(&hc->lock, flags);
1513 break;
1514 case HW_TESTRX_HDLC:
1515 spin_lock_irqsave(&hc->lock, flags);
1516 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1517 spin_unlock_irqrestore(&hc->lock, flags);
1518 break;
1519 case HW_TESTRX_OFF:
1520 spin_lock_irqsave(&hc->lock, flags);
1521 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1522 spin_unlock_irqrestore(&hc->lock, flags);
1523 ret = 0;
1524 break;
1525 case CLOSE_CHANNEL:
1526 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1527 if (test_bit(FLG_ACTIVE, &bch->Flags))
1528 deactivate_bchannel(bch);
1529 ch->protocol = ISDN_P_NONE;
1530 ch->peer = NULL;
1531 module_put(THIS_MODULE);
1532 ret = 0;
1533 break;
1534 case CONTROL_CHANNEL:
1535 ret = channel_bctrl(bch, arg);
1536 break;
1537 default:
1538 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1539 __func__, cmd);
1540 }
1541 return ret;
1542}
1543
1544/*
1545 * Layer2 -> Layer 1 Dchannel data
1546 */
1547static int
1548hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1549{
1550 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1551 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1552 struct hfc_pci *hc = dch->hw;
1553 int ret = -EINVAL;
1554 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1555 unsigned int id;
1556 u_long flags;
1557
1558 switch (hh->prim) {
1559 case PH_DATA_REQ:
1560 spin_lock_irqsave(&hc->lock, flags);
1561 ret = dchannel_senddata(dch, skb);
1562 if (ret > 0) { /* direct TX */
1563 id = hh->id; /* skb can be freed */
1564 hfcpci_fill_dfifo(dch->hw);
1565 ret = 0;
1566 spin_unlock_irqrestore(&hc->lock, flags);
1567 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1568 } else
1569 spin_unlock_irqrestore(&hc->lock, flags);
1570 return ret;
1571 case PH_ACTIVATE_REQ:
1572 spin_lock_irqsave(&hc->lock, flags);
1573 if (hc->hw.protocol == ISDN_P_NT_S0) {
1574 ret = 0;
1575 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1576 hc->hw.mst_m |= HFCPCI_MASTER;
1577 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1578 if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1579 spin_unlock_irqrestore(&hc->lock, flags);
1580 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1581 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1582 break;
1583 }
1584 test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1585 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1586 HFCPCI_DO_ACTION | 1);
1587 } else
1588 ret = l1_event(dch->l1, hh->prim);
1589 spin_unlock_irqrestore(&hc->lock, flags);
1590 break;
1591 case PH_DEACTIVATE_REQ:
1592 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1593 spin_lock_irqsave(&hc->lock, flags);
1594 if (hc->hw.protocol == ISDN_P_NT_S0) {
1595 /* prepare deactivation */
1596 Write_hfc(hc, HFCPCI_STATES, 0x40);
1597 skb_queue_purge(&dch->squeue);
1598 if (dch->tx_skb) {
1599 dev_kfree_skb(dch->tx_skb);
1600 dch->tx_skb = NULL;
1601 }
1602 dch->tx_idx = 0;
1603 if (dch->rx_skb) {
1604 dev_kfree_skb(dch->rx_skb);
1605 dch->rx_skb = NULL;
1606 }
1607 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1608 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1609 del_timer(&dch->timer);
1610#ifdef FIXME
1611 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1612 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1613#endif
1614 hc->hw.mst_m &= ~HFCPCI_MASTER;
1615 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1616 ret = 0;
1617 } else {
1618 ret = l1_event(dch->l1, hh->prim);
1619 }
1620 spin_unlock_irqrestore(&hc->lock, flags);
1621 break;
1622 }
1623 if (!ret)
1624 dev_kfree_skb(skb);
1625 return ret;
1626}
1627
1628/*
1629 * Layer2 -> Layer 1 Bchannel data
1630 */
1631static int
1632hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1633{
1634 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1635 struct hfc_pci *hc = bch->hw;
1636 int ret = -EINVAL;
1637 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1638 unsigned int id;
1639 u_long flags;
1640
1641 switch (hh->prim) {
1642 case PH_DATA_REQ:
1643 spin_lock_irqsave(&hc->lock, flags);
1644 ret = bchannel_senddata(bch, skb);
1645 if (ret > 0) { /* direct TX */
1646 id = hh->id; /* skb can be freed */
1647 hfcpci_fill_fifo(bch);
1648 ret = 0;
1649 spin_unlock_irqrestore(&hc->lock, flags);
1650 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1651 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1652 } else
1653 spin_unlock_irqrestore(&hc->lock, flags);
1654 return ret;
1655 case PH_ACTIVATE_REQ:
1656 spin_lock_irqsave(&hc->lock, flags);
1657 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1658 ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1659 else
1660 ret = 0;
1661 spin_unlock_irqrestore(&hc->lock, flags);
1662 if (!ret)
1663 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1664 NULL, GFP_KERNEL);
1665 break;
1666 case PH_DEACTIVATE_REQ:
1667 deactivate_bchannel(bch);
1668 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1669 NULL, GFP_KERNEL);
1670 ret = 0;
1671 break;
1672 }
1673 if (!ret)
1674 dev_kfree_skb(skb);
1675 return ret;
1676}
1677
1678/*
1679 * called for card init message
1680 */
1681
1682void
1683inithfcpci(struct hfc_pci *hc)
1684{
1685 printk(KERN_DEBUG "inithfcpci: entered\n");
1686 hc->dch.timer.function = (void *) hfcpci_dbusy_timer;
1687 hc->dch.timer.data = (long) &hc->dch;
1688 init_timer(&hc->dch.timer);
1689 hc->chanlimit = 2;
1690 mode_hfcpci(&hc->bch[0], 1, -1);
1691 mode_hfcpci(&hc->bch[1], 2, -1);
1692}
1693
1694
1695static int
1696init_card(struct hfc_pci *hc)
1697{
1698 int cnt = 3;
1699 u_long flags;
1700
1701 printk(KERN_DEBUG "init_card: entered\n");
1702
1703
1704 spin_lock_irqsave(&hc->lock, flags);
1705 disable_hwirq(hc);
1706 spin_unlock_irqrestore(&hc->lock, flags);
1707 if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1708 printk(KERN_WARNING
1709 "mISDN: couldn't get interrupt %d\n", hc->irq);
1710 return -EIO;
1711 }
1712 spin_lock_irqsave(&hc->lock, flags);
1713 reset_hfcpci(hc);
1714 while (cnt) {
1715 inithfcpci(hc);
1716 /*
1717 * Finally enable IRQ output
1718 * this is only allowed, if an IRQ routine is allready
1719 * established for this HFC, so don't do that earlier
1720 */
1721 enable_hwirq(hc);
1722 spin_unlock_irqrestore(&hc->lock, flags);
1723 /* Timeout 80ms */
1724 current->state = TASK_UNINTERRUPTIBLE;
1725 schedule_timeout((80*HZ)/1000);
1726 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1727 hc->irq, hc->irqcnt);
1728 /* now switch timer interrupt off */
1729 spin_lock_irqsave(&hc->lock, flags);
1730 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1731 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1732 /* reinit mode reg */
1733 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1734 if (!hc->irqcnt) {
1735 printk(KERN_WARNING
1736 "HFC PCI: IRQ(%d) getting no interrupts "
1737 "during init %d\n", hc->irq, 4 - cnt);
1738 if (cnt == 1) {
1739 spin_unlock_irqrestore(&hc->lock, flags);
1740 return -EIO;
1741 } else {
1742 reset_hfcpci(hc);
1743 cnt--;
1744 }
1745 } else {
1746 spin_unlock_irqrestore(&hc->lock, flags);
1747 hc->initdone = 1;
1748 return 0;
1749 }
1750 }
1751 disable_hwirq(hc);
1752 spin_unlock_irqrestore(&hc->lock, flags);
1753 free_irq(hc->irq, hc);
1754 return -EIO;
1755}
1756
1757static int
1758channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1759{
1760 int ret = 0;
1761 u_char slot;
1762
1763 switch (cq->op) {
1764 case MISDN_CTRL_GETOP:
1765 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1766 MISDN_CTRL_DISCONNECT;
1767 break;
1768 case MISDN_CTRL_LOOP:
1769 /* channel 0 disabled loop */
1770 if (cq->channel < 0 || cq->channel > 2) {
1771 ret = -EINVAL;
1772 break;
1773 }
1774 if (cq->channel & 1) {
1775 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1776 slot = 0xC0;
1777 else
1778 slot = 0x80;
1779 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1780 __func__, slot);
1781 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1782 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1783 hc->hw.conn = (hc->hw.conn & ~7) | 6;
1784 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1785 }
1786 if (cq->channel & 2) {
1787 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1788 slot = 0xC1;
1789 else
1790 slot = 0x81;
1791 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1792 __func__, slot);
1793 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1794 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1795 hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1796 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1797 }
1798 if (cq->channel & 3)
1799 hc->hw.trm |= 0x80; /* enable IOM-loop */
1800 else {
1801 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1802 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1803 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1804 }
1805 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1806 break;
1807 case MISDN_CTRL_CONNECT:
1808 if (cq->channel == cq->p1) {
1809 ret = -EINVAL;
1810 break;
1811 }
1812 if (cq->channel < 1 || cq->channel > 2 ||
1813 cq->p1 < 1 || cq->p1 > 2) {
1814 ret = -EINVAL;
1815 break;
1816 }
1817 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1818 slot = 0xC0;
1819 else
1820 slot = 0x80;
1821 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1822 __func__, slot);
1823 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1824 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1825 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1826 slot = 0xC1;
1827 else
1828 slot = 0x81;
1829 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1830 __func__, slot);
1831 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1832 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1833 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1834 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1835 hc->hw.trm |= 0x80;
1836 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1837 break;
1838 case MISDN_CTRL_DISCONNECT:
1839 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1840 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1841 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1842 break;
1843 default:
1844 printk(KERN_WARNING "%s: unknown Op %x\n",
1845 __func__, cq->op);
1846 ret = -EINVAL;
1847 break;
1848 }
1849 return ret;
1850}
1851
1852static int
1853open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1854 struct channel_req *rq)
1855{
1856 int err = 0;
1857
1858 if (debug & DEBUG_HW_OPEN)
1859 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1860 hc->dch.dev.id, __builtin_return_address(0));
1861 if (rq->protocol == ISDN_P_NONE)
1862 return -EINVAL;
1863 if (!hc->initdone) {
1864 if (rq->protocol == ISDN_P_TE_S0) {
1865 err = create_l1(&hc->dch, hfc_l1callback);
1866 if (err)
1867 return err;
1868 }
1869 hc->hw.protocol = rq->protocol;
1870 ch->protocol = rq->protocol;
1871 err = init_card(hc);
1872 if (err)
1873 return err;
1874 } else {
1875 if (rq->protocol != ch->protocol) {
1876 if (hc->hw.protocol == ISDN_P_TE_S0)
1877 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1878 hc->hw.protocol = rq->protocol;
1879 ch->protocol = rq->protocol;
1880 hfcpci_setmode(hc);
1881 }
1882 }
1883
1884 if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1885 ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1886 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1887 0, NULL, GFP_KERNEL);
1888 }
1889 rq->ch = ch;
1890 if (!try_module_get(THIS_MODULE))
1891 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1892 return 0;
1893}
1894
1895static int
1896open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1897{
1898 struct bchannel *bch;
1899
1900 if (rq->adr.channel > 2)
1901 return -EINVAL;
1902 if (rq->protocol == ISDN_P_NONE)
1903 return -EINVAL;
1904 bch = &hc->bch[rq->adr.channel - 1];
1905 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1906 return -EBUSY; /* b-channel can be only open once */
1907 bch->ch.protocol = rq->protocol;
1908 rq->ch = &bch->ch; /* TODO: E-channel */
1909 if (!try_module_get(THIS_MODULE))
1910 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1911 return 0;
1912}
1913
1914/*
1915 * device control function
1916 */
1917static int
1918hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1919{
1920 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1921 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1922 struct hfc_pci *hc = dch->hw;
1923 struct channel_req *rq;
1924 int err = 0;
1925
1926 if (dch->debug & DEBUG_HW)
1927 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1928 __func__, cmd, arg);
1929 switch (cmd) {
1930 case OPEN_CHANNEL:
1931 rq = arg;
1932 if (rq->adr.channel == 0)
1933 err = open_dchannel(hc, ch, rq);
1934 else
1935 err = open_bchannel(hc, rq);
1936 break;
1937 case CLOSE_CHANNEL:
1938 if (debug & DEBUG_HW_OPEN)
1939 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
1940 __func__, hc->dch.dev.id,
1941 __builtin_return_address(0));
1942 module_put(THIS_MODULE);
1943 break;
1944 case CONTROL_CHANNEL:
1945 err = channel_ctrl(hc, arg);
1946 break;
1947 default:
1948 if (dch->debug & DEBUG_HW)
1949 printk(KERN_DEBUG "%s: unknown command %x\n",
1950 __func__, cmd);
1951 return -EINVAL;
1952 }
1953 return err;
1954}
1955
1956static int
1957setup_hw(struct hfc_pci *hc)
1958{
1959 void *buffer;
1960
1961 printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
1962 hc->hw.cirm = 0;
1963 hc->dch.state = 0;
1964 pci_set_master(hc->pdev);
1965 if (!hc->irq) {
1966 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
1967 return 1;
1968 }
1969 hc->hw.pci_io = (char *)(ulong)hc->pdev->resource[1].start;
1970
1971 if (!hc->hw.pci_io) {
1972 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
1973 return 1;
1974 }
1975 /* Allocate memory for FIFOS */
1976 /* the memory needs to be on a 32k boundary within the first 4G */
1977 pci_set_dma_mask(hc->pdev, 0xFFFF8000);
1978 buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
1979 /* We silently assume the address is okay if nonzero */
1980 if (!buffer) {
1981 printk(KERN_WARNING
1982 "HFC-PCI: Error allocating memory for FIFO!\n");
1983 return 1;
1984 }
1985 hc->hw.fifos = buffer;
1986 pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
1987 hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
1988 printk(KERN_INFO
1989 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
1990 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
1991 (u_long) virt_to_bus(hc->hw.fifos),
1992 hc->irq, HZ);
1993 /* enable memory mapped ports, disable busmaster */
1994 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
1995 hc->hw.int_m2 = 0;
1996 disable_hwirq(hc);
1997 hc->hw.int_m1 = 0;
1998 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1999 /* At this point the needed PCI config is done */
2000 /* fifos are still not enabled */
2001 hc->hw.timer.function = (void *) hfcpci_Timer;
2002 hc->hw.timer.data = (long) hc;
2003 init_timer(&hc->hw.timer);
2004 /* default PCM master */
2005 test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2006 return 0;
2007}
2008
2009static void
2010release_card(struct hfc_pci *hc) {
2011 u_long flags;
2012
2013 spin_lock_irqsave(&hc->lock, flags);
2014 hc->hw.int_m2 = 0; /* interrupt output off ! */
2015 disable_hwirq(hc);
2016 mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2017 mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2018 if (hc->dch.timer.function != NULL) {
2019 del_timer(&hc->dch.timer);
2020 hc->dch.timer.function = NULL;
2021 }
2022 spin_unlock_irqrestore(&hc->lock, flags);
2023 if (hc->hw.protocol == ISDN_P_TE_S0)
2024 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2025 if (hc->initdone)
2026 free_irq(hc->irq, hc);
2027 release_io_hfcpci(hc); /* must release after free_irq! */
2028 mISDN_unregister_device(&hc->dch.dev);
2029 mISDN_freebchannel(&hc->bch[1]);
2030 mISDN_freebchannel(&hc->bch[0]);
2031 mISDN_freedchannel(&hc->dch);
2032 list_del(&hc->list);
2033 pci_set_drvdata(hc->pdev, NULL);
2034 kfree(hc);
2035}
2036
2037static int
2038setup_card(struct hfc_pci *card)
2039{
2040 int err = -EINVAL;
2041 u_int i;
2042 u_long flags;
2043 char name[MISDN_MAX_IDLEN];
2044
2045 if (HFC_cnt >= MAX_CARDS)
2046 return -EINVAL; /* maybe better value */
2047
2048 card->dch.debug = debug;
2049 spin_lock_init(&card->lock);
2050 mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2051 card->dch.hw = card;
2052 card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2053 card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2054 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2055 card->dch.dev.D.send = hfcpci_l2l1D;
2056 card->dch.dev.D.ctrl = hfc_dctrl;
2057 card->dch.dev.nrbchan = 2;
2058 for (i = 0; i < 2; i++) {
2059 card->bch[i].nr = i + 1;
2060 test_and_set_bit(i + 1, &card->dch.dev.channelmap[0]);
2061 card->bch[i].debug = debug;
2062 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM);
2063 card->bch[i].hw = card;
2064 card->bch[i].ch.send = hfcpci_l2l1B;
2065 card->bch[i].ch.ctrl = hfc_bctrl;
2066 card->bch[i].ch.nr = i + 1;
2067 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2068 }
2069 err = setup_hw(card);
2070 if (err)
2071 goto error;
2072 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2073 err = mISDN_register_device(&card->dch.dev, name);
2074 if (err)
2075 goto error;
2076 HFC_cnt++;
2077 write_lock_irqsave(&HFClock, flags);
2078 list_add_tail(&card->list, &HFClist);
2079 write_unlock_irqrestore(&HFClock, flags);
2080 printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2081 return 0;
2082error:
2083 mISDN_freebchannel(&card->bch[1]);
2084 mISDN_freebchannel(&card->bch[0]);
2085 mISDN_freedchannel(&card->dch);
2086 kfree(card);
2087 return err;
2088}
2089
2090/* private data in the PCI devices list */
2091struct _hfc_map {
2092 u_int subtype;
2093 u_int flag;
2094 char *name;
2095};
2096
2097static const struct _hfc_map hfc_map[] =
2098{
2099 {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2100 {HFC_CCD_B000, 0, "Billion B000"},
2101 {HFC_CCD_B006, 0, "Billion B006"},
2102 {HFC_CCD_B007, 0, "Billion B007"},
2103 {HFC_CCD_B008, 0, "Billion B008"},
2104 {HFC_CCD_B009, 0, "Billion B009"},
2105 {HFC_CCD_B00A, 0, "Billion B00A"},
2106 {HFC_CCD_B00B, 0, "Billion B00B"},
2107 {HFC_CCD_B00C, 0, "Billion B00C"},
2108 {HFC_CCD_B100, 0, "Seyeon B100"},
2109 {HFC_CCD_B700, 0, "Primux II S0 B700"},
2110 {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2111 {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2112 {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2113 {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2114 {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2115 {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2116 {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2117 {HFC_DIGI_DF_M_IOM2_E, 0,
2118 "Digi International DataFire Micro V IOM2 (Europe)"},
2119 {HFC_DIGI_DF_M_E, 0,
2120 "Digi International DataFire Micro V (Europe)"},
2121 {HFC_DIGI_DF_M_IOM2_A, 0,
2122 "Digi International DataFire Micro V IOM2 (North America)"},
2123 {HFC_DIGI_DF_M_A, 0,
2124 "Digi International DataFire Micro V (North America)"},
2125 {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2126 {},
2127};
2128
2129static struct pci_device_id hfc_ids[] =
2130{
2131 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0,
2132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[0]},
2133 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000,
2134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[1]},
2135 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006,
2136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[2]},
2137 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007,
2138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[3]},
2139 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008,
2140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[4]},
2141 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009,
2142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[5]},
2143 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A,
2144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[6]},
2145 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B,
2146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[7]},
2147 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C,
2148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[8]},
2149 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100,
2150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[9]},
2151 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B700,
2152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[10]},
2153 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B701,
2154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[11]},
2155 {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1,
2156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[12]},
2157 {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675,
2158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[13]},
2159 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT,
2160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[14]},
2161 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T,
2162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[15]},
2163 {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575,
2164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[16]},
2165 {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0,
2166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[17]},
2167 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,
2168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[18]},
2169 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,
2170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[19]},
2171 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,
2172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[20]},
2173 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,
2174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[21]},
2175 {PCI_VENDOR_ID_SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2,
2176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[22]},
2177 {},
2178};
2179
2180static int __devinit
2181hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2182{
2183 int err = -ENOMEM;
2184 struct hfc_pci *card;
2185 struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2186
2187 card = kzalloc(sizeof(struct hfc_pci), GFP_ATOMIC);
2188 if (!card) {
2189 printk(KERN_ERR "No kmem for HFC card\n");
2190 return err;
2191 }
2192 card->pdev = pdev;
2193 card->subtype = m->subtype;
2194 err = pci_enable_device(pdev);
2195 if (err) {
2196 kfree(card);
2197 return err;
2198 }
2199
2200 printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2201 m->name, pci_name(pdev));
2202
2203 card->irq = pdev->irq;
2204 pci_set_drvdata(pdev, card);
2205 err = setup_card(card);
2206 if (err)
2207 pci_set_drvdata(pdev, NULL);
2208 return err;
2209}
2210
2211static void __devexit
2212hfc_remove_pci(struct pci_dev *pdev)
2213{
2214 struct hfc_pci *card = pci_get_drvdata(pdev);
2215 u_long flags;
2216
2217 if (card) {
2218 write_lock_irqsave(&HFClock, flags);
2219 release_card(card);
2220 write_unlock_irqrestore(&HFClock, flags);
2221 } else
2222 if (debug)
2223 printk(KERN_WARNING "%s: drvdata allready removed\n",
2224 __func__);
2225}
2226
2227
2228static struct pci_driver hfc_driver = {
2229 .name = "hfcpci",
2230 .probe = hfc_probe,
2231 .remove = __devexit_p(hfc_remove_pci),
2232 .id_table = hfc_ids,
2233};
2234
2235static int __init
2236HFC_init(void)
2237{
2238 int err;
2239
2240 err = pci_register_driver(&hfc_driver);
2241 return err;
2242}
2243
2244static void __exit
2245HFC_cleanup(void)
2246{
2247 struct hfc_pci *card, *next;
2248
2249 list_for_each_entry_safe(card, next, &HFClist, list) {
2250 release_card(card);
2251 }
2252 pci_unregister_driver(&hfc_driver);
2253}
2254
2255module_init(HFC_init);
2256module_exit(HFC_cleanup);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 03:06:10 -0500