Patched in Tegra support.

1 files changed, 39 insertions, 8 deletions

diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
index e1c8c9e919a..4bfe0a2f7d5 100644
--- a/include/linux/dw_dmac.h
+++ b/include/linux/dw_dmac.h
@@ -19,10 +19,6 @@
  * @nr_channels: Number of channels supported by hardware (max 8)
  * @is_private: The device channels should be marked as private and not for
  *      by the general purpose DMA channel allocator.
- * @block_size: Maximum block size supported by the controller
- * @nr_masters: Number of AHB masters supported by the controller
- * @data_width: Maximum data width supported by hardware per AHB master
- *              (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
  */
 struct dw_dma_platform_data {
         unsigned int    nr_channels;
@@ -33,9 +29,18 @@ struct dw_dma_platform_data {
 #define CHAN_PRIORITY_ASCENDING         0       /* chan0 highest */
 #define CHAN_PRIORITY_DESCENDING        1       /* chan7 highest */
         unsigned char   chan_priority;
-        unsigned short  block_size;
-        unsigned char   nr_masters;
-        unsigned char   data_width[4];
+};
+
+/**
+ * enum dw_dma_slave_width - DMA slave register access width.
+ * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
+ * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
+ * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
+ */
+enum dw_dma_slave_width {
+        DW_DMA_SLAVE_WIDTH_8BIT,
+        DW_DMA_SLAVE_WIDTH_16BIT,
+        DW_DMA_SLAVE_WIDTH_32BIT,
 };
 
 /* bursts size */
@@ -50,21 +55,47 @@ enum dw_dma_msize {
         DW_DMA_MSIZE_256,
 };
 
+/* flow controller */
+enum dw_dma_fc {
+        DW_DMA_FC_D_M2M,
+        DW_DMA_FC_D_M2P,
+        DW_DMA_FC_D_P2M,
+        DW_DMA_FC_D_P2P,
+        DW_DMA_FC_P_P2M,
+        DW_DMA_FC_SP_P2P,
+        DW_DMA_FC_P_M2P,
+        DW_DMA_FC_DP_P2P,
+};
+
 /**
  * struct dw_dma_slave - Controller-specific information about a slave
  *
  * @dma_dev: required DMA master device
+ * @tx_reg: physical address of data register used for
+ *      memory-to-peripheral transfers
+ * @rx_reg: physical address of data register used for
+ *      peripheral-to-memory transfers
+ * @reg_width: peripheral register width
  * @cfg_hi: Platform-specific initializer for the CFG_HI register
  * @cfg_lo: Platform-specific initializer for the CFG_LO register
  * @src_master: src master for transfers on allocated channel.
  * @dst_master: dest master for transfers on allocated channel.
+ * @src_msize: src burst size.
+ * @dst_msize: dest burst size.
+ * @fc: flow controller for DMA transfer
  */
 struct dw_dma_slave {
         struct device           *dma_dev;
+        dma_addr_t              tx_reg;
+        dma_addr_t              rx_reg;
+        enum dw_dma_slave_width reg_width;
         u32                     cfg_hi;
         u32                     cfg_lo;
         u8                      src_master;
         u8                      dst_master;
+        u8                      src_msize;
+        u8                      dst_msize;
+        u8                      fc;
 };
 
 /* Platform-configurable bits in CFG_HI */
@@ -96,7 +127,7 @@ struct dw_cyclic_desc {
 
 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
-                enum dma_transfer_direction direction);
+                enum dma_data_direction direction);
 void dw_dma_cyclic_free(struct dma_chan *chan);
 int dw_dma_cyclic_start(struct dma_chan *chan);
 void dw_dma_cyclic_stop(struct dma_chan *chan);