aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pci/pcie
diff options
context:
space:
mode:
authorJiang Liu <jiang.liu@huawei.com>2012-07-24 05:20:11 -0400
committerBjorn Helgaas <bhelgaas@google.com>2012-08-23 12:11:11 -0400
commit43bd4ee89f748111d2a0443e6ef58f08ceb359aa (patch)
tree0daf4db59ab1b78dc17982a7742d84be64c1610b /drivers/pci/pcie
parent263e54b99eb8f77be9b2144c5e466e95847c888c (diff)
PCI/AER: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify PCIe AER. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/pcie')
-rw-r--r--drivers/pci/pcie/aer/aerdrv.c17
-rw-r--r--drivers/pci/pcie/aer/aerdrv_core.c51
2 files changed, 17 insertions, 51 deletions
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index f7c62453ae0..c78778fc0cb 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -122,19 +122,17 @@ static void set_downstream_devices_error_reporting(struct pci_dev *dev,
122static void aer_enable_rootport(struct aer_rpc *rpc) 122static void aer_enable_rootport(struct aer_rpc *rpc)
123{ 123{
124 struct pci_dev *pdev = rpc->rpd->port; 124 struct pci_dev *pdev = rpc->rpd->port;
125 int pos, aer_pos; 125 int aer_pos;
126 u16 reg16; 126 u16 reg16;
127 u32 reg32; 127 u32 reg32;
128 128
129 pos = pci_pcie_cap(pdev);
130 /* Clear PCIe Capability's Device Status */ 129 /* Clear PCIe Capability's Device Status */
131 pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, &reg16); 130 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, &reg16);
132 pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16); 131 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
133 132
134 /* Disable system error generation in response to error messages */ 133 /* Disable system error generation in response to error messages */
135 pci_read_config_word(pdev, pos + PCI_EXP_RTCTL, &reg16); 134 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
136 reg16 &= ~(SYSTEM_ERROR_INTR_ON_MESG_MASK); 135 SYSTEM_ERROR_INTR_ON_MESG_MASK);
137 pci_write_config_word(pdev, pos + PCI_EXP_RTCTL, reg16);
138 136
139 aer_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 137 aer_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
140 /* Clear error status */ 138 /* Clear error status */
@@ -396,9 +394,8 @@ static void aer_error_resume(struct pci_dev *dev)
396 u16 reg16; 394 u16 reg16;
397 395
398 /* Clean up Root device status */ 396 /* Clean up Root device status */
399 pos = pci_pcie_cap(dev); 397 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &reg16);
400 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &reg16); 398 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, reg16);
401 pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, reg16);
402 399
403 /* Clean AER Root Error Status */ 400 /* Clean AER Root Error Status */
404 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 401 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index f5515348985..cefc0ddcacf 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -32,53 +32,28 @@ static bool nosourceid;
32module_param(forceload, bool, 0); 32module_param(forceload, bool, 0);
33module_param(nosourceid, bool, 0); 33module_param(nosourceid, bool, 0);
34 34
35#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
36 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
37
35int pci_enable_pcie_error_reporting(struct pci_dev *dev) 38int pci_enable_pcie_error_reporting(struct pci_dev *dev)
36{ 39{
37 u16 reg16 = 0;
38 int pos;
39
40 if (pcie_aer_get_firmware_first(dev)) 40 if (pcie_aer_get_firmware_first(dev))
41 return -EIO; 41 return -EIO;
42 42
43 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 43 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))
44 if (!pos)
45 return -EIO;
46
47 pos = pci_pcie_cap(dev);
48 if (!pos)
49 return -EIO; 44 return -EIO;
50 45
51 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16); 46 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
52 reg16 |= (PCI_EXP_DEVCTL_CERE |
53 PCI_EXP_DEVCTL_NFERE |
54 PCI_EXP_DEVCTL_FERE |
55 PCI_EXP_DEVCTL_URRE);
56 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
57
58 return 0;
59} 47}
60EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting); 48EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
61 49
62int pci_disable_pcie_error_reporting(struct pci_dev *dev) 50int pci_disable_pcie_error_reporting(struct pci_dev *dev)
63{ 51{
64 u16 reg16 = 0;
65 int pos;
66
67 if (pcie_aer_get_firmware_first(dev)) 52 if (pcie_aer_get_firmware_first(dev))
68 return -EIO; 53 return -EIO;
69 54
70 pos = pci_pcie_cap(dev); 55 return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
71 if (!pos) 56 PCI_EXP_AER_FLAGS);
72 return -EIO;
73
74 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16);
75 reg16 &= ~(PCI_EXP_DEVCTL_CERE |
76 PCI_EXP_DEVCTL_NFERE |
77 PCI_EXP_DEVCTL_FERE |
78 PCI_EXP_DEVCTL_URRE);
79 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
80
81 return 0;
82} 57}
83EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting); 58EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
84 59
@@ -151,18 +126,12 @@ static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
151 */ 126 */
152 if (atomic_read(&dev->enable_cnt) == 0) 127 if (atomic_read(&dev->enable_cnt) == 0)
153 return false; 128 return false;
154 pos = pci_pcie_cap(dev);
155 if (!pos)
156 return false;
157 129
158 /* Check if AER is enabled */ 130 /* Check if AER is enabled */
159 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16); 131 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &reg16);
160 if (!(reg16 & ( 132 if (!(reg16 & PCI_EXP_AER_FLAGS))
161 PCI_EXP_DEVCTL_CERE |
162 PCI_EXP_DEVCTL_NFERE |
163 PCI_EXP_DEVCTL_FERE |
164 PCI_EXP_DEVCTL_URRE)))
165 return false; 133 return false;
134
166 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 135 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
167 if (!pos) 136 if (!pos)
168 return false; 137 return false;