PCI/PM: Fix config reg access for D3cold and bridge suspending

This patch fixes the following bug:

http://marc.info/?l=linux-pci&m=134338059022620&w=2

Where lspci does not work properly if a device and the corresponding
parent bridge (such as PCIe port) is suspended.  This is because the
device configuration space registers will be not accessible if the
corresponding parent bridge is suspended or the device is put into
D3cold state.

To solve the issue, the bridge/PCIe port connected to the device is
put into active state before read/write configuration space registers.
If the device is in D3cold state, it will be put into active state
too.

To avoid resume/suspend PCIe port for each configuration register
read/write, a small delay is added before the PCIe port to go
suspended.

Reported-by: Bjorn Mork <bjorn@mork.no>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>

1 files changed, 9 insertions, 0 deletions

diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c
index 62f5a76c8f8..e76b44777db 100644
--- a/drivers/pci/pcie/portdrv_pci.c
+++ b/drivers/pci/pcie/portdrv_pci.c
@@ -140,9 +140,17 @@ static int pcie_port_runtime_resume(struct device *dev)
 {
         return 0;
 }
+
+static int pcie_port_runtime_idle(struct device *dev)
+{
+        /* Delay for a short while to prevent too frequent suspend/resume */
+        pm_schedule_suspend(dev, 10);
+        return -EBUSY;
+}
 #else
 #define pcie_port_runtime_suspend       NULL
 #define pcie_port_runtime_resume        NULL
+#define pcie_port_runtime_idle          NULL
 #endif
 
 static const struct dev_pm_ops pcie_portdrv_pm_ops = {
@@ -155,6 +163,7 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = {
         .resume_noirq   = pcie_port_resume_noirq,
         .runtime_suspend = pcie_port_runtime_suspend,
         .runtime_resume = pcie_port_runtime_resume,
+        .runtime_idle   = pcie_port_runtime_idle,
 };
 
 #define PCIE_PORTDRV_PM_OPS     (&pcie_portdrv_pm_ops)